1 /*!
2 * \file trc_mem_acc_cache.h
3 * \brief OpenCSD : Memory accessor cache.
4 *
5 * \copyright Copyright (c) 2018, ARM Limited. All Rights Reserved.
6 */
7
8 /*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #ifndef ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
36 #define ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
37
38 #include <string>
39 #include "opencsd/ocsd_if_types.h"
40
41 #define MEM_ACC_CACHE_DEFAULT_PAGE_SIZE 2048
42 #define MEM_ACC_CACHE_DEFAULT_MRU_SIZE 16
43 #define MEM_ACC_CACHE_PAGE_SIZE_MAX 16384
44 #define MEM_ACC_CACHE_MRU_SIZE_MAX 256
45 #define MEM_ACC_CACHE_PAGE_SIZE_MIN 64
46 #define MEM_ACC_CACHE_MRU_SIZE_MIN 4
47
48 #define OCSD_ENV_MEMACC_CACHE_OFF "OPENCSD_MEMACC_CACHE_OFF"
49 #define OCSD_ENV_MEMACC_CACHE_PG_SIZE "OPENCSD_MEMACC_CACHE_PAGE_SIZE"
50 #define OCSD_ENV_MEMACC_CACHE_PG_NUM "OPENCSD_MEMACC_CACHE_PAGE_NUM"
51
52
53 class TrcMemAccessorBase;
54 class ITraceErrorLog;
55
56 typedef struct cache_block {
57 ocsd_vaddr_t st_addr;
58 uint32_t valid_len;
59 uint8_t* data;
60 uint8_t trcID; // trace ID associated with the page
61 uint32_t use_sequence; // number representing the sequence of allocation to evict oldest page.
62 } cache_block_t;
63
64 // enable define to collect stats for debugging / cache performance tests
65 // #define LOG_CACHE_STATS
66
67
68 /** class TrcMemAccCache - cache small amounts of data from accessors to speed up decode.
69 *
70 * Reduce the need to read files / make callbacks into clients when walking memory images.
71 *
72 * Caching is done on a per Core/Trace ID basis - all caches from that ID are invalidated when a context
73 * switch appears on the core. This means that we do not account for memory spaces in the cache pages as
74 * these only change via a context switch.
75 *
76 * Memory space is used on cache miss if reading data from the underlying accessor (file / callback).
77 */
78 class TrcMemAccCache
79 {
80 public:
81 TrcMemAccCache();
82 ~TrcMemAccCache();
83
84 /* cache enabling and usage */
85 ocsd_err_t enableCaching(bool bEnable);
86 // optionally error if outside limits - otherwise set to max / min automatically
87 ocsd_err_t setCacheSizes(const uint16_t page_size, const int nr_pages, const bool err_on_limit = false);
88
enabled()89 const bool enabled() const { return m_bCacheEnabled; };
enabled_for_size(const uint32_t reqSize)90 const bool enabled_for_size(const uint32_t reqSize) const
91 {
92 return (m_bCacheEnabled && (reqSize <= m_mru_page_size));
93 }
94
95 /* cache invalidation */
96 void invalidateAll();
97 void invalidateByTraceID(int8_t trcID);
98 void clearPage(cache_block_t* page);
99
100 /** read bytes from cache if possible - load new page if needed from underlying accessor, bail out if data not available */
101 ocsd_err_t readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer);
102
103 void setErrorLog(ITraceErrorLog *log);
104 void logAndClearCounts();
105
106 /* look for runtime cache tuning vars */
107 static void getenvMemaccCacheSizes(bool& enable, int& page_size, int& num_pages);
108
109 private:
110 bool blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes, const uint8_t trcID); // run through each page to look for data.
111 bool blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes, const uint8_t trcID);
112
113 void logMsg(const std::string &szMsg, ocsd_err_t err = OCSD_OK);
114 int findNewPage();
115 void incSequence(); // increment sequence on current block
116
117 ocsd_err_t createCaches(); // create caches according to current sizes
118 void destroyCaches(); // destroy the cache blocks
119
120 cache_block_t *m_mru; // cache pages
121 int m_mru_idx = 0; // in use index - most recently used page
122 uint16_t m_mru_page_size; // page size
123 int m_mru_num_pages; // number of pages
124 uint32_t m_mru_sequence; // allocation & use sequence number
125
126 bool m_bCacheEnabled = false;
127
128 #ifdef LOG_CACHE_STATS
129 uint32_t m_hits = 0;
130 uint32_t m_misses = 0;
131 uint32_t m_pages = 0;
132 uint32_t* m_hit_rl = 0;
133 uint32_t* m_hit_rl_max = 0;
134 #endif
135
136 ITraceErrorLog *m_err_log = 0;
137 };
138
TrcMemAccCache()139 inline TrcMemAccCache::TrcMemAccCache() :
140 m_mru(0), m_mru_sequence(1)
141 {
142 /* set default cache sizes */
143 m_mru_page_size = MEM_ACC_CACHE_DEFAULT_PAGE_SIZE;
144 m_mru_num_pages = MEM_ACC_CACHE_DEFAULT_MRU_SIZE;
145 }
146
~TrcMemAccCache()147 inline TrcMemAccCache::~TrcMemAccCache()
148 {
149 destroyCaches();
150 }
151
152
blockInPage(const ocsd_vaddr_t address,const uint32_t reqBytes,const uint8_t trcID)153 inline bool TrcMemAccCache::blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes, const uint8_t trcID)
154 {
155 /* check has data, trcID and mem space */
156 if ((m_mru[m_mru_idx].trcID != trcID) ||
157 (m_mru[m_mru_idx].valid_len == 0)
158 )
159 return false;
160
161 /* check block is in this page */
162 if ((m_mru[m_mru_idx].st_addr <= address) &&
163 m_mru[m_mru_idx].st_addr + m_mru[m_mru_idx].valid_len >= (address + reqBytes))
164 return true;
165 return false;
166 }
167
blockInCache(const ocsd_vaddr_t address,const uint32_t reqBytes,const uint8_t trcID)168 inline bool TrcMemAccCache::blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes, const uint8_t trcID)
169 {
170 int tests = m_mru_num_pages;
171 while (tests)
172 {
173 if (blockInPage(address, reqBytes, trcID))
174 return true; // found address in page
175 #ifdef LOG_CACHE_STATS
176 // miss counts of current page only - to determine if we hit other page
177 if (tests == m_mru_num_pages)
178 m_misses++;
179 #endif
180
181 tests--;
182 m_mru_idx++;
183 if (m_mru_idx == m_mru_num_pages)
184 m_mru_idx = 0;
185 }
186 return false;
187 }
188
189 // zero out page parameters rendering it empty
clearPage(cache_block_t * page)190 inline void TrcMemAccCache::clearPage(cache_block_t* page)
191 {
192 page->use_sequence = 0;
193 page->st_addr = 0;
194 page->valid_len = 0;
195 page->trcID = OCSD_BAD_CS_SRC_ID;
196 }
197
198 #endif // ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
199
200 /* End of File trc_mem_acc_cache.h */
201