1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef __TIMED_CTRL_GLOBAL_H_INCLUDED__ 8 #define __TIMED_CTRL_GLOBAL_H_INCLUDED__ 9 10 #define IS_TIMED_CTRL_VERSION_1 11 12 #include "timed_controller_defs.h" 13 14 /** 15 * Order of the input bits for the timed controller taken from 16 * ISP_CSS_2401 System Architecture Description valid for 17 * 2400, 2401. 18 * 19 * Check for other systems. 20 */ 21 #define HIVE_TIMED_CTRL_GPIO_PIN_0_BIT_ID 0 22 #define HIVE_TIMED_CTRL_GPIO_PIN_1_BIT_ID 1 23 #define HIVE_TIMED_CTRL_GPIO_PIN_2_BIT_ID 2 24 #define HIVE_TIMED_CTRL_GPIO_PIN_3_BIT_ID 3 25 #define HIVE_TIMED_CTRL_GPIO_PIN_4_BIT_ID 4 26 #define HIVE_TIMED_CTRL_GPIO_PIN_5_BIT_ID 5 27 #define HIVE_TIMED_CTRL_GPIO_PIN_6_BIT_ID 6 28 #define HIVE_TIMED_CTRL_GPIO_PIN_7_BIT_ID 7 29 #define HIVE_TIMED_CTRL_GPIO_PIN_8_BIT_ID 8 30 #define HIVE_TIMED_CTRL_GPIO_PIN_9_BIT_ID 9 31 #define HIVE_TIMED_CTRL_GPIO_PIN_10_BIT_ID 10 32 #define HIVE_TIMED_CTRL_GPIO_PIN_11_BIT_ID 11 33 #define HIVE_TIMED_CTRL_IRQ_SP_BIT_ID 12 34 #define HIVE_TIMED_CTRL_IRQ_ISP_BIT_ID 13 35 #define HIVE_TIMED_CTRL_IRQ_INPUT_SYSTEM_BIT_ID 14 36 #define HIVE_TIMED_CTRL_IRQ_INPUT_SELECTOR_BIT_ID 15 37 #define HIVE_TIMED_CTRL_IRQ_IF_BLOCK_BIT_ID 16 38 #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_0_BIT_ID 17 39 #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_1_BIT_ID 18 40 #define HIVE_TIMED_CTRL_CSI_SOL_BIT_ID 19 41 #define HIVE_TIMED_CTRL_CSI_EOL_BIT_ID 20 42 #define HIVE_TIMED_CTRL_CSI_SOF_BIT_ID 21 43 #define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID 22 44 #define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID 23 45 46 #endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */ 47