xref: /aosp_15_r20/external/coreboot/src/soc/intel/common/block/thermal/thermal_pci.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/mmio.h>
6 #include <intelblocks/thermal.h>
7 #include <soc/pci_devs.h>
8 
9 #define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c
10 #define CATASTROPHIC_TRIP_POINT_MASK 0x1ff
11 
12 /* Enable thermal sensor power management */
pch_thermal_configuration(void)13 void pch_thermal_configuration(void)
14 {
15 	uintptr_t thermalbar;
16 	uintptr_t thermalbar_pm;
17 	const struct device *dev;
18 	struct resource *res;
19 
20 	dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
21 	if (!dev) {
22 		printk(BIOS_ERR, "PCH_DEVFN_THERMAL device not found!\n");
23 		return;
24 	}
25 
26 	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
27 	if (!res) {
28 		printk(BIOS_ERR, "PCH thermal device not found!\n");
29 		return;
30 	}
31 
32 	/* Get the base address of the resource */
33 	thermalbar = res->base;
34 
35 	/* Get the required thermal address to write the register value */
36 	thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT;
37 
38 	/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
39 	clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value());
40 }
41