1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "nir_test.h"
25
26 namespace {
27
28 class nir_builder_test : public nir_test {
29 private:
type_for_def(nir_def * def)30 const glsl_type *type_for_def(nir_def *def)
31 {
32 switch (def->bit_size) {
33 case 8: return glsl_u8vec_type(def->num_components);
34 case 16: return glsl_u16vec_type(def->num_components);
35 case 32: return glsl_uvec_type(def->num_components);
36 case 64: return glsl_u64vec_type(def->num_components);
37 default: unreachable("Invalid bit size");
38 }
39 }
40
41 protected:
nir_builder_test()42 nir_builder_test()
43 : nir_test::nir_test("nir_builder_test")
44 {
45 }
46
store_test_val(nir_def * val)47 void store_test_val(nir_def *val)
48 {
49 nir_variable *var = nir_variable_create(b->shader, nir_var_mem_ssbo,
50 type_for_def(val), NULL);
51 nir_intrinsic_instr *store =
52 nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_deref);
53 store->num_components = val->num_components;
54 store->src[0] = nir_src_for_ssa(&nir_build_deref_var(b, var)->def);
55 store->src[1] = nir_src_for_ssa(val);
56 nir_intrinsic_set_write_mask(store, ((1 << val->num_components) - 1));
57 nir_builder_instr_insert(b, &store->instr);
58
59 stores.push_back(store);
60 }
61
test_val(unsigned idx)62 nir_def *test_val(unsigned idx)
63 {
64 return stores[idx]->src[1].ssa;
65 }
66
67 std::vector<nir_intrinsic_instr *> stores;
68 };
69
70 /* Allow grouping the tests while still sharing the helpers. */
71 class nir_extract_bits_test : public nir_builder_test {};
72
73 } // namespace
74
75 // TODO: Re-enable this once we get vec8 support in NIR
TEST_F(nir_extract_bits_test,DISABLED_unaligned8)76 TEST_F(nir_extract_bits_test, DISABLED_unaligned8)
77 {
78 nir_def *srcs[] = {
79 nir_imm_int(b, 0x03020100),
80 nir_imm_ivec2(b, 0x07060504, 0x0b0a0908),
81 };
82
83 store_test_val(nir_extract_bits(b, srcs, 2, 24, 1, 64));
84
85 NIR_PASS_V(b->shader, nir_opt_constant_folding);
86
87 nir_src val = nir_src_for_ssa(test_val(0));
88
89 ASSERT_EQ(nir_src_as_uint(val), 0x0a09080706050403);
90 }
91
TEST_F(nir_extract_bits_test,unaligned16_disabled)92 TEST_F(nir_extract_bits_test, unaligned16_disabled)
93 {
94 nir_def *srcs[] = {
95 nir_imm_int(b, 0x03020100),
96 nir_imm_ivec2(b, 0x07060504, 0x0b0a0908),
97 };
98
99 store_test_val(nir_extract_bits(b, srcs, 2, 16, 1, 64));
100
101 NIR_PASS_V(b->shader, nir_opt_constant_folding);
102
103 nir_src val = nir_src_for_ssa(test_val(0));
104
105 ASSERT_EQ(nir_src_as_uint(val), 0x0908070605040302);
106 }
107
TEST_F(nir_extract_bits_test,mixed_bit_sizes)108 TEST_F(nir_extract_bits_test, mixed_bit_sizes)
109 {
110 nir_def *srcs[] = {
111 nir_imm_int(b, 0x03020100),
112 nir_imm_intN_t(b, 0x04, 8),
113 nir_imm_intN_t(b, 0x08070605, 32),
114 nir_vec2(b, nir_imm_intN_t(b, 0x0a09, 16),
115 nir_imm_intN_t(b, 0x0c0b, 16)),
116 };
117
118 store_test_val(nir_extract_bits(b, srcs, 4, 24, 2, 32));
119
120 NIR_PASS_V(b->shader, nir_opt_constant_folding);
121
122 nir_src val = nir_src_for_ssa(test_val(0));
123
124 ASSERT_EQ(nir_src_comp_as_uint(val, 0), 0x06050403);
125 ASSERT_EQ(nir_src_comp_as_uint(val, 1), 0x0a090807);
126 }
127