1 /**************************************************************************//**
2  * @file     system_S128.h
3  * @brief    CMSIS Cortex-M0+ Device Peripheral Access Layer Header File for
4  *           Device S128
5  * @version  V3.10
6  * @date     23. November 2012
7  *
8  * @note
9  *
10  ******************************************************************************/
11 /* Copyright (c) 2012 ARM LIMITED
12 
13    All rights reserved.
14    Redistribution and use in source and binary forms, with or without
15    modification, are permitted provided that the following conditions are met:
16    - Redistributions of source code must retain the above copyright
17      notice, this list of conditions and the following disclaimer.
18    - Redistributions in binary form must reproduce the above copyright
19      notice, this list of conditions and the following disclaimer in the
20      documentation and/or other materials provided with the distribution.
21    - Neither the name of ARM nor the names of its contributors may be used
22      to endorse or promote products derived from this software without
23      specific prior written permission.
24    *
25    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35    POSSIBILITY OF SUCH DAMAGE.
36    ---------------------------------------------------------------------------*/
37 
38 
39 #ifndef SYSTEM_S1JA_H
40 #define SYSTEM_S1JA_H
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 #include <stdint.h>
47 
48 extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
49 
50 
51 /**
52  * Initialize the system
53  *
54  * @return none
55  *
56  * @brief  Setup the microcontroller system.
57  *         Initialize the System and update the SystemCoreClock variable.
58  */
59 extern void SystemInit (void);
60 
61 /**
62  * Update SystemCoreClock variable
63  *
64  * @return none
65  *
66  * @brief  Updates the SystemCoreClock with current core Clock
67  *         retrieved from cpu registers.
68  */
69 extern void SystemCoreClockUpdate (void);
70 
71 #ifdef __cplusplus
72 }
73 #endif
74 
75 #endif /* SYSTEM_S1JA_H */
76