1 /**************************************************************************//**
2 * @file core_armv8mml.h
3 * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File
4 * @version V5.0.2
5 * @date 19. April 2017
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_ARMV8MML_H_GENERIC
32 #define __CORE_ARMV8MML_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_ARMv8MML
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS ARMv8MML definitions */
66 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
69 __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M (81U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75 */
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #if defined __ARM_PCS_VFP
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91 #define __FPU_USED 1U
92 #else
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #define __FPU_USED 0U
95 #endif
96 #else
97 #define __FPU_USED 0U
98 #endif
99
100 #elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112 #elif defined ( __ICCARM__ )
113 #if defined __ARMVFP__
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
116 #else
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
119 #endif
120 #else
121 #define __FPU_USED 0U
122 #endif
123
124 #elif defined ( __TI_ARM__ )
125 #if defined __TI_VFP_SUPPORT__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
140 #else
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148 #elif defined ( __CSMC__ )
149 #if ( __CSMC__ & 0x400U)
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160 #endif
161
162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163
164
165 #ifdef __cplusplus
166 }
167 #endif
168
169 #endif /* __CORE_ARMV8MML_H_GENERIC */
170
171 #ifndef __CMSIS_GENERIC
172
173 #ifndef __CORE_ARMV8MML_H_DEPENDANT
174 #define __CORE_ARMV8MML_H_DEPENDANT
175
176 #ifdef __cplusplus
177 extern "C" {
178 #endif
179
180 /* check device defines and use defaults */
181 #if defined __CHECK_DEVICE_DEFINES
182 #ifndef __ARMv8MML_REV
183 #define __ARMv8MML_REV 0x0000U
184 #warning "__ARMv8MML_REV not defined in device header file; using default!"
185 #endif
186
187 #ifndef __FPU_PRESENT
188 #define __FPU_PRESENT 0U
189 #warning "__FPU_PRESENT not defined in device header file; using default!"
190 #endif
191
192 #ifndef __MPU_PRESENT
193 #define __MPU_PRESENT 0U
194 #warning "__MPU_PRESENT not defined in device header file; using default!"
195 #endif
196
197 #ifndef __SAUREGION_PRESENT
198 #define __SAUREGION_PRESENT 0U
199 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
200 #endif
201
202 #ifndef __DSP_PRESENT
203 #define __DSP_PRESENT 0U
204 #warning "__DSP_PRESENT not defined in device header file; using default!"
205 #endif
206
207 #ifndef __NVIC_PRIO_BITS
208 #define __NVIC_PRIO_BITS 3U
209 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
210 #endif
211
212 #ifndef __Vendor_SysTickConfig
213 #define __Vendor_SysTickConfig 0U
214 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
215 #endif
216 #endif
217
218 /* IO definitions (access restrictions to peripheral registers) */
219 /**
220 \defgroup CMSIS_glob_defs CMSIS Global Defines
221
222 <strong>IO Type Qualifiers</strong> are used
223 \li to specify the access to peripheral variables.
224 \li for automatic generation of peripheral register debug information.
225 */
226 #ifdef __cplusplus
227 #define __I volatile /*!< Defines 'read only' permissions */
228 #else
229 #define __I volatile const /*!< Defines 'read only' permissions */
230 #endif
231 #define __O volatile /*!< Defines 'write only' permissions */
232 #define __IO volatile /*!< Defines 'read / write' permissions */
233
234 /* following defines should be used for structure members */
235 #define __IM volatile const /*! Defines 'read only' structure member permissions */
236 #define __OM volatile /*! Defines 'write only' structure member permissions */
237 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
238
239 /*@} end of group ARMv8MML */
240
241
242
243 /*******************************************************************************
244 * Register Abstraction
245 Core Register contain:
246 - Core Register
247 - Core NVIC Register
248 - Core SCB Register
249 - Core SysTick Register
250 - Core Debug Register
251 - Core MPU Register
252 - Core SAU Register
253 - Core FPU Register
254 ******************************************************************************/
255 /**
256 \defgroup CMSIS_core_register Defines and Type Definitions
257 \brief Type definitions and defines for Cortex-M processor based devices.
258 */
259
260 /**
261 \ingroup CMSIS_core_register
262 \defgroup CMSIS_CORE Status and Control Registers
263 \brief Core Register type definitions.
264 @{
265 */
266
267 /**
268 \brief Union type to access the Application Program Status Register (APSR).
269 */
270 typedef union
271 {
272 struct
273 {
274 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
275 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
276 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
277 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
282 } b; /*!< Structure used for bit access */
283 uint32_t w; /*!< Type used for word access */
284 } APSR_Type;
285
286 /* APSR Register Definitions */
287 #define APSR_N_Pos 31U /*!< APSR: N Position */
288 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
289
290 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
291 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
292
293 #define APSR_C_Pos 29U /*!< APSR: C Position */
294 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
295
296 #define APSR_V_Pos 28U /*!< APSR: V Position */
297 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
298
299 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
300 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
301
302 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
303 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
304
305
306 /**
307 \brief Union type to access the Interrupt Program Status Register (IPSR).
308 */
309 typedef union
310 {
311 struct
312 {
313 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
314 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
315 } b; /*!< Structure used for bit access */
316 uint32_t w; /*!< Type used for word access */
317 } IPSR_Type;
318
319 /* IPSR Register Definitions */
320 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
321 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
322
323
324 /**
325 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
326 */
327 typedef union
328 {
329 struct
330 {
331 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
332 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
333 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
334 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
335 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
336 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
337 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
338 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
339 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
340 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
341 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
342 } b; /*!< Structure used for bit access */
343 uint32_t w; /*!< Type used for word access */
344 } xPSR_Type;
345
346 /* xPSR Register Definitions */
347 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
348 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
349
350 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
351 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
352
353 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
354 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
355
356 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
357 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
358
359 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
360 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
361
362 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
363 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
364
365 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
366 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
367
368 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
369 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
370
371 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
372 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
373
374
375 /**
376 \brief Union type to access the Control Registers (CONTROL).
377 */
378 typedef union
379 {
380 struct
381 {
382 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
383 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
384 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
385 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
386 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
387 } b; /*!< Structure used for bit access */
388 uint32_t w; /*!< Type used for word access */
389 } CONTROL_Type;
390
391 /* CONTROL Register Definitions */
392 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
393 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
394
395 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
396 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
397
398 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
399 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
400
401 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
402 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
403
404 /*@} end of group CMSIS_CORE */
405
406
407 /**
408 \ingroup CMSIS_core_register
409 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
410 \brief Type definitions for the NVIC Registers
411 @{
412 */
413
414 /**
415 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
416 */
417 typedef struct
418 {
419 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
420 uint32_t RESERVED0[16U];
421 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
422 uint32_t RSERVED1[16U];
423 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
424 uint32_t RESERVED2[16U];
425 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
426 uint32_t RESERVED3[16U];
427 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
428 uint32_t RESERVED4[16U];
429 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
430 uint32_t RESERVED5[16U];
431 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
432 uint32_t RESERVED6[580U];
433 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
434 } NVIC_Type;
435
436 /* Software Triggered Interrupt Register Definitions */
437 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
438 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
439
440 /*@} end of group CMSIS_NVIC */
441
442
443 /**
444 \ingroup CMSIS_core_register
445 \defgroup CMSIS_SCB System Control Block (SCB)
446 \brief Type definitions for the System Control Block Registers
447 @{
448 */
449
450 /**
451 \brief Structure type to access the System Control Block (SCB).
452 */
453 typedef struct
454 {
455 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
456 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
457 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
458 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
459 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
460 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
461 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
462 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
463 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
464 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
465 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
466 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
467 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
468 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
469 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
470 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
471 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
472 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
473 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
474 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
475 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
476 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
477 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
478 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
479 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
480 uint32_t RESERVED3[92U];
481 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
482 uint32_t RESERVED4[15U];
483 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
484 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
485 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
486 uint32_t RESERVED5[1U];
487 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
488 uint32_t RESERVED6[1U];
489 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
490 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
491 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
492 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
493 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
494 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
495 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
496 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
497 uint32_t RESERVED7[6U];
498 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
499 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
500 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
501 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
502 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
503 uint32_t RESERVED8[1U];
504 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
505 } SCB_Type;
506
507 /* SCB CPUID Register Definitions */
508 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
509 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
510
511 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
512 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
513
514 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
515 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
516
517 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
518 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
519
520 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
521 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
522
523 /* SCB Interrupt Control State Register Definitions */
524 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
525 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
526
527 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
528 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
529
530 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
531 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
532
533 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
534 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
535
536 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
537 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
538
539 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
540 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
541
542 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
543 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
544
545 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
546 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
547
548 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
549 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
550
551 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
552 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
553
554 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
555 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
556
557 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
558 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
559
560 /* SCB Vector Table Offset Register Definitions */
561 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
562 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
563
564 /* SCB Application Interrupt and Reset Control Register Definitions */
565 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
566 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
567
568 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
569 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
570
571 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
572 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
573
574 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
575 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
576
577 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
578 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
579
580 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
581 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
582
583 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
584 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
585
586 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
587 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
588
589 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
590 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
591
592 /* SCB System Control Register Definitions */
593 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
594 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
595
596 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
597 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
598
599 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
600 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
601
602 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
603 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
604
605 /* SCB Configuration Control Register Definitions */
606 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
607 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
608
609 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
610 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
611
612 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
613 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
614
615 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
616 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
617
618 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
619 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
620
621 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
622 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
623
624 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
625 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
626
627 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
628 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
629
630 /* SCB System Handler Control and State Register Definitions */
631 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
632 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
633
634 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
635 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
636
637 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
638 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
639
640 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
641 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
642
643 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
644 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
645
646 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
647 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
648
649 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
650 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
651
652 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
653 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
654
655 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
656 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
657
658 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
659 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
660
661 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
662 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
663
664 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
665 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
666
667 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
668 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
669
670 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
671 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
672
673 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
674 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
675
676 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
677 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
678
679 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
680 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
681
682 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
683 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
684
685 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
686 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
687
688 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
689 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
690
691 /* SCB Configurable Fault Status Register Definitions */
692 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
693 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
694
695 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
696 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
697
698 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
699 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
700
701 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
702 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
703 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
704
705 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
706 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
707
708 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
709 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
710
711 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
712 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
713
714 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
715 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
716
717 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
718 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
719
720 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
721 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
722 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
723
724 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
725 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
726
727 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
728 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
729
730 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
731 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
732
733 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
734 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
735
736 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
737 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
738
739 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
740 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
741
742 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
743 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
744 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
745
746 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
747 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
748
749 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
750 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
751
752 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
753 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
754
755 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
756 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
757
758 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
759 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
760
761 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
762 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
763
764 /* SCB Hard Fault Status Register Definitions */
765 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
766 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
767
768 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
769 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
770
771 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
772 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
773
774 /* SCB Debug Fault Status Register Definitions */
775 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
776 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
777
778 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
779 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
780
781 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
782 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
783
784 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
785 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
786
787 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
788 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
789
790 /* SCB Non-Secure Access Control Register Definitions */
791 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
792 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
793
794 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
795 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
796
797 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
798 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
799
800 /* SCB Cache Level ID Register Definitions */
801 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
802 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
803
804 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
805 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
806
807 /* SCB Cache Type Register Definitions */
808 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
809 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
810
811 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
812 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
813
814 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
815 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
816
817 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
818 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
819
820 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
821 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
822
823 /* SCB Cache Size ID Register Definitions */
824 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
825 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
826
827 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
828 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
829
830 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
831 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
832
833 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
834 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
835
836 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
837 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
838
839 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
840 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
841
842 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
843 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
844
845 /* SCB Cache Size Selection Register Definitions */
846 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
847 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
848
849 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
850 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
851
852 /* SCB Software Triggered Interrupt Register Definitions */
853 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
854 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
855
856 /* SCB D-Cache Invalidate by Set-way Register Definitions */
857 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
858 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
859
860 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
861 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
862
863 /* SCB D-Cache Clean by Set-way Register Definitions */
864 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
865 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
866
867 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
868 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
869
870 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
871 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
872 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
873
874 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
875 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
876
877 /* Instruction Tightly-Coupled Memory Control Register Definitions */
878 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
879 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
880
881 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
882 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
883
884 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
885 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
886
887 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
888 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
889
890 /* Data Tightly-Coupled Memory Control Register Definitions */
891 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
892 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
893
894 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
895 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
896
897 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
898 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
899
900 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
901 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
902
903 /* AHBP Control Register Definitions */
904 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
905 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
906
907 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
908 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
909
910 /* L1 Cache Control Register Definitions */
911 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
912 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
913
914 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
915 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
916
917 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
918 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
919
920 /* AHBS Control Register Definitions */
921 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
922 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
923
924 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
925 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
926
927 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
928 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
929
930 /* Auxiliary Bus Fault Status Register Definitions */
931 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
932 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
933
934 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
935 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
936
937 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
938 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
939
940 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
941 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
942
943 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
944 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
945
946 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
947 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
948
949 /*@} end of group CMSIS_SCB */
950
951
952 /**
953 \ingroup CMSIS_core_register
954 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
955 \brief Type definitions for the System Control and ID Register not in the SCB
956 @{
957 */
958
959 /**
960 \brief Structure type to access the System Control and ID Register not in the SCB.
961 */
962 typedef struct
963 {
964 uint32_t RESERVED0[1U];
965 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
966 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
967 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
968 } SCnSCB_Type;
969
970 /* Interrupt Controller Type Register Definitions */
971 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
972 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
973
974 /*@} end of group CMSIS_SCnotSCB */
975
976
977 /**
978 \ingroup CMSIS_core_register
979 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
980 \brief Type definitions for the System Timer Registers.
981 @{
982 */
983
984 /**
985 \brief Structure type to access the System Timer (SysTick).
986 */
987 typedef struct
988 {
989 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
990 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
991 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
992 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
993 } SysTick_Type;
994
995 /* SysTick Control / Status Register Definitions */
996 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
997 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
998
999 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1000 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1001
1002 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1003 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1004
1005 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1006 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1007
1008 /* SysTick Reload Register Definitions */
1009 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1010 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1011
1012 /* SysTick Current Register Definitions */
1013 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1014 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1015
1016 /* SysTick Calibration Register Definitions */
1017 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1018 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1019
1020 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1021 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1022
1023 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1024 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1025
1026 /*@} end of group CMSIS_SysTick */
1027
1028
1029 /**
1030 \ingroup CMSIS_core_register
1031 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1032 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1033 @{
1034 */
1035
1036 /**
1037 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1038 */
1039 typedef struct
1040 {
1041 __OM union
1042 {
1043 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1044 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1045 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1046 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1047 uint32_t RESERVED0[864U];
1048 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1049 uint32_t RESERVED1[15U];
1050 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1051 uint32_t RESERVED2[15U];
1052 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1053 uint32_t RESERVED3[29U];
1054 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
1055 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
1056 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
1057 uint32_t RESERVED4[43U];
1058 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1059 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1060 uint32_t RESERVED5[1U];
1061 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1062 uint32_t RESERVED6[4U];
1063 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1064 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1065 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1066 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1067 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1068 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1069 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1070 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1071 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1072 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1073 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1074 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1075 } ITM_Type;
1076
1077 /* ITM Stimulus Port Register Definitions */
1078 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1079 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1080
1081 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1082 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1083
1084 /* ITM Trace Privilege Register Definitions */
1085 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1086 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1087
1088 /* ITM Trace Control Register Definitions */
1089 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1090 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1091
1092 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1093 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1094
1095 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1096 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1097
1098 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1099 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1100
1101 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1102 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1103
1104 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1105 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1106
1107 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1108 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1109
1110 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1111 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1112
1113 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1114 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1115
1116 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1117 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1118
1119 /* ITM Integration Write Register Definitions */
1120 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
1121 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
1122
1123 /* ITM Integration Read Register Definitions */
1124 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
1125 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
1126
1127 /* ITM Integration Mode Control Register Definitions */
1128 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
1129 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
1130
1131 /* ITM Lock Status Register Definitions */
1132 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1133 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1134
1135 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1136 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1137
1138 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1139 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1140
1141 /*@}*/ /* end of group CMSIS_ITM */
1142
1143
1144 /**
1145 \ingroup CMSIS_core_register
1146 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1147 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1148 @{
1149 */
1150
1151 /**
1152 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1153 */
1154 typedef struct
1155 {
1156 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1157 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1158 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1159 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1160 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1161 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1162 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1163 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1164 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1165 uint32_t RESERVED1[1U];
1166 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1167 uint32_t RESERVED2[1U];
1168 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1169 uint32_t RESERVED3[1U];
1170 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1171 uint32_t RESERVED4[1U];
1172 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1173 uint32_t RESERVED5[1U];
1174 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1175 uint32_t RESERVED6[1U];
1176 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1177 uint32_t RESERVED7[1U];
1178 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1179 uint32_t RESERVED8[1U];
1180 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1181 uint32_t RESERVED9[1U];
1182 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1183 uint32_t RESERVED10[1U];
1184 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1185 uint32_t RESERVED11[1U];
1186 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1187 uint32_t RESERVED12[1U];
1188 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1189 uint32_t RESERVED13[1U];
1190 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1191 uint32_t RESERVED14[1U];
1192 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1193 uint32_t RESERVED15[1U];
1194 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1195 uint32_t RESERVED16[1U];
1196 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1197 uint32_t RESERVED17[1U];
1198 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1199 uint32_t RESERVED18[1U];
1200 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1201 uint32_t RESERVED19[1U];
1202 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1203 uint32_t RESERVED20[1U];
1204 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1205 uint32_t RESERVED21[1U];
1206 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1207 uint32_t RESERVED22[1U];
1208 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1209 uint32_t RESERVED23[1U];
1210 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1211 uint32_t RESERVED24[1U];
1212 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1213 uint32_t RESERVED25[1U];
1214 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1215 uint32_t RESERVED26[1U];
1216 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1217 uint32_t RESERVED27[1U];
1218 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1219 uint32_t RESERVED28[1U];
1220 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1221 uint32_t RESERVED29[1U];
1222 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1223 uint32_t RESERVED30[1U];
1224 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1225 uint32_t RESERVED31[1U];
1226 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1227 uint32_t RESERVED32[934U];
1228 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1229 uint32_t RESERVED33[1U];
1230 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1231 } DWT_Type;
1232
1233 /* DWT Control Register Definitions */
1234 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1235 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1236
1237 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1238 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1239
1240 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1241 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1242
1243 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1244 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1245
1246 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1247 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1248
1249 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1250 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1251
1252 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1253 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1254
1255 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1256 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1257
1258 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1259 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1260
1261 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1262 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1263
1264 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1265 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1266
1267 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1268 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1269
1270 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1271 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1272
1273 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1274 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1275
1276 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1277 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1278
1279 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1280 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1281
1282 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1283 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1284
1285 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1286 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1287
1288 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1289 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1290
1291 /* DWT CPI Count Register Definitions */
1292 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1293 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1294
1295 /* DWT Exception Overhead Count Register Definitions */
1296 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1297 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1298
1299 /* DWT Sleep Count Register Definitions */
1300 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1301 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1302
1303 /* DWT LSU Count Register Definitions */
1304 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1305 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1306
1307 /* DWT Folded-instruction Count Register Definitions */
1308 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1309 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1310
1311 /* DWT Comparator Function Register Definitions */
1312 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1313 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1314
1315 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1316 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1317
1318 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1319 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1320
1321 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1322 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1323
1324 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1325 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1326
1327 /*@}*/ /* end of group CMSIS_DWT */
1328
1329
1330 /**
1331 \ingroup CMSIS_core_register
1332 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1333 \brief Type definitions for the Trace Port Interface (TPI)
1334 @{
1335 */
1336
1337 /**
1338 \brief Structure type to access the Trace Port Interface Register (TPI).
1339 */
1340 typedef struct
1341 {
1342 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1343 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1344 uint32_t RESERVED0[2U];
1345 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1346 uint32_t RESERVED1[55U];
1347 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1348 uint32_t RESERVED2[131U];
1349 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1350 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1351 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1352 uint32_t RESERVED3[759U];
1353 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1354 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1355 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1356 uint32_t RESERVED4[1U];
1357 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1358 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1359 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1360 uint32_t RESERVED5[39U];
1361 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1362 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1363 uint32_t RESERVED7[8U];
1364 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1365 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1366 } TPI_Type;
1367
1368 /* TPI Asynchronous Clock Prescaler Register Definitions */
1369 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1370 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1371
1372 /* TPI Selected Pin Protocol Register Definitions */
1373 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1374 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1375
1376 /* TPI Formatter and Flush Status Register Definitions */
1377 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1378 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1379
1380 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1381 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1382
1383 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1384 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1385
1386 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1387 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1388
1389 /* TPI Formatter and Flush Control Register Definitions */
1390 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1391 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1392
1393 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1394 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1395
1396 /* TPI TRIGGER Register Definitions */
1397 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1398 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1399
1400 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1401 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1402 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1403
1404 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1405 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1406
1407 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1408 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1409
1410 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1411 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1412
1413 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1414 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1415
1416 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1417 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1418
1419 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1420 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1421
1422 /* TPI ITATBCTR2 Register Definitions */
1423 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1424 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1425
1426 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1427 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1428 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1429
1430 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1431 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1432
1433 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1434 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1435
1436 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1437 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1438
1439 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1440 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1441
1442 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1443 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1444
1445 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1446 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1447
1448 /* TPI ITATBCTR0 Register Definitions */
1449 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1450 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1451
1452 /* TPI Integration Mode Control Register Definitions */
1453 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1454 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1455
1456 /* TPI DEVID Register Definitions */
1457 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1458 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1459
1460 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1461 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1462
1463 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1464 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1465
1466 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1467 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1468
1469 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1470 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1471
1472 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1473 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1474
1475 /* TPI DEVTYPE Register Definitions */
1476 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1477 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1478
1479 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1480 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1481
1482 /*@}*/ /* end of group CMSIS_TPI */
1483
1484
1485 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1486 /**
1487 \ingroup CMSIS_core_register
1488 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1489 \brief Type definitions for the Memory Protection Unit (MPU)
1490 @{
1491 */
1492
1493 /**
1494 \brief Structure type to access the Memory Protection Unit (MPU).
1495 */
1496 typedef struct
1497 {
1498 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1499 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1500 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1501 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1502 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1503 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1504 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1505 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1506 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1507 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1508 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1509 uint32_t RESERVED0[1];
1510 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1511 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1512 } MPU_Type;
1513
1514 /* MPU Type Register Definitions */
1515 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1516 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1517
1518 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1519 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1520
1521 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1522 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1523
1524 /* MPU Control Register Definitions */
1525 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1526 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1527
1528 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1529 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1530
1531 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1532 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1533
1534 /* MPU Region Number Register Definitions */
1535 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1536 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1537
1538 /* MPU Region Base Address Register Definitions */
1539 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1540 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1541
1542 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1543 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1544
1545 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1546 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1547
1548 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1549 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1550
1551 /* MPU Region Limit Address Register Definitions */
1552 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1553 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1554
1555 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1556 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1557
1558 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1559 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1560
1561 /* MPU Memory Attribute Indirection Register 0 Definitions */
1562 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1563 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1564
1565 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1566 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1567
1568 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1569 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1570
1571 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1572 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1573
1574 /* MPU Memory Attribute Indirection Register 1 Definitions */
1575 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1576 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1577
1578 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1579 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1580
1581 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1582 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1583
1584 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1585 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1586
1587 /*@} end of group CMSIS_MPU */
1588 #endif
1589
1590
1591 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1592 /**
1593 \ingroup CMSIS_core_register
1594 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1595 \brief Type definitions for the Security Attribution Unit (SAU)
1596 @{
1597 */
1598
1599 /**
1600 \brief Structure type to access the Security Attribution Unit (SAU).
1601 */
1602 typedef struct
1603 {
1604 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1605 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1606 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1607 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1608 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1609 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1610 #else
1611 uint32_t RESERVED0[3];
1612 #endif
1613 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1614 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1615 } SAU_Type;
1616
1617 /* SAU Control Register Definitions */
1618 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1619 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1620
1621 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1622 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1623
1624 /* SAU Type Register Definitions */
1625 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1626 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1627
1628 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1629 /* SAU Region Number Register Definitions */
1630 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1631 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1632
1633 /* SAU Region Base Address Register Definitions */
1634 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1635 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1636
1637 /* SAU Region Limit Address Register Definitions */
1638 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1639 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1640
1641 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1642 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1643
1644 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1645 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1646
1647 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1648
1649 /* Secure Fault Status Register Definitions */
1650 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1651 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1652
1653 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1654 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1655
1656 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1657 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1658
1659 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1660 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1661
1662 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1663 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1664
1665 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1666 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1667
1668 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1669 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1670
1671 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1672 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1673
1674 /*@} end of group CMSIS_SAU */
1675 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1676
1677
1678 /**
1679 \ingroup CMSIS_core_register
1680 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1681 \brief Type definitions for the Floating Point Unit (FPU)
1682 @{
1683 */
1684
1685 /**
1686 \brief Structure type to access the Floating Point Unit (FPU).
1687 */
1688 typedef struct
1689 {
1690 uint32_t RESERVED0[1U];
1691 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1692 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1693 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1694 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1695 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1696 } FPU_Type;
1697
1698 /* Floating-Point Context Control Register Definitions */
1699 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1700 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1701
1702 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1703 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1704
1705 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1706 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1707
1708 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1709 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1710
1711 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1712 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1713
1714 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1715 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1716
1717 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1718 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1719
1720 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1721 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1722
1723 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1724 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1725
1726 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1727 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1728
1729 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1730 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1731
1732 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1733 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1734
1735 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1736 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1737
1738 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1739 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1740
1741 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1742 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1743
1744 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1745 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1746
1747 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1748 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1749
1750 /* Floating-Point Context Address Register Definitions */
1751 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1752 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1753
1754 /* Floating-Point Default Status Control Register Definitions */
1755 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1756 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1757
1758 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1759 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1760
1761 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1762 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1763
1764 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1765 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1766
1767 /* Media and FP Feature Register 0 Definitions */
1768 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1769 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1770
1771 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1772 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1773
1774 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1775 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1776
1777 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1778 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1779
1780 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1781 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1782
1783 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1784 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1785
1786 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1787 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1788
1789 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1790 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1791
1792 /* Media and FP Feature Register 1 Definitions */
1793 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1794 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1795
1796 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1797 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1798
1799 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1800 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1801
1802 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1803 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1804
1805 /*@} end of group CMSIS_FPU */
1806
1807
1808 /**
1809 \ingroup CMSIS_core_register
1810 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1811 \brief Type definitions for the Core Debug Registers
1812 @{
1813 */
1814
1815 /**
1816 \brief Structure type to access the Core Debug Register (CoreDebug).
1817 */
1818 typedef struct
1819 {
1820 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1821 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1822 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1823 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1824 uint32_t RESERVED4[1U];
1825 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1826 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1827 } CoreDebug_Type;
1828
1829 /* Debug Halting Control and Status Register Definitions */
1830 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1831 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1832
1833 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1834 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1835
1836 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1837 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1838
1839 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1840 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1841
1842 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1843 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1844
1845 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1846 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1847
1848 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1849 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1850
1851 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1852 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1853
1854 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1855 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1856
1857 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1858 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1859
1860 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1861 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1862
1863 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1864 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1865
1866 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1867 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1868
1869 /* Debug Core Register Selector Register Definitions */
1870 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1871 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1872
1873 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1874 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1875
1876 /* Debug Exception and Monitor Control Register Definitions */
1877 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1878 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1879
1880 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1881 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1882
1883 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1884 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1885
1886 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1887 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1888
1889 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1890 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1891
1892 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1893 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1894
1895 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1896 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1897
1898 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1899 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1900
1901 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1902 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1903
1904 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1905 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1906
1907 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1908 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1909
1910 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1911 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1912
1913 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1914 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1915
1916 /* Debug Authentication Control Register Definitions */
1917 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1918 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1919
1920 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1921 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1922
1923 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1924 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1925
1926 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1927 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1928
1929 /* Debug Security Control and Status Register Definitions */
1930 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1931 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1932
1933 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1934 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1935
1936 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1937 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1938
1939 /*@} end of group CMSIS_CoreDebug */
1940
1941
1942 /**
1943 \ingroup CMSIS_core_register
1944 \defgroup CMSIS_core_bitfield Core register bit field macros
1945 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1946 @{
1947 */
1948
1949 /**
1950 \brief Mask and shift a bit field value for use in a register bit range.
1951 \param[in] field Name of the register bit field.
1952 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1953 \return Masked and shifted value.
1954 */
1955 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1956
1957 /**
1958 \brief Mask and shift a register value to extract a bit filed value.
1959 \param[in] field Name of the register bit field.
1960 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1961 \return Masked and shifted bit field value.
1962 */
1963 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1964
1965 /*@} end of group CMSIS_core_bitfield */
1966
1967
1968 /**
1969 \ingroup CMSIS_core_register
1970 \defgroup CMSIS_core_base Core Definitions
1971 \brief Definitions for base addresses, unions, and structures.
1972 @{
1973 */
1974
1975 /* Memory mapping of Core Hardware */
1976 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1977 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1978 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1979 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1980 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1981 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1982 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1983 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1984
1985 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1986 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1987 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1988 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1989 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1990 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1991 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1992 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
1993
1994 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1995 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1996 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1997 #endif
1998
1999 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2000 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2001 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2002 #endif
2003
2004 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2005 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2006
2007 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2008 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2009 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
2010 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2011 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2012 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2013
2014 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2015 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2016 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2017 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2018 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
2019
2020 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2021 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2022 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2023 #endif
2024
2025 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2026 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2027
2028 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2029 /*@} */
2030
2031
2032
2033 /*******************************************************************************
2034 * Hardware Abstraction Layer
2035 Core Function Interface contains:
2036 - Core NVIC Functions
2037 - Core SysTick Functions
2038 - Core Debug Functions
2039 - Core Register Access Functions
2040 ******************************************************************************/
2041 /**
2042 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2043 */
2044
2045
2046
2047 /* ########################## NVIC functions #################################### */
2048 /**
2049 \ingroup CMSIS_Core_FunctionInterface
2050 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2051 \brief Functions that manage interrupts and exceptions via the NVIC.
2052 @{
2053 */
2054
2055 #ifdef CMSIS_NVIC_VIRTUAL
2056 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2057 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2058 #endif
2059 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2060 #else
2061 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2062 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2063 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2064 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2065 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2066 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2067 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2068 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2069 #define NVIC_GetActive __NVIC_GetActive
2070 #define NVIC_SetPriority __NVIC_SetPriority
2071 #define NVIC_GetPriority __NVIC_GetPriority
2072 #define NVIC_SystemReset __NVIC_SystemReset
2073 #endif /* CMSIS_NVIC_VIRTUAL */
2074
2075 #ifdef CMSIS_VECTAB_VIRTUAL
2076 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2077 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2078 #endif
2079 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2080 #else
2081 #define NVIC_SetVector __NVIC_SetVector
2082 #define NVIC_GetVector __NVIC_GetVector
2083 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2084
2085 #define NVIC_USER_IRQ_OFFSET 16
2086
2087
2088
2089 /**
2090 \brief Set Priority Grouping
2091 \details Sets the priority grouping field using the required unlock sequence.
2092 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2093 Only values from 0..7 are used.
2094 In case of a conflict between priority grouping and available
2095 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2096 \param [in] PriorityGroup Priority grouping field.
2097 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2098 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2099 {
2100 uint32_t reg_value;
2101 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2102
2103 reg_value = SCB->AIRCR; /* read old register configuration */
2104 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2105 reg_value = (reg_value |
2106 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2107 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2108 SCB->AIRCR = reg_value;
2109 }
2110
2111
2112 /**
2113 \brief Get Priority Grouping
2114 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2115 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2116 */
__NVIC_GetPriorityGrouping(void)2117 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2118 {
2119 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2120 }
2121
2122
2123 /**
2124 \brief Enable Interrupt
2125 \details Enables a device specific interrupt in the NVIC interrupt controller.
2126 \param [in] IRQn Device specific interrupt number.
2127 \note IRQn must not be negative.
2128 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2129 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2130 {
2131 if ((int32_t)(IRQn) >= 0)
2132 {
2133 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2134 }
2135 }
2136
2137
2138 /**
2139 \brief Get Interrupt Enable status
2140 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2141 \param [in] IRQn Device specific interrupt number.
2142 \return 0 Interrupt is not enabled.
2143 \return 1 Interrupt is enabled.
2144 \note IRQn must not be negative.
2145 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2146 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2147 {
2148 if ((int32_t)(IRQn) >= 0)
2149 {
2150 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2151 }
2152 else
2153 {
2154 return(0U);
2155 }
2156 }
2157
2158
2159 /**
2160 \brief Disable Interrupt
2161 \details Disables a device specific interrupt in the NVIC interrupt controller.
2162 \param [in] IRQn Device specific interrupt number.
2163 \note IRQn must not be negative.
2164 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2165 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2166 {
2167 if ((int32_t)(IRQn) >= 0)
2168 {
2169 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2170 __DSB();
2171 __ISB();
2172 }
2173 }
2174
2175
2176 /**
2177 \brief Get Pending Interrupt
2178 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2179 \param [in] IRQn Device specific interrupt number.
2180 \return 0 Interrupt status is not pending.
2181 \return 1 Interrupt status is pending.
2182 \note IRQn must not be negative.
2183 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2184 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2185 {
2186 if ((int32_t)(IRQn) >= 0)
2187 {
2188 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2189 }
2190 else
2191 {
2192 return(0U);
2193 }
2194 }
2195
2196
2197 /**
2198 \brief Set Pending Interrupt
2199 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2200 \param [in] IRQn Device specific interrupt number.
2201 \note IRQn must not be negative.
2202 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2203 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2204 {
2205 if ((int32_t)(IRQn) >= 0)
2206 {
2207 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2208 }
2209 }
2210
2211
2212 /**
2213 \brief Clear Pending Interrupt
2214 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2215 \param [in] IRQn Device specific interrupt number.
2216 \note IRQn must not be negative.
2217 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2218 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2219 {
2220 if ((int32_t)(IRQn) >= 0)
2221 {
2222 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2223 }
2224 }
2225
2226
2227 /**
2228 \brief Get Active Interrupt
2229 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2230 \param [in] IRQn Device specific interrupt number.
2231 \return 0 Interrupt status is not active.
2232 \return 1 Interrupt status is active.
2233 \note IRQn must not be negative.
2234 */
__NVIC_GetActive(IRQn_Type IRQn)2235 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2236 {
2237 if ((int32_t)(IRQn) >= 0)
2238 {
2239 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2240 }
2241 else
2242 {
2243 return(0U);
2244 }
2245 }
2246
2247
2248 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2249 /**
2250 \brief Get Interrupt Target State
2251 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2252 \param [in] IRQn Device specific interrupt number.
2253 \return 0 if interrupt is assigned to Secure
2254 \return 1 if interrupt is assigned to Non Secure
2255 \note IRQn must not be negative.
2256 */
NVIC_GetTargetState(IRQn_Type IRQn)2257 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2258 {
2259 if ((int32_t)(IRQn) >= 0)
2260 {
2261 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2262 }
2263 else
2264 {
2265 return(0U);
2266 }
2267 }
2268
2269
2270 /**
2271 \brief Set Interrupt Target State
2272 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2273 \param [in] IRQn Device specific interrupt number.
2274 \return 0 if interrupt is assigned to Secure
2275 1 if interrupt is assigned to Non Secure
2276 \note IRQn must not be negative.
2277 */
NVIC_SetTargetState(IRQn_Type IRQn)2278 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2279 {
2280 if ((int32_t)(IRQn) >= 0)
2281 {
2282 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
2283 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2284 }
2285 else
2286 {
2287 return(0U);
2288 }
2289 }
2290
2291
2292 /**
2293 \brief Clear Interrupt Target State
2294 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2295 \param [in] IRQn Device specific interrupt number.
2296 \return 0 if interrupt is assigned to Secure
2297 1 if interrupt is assigned to Non Secure
2298 \note IRQn must not be negative.
2299 */
NVIC_ClearTargetState(IRQn_Type IRQn)2300 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2301 {
2302 if ((int32_t)(IRQn) >= 0)
2303 {
2304 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
2305 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2306 }
2307 else
2308 {
2309 return(0U);
2310 }
2311 }
2312 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2313
2314
2315 /**
2316 \brief Set Interrupt Priority
2317 \details Sets the priority of a device specific interrupt or a processor exception.
2318 The interrupt number can be positive to specify a device specific interrupt,
2319 or negative to specify a processor exception.
2320 \param [in] IRQn Interrupt number.
2321 \param [in] priority Priority to set.
2322 \note The priority cannot be set for every processor exception.
2323 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2324 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2325 {
2326 if ((int32_t)(IRQn) >= 0)
2327 {
2328 NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2329 }
2330 else
2331 {
2332 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2333 }
2334 }
2335
2336
2337 /**
2338 \brief Get Interrupt Priority
2339 \details Reads the priority of a device specific interrupt or a processor exception.
2340 The interrupt number can be positive to specify a device specific interrupt,
2341 or negative to specify a processor exception.
2342 \param [in] IRQn Interrupt number.
2343 \return Interrupt Priority.
2344 Value is aligned automatically to the implemented priority bits of the microcontroller.
2345 */
__NVIC_GetPriority(IRQn_Type IRQn)2346 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2347 {
2348
2349 if ((int32_t)(IRQn) >= 0)
2350 {
2351 return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2352 }
2353 else
2354 {
2355 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2356 }
2357 }
2358
2359
2360 /**
2361 \brief Encode Priority
2362 \details Encodes the priority for an interrupt with the given priority group,
2363 preemptive priority value, and subpriority value.
2364 In case of a conflict between priority grouping and available
2365 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2366 \param [in] PriorityGroup Used priority group.
2367 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2368 \param [in] SubPriority Subpriority value (starting from 0).
2369 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2370 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2371 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2372 {
2373 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2374 uint32_t PreemptPriorityBits;
2375 uint32_t SubPriorityBits;
2376
2377 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2378 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2379
2380 return (
2381 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2382 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2383 );
2384 }
2385
2386
2387 /**
2388 \brief Decode Priority
2389 \details Decodes an interrupt priority value with a given priority group to
2390 preemptive priority value and subpriority value.
2391 In case of a conflict between priority grouping and available
2392 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2393 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2394 \param [in] PriorityGroup Used priority group.
2395 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2396 \param [out] pSubPriority Subpriority value (starting from 0).
2397 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2398 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2399 {
2400 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2401 uint32_t PreemptPriorityBits;
2402 uint32_t SubPriorityBits;
2403
2404 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2405 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2406
2407 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2408 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2409 }
2410
2411
2412 /**
2413 \brief Set Interrupt Vector
2414 \details Sets an interrupt vector in SRAM based interrupt vector table.
2415 The interrupt number can be positive to specify a device specific interrupt,
2416 or negative to specify a processor exception.
2417 VTOR must been relocated to SRAM before.
2418 \param [in] IRQn Interrupt number
2419 \param [in] vector Address of interrupt handler function
2420 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2421 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2422 {
2423 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2424 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2425 }
2426
2427
2428 /**
2429 \brief Get Interrupt Vector
2430 \details Reads an interrupt vector from interrupt vector table.
2431 The interrupt number can be positive to specify a device specific interrupt,
2432 or negative to specify a processor exception.
2433 \param [in] IRQn Interrupt number.
2434 \return Address of interrupt handler function
2435 */
__NVIC_GetVector(IRQn_Type IRQn)2436 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2437 {
2438 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2439 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2440 }
2441
2442
2443 /**
2444 \brief System Reset
2445 \details Initiates a system reset request to reset the MCU.
2446 */
__NVIC_SystemReset(void)2447 __STATIC_INLINE void __NVIC_SystemReset(void)
2448 {
2449 __DSB(); /* Ensure all outstanding memory accesses included
2450 buffered write are completed before reset */
2451 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2452 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2453 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2454 __DSB(); /* Ensure completion of memory access */
2455
2456 for(;;) /* wait until reset */
2457 {
2458 __NOP();
2459 }
2460 }
2461
2462 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2463 /**
2464 \brief Set Priority Grouping (non-secure)
2465 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2466 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2467 Only values from 0..7 are used.
2468 In case of a conflict between priority grouping and available
2469 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2470 \param [in] PriorityGroup Priority grouping field.
2471 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2472 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2473 {
2474 uint32_t reg_value;
2475 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2476
2477 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2478 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2479 reg_value = (reg_value |
2480 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2481 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
2482 SCB_NS->AIRCR = reg_value;
2483 }
2484
2485
2486 /**
2487 \brief Get Priority Grouping (non-secure)
2488 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2489 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2490 */
TZ_NVIC_GetPriorityGrouping_NS(void)2491 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2492 {
2493 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2494 }
2495
2496
2497 /**
2498 \brief Enable Interrupt (non-secure)
2499 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2500 \param [in] IRQn Device specific interrupt number.
2501 \note IRQn must not be negative.
2502 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2503 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2504 {
2505 if ((int32_t)(IRQn) >= 0)
2506 {
2507 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2508 }
2509 }
2510
2511
2512 /**
2513 \brief Get Interrupt Enable status (non-secure)
2514 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2515 \param [in] IRQn Device specific interrupt number.
2516 \return 0 Interrupt is not enabled.
2517 \return 1 Interrupt is enabled.
2518 \note IRQn must not be negative.
2519 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2520 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2521 {
2522 if ((int32_t)(IRQn) >= 0)
2523 {
2524 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2525 }
2526 else
2527 {
2528 return(0U);
2529 }
2530 }
2531
2532
2533 /**
2534 \brief Disable Interrupt (non-secure)
2535 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2536 \param [in] IRQn Device specific interrupt number.
2537 \note IRQn must not be negative.
2538 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2539 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2540 {
2541 if ((int32_t)(IRQn) >= 0)
2542 {
2543 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2544 }
2545 }
2546
2547
2548 /**
2549 \brief Get Pending Interrupt (non-secure)
2550 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2551 \param [in] IRQn Device specific interrupt number.
2552 \return 0 Interrupt status is not pending.
2553 \return 1 Interrupt status is pending.
2554 \note IRQn must not be negative.
2555 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2556 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2557 {
2558 if ((int32_t)(IRQn) >= 0)
2559 {
2560 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2561 }
2562 else
2563 {
2564 return(0U);
2565 }
2566 }
2567
2568
2569 /**
2570 \brief Set Pending Interrupt (non-secure)
2571 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2572 \param [in] IRQn Device specific interrupt number.
2573 \note IRQn must not be negative.
2574 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2575 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2576 {
2577 if ((int32_t)(IRQn) >= 0)
2578 {
2579 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2580 }
2581 }
2582
2583
2584 /**
2585 \brief Clear Pending Interrupt (non-secure)
2586 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2587 \param [in] IRQn Device specific interrupt number.
2588 \note IRQn must not be negative.
2589 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2590 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2591 {
2592 if ((int32_t)(IRQn) >= 0)
2593 {
2594 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
2595 }
2596 }
2597
2598
2599 /**
2600 \brief Get Active Interrupt (non-secure)
2601 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2602 \param [in] IRQn Device specific interrupt number.
2603 \return 0 Interrupt status is not active.
2604 \return 1 Interrupt status is active.
2605 \note IRQn must not be negative.
2606 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2607 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2608 {
2609 if ((int32_t)(IRQn) >= 0)
2610 {
2611 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2612 }
2613 else
2614 {
2615 return(0U);
2616 }
2617 }
2618
2619
2620 /**
2621 \brief Set Interrupt Priority (non-secure)
2622 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2623 The interrupt number can be positive to specify a device specific interrupt,
2624 or negative to specify a processor exception.
2625 \param [in] IRQn Interrupt number.
2626 \param [in] priority Priority to set.
2627 \note The priority cannot be set for every non-secure processor exception.
2628 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2629 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2630 {
2631 if ((int32_t)(IRQn) >= 0)
2632 {
2633 NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2634 }
2635 else
2636 {
2637 SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2638 }
2639 }
2640
2641
2642 /**
2643 \brief Get Interrupt Priority (non-secure)
2644 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2645 The interrupt number can be positive to specify a device specific interrupt,
2646 or negative to specify a processor exception.
2647 \param [in] IRQn Interrupt number.
2648 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2649 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2650 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2651 {
2652
2653 if ((int32_t)(IRQn) >= 0)
2654 {
2655 return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2656 }
2657 else
2658 {
2659 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2660 }
2661 }
2662 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2663
2664 /*@} end of CMSIS_Core_NVICFunctions */
2665
2666
2667 /* ########################## FPU functions #################################### */
2668 /**
2669 \ingroup CMSIS_Core_FunctionInterface
2670 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2671 \brief Function that provides FPU type.
2672 @{
2673 */
2674
2675 /**
2676 \brief get FPU type
2677 \details returns the FPU type
2678 \returns
2679 - \b 0: No FPU
2680 - \b 1: Single precision FPU
2681 - \b 2: Double + Single precision FPU
2682 */
SCB_GetFPUType(void)2683 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2684 {
2685 uint32_t mvfr0;
2686
2687 mvfr0 = FPU->MVFR0;
2688 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2689 {
2690 return 2U; /* Double + Single precision FPU */
2691 }
2692 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2693 {
2694 return 1U; /* Single precision FPU */
2695 }
2696 else
2697 {
2698 return 0U; /* No FPU */
2699 }
2700 }
2701
2702
2703 /*@} end of CMSIS_Core_FpuFunctions */
2704
2705
2706
2707 /* ########################## SAU functions #################################### */
2708 /**
2709 \ingroup CMSIS_Core_FunctionInterface
2710 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2711 \brief Functions that configure the SAU.
2712 @{
2713 */
2714
2715 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2716
2717 /**
2718 \brief Enable SAU
2719 \details Enables the Security Attribution Unit (SAU).
2720 */
TZ_SAU_Enable(void)2721 __STATIC_INLINE void TZ_SAU_Enable(void)
2722 {
2723 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2724 }
2725
2726
2727
2728 /**
2729 \brief Disable SAU
2730 \details Disables the Security Attribution Unit (SAU).
2731 */
TZ_SAU_Disable(void)2732 __STATIC_INLINE void TZ_SAU_Disable(void)
2733 {
2734 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2735 }
2736
2737 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2738
2739 /*@} end of CMSIS_Core_SAUFunctions */
2740
2741
2742
2743
2744 /* ################################## SysTick function ############################################ */
2745 /**
2746 \ingroup CMSIS_Core_FunctionInterface
2747 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2748 \brief Functions that configure the System.
2749 @{
2750 */
2751
2752 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2753
2754 /**
2755 \brief System Tick Configuration
2756 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2757 Counter is in free running mode to generate periodic interrupts.
2758 \param [in] ticks Number of ticks between two interrupts.
2759 \return 0 Function succeeded.
2760 \return 1 Function failed.
2761 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2762 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2763 must contain a vendor-specific implementation of this function.
2764 */
SysTick_Config(uint32_t ticks)2765 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2766 {
2767 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2768 {
2769 return (1UL); /* Reload value impossible */
2770 }
2771
2772 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2773 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2774 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2775 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2776 SysTick_CTRL_TICKINT_Msk |
2777 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2778 return (0UL); /* Function successful */
2779 }
2780
2781 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2782 /**
2783 \brief System Tick Configuration (non-secure)
2784 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2785 Counter is in free running mode to generate periodic interrupts.
2786 \param [in] ticks Number of ticks between two interrupts.
2787 \return 0 Function succeeded.
2788 \return 1 Function failed.
2789 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2790 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2791 must contain a vendor-specific implementation of this function.
2792
2793 */
TZ_SysTick_Config_NS(uint32_t ticks)2794 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2795 {
2796 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2797 {
2798 return (1UL); /* Reload value impossible */
2799 }
2800
2801 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2802 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2803 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2804 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2805 SysTick_CTRL_TICKINT_Msk |
2806 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2807 return (0UL); /* Function successful */
2808 }
2809 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2810
2811 #endif
2812
2813 /*@} end of CMSIS_Core_SysTickFunctions */
2814
2815
2816
2817 /* ##################################### Debug In/Output function ########################################### */
2818 /**
2819 \ingroup CMSIS_Core_FunctionInterface
2820 \defgroup CMSIS_core_DebugFunctions ITM Functions
2821 \brief Functions that access the ITM debug interface.
2822 @{
2823 */
2824
2825 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2826 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2827
2828
2829 /**
2830 \brief ITM Send Character
2831 \details Transmits a character via the ITM channel 0, and
2832 \li Just returns when no debugger is connected that has booked the output.
2833 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2834 \param [in] ch Character to transmit.
2835 \returns Character to transmit.
2836 */
ITM_SendChar(uint32_t ch)2837 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2838 {
2839 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2840 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2841 {
2842 while (ITM->PORT[0U].u32 == 0UL)
2843 {
2844 __NOP();
2845 }
2846 ITM->PORT[0U].u8 = (uint8_t)ch;
2847 }
2848 return (ch);
2849 }
2850
2851
2852 /**
2853 \brief ITM Receive Character
2854 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2855 \return Received character.
2856 \return -1 No character pending.
2857 */
ITM_ReceiveChar(void)2858 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2859 {
2860 int32_t ch = -1; /* no character available */
2861
2862 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2863 {
2864 ch = ITM_RxBuffer;
2865 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2866 }
2867
2868 return (ch);
2869 }
2870
2871
2872 /**
2873 \brief ITM Check Character
2874 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2875 \return 0 No character available.
2876 \return 1 Character available.
2877 */
ITM_CheckChar(void)2878 __STATIC_INLINE int32_t ITM_CheckChar (void)
2879 {
2880
2881 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2882 {
2883 return (0); /* no character available */
2884 }
2885 else
2886 {
2887 return (1); /* character available */
2888 }
2889 }
2890
2891 /*@} end of CMSIS_core_DebugFunctions */
2892
2893
2894
2895
2896 #ifdef __cplusplus
2897 }
2898 #endif
2899
2900 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
2901
2902 #endif /* __CMSIS_GENERIC */
2903