1 /**************************************************************************//**
2 * @file cmsis_gcc.h
3 * @brief CMSIS compiler GCC header file
4 * @version V5.0.2
5 * @date 13. February 2017
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_GCC_H
26 #define __CMSIS_GCC_H
27
28 /* ignore some GCC warnings */
29 #pragma GCC diagnostic push
30 #pragma GCC diagnostic ignored "-Wsign-conversion"
31 #pragma GCC diagnostic ignored "-Wconversion"
32 #pragma GCC diagnostic ignored "-Wunused-parameter"
33
34 /* Fallback for __has_builtin */
35 #ifndef __has_builtin
36 #define __has_builtin(x) (0)
37 #endif
38
39 /* CMSIS compiler specific defines */
40 #ifndef __ASM
41 #define __ASM __asm
42 #endif
43 #ifndef __INLINE
44 #define __INLINE inline
45 #endif
46 #ifndef __STATIC_INLINE
47 #define __STATIC_INLINE static inline
48 #endif
49 #ifndef __NO_RETURN
50 #define __NO_RETURN __attribute__((noreturn))
51 #endif
52 #ifndef __USED
53 #define __USED __attribute__((used))
54 #endif
55 #ifndef __WEAK
56 #define __WEAK __attribute__((weak))
57 #endif
58 #ifndef __PACKED
59 #define __PACKED __attribute__((packed, aligned(1)))
60 #endif
61 #ifndef __PACKED_STRUCT
62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
63 #endif
64 #ifndef __PACKED_UNION
65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
66 #endif
67 #ifndef __UNALIGNED_UINT32 /* deprecated */
68 #pragma GCC diagnostic push
69 #pragma GCC diagnostic ignored "-Wpacked"
70 #pragma GCC diagnostic ignored "-Wattributes"
71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
72 #pragma GCC diagnostic pop
73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
74 #endif
75 #ifndef __UNALIGNED_UINT16_WRITE
76 #pragma GCC diagnostic push
77 #pragma GCC diagnostic ignored "-Wpacked"
78 #pragma GCC diagnostic ignored "-Wattributes"
79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
80 #pragma GCC diagnostic pop
81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
82 #endif
83 #ifndef __UNALIGNED_UINT16_READ
84 #pragma GCC diagnostic push
85 #pragma GCC diagnostic ignored "-Wpacked"
86 #pragma GCC diagnostic ignored "-Wattributes"
87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
88 #pragma GCC diagnostic pop
89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
90 #endif
91 #ifndef __UNALIGNED_UINT32_WRITE
92 #pragma GCC diagnostic push
93 #pragma GCC diagnostic ignored "-Wpacked"
94 #pragma GCC diagnostic ignored "-Wattributes"
95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
96 #pragma GCC diagnostic pop
97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
98 #endif
99 #ifndef __UNALIGNED_UINT32_READ
100 #pragma GCC diagnostic push
101 #pragma GCC diagnostic ignored "-Wpacked"
102 #pragma GCC diagnostic ignored "-Wattributes"
103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
104 #pragma GCC diagnostic pop
105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
106 #endif
107 #ifndef __ALIGNED
108 #define __ALIGNED(x) __attribute__((aligned(x)))
109 #endif
110 #ifndef __RESTRICT
111 #define __RESTRICT __restrict
112 #endif
113
114
115 /* ########################### Core Function Access ########################### */
116 /** \ingroup CMSIS_Core_FunctionInterface
117 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
118 @{
119 */
120
121 /**
122 \brief Enable IRQ Interrupts
123 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
124 Can only be executed in Privileged modes.
125 */
__enable_irq(void)126 __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
127 {
128 __ASM volatile ("cpsie i" : : : "memory");
129 }
130
131
132 /**
133 \brief Disable IRQ Interrupts
134 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
135 Can only be executed in Privileged modes.
136 */
__disable_irq(void)137 __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
138 {
139 __ASM volatile ("cpsid i" : : : "memory");
140 }
141
142
143 /**
144 \brief Get Control Register
145 \details Returns the content of the Control Register.
146 \return Control Register value
147 */
__get_CONTROL(void)148 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
149 {
150 uint32_t result;
151
152 __ASM volatile ("MRS %0, control" : "=r" (result) );
153 return(result);
154 }
155
156
157 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
158 /**
159 \brief Get Control Register (non-secure)
160 \details Returns the content of the non-secure Control Register when in secure mode.
161 \return non-secure Control Register value
162 */
__TZ_get_CONTROL_NS(void)163 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
164 {
165 uint32_t result;
166
167 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
168 return(result);
169 }
170 #endif
171
172
173 /**
174 \brief Set Control Register
175 \details Writes the given value to the Control Register.
176 \param [in] control Control Register value to set
177 */
__set_CONTROL(uint32_t control)178 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
179 {
180 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
181 }
182
183
184 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
185 /**
186 \brief Set Control Register (non-secure)
187 \details Writes the given value to the non-secure Control Register when in secure state.
188 \param [in] control Control Register value to set
189 */
__TZ_set_CONTROL_NS(uint32_t control)190 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
191 {
192 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
193 }
194 #endif
195
196
197 /**
198 \brief Get IPSR Register
199 \details Returns the content of the IPSR Register.
200 \return IPSR Register value
201 */
__get_IPSR(void)202 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
203 {
204 uint32_t result;
205
206 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
207 return(result);
208 }
209
210
211 /**
212 \brief Get APSR Register
213 \details Returns the content of the APSR Register.
214 \return APSR Register value
215 */
__get_APSR(void)216 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
217 {
218 uint32_t result;
219
220 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
221 return(result);
222 }
223
224
225 /**
226 \brief Get xPSR Register
227 \details Returns the content of the xPSR Register.
228 \return xPSR Register value
229 */
__get_xPSR(void)230 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
231 {
232 uint32_t result;
233
234 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
235 return(result);
236 }
237
238
239 /**
240 \brief Get Process Stack Pointer
241 \details Returns the current value of the Process Stack Pointer (PSP).
242 \return PSP Register value
243 */
__get_PSP(void)244 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
245 {
246 register uint32_t result;
247
248 __ASM volatile ("MRS %0, psp" : "=r" (result) );
249 return(result);
250 }
251
252
253 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
254 /**
255 \brief Get Process Stack Pointer (non-secure)
256 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
257 \return PSP Register value
258 */
__TZ_get_PSP_NS(void)259 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
260 {
261 register uint32_t result;
262
263 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
264 return(result);
265 }
266 #endif
267
268
269 /**
270 \brief Set Process Stack Pointer
271 \details Assigns the given value to the Process Stack Pointer (PSP).
272 \param [in] topOfProcStack Process Stack Pointer value to set
273 */
__set_PSP(uint32_t topOfProcStack)274 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
275 {
276 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
277 }
278
279
280 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
281 /**
282 \brief Set Process Stack Pointer (non-secure)
283 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
284 \param [in] topOfProcStack Process Stack Pointer value to set
285 */
__TZ_set_PSP_NS(uint32_t topOfProcStack)286 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
287 {
288 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
289 }
290 #endif
291
292
293 /**
294 \brief Get Main Stack Pointer
295 \details Returns the current value of the Main Stack Pointer (MSP).
296 \return MSP Register value
297 */
__get_MSP(void)298 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
299 {
300 register uint32_t result;
301
302 __ASM volatile ("MRS %0, msp" : "=r" (result) );
303 return(result);
304 }
305
306
307 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
308 /**
309 \brief Get Main Stack Pointer (non-secure)
310 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
311 \return MSP Register value
312 */
__TZ_get_MSP_NS(void)313 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
314 {
315 register uint32_t result;
316
317 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
318 return(result);
319 }
320 #endif
321
322
323 /**
324 \brief Set Main Stack Pointer
325 \details Assigns the given value to the Main Stack Pointer (MSP).
326 \param [in] topOfMainStack Main Stack Pointer value to set
327 */
__set_MSP(uint32_t topOfMainStack)328 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
329 {
330 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
331 }
332
333
334 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
335 /**
336 \brief Set Main Stack Pointer (non-secure)
337 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
338 \param [in] topOfMainStack Main Stack Pointer value to set
339 */
__TZ_set_MSP_NS(uint32_t topOfMainStack)340 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
341 {
342 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
343 }
344 #endif
345
346
347 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
348 /**
349 \brief Get Stack Pointer (non-secure)
350 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
351 \return SP Register value
352 */
__TZ_get_SP_NS(void)353 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
354 {
355 register uint32_t result;
356
357 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
358 return(result);
359 }
360
361
362 /**
363 \brief Set Stack Pointer (non-secure)
364 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
365 \param [in] topOfStack Stack Pointer value to set
366 */
__TZ_set_SP_NS(uint32_t topOfStack)367 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
368 {
369 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
370 }
371 #endif
372
373
374 /**
375 \brief Get Priority Mask
376 \details Returns the current state of the priority mask bit from the Priority Mask Register.
377 \return Priority Mask value
378 */
__get_PRIMASK(void)379 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
380 {
381 uint32_t result;
382
383 __ASM volatile ("MRS %0, primask" : "=r" (result) );
384 return(result);
385 }
386
387
388 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
389 /**
390 \brief Get Priority Mask (non-secure)
391 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
392 \return Priority Mask value
393 */
__TZ_get_PRIMASK_NS(void)394 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
395 {
396 uint32_t result;
397
398 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
399 return(result);
400 }
401 #endif
402
403
404 /**
405 \brief Set Priority Mask
406 \details Assigns the given value to the Priority Mask Register.
407 \param [in] priMask Priority Mask
408 */
__set_PRIMASK(uint32_t priMask)409 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
410 {
411 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
412 }
413
414
415 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
416 /**
417 \brief Set Priority Mask (non-secure)
418 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
419 \param [in] priMask Priority Mask
420 */
__TZ_set_PRIMASK_NS(uint32_t priMask)421 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
422 {
423 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
424 }
425 #endif
426
427
428 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
429 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
430 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
431 /**
432 \brief Enable FIQ
433 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
434 Can only be executed in Privileged modes.
435 */
__enable_fault_irq(void)436 __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
437 {
438 __ASM volatile ("cpsie f" : : : "memory");
439 }
440
441
442 /**
443 \brief Disable FIQ
444 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
445 Can only be executed in Privileged modes.
446 */
__disable_fault_irq(void)447 __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
448 {
449 __ASM volatile ("cpsid f" : : : "memory");
450 }
451
452
453 /**
454 \brief Get Base Priority
455 \details Returns the current value of the Base Priority register.
456 \return Base Priority register value
457 */
__get_BASEPRI(void)458 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
459 {
460 uint32_t result;
461
462 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
463 return(result);
464 }
465
466
467 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
468 /**
469 \brief Get Base Priority (non-secure)
470 \details Returns the current value of the non-secure Base Priority register when in secure state.
471 \return Base Priority register value
472 */
__TZ_get_BASEPRI_NS(void)473 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
474 {
475 uint32_t result;
476
477 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
478 return(result);
479 }
480 #endif
481
482
483 /**
484 \brief Set Base Priority
485 \details Assigns the given value to the Base Priority register.
486 \param [in] basePri Base Priority value to set
487 */
__set_BASEPRI(uint32_t basePri)488 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
489 {
490 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
491 }
492
493
494 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
495 /**
496 \brief Set Base Priority (non-secure)
497 \details Assigns the given value to the non-secure Base Priority register when in secure state.
498 \param [in] basePri Base Priority value to set
499 */
__TZ_set_BASEPRI_NS(uint32_t basePri)500 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
501 {
502 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
503 }
504 #endif
505
506
507 /**
508 \brief Set Base Priority with condition
509 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
510 or the new value increases the BASEPRI priority level.
511 \param [in] basePri Base Priority value to set
512 */
__set_BASEPRI_MAX(uint32_t basePri)513 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
514 {
515 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
516 }
517
518
519 /**
520 \brief Get Fault Mask
521 \details Returns the current value of the Fault Mask register.
522 \return Fault Mask register value
523 */
__get_FAULTMASK(void)524 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
525 {
526 uint32_t result;
527
528 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
529 return(result);
530 }
531
532
533 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
534 /**
535 \brief Get Fault Mask (non-secure)
536 \details Returns the current value of the non-secure Fault Mask register when in secure state.
537 \return Fault Mask register value
538 */
__TZ_get_FAULTMASK_NS(void)539 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
540 {
541 uint32_t result;
542
543 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
544 return(result);
545 }
546 #endif
547
548
549 /**
550 \brief Set Fault Mask
551 \details Assigns the given value to the Fault Mask register.
552 \param [in] faultMask Fault Mask value to set
553 */
__set_FAULTMASK(uint32_t faultMask)554 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
555 {
556 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
557 }
558
559
560 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
561 /**
562 \brief Set Fault Mask (non-secure)
563 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
564 \param [in] faultMask Fault Mask value to set
565 */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)566 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
567 {
568 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
569 }
570 #endif
571
572 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
573 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
574 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
575
576
577 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
578 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
579
580 /**
581 \brief Get Process Stack Pointer Limit
582 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
583 \return PSPLIM Register value
584 */
__get_PSPLIM(void)585 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
586 {
587 register uint32_t result;
588
589 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
590 return(result);
591 }
592
593
594 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
595 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
596 /**
597 \brief Get Process Stack Pointer Limit (non-secure)
598 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
599 \return PSPLIM Register value
600 */
__TZ_get_PSPLIM_NS(void)601 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
602 {
603 register uint32_t result;
604
605 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
606 return(result);
607 }
608 #endif
609
610
611 /**
612 \brief Set Process Stack Pointer Limit
613 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
614 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
615 */
__set_PSPLIM(uint32_t ProcStackPtrLimit)616 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
617 {
618 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
619 }
620
621
622 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
623 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
624 /**
625 \brief Set Process Stack Pointer (non-secure)
626 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
627 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
628 */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)629 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
630 {
631 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
632 }
633 #endif
634
635
636 /**
637 \brief Get Main Stack Pointer Limit
638 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
639 \return MSPLIM Register value
640 */
__get_MSPLIM(void)641 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
642 {
643 register uint32_t result;
644
645 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
646
647 return(result);
648 }
649
650
651 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
652 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
653 /**
654 \brief Get Main Stack Pointer Limit (non-secure)
655 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
656 \return MSPLIM Register value
657 */
__TZ_get_MSPLIM_NS(void)658 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
659 {
660 register uint32_t result;
661
662 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
663 return(result);
664 }
665 #endif
666
667
668 /**
669 \brief Set Main Stack Pointer Limit
670 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
671 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
672 */
__set_MSPLIM(uint32_t MainStackPtrLimit)673 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
674 {
675 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
676 }
677
678
679 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
680 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
681 /**
682 \brief Set Main Stack Pointer Limit (non-secure)
683 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
684 \param [in] MainStackPtrLimit Main Stack Pointer value to set
685 */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)686 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
687 {
688 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
689 }
690 #endif
691
692 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
693 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
694
695
696 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
697 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
698
699 /**
700 \brief Get FPSCR
701 \details Returns the current value of the Floating Point Status/Control register.
702 \return Floating Point Status/Control register value
703 */
__get_FPSCR(void)704 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
705 {
706 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
707 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
708 #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
709 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
710 return __builtin_arm_get_fpscr();
711 #else
712 uint32_t result;
713
714 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
715 return(result);
716 #endif
717 #else
718 return(0U);
719 #endif
720 }
721
722
723 /**
724 \brief Set FPSCR
725 \details Assigns the given value to the Floating Point Status/Control register.
726 \param [in] fpscr Floating Point Status/Control value to set
727 */
__set_FPSCR(uint32_t fpscr)728 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
729 {
730 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
731 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
732 #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
733 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
734 __builtin_arm_set_fpscr(fpscr);
735 #else
736 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
737 #endif
738 #else
739 (void)fpscr;
740 #endif
741 }
742
743 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
744 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
745
746
747
748 /*@} end of CMSIS_Core_RegAccFunctions */
749
750
751 /* ########################## Core Instruction Access ######################### */
752 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
753 Access to dedicated instructions
754 @{
755 */
756
757 /* Define macros for porting to both thumb1 and thumb2.
758 * For thumb1, use low register (r0-r7), specified by constraint "l"
759 * Otherwise, use general registers, specified by constraint "r" */
760 #if defined (__thumb__) && !defined (__thumb2__)
761 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
762 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
763 #define __CMSIS_GCC_USE_REG(r) "l" (r)
764 #else
765 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
766 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
767 #define __CMSIS_GCC_USE_REG(r) "r" (r)
768 #endif
769
770 /**
771 \brief No Operation
772 \details No Operation does nothing. This instruction can be used for code alignment purposes.
773 */
774 //__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
775 //{
776 // __ASM volatile ("nop");
777 //}
778 #define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
779
780 /**
781 \brief Wait For Interrupt
782 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
783 */
784 //__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
785 //{
786 // __ASM volatile ("wfi");
787 //}
788 #define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
789
790
791 /**
792 \brief Wait For Event
793 \details Wait For Event is a hint instruction that permits the processor to enter
794 a low-power state until one of a number of events occurs.
795 */
796 //__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
797 //{
798 // __ASM volatile ("wfe");
799 //}
800 #define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
801
802
803 /**
804 \brief Send Event
805 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
806 */
807 //__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
808 //{
809 // __ASM volatile ("sev");
810 //}
811 #define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
812
813
814 /**
815 \brief Instruction Synchronization Barrier
816 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
817 so that all instructions following the ISB are fetched from cache or memory,
818 after the instruction has been completed.
819 */
__ISB(void)820 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
821 {
822 __ASM volatile ("isb 0xF":::"memory");
823 }
824
825
826 /**
827 \brief Data Synchronization Barrier
828 \details Acts as a special kind of Data Memory Barrier.
829 It completes when all explicit memory accesses before this instruction complete.
830 */
__DSB(void)831 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
832 {
833 __ASM volatile ("dsb 0xF":::"memory");
834 }
835
836
837 /**
838 \brief Data Memory Barrier
839 \details Ensures the apparent order of the explicit memory operations before
840 and after the instruction, without ensuring their completion.
841 */
__DMB(void)842 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
843 {
844 __ASM volatile ("dmb 0xF":::"memory");
845 }
846
847
848 /**
849 \brief Reverse byte order (32 bit)
850 \details Reverses the byte order in integer value.
851 \param [in] value Value to reverse
852 \return Reversed value
853 */
__REV(uint32_t value)854 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
855 {
856 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
857 return __builtin_bswap32(value);
858 #else
859 uint32_t result;
860
861 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
862 return(result);
863 #endif
864 }
865
866
867 /**
868 \brief Reverse byte order (16 bit)
869 \details Reverses the byte order in two unsigned short values.
870 \param [in] value Value to reverse
871 \return Reversed value
872 */
__REV16(uint32_t value)873 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
874 {
875 uint32_t result;
876
877 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
878 return(result);
879 }
880
881
882 /**
883 \brief Reverse byte order in signed short value
884 \details Reverses the byte order in a signed short value with sign extension to integer.
885 \param [in] value Value to reverse
886 \return Reversed value
887 */
__REVSH(int32_t value)888 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
889 {
890 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
891 return (short)__builtin_bswap16(value);
892 #else
893 int32_t result;
894
895 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
896 return(result);
897 #endif
898 }
899
900
901 /**
902 \brief Rotate Right in unsigned value (32 bit)
903 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
904 \param [in] op1 Value to rotate
905 \param [in] op2 Number of Bits to rotate
906 \return Rotated value
907 */
__ROR(uint32_t op1,uint32_t op2)908 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
909 {
910 return (op1 >> op2) | (op1 << (32U - op2));
911 }
912
913
914 /**
915 \brief Breakpoint
916 \details Causes the processor to enter Debug state.
917 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
918 \param [in] value is ignored by the processor.
919 If required, a debugger can use it to store additional information about the breakpoint.
920 */
921 #define __BKPT(value) __ASM volatile ("bkpt "#value)
922
923
924 /**
925 \brief Reverse bit order of value
926 \details Reverses the bit order of the given value.
927 \param [in] value Value to reverse
928 \return Reversed value
929 */
__RBIT(uint32_t value)930 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
931 {
932 uint32_t result;
933
934 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
935 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
936 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
937 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
938 #else
939 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
940
941 result = value; /* r will be reversed bits of v; first get LSB of v */
942 for (value >>= 1U; value; value >>= 1U)
943 {
944 result <<= 1U;
945 result |= value & 1U;
946 s--;
947 }
948 result <<= s; /* shift when v's highest bits are zero */
949 #endif
950 return(result);
951 }
952
953
954 /**
955 \brief Count leading zeros
956 \details Counts the number of leading zeros of a data value.
957 \param [in] value Value to count the leading zeros
958 \return number of leading zeros in value
959 */
960 #define __CLZ __builtin_clz
961
962
963 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
964 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
965 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
966 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
967 /**
968 \brief LDR Exclusive (8 bit)
969 \details Executes a exclusive LDR instruction for 8 bit value.
970 \param [in] ptr Pointer to data
971 \return value of type uint8_t at (*ptr)
972 */
__LDREXB(volatile uint8_t * addr)973 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
974 {
975 uint32_t result;
976
977 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
978 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
979 #else
980 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
981 accepted by assembler. So has to use following less efficient pattern.
982 */
983 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
984 #endif
985 return ((uint8_t) result); /* Add explicit type cast here */
986 }
987
988
989 /**
990 \brief LDR Exclusive (16 bit)
991 \details Executes a exclusive LDR instruction for 16 bit values.
992 \param [in] ptr Pointer to data
993 \return value of type uint16_t at (*ptr)
994 */
__LDREXH(volatile uint16_t * addr)995 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
996 {
997 uint32_t result;
998
999 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1000 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
1001 #else
1002 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1003 accepted by assembler. So has to use following less efficient pattern.
1004 */
1005 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
1006 #endif
1007 return ((uint16_t) result); /* Add explicit type cast here */
1008 }
1009
1010
1011 /**
1012 \brief LDR Exclusive (32 bit)
1013 \details Executes a exclusive LDR instruction for 32 bit values.
1014 \param [in] ptr Pointer to data
1015 \return value of type uint32_t at (*ptr)
1016 */
__LDREXW(volatile uint32_t * addr)1017 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
1018 {
1019 uint32_t result;
1020
1021 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
1022 return(result);
1023 }
1024
1025
1026 /**
1027 \brief STR Exclusive (8 bit)
1028 \details Executes a exclusive STR instruction for 8 bit values.
1029 \param [in] value Value to store
1030 \param [in] ptr Pointer to location
1031 \return 0 Function succeeded
1032 \return 1 Function failed
1033 */
__STREXB(uint8_t value,volatile uint8_t * addr)1034 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
1035 {
1036 uint32_t result;
1037
1038 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
1039 return(result);
1040 }
1041
1042
1043 /**
1044 \brief STR Exclusive (16 bit)
1045 \details Executes a exclusive STR instruction for 16 bit values.
1046 \param [in] value Value to store
1047 \param [in] ptr Pointer to location
1048 \return 0 Function succeeded
1049 \return 1 Function failed
1050 */
__STREXH(uint16_t value,volatile uint16_t * addr)1051 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
1052 {
1053 uint32_t result;
1054
1055 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
1056 return(result);
1057 }
1058
1059
1060 /**
1061 \brief STR Exclusive (32 bit)
1062 \details Executes a exclusive STR instruction for 32 bit values.
1063 \param [in] value Value to store
1064 \param [in] ptr Pointer to location
1065 \return 0 Function succeeded
1066 \return 1 Function failed
1067 */
__STREXW(uint32_t value,volatile uint32_t * addr)1068 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
1069 {
1070 uint32_t result;
1071
1072 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
1073 return(result);
1074 }
1075
1076
1077 /**
1078 \brief Remove the exclusive lock
1079 \details Removes the exclusive lock which is created by LDREX.
1080 */
__CLREX(void)1081 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
1082 {
1083 __ASM volatile ("clrex" ::: "memory");
1084 }
1085
1086 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1087 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1088 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1089 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1090
1091
1092 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1093 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1094 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1095 /**
1096 \brief Signed Saturate
1097 \details Saturates a signed value.
1098 \param [in] value Value to be saturated
1099 \param [in] sat Bit position to saturate to (1..32)
1100 \return Saturated value
1101 */
1102 #define __SSAT(ARG1,ARG2) \
1103 ({ \
1104 int32_t __RES, __ARG1 = (ARG1); \
1105 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1106 __RES; \
1107 })
1108
1109
1110 /**
1111 \brief Unsigned Saturate
1112 \details Saturates an unsigned value.
1113 \param [in] value Value to be saturated
1114 \param [in] sat Bit position to saturate to (0..31)
1115 \return Saturated value
1116 */
1117 #define __USAT(ARG1,ARG2) \
1118 ({ \
1119 uint32_t __RES, __ARG1 = (ARG1); \
1120 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1121 __RES; \
1122 })
1123
1124
1125 /**
1126 \brief Rotate Right with Extend (32 bit)
1127 \details Moves each bit of a bitstring right by one bit.
1128 The carry input is shifted in at the left end of the bitstring.
1129 \param [in] value Value to rotate
1130 \return Rotated value
1131 */
__RRX(uint32_t value)1132 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
1133 {
1134 uint32_t result;
1135
1136 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1137 return(result);
1138 }
1139
1140
1141 /**
1142 \brief LDRT Unprivileged (8 bit)
1143 \details Executes a Unprivileged LDRT instruction for 8 bit value.
1144 \param [in] ptr Pointer to data
1145 \return value of type uint8_t at (*ptr)
1146 */
__LDRBT(volatile uint8_t * ptr)1147 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
1148 {
1149 uint32_t result;
1150
1151 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1152 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
1153 #else
1154 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1155 accepted by assembler. So has to use following less efficient pattern.
1156 */
1157 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
1158 #endif
1159 return ((uint8_t) result); /* Add explicit type cast here */
1160 }
1161
1162
1163 /**
1164 \brief LDRT Unprivileged (16 bit)
1165 \details Executes a Unprivileged LDRT instruction for 16 bit values.
1166 \param [in] ptr Pointer to data
1167 \return value of type uint16_t at (*ptr)
1168 */
__LDRHT(volatile uint16_t * ptr)1169 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
1170 {
1171 uint32_t result;
1172
1173 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1174 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
1175 #else
1176 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
1177 accepted by assembler. So has to use following less efficient pattern.
1178 */
1179 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
1180 #endif
1181 return ((uint16_t) result); /* Add explicit type cast here */
1182 }
1183
1184
1185 /**
1186 \brief LDRT Unprivileged (32 bit)
1187 \details Executes a Unprivileged LDRT instruction for 32 bit values.
1188 \param [in] ptr Pointer to data
1189 \return value of type uint32_t at (*ptr)
1190 */
__LDRT(volatile uint32_t * ptr)1191 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
1192 {
1193 uint32_t result;
1194
1195 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
1196 return(result);
1197 }
1198
1199
1200 /**
1201 \brief STRT Unprivileged (8 bit)
1202 \details Executes a Unprivileged STRT instruction for 8 bit values.
1203 \param [in] value Value to store
1204 \param [in] ptr Pointer to location
1205 */
__STRBT(uint8_t value,volatile uint8_t * ptr)1206 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
1207 {
1208 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1209 }
1210
1211
1212 /**
1213 \brief STRT Unprivileged (16 bit)
1214 \details Executes a Unprivileged STRT instruction for 16 bit values.
1215 \param [in] value Value to store
1216 \param [in] ptr Pointer to location
1217 */
__STRHT(uint16_t value,volatile uint16_t * ptr)1218 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
1219 {
1220 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1221 }
1222
1223
1224 /**
1225 \brief STRT Unprivileged (32 bit)
1226 \details Executes a Unprivileged STRT instruction for 32 bit values.
1227 \param [in] value Value to store
1228 \param [in] ptr Pointer to location
1229 */
__STRT(uint32_t value,volatile uint32_t * ptr)1230 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
1231 {
1232 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
1233 }
1234
1235 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1236 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1237 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1238
1239
1240 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1241 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1242 /**
1243 \brief Load-Acquire (8 bit)
1244 \details Executes a LDAB instruction for 8 bit value.
1245 \param [in] ptr Pointer to data
1246 \return value of type uint8_t at (*ptr)
1247 */
__LDAB(volatile uint8_t * ptr)1248 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
1249 {
1250 uint32_t result;
1251
1252 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
1253 return ((uint8_t) result);
1254 }
1255
1256
1257 /**
1258 \brief Load-Acquire (16 bit)
1259 \details Executes a LDAH instruction for 16 bit values.
1260 \param [in] ptr Pointer to data
1261 \return value of type uint16_t at (*ptr)
1262 */
__LDAH(volatile uint16_t * ptr)1263 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
1264 {
1265 uint32_t result;
1266
1267 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
1268 return ((uint16_t) result);
1269 }
1270
1271
1272 /**
1273 \brief Load-Acquire (32 bit)
1274 \details Executes a LDA instruction for 32 bit values.
1275 \param [in] ptr Pointer to data
1276 \return value of type uint32_t at (*ptr)
1277 */
__LDA(volatile uint32_t * ptr)1278 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
1279 {
1280 uint32_t result;
1281
1282 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
1283 return(result);
1284 }
1285
1286
1287 /**
1288 \brief Store-Release (8 bit)
1289 \details Executes a STLB instruction for 8 bit values.
1290 \param [in] value Value to store
1291 \param [in] ptr Pointer to location
1292 */
__STLB(uint8_t value,volatile uint8_t * ptr)1293 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
1294 {
1295 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1296 }
1297
1298
1299 /**
1300 \brief Store-Release (16 bit)
1301 \details Executes a STLH instruction for 16 bit values.
1302 \param [in] value Value to store
1303 \param [in] ptr Pointer to location
1304 */
__STLH(uint16_t value,volatile uint16_t * ptr)1305 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
1306 {
1307 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1308 }
1309
1310
1311 /**
1312 \brief Store-Release (32 bit)
1313 \details Executes a STL instruction for 32 bit values.
1314 \param [in] value Value to store
1315 \param [in] ptr Pointer to location
1316 */
__STL(uint32_t value,volatile uint32_t * ptr)1317 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
1318 {
1319 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1320 }
1321
1322
1323 /**
1324 \brief Load-Acquire Exclusive (8 bit)
1325 \details Executes a LDAB exclusive instruction for 8 bit value.
1326 \param [in] ptr Pointer to data
1327 \return value of type uint8_t at (*ptr)
1328 */
__LDAEXB(volatile uint8_t * ptr)1329 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
1330 {
1331 uint32_t result;
1332
1333 __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
1334 return ((uint8_t) result);
1335 }
1336
1337
1338 /**
1339 \brief Load-Acquire Exclusive (16 bit)
1340 \details Executes a LDAH exclusive instruction for 16 bit values.
1341 \param [in] ptr Pointer to data
1342 \return value of type uint16_t at (*ptr)
1343 */
__LDAEXH(volatile uint16_t * ptr)1344 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
1345 {
1346 uint32_t result;
1347
1348 __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
1349 return ((uint16_t) result);
1350 }
1351
1352
1353 /**
1354 \brief Load-Acquire Exclusive (32 bit)
1355 \details Executes a LDA exclusive instruction for 32 bit values.
1356 \param [in] ptr Pointer to data
1357 \return value of type uint32_t at (*ptr)
1358 */
__LDAEX(volatile uint32_t * ptr)1359 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
1360 {
1361 uint32_t result;
1362
1363 __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
1364 return(result);
1365 }
1366
1367
1368 /**
1369 \brief Store-Release Exclusive (8 bit)
1370 \details Executes a STLB exclusive instruction for 8 bit values.
1371 \param [in] value Value to store
1372 \param [in] ptr Pointer to location
1373 \return 0 Function succeeded
1374 \return 1 Function failed
1375 */
__STLEXB(uint8_t value,volatile uint8_t * ptr)1376 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
1377 {
1378 uint32_t result;
1379
1380 __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
1381 return(result);
1382 }
1383
1384
1385 /**
1386 \brief Store-Release Exclusive (16 bit)
1387 \details Executes a STLH exclusive instruction for 16 bit values.
1388 \param [in] value Value to store
1389 \param [in] ptr Pointer to location
1390 \return 0 Function succeeded
1391 \return 1 Function failed
1392 */
__STLEXH(uint16_t value,volatile uint16_t * ptr)1393 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
1394 {
1395 uint32_t result;
1396
1397 __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
1398 return(result);
1399 }
1400
1401
1402 /**
1403 \brief Store-Release Exclusive (32 bit)
1404 \details Executes a STL exclusive instruction for 32 bit values.
1405 \param [in] value Value to store
1406 \param [in] ptr Pointer to location
1407 \return 0 Function succeeded
1408 \return 1 Function failed
1409 */
__STLEX(uint32_t value,volatile uint32_t * ptr)1410 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
1411 {
1412 uint32_t result;
1413
1414 __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
1415 return(result);
1416 }
1417
1418 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1419 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1420
1421 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
1422
1423
1424 /* ################### Compiler specific Intrinsics ########################### */
1425 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1426 Access to dedicated SIMD instructions
1427 @{
1428 */
1429
1430 #if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
1431
__SADD8(uint32_t op1,uint32_t op2)1432 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1433 {
1434 uint32_t result;
1435
1436 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1437 return(result);
1438 }
1439
__QADD8(uint32_t op1,uint32_t op2)1440 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1441 {
1442 uint32_t result;
1443
1444 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1445 return(result);
1446 }
1447
__SHADD8(uint32_t op1,uint32_t op2)1448 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1449 {
1450 uint32_t result;
1451
1452 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1453 return(result);
1454 }
1455
__UADD8(uint32_t op1,uint32_t op2)1456 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1457 {
1458 uint32_t result;
1459
1460 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1461 return(result);
1462 }
1463
__UQADD8(uint32_t op1,uint32_t op2)1464 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1465 {
1466 uint32_t result;
1467
1468 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1469 return(result);
1470 }
1471
__UHADD8(uint32_t op1,uint32_t op2)1472 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1473 {
1474 uint32_t result;
1475
1476 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1477 return(result);
1478 }
1479
1480
__SSUB8(uint32_t op1,uint32_t op2)1481 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1482 {
1483 uint32_t result;
1484
1485 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1486 return(result);
1487 }
1488
__QSUB8(uint32_t op1,uint32_t op2)1489 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1490 {
1491 uint32_t result;
1492
1493 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1494 return(result);
1495 }
1496
__SHSUB8(uint32_t op1,uint32_t op2)1497 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1498 {
1499 uint32_t result;
1500
1501 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1502 return(result);
1503 }
1504
__USUB8(uint32_t op1,uint32_t op2)1505 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1506 {
1507 uint32_t result;
1508
1509 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1510 return(result);
1511 }
1512
__UQSUB8(uint32_t op1,uint32_t op2)1513 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1514 {
1515 uint32_t result;
1516
1517 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1518 return(result);
1519 }
1520
__UHSUB8(uint32_t op1,uint32_t op2)1521 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1522 {
1523 uint32_t result;
1524
1525 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1526 return(result);
1527 }
1528
1529
__SADD16(uint32_t op1,uint32_t op2)1530 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1531 {
1532 uint32_t result;
1533
1534 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1535 return(result);
1536 }
1537
__QADD16(uint32_t op1,uint32_t op2)1538 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1539 {
1540 uint32_t result;
1541
1542 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1543 return(result);
1544 }
1545
__SHADD16(uint32_t op1,uint32_t op2)1546 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1547 {
1548 uint32_t result;
1549
1550 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1551 return(result);
1552 }
1553
__UADD16(uint32_t op1,uint32_t op2)1554 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1555 {
1556 uint32_t result;
1557
1558 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1559 return(result);
1560 }
1561
__UQADD16(uint32_t op1,uint32_t op2)1562 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1563 {
1564 uint32_t result;
1565
1566 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1567 return(result);
1568 }
1569
__UHADD16(uint32_t op1,uint32_t op2)1570 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1571 {
1572 uint32_t result;
1573
1574 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1575 return(result);
1576 }
1577
__SSUB16(uint32_t op1,uint32_t op2)1578 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1579 {
1580 uint32_t result;
1581
1582 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1583 return(result);
1584 }
1585
__QSUB16(uint32_t op1,uint32_t op2)1586 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1587 {
1588 uint32_t result;
1589
1590 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1591 return(result);
1592 }
1593
__SHSUB16(uint32_t op1,uint32_t op2)1594 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1595 {
1596 uint32_t result;
1597
1598 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1599 return(result);
1600 }
1601
__USUB16(uint32_t op1,uint32_t op2)1602 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1603 {
1604 uint32_t result;
1605
1606 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1607 return(result);
1608 }
1609
__UQSUB16(uint32_t op1,uint32_t op2)1610 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1611 {
1612 uint32_t result;
1613
1614 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1615 return(result);
1616 }
1617
__UHSUB16(uint32_t op1,uint32_t op2)1618 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1619 {
1620 uint32_t result;
1621
1622 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1623 return(result);
1624 }
1625
__SASX(uint32_t op1,uint32_t op2)1626 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1627 {
1628 uint32_t result;
1629
1630 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1631 return(result);
1632 }
1633
__QASX(uint32_t op1,uint32_t op2)1634 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1635 {
1636 uint32_t result;
1637
1638 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1639 return(result);
1640 }
1641
__SHASX(uint32_t op1,uint32_t op2)1642 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1643 {
1644 uint32_t result;
1645
1646 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1647 return(result);
1648 }
1649
__UASX(uint32_t op1,uint32_t op2)1650 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1651 {
1652 uint32_t result;
1653
1654 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1655 return(result);
1656 }
1657
__UQASX(uint32_t op1,uint32_t op2)1658 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1659 {
1660 uint32_t result;
1661
1662 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1663 return(result);
1664 }
1665
__UHASX(uint32_t op1,uint32_t op2)1666 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1667 {
1668 uint32_t result;
1669
1670 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1671 return(result);
1672 }
1673
__SSAX(uint32_t op1,uint32_t op2)1674 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1675 {
1676 uint32_t result;
1677
1678 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1679 return(result);
1680 }
1681
__QSAX(uint32_t op1,uint32_t op2)1682 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1683 {
1684 uint32_t result;
1685
1686 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1687 return(result);
1688 }
1689
__SHSAX(uint32_t op1,uint32_t op2)1690 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1691 {
1692 uint32_t result;
1693
1694 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1695 return(result);
1696 }
1697
__USAX(uint32_t op1,uint32_t op2)1698 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1699 {
1700 uint32_t result;
1701
1702 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1703 return(result);
1704 }
1705
__UQSAX(uint32_t op1,uint32_t op2)1706 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1707 {
1708 uint32_t result;
1709
1710 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1711 return(result);
1712 }
1713
__UHSAX(uint32_t op1,uint32_t op2)1714 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1715 {
1716 uint32_t result;
1717
1718 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1719 return(result);
1720 }
1721
__USAD8(uint32_t op1,uint32_t op2)1722 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1723 {
1724 uint32_t result;
1725
1726 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1727 return(result);
1728 }
1729
__USADA8(uint32_t op1,uint32_t op2,uint32_t op3)1730 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1731 {
1732 uint32_t result;
1733
1734 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1735 return(result);
1736 }
1737
1738 #define __SSAT16(ARG1,ARG2) \
1739 ({ \
1740 int32_t __RES, __ARG1 = (ARG1); \
1741 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1742 __RES; \
1743 })
1744
1745 #define __USAT16(ARG1,ARG2) \
1746 ({ \
1747 uint32_t __RES, __ARG1 = (ARG1); \
1748 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1749 __RES; \
1750 })
1751
__UXTB16(uint32_t op1)1752 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
1753 {
1754 uint32_t result;
1755
1756 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1757 return(result);
1758 }
1759
__UXTAB16(uint32_t op1,uint32_t op2)1760 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1761 {
1762 uint32_t result;
1763
1764 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1765 return(result);
1766 }
1767
__SXTB16(uint32_t op1)1768 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
1769 {
1770 uint32_t result;
1771
1772 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1773 return(result);
1774 }
1775
__SXTAB16(uint32_t op1,uint32_t op2)1776 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
1777 {
1778 uint32_t result;
1779
1780 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1781 return(result);
1782 }
1783
__SMUAD(uint32_t op1,uint32_t op2)1784 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
1785 {
1786 uint32_t result;
1787
1788 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1789 return(result);
1790 }
1791
__SMUADX(uint32_t op1,uint32_t op2)1792 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
1793 {
1794 uint32_t result;
1795
1796 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1797 return(result);
1798 }
1799
__SMLAD(uint32_t op1,uint32_t op2,uint32_t op3)1800 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
1801 {
1802 uint32_t result;
1803
1804 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1805 return(result);
1806 }
1807
__SMLADX(uint32_t op1,uint32_t op2,uint32_t op3)1808 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
1809 {
1810 uint32_t result;
1811
1812 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1813 return(result);
1814 }
1815
__SMLALD(uint32_t op1,uint32_t op2,uint64_t acc)1816 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
1817 {
1818 union llreg_u{
1819 uint32_t w32[2];
1820 uint64_t w64;
1821 } llr;
1822 llr.w64 = acc;
1823
1824 #ifndef __ARMEB__ /* Little endian */
1825 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1826 #else /* Big endian */
1827 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1828 #endif
1829
1830 return(llr.w64);
1831 }
1832
__SMLALDX(uint32_t op1,uint32_t op2,uint64_t acc)1833 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
1834 {
1835 union llreg_u{
1836 uint32_t w32[2];
1837 uint64_t w64;
1838 } llr;
1839 llr.w64 = acc;
1840
1841 #ifndef __ARMEB__ /* Little endian */
1842 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1843 #else /* Big endian */
1844 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1845 #endif
1846
1847 return(llr.w64);
1848 }
1849
__SMUSD(uint32_t op1,uint32_t op2)1850 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
1851 {
1852 uint32_t result;
1853
1854 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1855 return(result);
1856 }
1857
__SMUSDX(uint32_t op1,uint32_t op2)1858 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
1859 {
1860 uint32_t result;
1861
1862 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1863 return(result);
1864 }
1865
__SMLSD(uint32_t op1,uint32_t op2,uint32_t op3)1866 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
1867 {
1868 uint32_t result;
1869
1870 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1871 return(result);
1872 }
1873
__SMLSDX(uint32_t op1,uint32_t op2,uint32_t op3)1874 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
1875 {
1876 uint32_t result;
1877
1878 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1879 return(result);
1880 }
1881
__SMLSLD(uint32_t op1,uint32_t op2,uint64_t acc)1882 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
1883 {
1884 union llreg_u{
1885 uint32_t w32[2];
1886 uint64_t w64;
1887 } llr;
1888 llr.w64 = acc;
1889
1890 #ifndef __ARMEB__ /* Little endian */
1891 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1892 #else /* Big endian */
1893 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1894 #endif
1895
1896 return(llr.w64);
1897 }
1898
__SMLSLDX(uint32_t op1,uint32_t op2,uint64_t acc)1899 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
1900 {
1901 union llreg_u{
1902 uint32_t w32[2];
1903 uint64_t w64;
1904 } llr;
1905 llr.w64 = acc;
1906
1907 #ifndef __ARMEB__ /* Little endian */
1908 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1909 #else /* Big endian */
1910 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1911 #endif
1912
1913 return(llr.w64);
1914 }
1915
__SEL(uint32_t op1,uint32_t op2)1916 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
1917 {
1918 uint32_t result;
1919
1920 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1921 return(result);
1922 }
1923
__QADD(int32_t op1,int32_t op2)1924 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
1925 {
1926 int32_t result;
1927
1928 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1929 return(result);
1930 }
1931
__QSUB(int32_t op1,int32_t op2)1932 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
1933 {
1934 int32_t result;
1935
1936 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1937 return(result);
1938 }
1939
1940 #if 0
1941 #define __PKHBT(ARG1,ARG2,ARG3) \
1942 ({ \
1943 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
1944 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1945 __RES; \
1946 })
1947
1948 #define __PKHTB(ARG1,ARG2,ARG3) \
1949 ({ \
1950 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
1951 if (ARG3 == 0) \
1952 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
1953 else \
1954 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1955 __RES; \
1956 })
1957 #endif
1958
1959 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1960 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1961
1962 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1963 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1964
__SMMLA(int32_t op1,int32_t op2,int32_t op3)1965 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1966 {
1967 int32_t result;
1968
1969 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1970 return(result);
1971 }
1972
1973 #endif /* (__ARM_FEATURE_DSP == 1) */
1974 /*@} end of group CMSIS_SIMD_intrinsics */
1975
1976
1977 #pragma GCC diagnostic pop
1978
1979 #endif /* __CMSIS_GCC_H */
1980