1 /**************************************************************************//**
2 * @file cmsis_armclang.h
3 * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
4 * @version V5.0.3
5 * @date 27. March 2017
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
26
27 #ifndef __CMSIS_ARMCLANG_H
28 #define __CMSIS_ARMCLANG_H
29
30 #ifndef __ARM_COMPAT_H
31 #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
32 #endif
33
34 /* CMSIS compiler specific defines */
35 #ifndef __ASM
36 #define __ASM __asm
37 #endif
38 #ifndef __INLINE
39 #define __INLINE __inline
40 #endif
41 #ifndef __STATIC_INLINE
42 #define __STATIC_INLINE static __inline
43 #endif
44 #ifndef __NO_RETURN
45 #define __NO_RETURN __attribute__((noreturn))
46 #endif
47 #ifndef __USED
48 #define __USED __attribute__((used))
49 #endif
50 #ifndef __WEAK
51 #define __WEAK __attribute__((weak))
52 #endif
53 #ifndef __PACKED
54 #define __PACKED __attribute__((packed, aligned(1)))
55 #endif
56 #ifndef __PACKED_STRUCT
57 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
58 #endif
59 #ifndef __PACKED_UNION
60 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
61 #endif
62 #ifndef __UNALIGNED_UINT32 /* deprecated */
63 #pragma clang diagnostic push
64 #pragma clang diagnostic ignored "-Wpacked"
65 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
66 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
67 #pragma clang diagnostic pop
68 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
69 #endif
70 #ifndef __UNALIGNED_UINT16_WRITE
71 #pragma clang diagnostic push
72 #pragma clang diagnostic ignored "-Wpacked"
73 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
74 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
75 #pragma clang diagnostic pop
76 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
77 #endif
78 #ifndef __UNALIGNED_UINT16_READ
79 #pragma clang diagnostic push
80 #pragma clang diagnostic ignored "-Wpacked"
81 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
82 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
83 #pragma clang diagnostic pop
84 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
85 #endif
86 #ifndef __UNALIGNED_UINT32_WRITE
87 #pragma clang diagnostic push
88 #pragma clang diagnostic ignored "-Wpacked"
89 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
90 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
91 #pragma clang diagnostic pop
92 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
93 #endif
94 #ifndef __UNALIGNED_UINT32_READ
95 #pragma clang diagnostic push
96 #pragma clang diagnostic ignored "-Wpacked"
97 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
98 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
99 #pragma clang diagnostic pop
100 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
101 #endif
102 #ifndef __ALIGNED
103 #define __ALIGNED(x) __attribute__((aligned(x)))
104 #endif
105 #ifndef __RESTRICT
106 #define __RESTRICT __restrict
107 #endif
108
109
110 /* ########################### Core Function Access ########################### */
111 /** \ingroup CMSIS_Core_FunctionInterface
112 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
113 @{
114 */
115
116 /**
117 \brief Enable IRQ Interrupts
118 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
119 Can only be executed in Privileged modes.
120 */
121 /* intrinsic void __enable_irq(); see arm_compat.h */
122
123
124 /**
125 \brief Disable IRQ Interrupts
126 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
127 Can only be executed in Privileged modes.
128 */
129 /* intrinsic void __disable_irq(); see arm_compat.h */
130
131
132 /**
133 \brief Get Control Register
134 \details Returns the content of the Control Register.
135 \return Control Register value
136 */
__get_CONTROL(void)137 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
138 {
139 uint32_t result;
140
141 __ASM volatile ("MRS %0, control" : "=r" (result) );
142 return(result);
143 }
144
145
146 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
147 /**
148 \brief Get Control Register (non-secure)
149 \details Returns the content of the non-secure Control Register when in secure mode.
150 \return non-secure Control Register value
151 */
__TZ_get_CONTROL_NS(void)152 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
153 {
154 uint32_t result;
155
156 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
157 return(result);
158 }
159 #endif
160
161
162 /**
163 \brief Set Control Register
164 \details Writes the given value to the Control Register.
165 \param [in] control Control Register value to set
166 */
__set_CONTROL(uint32_t control)167 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
168 {
169 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
170 }
171
172
173 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
174 /**
175 \brief Set Control Register (non-secure)
176 \details Writes the given value to the non-secure Control Register when in secure state.
177 \param [in] control Control Register value to set
178 */
__TZ_set_CONTROL_NS(uint32_t control)179 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
180 {
181 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
182 }
183 #endif
184
185
186 /**
187 \brief Get IPSR Register
188 \details Returns the content of the IPSR Register.
189 \return IPSR Register value
190 */
__get_IPSR(void)191 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
192 {
193 uint32_t result;
194
195 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
196 return(result);
197 }
198
199
200 /**
201 \brief Get APSR Register
202 \details Returns the content of the APSR Register.
203 \return APSR Register value
204 */
__get_APSR(void)205 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
206 {
207 uint32_t result;
208
209 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
210 return(result);
211 }
212
213
214 /**
215 \brief Get xPSR Register
216 \details Returns the content of the xPSR Register.
217 \return xPSR Register value
218 */
__get_xPSR(void)219 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
220 {
221 uint32_t result;
222
223 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
224 return(result);
225 }
226
227
228 /**
229 \brief Get Process Stack Pointer
230 \details Returns the current value of the Process Stack Pointer (PSP).
231 \return PSP Register value
232 */
__get_PSP(void)233 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
234 {
235 register uint32_t result;
236
237 __ASM volatile ("MRS %0, psp" : "=r" (result) );
238 return(result);
239 }
240
241
242 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
243 /**
244 \brief Get Process Stack Pointer (non-secure)
245 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
246 \return PSP Register value
247 */
__TZ_get_PSP_NS(void)248 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
249 {
250 register uint32_t result;
251
252 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
253 return(result);
254 }
255 #endif
256
257
258 /**
259 \brief Set Process Stack Pointer
260 \details Assigns the given value to the Process Stack Pointer (PSP).
261 \param [in] topOfProcStack Process Stack Pointer value to set
262 */
__set_PSP(uint32_t topOfProcStack)263 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
264 {
265 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
266 }
267
268
269 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
270 /**
271 \brief Set Process Stack Pointer (non-secure)
272 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
273 \param [in] topOfProcStack Process Stack Pointer value to set
274 */
__TZ_set_PSP_NS(uint32_t topOfProcStack)275 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
276 {
277 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
278 }
279 #endif
280
281
282 /**
283 \brief Get Main Stack Pointer
284 \details Returns the current value of the Main Stack Pointer (MSP).
285 \return MSP Register value
286 */
__get_MSP(void)287 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
288 {
289 register uint32_t result;
290
291 __ASM volatile ("MRS %0, msp" : "=r" (result) );
292 return(result);
293 }
294
295
296 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
297 /**
298 \brief Get Main Stack Pointer (non-secure)
299 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
300 \return MSP Register value
301 */
__TZ_get_MSP_NS(void)302 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
303 {
304 register uint32_t result;
305
306 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
307 return(result);
308 }
309 #endif
310
311
312 /**
313 \brief Set Main Stack Pointer
314 \details Assigns the given value to the Main Stack Pointer (MSP).
315 \param [in] topOfMainStack Main Stack Pointer value to set
316 */
__set_MSP(uint32_t topOfMainStack)317 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
318 {
319 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
320 }
321
322
323 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
324 /**
325 \brief Set Main Stack Pointer (non-secure)
326 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
327 \param [in] topOfMainStack Main Stack Pointer value to set
328 */
__TZ_set_MSP_NS(uint32_t topOfMainStack)329 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
330 {
331 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
332 }
333 #endif
334
335
336 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
337 /**
338 \brief Get Stack Pointer (non-secure)
339 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
340 \return SP Register value
341 */
__TZ_get_SP_NS(void)342 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
343 {
344 register uint32_t result;
345
346 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
347 return(result);
348 }
349
350
351 /**
352 \brief Set Stack Pointer (non-secure)
353 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
354 \param [in] topOfStack Stack Pointer value to set
355 */
__TZ_set_SP_NS(uint32_t topOfStack)356 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
357 {
358 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
359 }
360 #endif
361
362
363 /**
364 \brief Get Priority Mask
365 \details Returns the current state of the priority mask bit from the Priority Mask Register.
366 \return Priority Mask value
367 */
__get_PRIMASK(void)368 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
369 {
370 uint32_t result;
371
372 __ASM volatile ("MRS %0, primask" : "=r" (result) );
373 return(result);
374 }
375
376
377 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
378 /**
379 \brief Get Priority Mask (non-secure)
380 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
381 \return Priority Mask value
382 */
__TZ_get_PRIMASK_NS(void)383 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
384 {
385 uint32_t result;
386
387 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
388 return(result);
389 }
390 #endif
391
392
393 /**
394 \brief Set Priority Mask
395 \details Assigns the given value to the Priority Mask Register.
396 \param [in] priMask Priority Mask
397 */
__set_PRIMASK(uint32_t priMask)398 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
399 {
400 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
401 }
402
403
404 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
405 /**
406 \brief Set Priority Mask (non-secure)
407 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
408 \param [in] priMask Priority Mask
409 */
__TZ_set_PRIMASK_NS(uint32_t priMask)410 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
411 {
412 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
413 }
414 #endif
415
416
417 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
418 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
419 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
420 /**
421 \brief Enable FIQ
422 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
423 Can only be executed in Privileged modes.
424 */
425 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
426
427
428 /**
429 \brief Disable FIQ
430 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
431 Can only be executed in Privileged modes.
432 */
433 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
434
435
436 /**
437 \brief Get Base Priority
438 \details Returns the current value of the Base Priority register.
439 \return Base Priority register value
440 */
__get_BASEPRI(void)441 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
442 {
443 uint32_t result;
444
445 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
446 return(result);
447 }
448
449
450 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
451 /**
452 \brief Get Base Priority (non-secure)
453 \details Returns the current value of the non-secure Base Priority register when in secure state.
454 \return Base Priority register value
455 */
__TZ_get_BASEPRI_NS(void)456 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
457 {
458 uint32_t result;
459
460 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
461 return(result);
462 }
463 #endif
464
465
466 /**
467 \brief Set Base Priority
468 \details Assigns the given value to the Base Priority register.
469 \param [in] basePri Base Priority value to set
470 */
__set_BASEPRI(uint32_t basePri)471 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
472 {
473 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
474 }
475
476
477 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
478 /**
479 \brief Set Base Priority (non-secure)
480 \details Assigns the given value to the non-secure Base Priority register when in secure state.
481 \param [in] basePri Base Priority value to set
482 */
__TZ_set_BASEPRI_NS(uint32_t basePri)483 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
484 {
485 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
486 }
487 #endif
488
489
490 /**
491 \brief Set Base Priority with condition
492 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
493 or the new value increases the BASEPRI priority level.
494 \param [in] basePri Base Priority value to set
495 */
__set_BASEPRI_MAX(uint32_t basePri)496 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
497 {
498 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
499 }
500
501
502 /**
503 \brief Get Fault Mask
504 \details Returns the current value of the Fault Mask register.
505 \return Fault Mask register value
506 */
__get_FAULTMASK(void)507 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
508 {
509 uint32_t result;
510
511 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
512 return(result);
513 }
514
515
516 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
517 /**
518 \brief Get Fault Mask (non-secure)
519 \details Returns the current value of the non-secure Fault Mask register when in secure state.
520 \return Fault Mask register value
521 */
__TZ_get_FAULTMASK_NS(void)522 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
523 {
524 uint32_t result;
525
526 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
527 return(result);
528 }
529 #endif
530
531
532 /**
533 \brief Set Fault Mask
534 \details Assigns the given value to the Fault Mask register.
535 \param [in] faultMask Fault Mask value to set
536 */
__set_FAULTMASK(uint32_t faultMask)537 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
538 {
539 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
540 }
541
542
543 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
544 /**
545 \brief Set Fault Mask (non-secure)
546 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
547 \param [in] faultMask Fault Mask value to set
548 */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)549 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
550 {
551 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
552 }
553 #endif
554
555 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
556 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
557 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
558
559
560 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
561 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
562
563 /**
564 \brief Get Process Stack Pointer Limit
565 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
566 \return PSPLIM Register value
567 */
__get_PSPLIM(void)568 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
569 {
570 register uint32_t result;
571
572 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
573 return(result);
574 }
575
576
577 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
578 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
579 /**
580 \brief Get Process Stack Pointer Limit (non-secure)
581 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
582 \return PSPLIM Register value
583 */
__TZ_get_PSPLIM_NS(void)584 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
585 {
586 register uint32_t result;
587
588 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
589 return(result);
590 }
591 #endif
592
593
594 /**
595 \brief Set Process Stack Pointer Limit
596 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
597 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
598 */
__set_PSPLIM(uint32_t ProcStackPtrLimit)599 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
600 {
601 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
602 }
603
604
605 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
606 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
607 /**
608 \brief Set Process Stack Pointer (non-secure)
609 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
610 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
611 */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)612 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
613 {
614 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
615 }
616 #endif
617
618
619 /**
620 \brief Get Main Stack Pointer Limit
621 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
622 \return MSPLIM Register value
623 */
__get_MSPLIM(void)624 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
625 {
626 register uint32_t result;
627
628 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
629
630 return(result);
631 }
632
633
634 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
635 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
636 /**
637 \brief Get Main Stack Pointer Limit (non-secure)
638 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
639 \return MSPLIM Register value
640 */
__TZ_get_MSPLIM_NS(void)641 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
642 {
643 register uint32_t result;
644
645 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
646 return(result);
647 }
648 #endif
649
650
651 /**
652 \brief Set Main Stack Pointer Limit
653 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
654 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
655 */
__set_MSPLIM(uint32_t MainStackPtrLimit)656 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
657 {
658 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
659 }
660
661
662 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
663 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
664 /**
665 \brief Set Main Stack Pointer Limit (non-secure)
666 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
667 \param [in] MainStackPtrLimit Main Stack Pointer value to set
668 */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)669 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
670 {
671 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
672 }
673 #endif
674
675 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
676 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
677
678
679 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
680 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
681
682 /**
683 \brief Get FPSCR
684 \details Returns the current value of the Floating Point Status/Control register.
685 \return Floating Point Status/Control register value
686 */
687 /* #define __get_FPSCR __builtin_arm_get_fpscr */
__get_FPSCR(void)688 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
689 {
690 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
691 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
692 uint32_t result;
693
694 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
695 return(result);
696 #else
697 return(0U);
698 #endif
699 }
700
701
702 /**
703 \brief Set FPSCR
704 \details Assigns the given value to the Floating Point Status/Control register.
705 \param [in] fpscr Floating Point Status/Control value to set
706 */
707 /* #define __set_FPSCR __builtin_arm_set_fpscr */
__set_FPSCR(uint32_t fpscr)708 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
709 {
710 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
711 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
712 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
713 #else
714 (void)fpscr;
715 #endif
716 }
717
718 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
719 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
720
721
722
723 /*@} end of CMSIS_Core_RegAccFunctions */
724
725
726 /* ########################## Core Instruction Access ######################### */
727 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
728 Access to dedicated instructions
729 @{
730 */
731
732 /* Define macros for porting to both thumb1 and thumb2.
733 * For thumb1, use low register (r0-r7), specified by constraint "l"
734 * Otherwise, use general registers, specified by constraint "r" */
735 #if defined (__thumb__) && !defined (__thumb2__)
736 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
737 #define __CMSIS_GCC_USE_REG(r) "l" (r)
738 #else
739 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
740 #define __CMSIS_GCC_USE_REG(r) "r" (r)
741 #endif
742
743 /**
744 \brief No Operation
745 \details No Operation does nothing. This instruction can be used for code alignment purposes.
746 */
747 #define __NOP __builtin_arm_nop
748
749 /**
750 \brief Wait For Interrupt
751 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
752 */
753 #define __WFI __builtin_arm_wfi
754
755
756 /**
757 \brief Wait For Event
758 \details Wait For Event is a hint instruction that permits the processor to enter
759 a low-power state until one of a number of events occurs.
760 */
761 #define __WFE __builtin_arm_wfe
762
763
764 /**
765 \brief Send Event
766 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
767 */
768 #define __SEV __builtin_arm_sev
769
770
771 /**
772 \brief Instruction Synchronization Barrier
773 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
774 so that all instructions following the ISB are fetched from cache or memory,
775 after the instruction has been completed.
776 */
777 #define __ISB() __builtin_arm_isb(0xF);
778
779 /**
780 \brief Data Synchronization Barrier
781 \details Acts as a special kind of Data Memory Barrier.
782 It completes when all explicit memory accesses before this instruction complete.
783 */
784 #define __DSB() __builtin_arm_dsb(0xF);
785
786
787 /**
788 \brief Data Memory Barrier
789 \details Ensures the apparent order of the explicit memory operations before
790 and after the instruction, without ensuring their completion.
791 */
792 #define __DMB() __builtin_arm_dmb(0xF);
793
794
795 /**
796 \brief Reverse byte order (32 bit)
797 \details Reverses the byte order in integer value.
798 \param [in] value Value to reverse
799 \return Reversed value
800 */
801 #define __REV __builtin_bswap32
802
803
804 /**
805 \brief Reverse byte order (16 bit)
806 \details Reverses the byte order in two unsigned short values.
807 \param [in] value Value to reverse
808 \return Reversed value
809 */
810 #define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
811 #if 0
812 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
813 {
814 uint32_t result;
815
816 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
817 return(result);
818 }
819 #endif
820
821
822 /**
823 \brief Reverse byte order in signed short value
824 \details Reverses the byte order in a signed short value with sign extension to integer.
825 \param [in] value Value to reverse
826 \return Reversed value
827 */
828 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
__REVSH(int32_t value)829 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
830 {
831 int32_t result;
832
833 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
834 return(result);
835 }
836
837
838 /**
839 \brief Rotate Right in unsigned value (32 bit)
840 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
841 \param [in] op1 Value to rotate
842 \param [in] op2 Number of Bits to rotate
843 \return Rotated value
844 */
__ROR(uint32_t op1,uint32_t op2)845 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
846 {
847 return (op1 >> op2) | (op1 << (32U - op2));
848 }
849
850
851 /**
852 \brief Breakpoint
853 \details Causes the processor to enter Debug state.
854 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
855 \param [in] value is ignored by the processor.
856 If required, a debugger can use it to store additional information about the breakpoint.
857 */
858 #define __BKPT(value) __ASM volatile ("bkpt "#value)
859
860
861 /**
862 \brief Reverse bit order of value
863 \details Reverses the bit order of the given value.
864 \param [in] value Value to reverse
865 \return Reversed value
866 */
867 /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
__RBIT(uint32_t value)868 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
869 {
870 uint32_t result;
871
872 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
873 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
874 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
875 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
876 #else
877 int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
878
879 result = value; /* r will be reversed bits of v; first get LSB of v */
880 for (value >>= 1U; value; value >>= 1U)
881 {
882 result <<= 1U;
883 result |= value & 1U;
884 s--;
885 }
886 result <<= s; /* shift when v's highest bits are zero */
887 #endif
888 return(result);
889 }
890
891
892 /**
893 \brief Count leading zeros
894 \details Counts the number of leading zeros of a data value.
895 \param [in] value Value to count the leading zeros
896 \return number of leading zeros in value
897 */
898 #define __CLZ __builtin_clz
899
900
901 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
902 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
903 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
904 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
905 /**
906 \brief LDR Exclusive (8 bit)
907 \details Executes a exclusive LDR instruction for 8 bit value.
908 \param [in] ptr Pointer to data
909 \return value of type uint8_t at (*ptr)
910 */
911 #define __LDREXB (uint8_t)__builtin_arm_ldrex
912
913
914 /**
915 \brief LDR Exclusive (16 bit)
916 \details Executes a exclusive LDR instruction for 16 bit values.
917 \param [in] ptr Pointer to data
918 \return value of type uint16_t at (*ptr)
919 */
920 #define __LDREXH (uint16_t)__builtin_arm_ldrex
921
922
923 /**
924 \brief LDR Exclusive (32 bit)
925 \details Executes a exclusive LDR instruction for 32 bit values.
926 \param [in] ptr Pointer to data
927 \return value of type uint32_t at (*ptr)
928 */
929 #define __LDREXW (uint32_t)__builtin_arm_ldrex
930
931
932 /**
933 \brief STR Exclusive (8 bit)
934 \details Executes a exclusive STR instruction for 8 bit values.
935 \param [in] value Value to store
936 \param [in] ptr Pointer to location
937 \return 0 Function succeeded
938 \return 1 Function failed
939 */
940 #define __STREXB (uint32_t)__builtin_arm_strex
941
942
943 /**
944 \brief STR Exclusive (16 bit)
945 \details Executes a exclusive STR instruction for 16 bit values.
946 \param [in] value Value to store
947 \param [in] ptr Pointer to location
948 \return 0 Function succeeded
949 \return 1 Function failed
950 */
951 #define __STREXH (uint32_t)__builtin_arm_strex
952
953
954 /**
955 \brief STR Exclusive (32 bit)
956 \details Executes a exclusive STR instruction for 32 bit values.
957 \param [in] value Value to store
958 \param [in] ptr Pointer to location
959 \return 0 Function succeeded
960 \return 1 Function failed
961 */
962 #define __STREXW (uint32_t)__builtin_arm_strex
963
964
965 /**
966 \brief Remove the exclusive lock
967 \details Removes the exclusive lock which is created by LDREX.
968 */
969 #define __CLREX __builtin_arm_clrex
970
971 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
972 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
973 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
974 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
975
976
977 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
978 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
979 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
980 /**
981 \brief Signed Saturate
982 \details Saturates a signed value.
983 \param [in] value Value to be saturated
984 \param [in] sat Bit position to saturate to (1..32)
985 \return Saturated value
986 */
987 #define __SSAT __builtin_arm_ssat
988
989
990 /**
991 \brief Unsigned Saturate
992 \details Saturates an unsigned value.
993 \param [in] value Value to be saturated
994 \param [in] sat Bit position to saturate to (0..31)
995 \return Saturated value
996 */
997 #define __USAT __builtin_arm_usat
998
999
1000 /**
1001 \brief Rotate Right with Extend (32 bit)
1002 \details Moves each bit of a bitstring right by one bit.
1003 The carry input is shifted in at the left end of the bitstring.
1004 \param [in] value Value to rotate
1005 \return Rotated value
1006 */
__RRX(uint32_t value)1007 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
1008 {
1009 uint32_t result;
1010
1011 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1012 return(result);
1013 }
1014
1015
1016 /**
1017 \brief LDRT Unprivileged (8 bit)
1018 \details Executes a Unprivileged LDRT instruction for 8 bit value.
1019 \param [in] ptr Pointer to data
1020 \return value of type uint8_t at (*ptr)
1021 */
__LDRBT(volatile uint8_t * ptr)1022 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
1023 {
1024 uint32_t result;
1025
1026 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
1027 return ((uint8_t) result); /* Add explicit type cast here */
1028 }
1029
1030
1031 /**
1032 \brief LDRT Unprivileged (16 bit)
1033 \details Executes a Unprivileged LDRT instruction for 16 bit values.
1034 \param [in] ptr Pointer to data
1035 \return value of type uint16_t at (*ptr)
1036 */
__LDRHT(volatile uint16_t * ptr)1037 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
1038 {
1039 uint32_t result;
1040
1041 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
1042 return ((uint16_t) result); /* Add explicit type cast here */
1043 }
1044
1045
1046 /**
1047 \brief LDRT Unprivileged (32 bit)
1048 \details Executes a Unprivileged LDRT instruction for 32 bit values.
1049 \param [in] ptr Pointer to data
1050 \return value of type uint32_t at (*ptr)
1051 */
__LDRT(volatile uint32_t * ptr)1052 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
1053 {
1054 uint32_t result;
1055
1056 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
1057 return(result);
1058 }
1059
1060
1061 /**
1062 \brief STRT Unprivileged (8 bit)
1063 \details Executes a Unprivileged STRT instruction for 8 bit values.
1064 \param [in] value Value to store
1065 \param [in] ptr Pointer to location
1066 */
__STRBT(uint8_t value,volatile uint8_t * ptr)1067 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
1068 {
1069 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1070 }
1071
1072
1073 /**
1074 \brief STRT Unprivileged (16 bit)
1075 \details Executes a Unprivileged STRT instruction for 16 bit values.
1076 \param [in] value Value to store
1077 \param [in] ptr Pointer to location
1078 */
__STRHT(uint16_t value,volatile uint16_t * ptr)1079 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
1080 {
1081 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1082 }
1083
1084
1085 /**
1086 \brief STRT Unprivileged (32 bit)
1087 \details Executes a Unprivileged STRT instruction for 32 bit values.
1088 \param [in] value Value to store
1089 \param [in] ptr Pointer to location
1090 */
__STRT(uint32_t value,volatile uint32_t * ptr)1091 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
1092 {
1093 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
1094 }
1095
1096 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1097 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1098 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1099
1100
1101 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1102 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1103 /**
1104 \brief Load-Acquire (8 bit)
1105 \details Executes a LDAB instruction for 8 bit value.
1106 \param [in] ptr Pointer to data
1107 \return value of type uint8_t at (*ptr)
1108 */
__LDAB(volatile uint8_t * ptr)1109 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
1110 {
1111 uint32_t result;
1112
1113 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
1114 return ((uint8_t) result);
1115 }
1116
1117
1118 /**
1119 \brief Load-Acquire (16 bit)
1120 \details Executes a LDAH instruction for 16 bit values.
1121 \param [in] ptr Pointer to data
1122 \return value of type uint16_t at (*ptr)
1123 */
__LDAH(volatile uint16_t * ptr)1124 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
1125 {
1126 uint32_t result;
1127
1128 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
1129 return ((uint16_t) result);
1130 }
1131
1132
1133 /**
1134 \brief Load-Acquire (32 bit)
1135 \details Executes a LDA instruction for 32 bit values.
1136 \param [in] ptr Pointer to data
1137 \return value of type uint32_t at (*ptr)
1138 */
__LDA(volatile uint32_t * ptr)1139 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
1140 {
1141 uint32_t result;
1142
1143 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
1144 return(result);
1145 }
1146
1147
1148 /**
1149 \brief Store-Release (8 bit)
1150 \details Executes a STLB instruction for 8 bit values.
1151 \param [in] value Value to store
1152 \param [in] ptr Pointer to location
1153 */
__STLB(uint8_t value,volatile uint8_t * ptr)1154 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
1155 {
1156 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1157 }
1158
1159
1160 /**
1161 \brief Store-Release (16 bit)
1162 \details Executes a STLH instruction for 16 bit values.
1163 \param [in] value Value to store
1164 \param [in] ptr Pointer to location
1165 */
__STLH(uint16_t value,volatile uint16_t * ptr)1166 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
1167 {
1168 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1169 }
1170
1171
1172 /**
1173 \brief Store-Release (32 bit)
1174 \details Executes a STL instruction for 32 bit values.
1175 \param [in] value Value to store
1176 \param [in] ptr Pointer to location
1177 */
__STL(uint32_t value,volatile uint32_t * ptr)1178 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
1179 {
1180 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
1181 }
1182
1183
1184 /**
1185 \brief Load-Acquire Exclusive (8 bit)
1186 \details Executes a LDAB exclusive instruction for 8 bit value.
1187 \param [in] ptr Pointer to data
1188 \return value of type uint8_t at (*ptr)
1189 */
1190 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
1191
1192
1193 /**
1194 \brief Load-Acquire Exclusive (16 bit)
1195 \details Executes a LDAH exclusive instruction for 16 bit values.
1196 \param [in] ptr Pointer to data
1197 \return value of type uint16_t at (*ptr)
1198 */
1199 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
1200
1201
1202 /**
1203 \brief Load-Acquire Exclusive (32 bit)
1204 \details Executes a LDA exclusive instruction for 32 bit values.
1205 \param [in] ptr Pointer to data
1206 \return value of type uint32_t at (*ptr)
1207 */
1208 #define __LDAEX (uint32_t)__builtin_arm_ldaex
1209
1210
1211 /**
1212 \brief Store-Release Exclusive (8 bit)
1213 \details Executes a STLB exclusive instruction for 8 bit values.
1214 \param [in] value Value to store
1215 \param [in] ptr Pointer to location
1216 \return 0 Function succeeded
1217 \return 1 Function failed
1218 */
1219 #define __STLEXB (uint32_t)__builtin_arm_stlex
1220
1221
1222 /**
1223 \brief Store-Release Exclusive (16 bit)
1224 \details Executes a STLH exclusive instruction for 16 bit values.
1225 \param [in] value Value to store
1226 \param [in] ptr Pointer to location
1227 \return 0 Function succeeded
1228 \return 1 Function failed
1229 */
1230 #define __STLEXH (uint32_t)__builtin_arm_stlex
1231
1232
1233 /**
1234 \brief Store-Release Exclusive (32 bit)
1235 \details Executes a STL exclusive instruction for 32 bit values.
1236 \param [in] value Value to store
1237 \param [in] ptr Pointer to location
1238 \return 0 Function succeeded
1239 \return 1 Function failed
1240 */
1241 #define __STLEX (uint32_t)__builtin_arm_stlex
1242
1243 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1244 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1245
1246 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
1247
1248
1249 /* ################### Compiler specific Intrinsics ########################### */
1250 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1251 Access to dedicated SIMD instructions
1252 @{
1253 */
1254
1255 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1256
__SADD8(uint32_t op1,uint32_t op2)1257 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1258 {
1259 uint32_t result;
1260
1261 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1262 return(result);
1263 }
1264
__QADD8(uint32_t op1,uint32_t op2)1265 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1266 {
1267 uint32_t result;
1268
1269 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1270 return(result);
1271 }
1272
__SHADD8(uint32_t op1,uint32_t op2)1273 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1274 {
1275 uint32_t result;
1276
1277 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1278 return(result);
1279 }
1280
__UADD8(uint32_t op1,uint32_t op2)1281 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1282 {
1283 uint32_t result;
1284
1285 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1286 return(result);
1287 }
1288
__UQADD8(uint32_t op1,uint32_t op2)1289 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1290 {
1291 uint32_t result;
1292
1293 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1294 return(result);
1295 }
1296
__UHADD8(uint32_t op1,uint32_t op2)1297 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1298 {
1299 uint32_t result;
1300
1301 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1302 return(result);
1303 }
1304
1305
__SSUB8(uint32_t op1,uint32_t op2)1306 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1307 {
1308 uint32_t result;
1309
1310 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1311 return(result);
1312 }
1313
__QSUB8(uint32_t op1,uint32_t op2)1314 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1315 {
1316 uint32_t result;
1317
1318 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1319 return(result);
1320 }
1321
__SHSUB8(uint32_t op1,uint32_t op2)1322 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1323 {
1324 uint32_t result;
1325
1326 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1327 return(result);
1328 }
1329
__USUB8(uint32_t op1,uint32_t op2)1330 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1331 {
1332 uint32_t result;
1333
1334 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1335 return(result);
1336 }
1337
__UQSUB8(uint32_t op1,uint32_t op2)1338 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1339 {
1340 uint32_t result;
1341
1342 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1343 return(result);
1344 }
1345
__UHSUB8(uint32_t op1,uint32_t op2)1346 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1347 {
1348 uint32_t result;
1349
1350 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1351 return(result);
1352 }
1353
1354
__SADD16(uint32_t op1,uint32_t op2)1355 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1356 {
1357 uint32_t result;
1358
1359 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1360 return(result);
1361 }
1362
__QADD16(uint32_t op1,uint32_t op2)1363 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1364 {
1365 uint32_t result;
1366
1367 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1368 return(result);
1369 }
1370
__SHADD16(uint32_t op1,uint32_t op2)1371 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1372 {
1373 uint32_t result;
1374
1375 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1376 return(result);
1377 }
1378
__UADD16(uint32_t op1,uint32_t op2)1379 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1380 {
1381 uint32_t result;
1382
1383 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1384 return(result);
1385 }
1386
__UQADD16(uint32_t op1,uint32_t op2)1387 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1388 {
1389 uint32_t result;
1390
1391 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1392 return(result);
1393 }
1394
__UHADD16(uint32_t op1,uint32_t op2)1395 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1396 {
1397 uint32_t result;
1398
1399 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1400 return(result);
1401 }
1402
__SSUB16(uint32_t op1,uint32_t op2)1403 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1404 {
1405 uint32_t result;
1406
1407 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1408 return(result);
1409 }
1410
__QSUB16(uint32_t op1,uint32_t op2)1411 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1412 {
1413 uint32_t result;
1414
1415 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1416 return(result);
1417 }
1418
__SHSUB16(uint32_t op1,uint32_t op2)1419 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1420 {
1421 uint32_t result;
1422
1423 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1424 return(result);
1425 }
1426
__USUB16(uint32_t op1,uint32_t op2)1427 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1428 {
1429 uint32_t result;
1430
1431 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1432 return(result);
1433 }
1434
__UQSUB16(uint32_t op1,uint32_t op2)1435 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1436 {
1437 uint32_t result;
1438
1439 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1440 return(result);
1441 }
1442
__UHSUB16(uint32_t op1,uint32_t op2)1443 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1444 {
1445 uint32_t result;
1446
1447 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1448 return(result);
1449 }
1450
__SASX(uint32_t op1,uint32_t op2)1451 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1452 {
1453 uint32_t result;
1454
1455 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1456 return(result);
1457 }
1458
__QASX(uint32_t op1,uint32_t op2)1459 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1460 {
1461 uint32_t result;
1462
1463 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1464 return(result);
1465 }
1466
__SHASX(uint32_t op1,uint32_t op2)1467 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1468 {
1469 uint32_t result;
1470
1471 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1472 return(result);
1473 }
1474
__UASX(uint32_t op1,uint32_t op2)1475 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1476 {
1477 uint32_t result;
1478
1479 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1480 return(result);
1481 }
1482
__UQASX(uint32_t op1,uint32_t op2)1483 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1484 {
1485 uint32_t result;
1486
1487 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1488 return(result);
1489 }
1490
__UHASX(uint32_t op1,uint32_t op2)1491 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1492 {
1493 uint32_t result;
1494
1495 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1496 return(result);
1497 }
1498
__SSAX(uint32_t op1,uint32_t op2)1499 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1500 {
1501 uint32_t result;
1502
1503 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1504 return(result);
1505 }
1506
__QSAX(uint32_t op1,uint32_t op2)1507 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1508 {
1509 uint32_t result;
1510
1511 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1512 return(result);
1513 }
1514
__SHSAX(uint32_t op1,uint32_t op2)1515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1516 {
1517 uint32_t result;
1518
1519 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1520 return(result);
1521 }
1522
__USAX(uint32_t op1,uint32_t op2)1523 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1524 {
1525 uint32_t result;
1526
1527 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1528 return(result);
1529 }
1530
__UQSAX(uint32_t op1,uint32_t op2)1531 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1532 {
1533 uint32_t result;
1534
1535 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1536 return(result);
1537 }
1538
__UHSAX(uint32_t op1,uint32_t op2)1539 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1540 {
1541 uint32_t result;
1542
1543 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1544 return(result);
1545 }
1546
__USAD8(uint32_t op1,uint32_t op2)1547 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1548 {
1549 uint32_t result;
1550
1551 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1552 return(result);
1553 }
1554
__USADA8(uint32_t op1,uint32_t op2,uint32_t op3)1555 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1556 {
1557 uint32_t result;
1558
1559 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1560 return(result);
1561 }
1562
1563 #define __SSAT16(ARG1,ARG2) \
1564 ({ \
1565 int32_t __RES, __ARG1 = (ARG1); \
1566 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1567 __RES; \
1568 })
1569
1570 #define __USAT16(ARG1,ARG2) \
1571 ({ \
1572 uint32_t __RES, __ARG1 = (ARG1); \
1573 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1574 __RES; \
1575 })
1576
__UXTB16(uint32_t op1)1577 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
1578 {
1579 uint32_t result;
1580
1581 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1582 return(result);
1583 }
1584
__UXTAB16(uint32_t op1,uint32_t op2)1585 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1586 {
1587 uint32_t result;
1588
1589 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1590 return(result);
1591 }
1592
__SXTB16(uint32_t op1)1593 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
1594 {
1595 uint32_t result;
1596
1597 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1598 return(result);
1599 }
1600
__SXTAB16(uint32_t op1,uint32_t op2)1601 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
1602 {
1603 uint32_t result;
1604
1605 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1606 return(result);
1607 }
1608
__SMUAD(uint32_t op1,uint32_t op2)1609 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
1610 {
1611 uint32_t result;
1612
1613 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1614 return(result);
1615 }
1616
__SMUADX(uint32_t op1,uint32_t op2)1617 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
1618 {
1619 uint32_t result;
1620
1621 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1622 return(result);
1623 }
1624
__SMLAD(uint32_t op1,uint32_t op2,uint32_t op3)1625 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
1626 {
1627 uint32_t result;
1628
1629 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1630 return(result);
1631 }
1632
__SMLADX(uint32_t op1,uint32_t op2,uint32_t op3)1633 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
1634 {
1635 uint32_t result;
1636
1637 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1638 return(result);
1639 }
1640
__SMLALD(uint32_t op1,uint32_t op2,uint64_t acc)1641 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
1642 {
1643 union llreg_u{
1644 uint32_t w32[2];
1645 uint64_t w64;
1646 } llr;
1647 llr.w64 = acc;
1648
1649 #ifndef __ARMEB__ /* Little endian */
1650 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1651 #else /* Big endian */
1652 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1653 #endif
1654
1655 return(llr.w64);
1656 }
1657
__SMLALDX(uint32_t op1,uint32_t op2,uint64_t acc)1658 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
1659 {
1660 union llreg_u{
1661 uint32_t w32[2];
1662 uint64_t w64;
1663 } llr;
1664 llr.w64 = acc;
1665
1666 #ifndef __ARMEB__ /* Little endian */
1667 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1668 #else /* Big endian */
1669 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1670 #endif
1671
1672 return(llr.w64);
1673 }
1674
__SMUSD(uint32_t op1,uint32_t op2)1675 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
1676 {
1677 uint32_t result;
1678
1679 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1680 return(result);
1681 }
1682
__SMUSDX(uint32_t op1,uint32_t op2)1683 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
1684 {
1685 uint32_t result;
1686
1687 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1688 return(result);
1689 }
1690
__SMLSD(uint32_t op1,uint32_t op2,uint32_t op3)1691 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
1692 {
1693 uint32_t result;
1694
1695 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1696 return(result);
1697 }
1698
__SMLSDX(uint32_t op1,uint32_t op2,uint32_t op3)1699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
1700 {
1701 uint32_t result;
1702
1703 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1704 return(result);
1705 }
1706
__SMLSLD(uint32_t op1,uint32_t op2,uint64_t acc)1707 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
1708 {
1709 union llreg_u{
1710 uint32_t w32[2];
1711 uint64_t w64;
1712 } llr;
1713 llr.w64 = acc;
1714
1715 #ifndef __ARMEB__ /* Little endian */
1716 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1717 #else /* Big endian */
1718 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1719 #endif
1720
1721 return(llr.w64);
1722 }
1723
__SMLSLDX(uint32_t op1,uint32_t op2,uint64_t acc)1724 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
1725 {
1726 union llreg_u{
1727 uint32_t w32[2];
1728 uint64_t w64;
1729 } llr;
1730 llr.w64 = acc;
1731
1732 #ifndef __ARMEB__ /* Little endian */
1733 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1734 #else /* Big endian */
1735 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1736 #endif
1737
1738 return(llr.w64);
1739 }
1740
__SEL(uint32_t op1,uint32_t op2)1741 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
1742 {
1743 uint32_t result;
1744
1745 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1746 return(result);
1747 }
1748
__QADD(int32_t op1,int32_t op2)1749 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
1750 {
1751 int32_t result;
1752
1753 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1754 return(result);
1755 }
1756
__QSUB(int32_t op1,int32_t op2)1757 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
1758 {
1759 int32_t result;
1760
1761 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1762 return(result);
1763 }
1764
1765 #if 0
1766 #define __PKHBT(ARG1,ARG2,ARG3) \
1767 ({ \
1768 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
1769 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1770 __RES; \
1771 })
1772
1773 #define __PKHTB(ARG1,ARG2,ARG3) \
1774 ({ \
1775 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
1776 if (ARG3 == 0) \
1777 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
1778 else \
1779 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1780 __RES; \
1781 })
1782 #endif
1783
1784 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1785 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1786
1787 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1788 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1789
__SMMLA(int32_t op1,int32_t op2,int32_t op3)1790 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1791 {
1792 int32_t result;
1793
1794 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1795 return(result);
1796 }
1797
1798 #endif /* (__ARM_FEATURE_DSP == 1) */
1799 /*@} end of group CMSIS_SIMD_intrinsics */
1800
1801
1802 #endif /* __CMSIS_ARMCLANG_H */
1803