1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16 (+) Access to VREFBUF registers
17
18 @endverbatim
19 ******************************************************************************
20 * @attention
21 *
22 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
23 * All rights reserved.</center></h2>
24 *
25 * This software component is licensed by ST under BSD 3-Clause license,
26 * the "License"; You may not use this file except in compliance with the
27 * License. You may obtain a copy of the License at:
28 * opensource.org/licenses/BSD-3-Clause
29 *
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef STM32WBxx_LL_SYSTEM_H
35 #define STM32WBxx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32wbxx.h"
43
44 /** @addtogroup STM32WBxx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /**
63 * @}
64 */
65
66 /* Private macros ------------------------------------------------------------*/
67
68 /* Exported types ------------------------------------------------------------*/
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
71 * @{
72 */
73
74 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
75 * @{
76 */
77 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
78 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
79 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
80 #if defined(QUADSPI)
81 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
82 #endif
83 /**
84 * @}
85 */
86
87 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
88 * @{
89 */
90 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
91 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
92 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
93 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
94 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
95 #if defined(I2C3)
96 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
97 #endif
98 /**
99 * @}
100 */
101
102 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
103 * @{
104 */
105 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
106 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
107 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
108 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
109 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
110 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
111 /**
112 * @}
113 */
114
115 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
116 * @{
117 */
118 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
119 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
120 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
121 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
122 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
123 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
124 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
125 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
126 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
127 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
128 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
129 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
130 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
131 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
132 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
133 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
134 /**
135 * @}
136 */
137
138 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
139 * @{
140 */
141 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
142 with Break Input of TIM1/16/17 */
143 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
144 with TIM1/16/17 Break Input
145 and also the PVDE and PLS bits of the Power Control Interface */
146 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
147 with Break Input of TIM1/16/17 */
148 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
149 with Break Input of TIM1/16/17 */
150 /**
151 * @}
152 */
153
154 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRITE PROTECTION
155 * @{
156 */
157 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR1_PAGE0 /*!< SRAM2A Write protection page 0 */
158 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR1_PAGE1 /*!< SRAM2A Write protection page 1 */
159 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR1_PAGE2 /*!< SRAM2A Write protection page 2 */
160 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR1_PAGE3 /*!< SRAM2A Write protection page 3 */
161 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR1_PAGE4 /*!< SRAM2A Write protection page 4 */
162 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR1_PAGE5 /*!< SRAM2A Write protection page 5 */
163 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR1_PAGE6 /*!< SRAM2A Write protection page 6 */
164 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR1_PAGE7 /*!< SRAM2A Write protection page 7 */
165 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR1_PAGE8 /*!< SRAM2A Write protection page 8 */
166 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR1_PAGE9 /*!< SRAM2A Write protection page 9 */
167 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR1_PAGE10 /*!< SRAM2A Write protection page 10 */
168 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR1_PAGE11 /*!< SRAM2A Write protection page 11 */
169 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR1_PAGE12 /*!< SRAM2A Write protection page 12 */
170 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR1_PAGE13 /*!< SRAM2A Write protection page 13 */
171 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR1_PAGE14 /*!< SRAM2A Write protection page 14 */
172 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR1_PAGE15 /*!< SRAM2A Write protection page 15 */
173 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR1_PAGE16 /*!< SRAM2A Write protection page 16 */
174 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR1_PAGE17 /*!< SRAM2A Write protection page 17 */
175 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR1_PAGE18 /*!< SRAM2A Write protection page 18 */
176 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR1_PAGE19 /*!< SRAM2A Write protection page 19 */
177 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR1_PAGE20 /*!< SRAM2A Write protection page 20 */
178 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR1_PAGE21 /*!< SRAM2A Write protection page 21 */
179 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR1_PAGE22 /*!< SRAM2A Write protection page 22 */
180 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR1_PAGE23 /*!< SRAM2A Write protection page 23 */
181 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR1_PAGE24 /*!< SRAM2A Write protection page 24 */
182 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR1_PAGE25 /*!< SRAM2A Write protection page 25 */
183 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR1_PAGE26 /*!< SRAM2A Write protection page 26 */
184 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR1_PAGE27 /*!< SRAM2A Write protection page 27 */
185 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR1_PAGE28 /*!< SRAM2A Write protection page 28 */
186 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR1_PAGE29 /*!< SRAM2A Write protection page 29 */
187 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR1_PAGE30 /*!< SRAM2A Write protection page 30 */
188 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR1_PAGE31 /*!< SRAM2A Write protection page 31 */
189
190 #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2B Write protection page 32 */
191 #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2B Write protection page 33 */
192 #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2B Write protection page 34 */
193 #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2B Write protection page 35 */
194 #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2B Write protection page 36 */
195 #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2B Write protection page 37 */
196 #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2B Write protection page 38 */
197 #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2B Write protection page 39 */
198 #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2B Write protection page 40 */
199 #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2B Write protection page 41 */
200 #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2B Write protection page 42 */
201 #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2B Write protection page 43 */
202 #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2B Write protection page 44 */
203 #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2B Write protection page 45 */
204 #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2B Write protection page 46 */
205 #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2B Write protection page 47 */
206 #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2B Write protection page 48 */
207 #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2B Write protection page 49 */
208 #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2B Write protection page 50 */
209 #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2B Write protection page 51 */
210 #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2B Write protection page 52 */
211 #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2B Write protection page 53 */
212 #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2B Write protection page 54 */
213 #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2B Write protection page 55 */
214 #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2B Write protection page 56 */
215 #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2B Write protection page 57 */
216 #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2B Write protection page 58 */
217 #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2B Write protection page 59 */
218 #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2B Write protection page 60 */
219 #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2B Write protection page 61 */
220 #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2B Write protection page 62 */
221 #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2B Write protection page 63 */
222 /**
223 * @}
224 */
225
226 /** @defgroup SYSTEM_LL_EC_IM SYSCFG CPU1 INTERRUPT MASK
227 * @{
228 */
229 #define LL_SYSCFG_GRP1_TIM1 SYSCFG_IMR1_TIM1IM /*!< Enabling of interrupt from Timer 1 to CPU1 */
230 #define LL_SYSCFG_GRP1_TIM16 SYSCFG_IMR1_TIM16IM /*!< Enabling of interrupt from Timer 16 to CPU1 */
231 #define LL_SYSCFG_GRP1_TIM17 SYSCFG_IMR1_TIM17IM /*!< Enabling of interrupt from Timer 17 to CPU1 */
232
233 #define LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */
234 #define LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */
235 #define LL_SYSCFG_GRP1_EXTI7 SYSCFG_IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */
236 #define LL_SYSCFG_GRP1_EXTI8 SYSCFG_IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */
237 #define LL_SYSCFG_GRP1_EXTI9 SYSCFG_IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */
238 #define LL_SYSCFG_GRP1_EXTI10 SYSCFG_IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */
239 #define LL_SYSCFG_GRP1_EXTI11 SYSCFG_IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */
240 #define LL_SYSCFG_GRP1_EXTI12 SYSCFG_IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */
241 #define LL_SYSCFG_GRP1_EXTI13 SYSCFG_IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */
242 #define LL_SYSCFG_GRP1_EXTI14 SYSCFG_IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */
243 #define LL_SYSCFG_GRP1_EXTI15 SYSCFG_IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */
244
245 #if defined(SYSCFG_IMR2_PVM1IM)
246 #define LL_SYSCFG_GRP2_PVM1 SYSCFG_IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU1 */
247 #endif
248 #define LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */
249 #define LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */
250 /**
251 * @}
252 */
253
254 /** @defgroup SYSTEM_LL_EC_C2_IM SYSCFG CPU2 INTERRUPT MASK
255 * @{
256 */
257 #define LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers
258 and LSE Clock Security System to CPU2 */
259 #define LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM /*!< Enabling of interrupt from RTC Wakeup to CPU2 */
260 #define LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM /*!< Enabling of interrupt from RTC Alarms to CPU2 */
261 #define LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM /*!< Enabling of interrupt from RCC to CPU2 */
262 #define LL_C2_SYSCFG_GRP1_FLASH SYSCFG_C2IMR1_FLASHIM /*!< Enabling of interrupt from FLASH to CPU2 */
263 #define LL_C2_SYSCFG_GRP1_PKA SYSCFG_C2IMR1_PKAIM /*!< Enabling of interrupt from Public Key Accelerator to CPU2 */
264 #define LL_C2_SYSCFG_GRP1_RNG SYSCFG_C2IMR1_RNGIM /*!< Enabling of interrupt from Random Number Generator to CPU2 */
265 #if defined(AES1)
266 #define LL_C2_SYSCFG_GRP1_AES1 SYSCFG_C2IMR1_AES1IM /*!< Enabling of interrupt from Advanced Encryption Standard 1 to CPU2 */
267 #endif
268 #if defined(COMP1)
269 #define LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM /*!< Enabling of interrupt from Comparator to CPU2 */
270 #endif
271 #define LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */
272
273 #define LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */
274 #define LL_C2_SYSCFG_GRP1_EXTI1 SYSCFG_C2IMR1_EXTI1IM /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */
275 #define LL_C2_SYSCFG_GRP1_EXTI2 SYSCFG_C2IMR1_EXTI2IM /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */
276 #define LL_C2_SYSCFG_GRP1_EXTI3 SYSCFG_C2IMR1_EXTI3IM /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */
277 #define LL_C2_SYSCFG_GRP1_EXTI4 SYSCFG_C2IMR1_EXTI4IM /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */
278 #define LL_C2_SYSCFG_GRP1_EXTI5 SYSCFG_C2IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */
279 #define LL_C2_SYSCFG_GRP1_EXTI6 SYSCFG_C2IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */
280 #define LL_C2_SYSCFG_GRP1_EXTI7 SYSCFG_C2IMR1_EXTI7IM /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */
281 #define LL_C2_SYSCFG_GRP1_EXTI8 SYSCFG_C2IMR1_EXTI8IM /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */
282 #define LL_C2_SYSCFG_GRP1_EXTI9 SYSCFG_C2IMR1_EXTI9IM /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */
283 #define LL_C2_SYSCFG_GRP1_EXTI10 SYSCFG_C2IMR1_EXTI10IM /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */
284 #define LL_C2_SYSCFG_GRP1_EXTI11 SYSCFG_C2IMR1_EXTI11IM /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */
285 #define LL_C2_SYSCFG_GRP1_EXTI12 SYSCFG_C2IMR1_EXTI12IM /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */
286 #define LL_C2_SYSCFG_GRP1_EXTI13 SYSCFG_C2IMR1_EXTI13IM /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */
287 #define LL_C2_SYSCFG_GRP1_EXTI14 SYSCFG_C2IMR1_EXTI14IM /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */
288 #define LL_C2_SYSCFG_GRP1_EXTI15 SYSCFG_C2IMR1_EXTI15IM /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */
289
290 #define LL_C2_SYSCFG_GRP2_DMA1CH1 SYSCFG_C2IMR2_DMA1CH1IM /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */
291 #define LL_C2_SYSCFG_GRP2_DMA1CH2 SYSCFG_C2IMR2_DMA1CH2IM /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */
292 #define LL_C2_SYSCFG_GRP2_DMA1CH3 SYSCFG_C2IMR2_DMA1CH3IM /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */
293 #define LL_C2_SYSCFG_GRP2_DMA1CH4 SYSCFG_C2IMR2_DMA1CH4IM /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */
294 #define LL_C2_SYSCFG_GRP2_DMA1CH5 SYSCFG_C2IMR2_DMA1CH5IM /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */
295 #define LL_C2_SYSCFG_GRP2_DMA1CH6 SYSCFG_C2IMR2_DMA1CH6IM /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */
296 #define LL_C2_SYSCFG_GRP2_DMA1CH7 SYSCFG_C2IMR2_DMA1CH7IM /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */
297
298 #if defined(DMA2)
299 #define LL_C2_SYSCFG_GRP2_DMA2CH1 SYSCFG_C2IMR2_DMA2CH1IM /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2 */
300 #define LL_C2_SYSCFG_GRP2_DMA2CH2 SYSCFG_C2IMR2_DMA2CH2IM /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2 */
301 #define LL_C2_SYSCFG_GRP2_DMA2CH3 SYSCFG_C2IMR2_DMA2CH3IM /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2 */
302 #define LL_C2_SYSCFG_GRP2_DMA2CH4 SYSCFG_C2IMR2_DMA2CH4IM /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2 */
303 #define LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */
304 #define LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */
305 #define LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */
306 #endif
307
308 #define LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM /*!< Enabling of interrupt from DMAMUX1 to CPU2 */
309 #if defined(SYSCFG_C2IMR2_PVM1IM)
310 #define LL_C2_SYSCFG_GRP2_PVM1 SYSCFG_C2IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU2 */
311 #endif
312 #define LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */
313 #define LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */
314 #define LL_C2_SYSCFG_GRP2_TSC SYSCFG_C2IMR2_TSCIM /*!< Enabling of interrupt from Touch Sensing Controller to CPU2 */
315 #if defined(LCD)
316 #define LL_C2_SYSCFG_GRP2_LCD SYSCFG_C2IMR2_LCDIM /*!< Enabling of interrupt from Liquid Crystal Display to CPU2 */
317 #endif
318 /**
319 * @}
320 */
321
322 /** @defgroup SYSTEM_LL_EC_SECURE_IP_ACCESS SYSCFG SECURE IP ACCESS
323 * @{
324 */
325 #if defined(AES1)
326 #define LL_SYSCFG_SECURE_ACCESS_AES1 SYSCFG_SIPCR_SAES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
327 #endif
328 #define LL_SYSCFG_SECURE_ACCESS_AES2 SYSCFG_SIPCR_SAES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */
329 #define LL_SYSCFG_SECURE_ACCESS_PKA SYSCFG_SIPCR_SPKA /*!< Enabling the security access of Public Key Accelerator */
330 #define LL_SYSCFG_SECURE_ACCESS_RNG SYSCFG_SIPCR_SRNG /*!< Enabling the security access of Random Number Generator */
331 /**
332 * @}
333 */
334
335 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU CPU1 APB1 GRP1 STOP IP
336 * @{
337 */
338 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */
339 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */
340 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted */
341 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */
342 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
343 #if defined(I2C3)
344 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
345 #endif
346 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
347 /**
348 * @}
349 */
350
351 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP1_STOP_IP DBGMCU CPU2 APB1 GRP1 STOP IP
352 * @{
353 */
354 #define LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted */
355 #define LL_C2_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted */
356 #define LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted */
357 #define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
358 #if defined(I2C3)
359 #define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
360 #endif
361 #define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
362 /**
363 * @}
364 */
365
366 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU CPU1 APB1 GRP2 STOP IP
367 * @{
368 */
369 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
370 /**
371 * @}
372 */
373
374 /** @defgroup SYSTEM_LL_EC_C2_APB1_GRP2_STOP_IP DBGMCU CPU2 APB1 GRP2 STOP IP
375 * @{
376 */
377 #define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
378 /**
379 * @}
380 */
381
382 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU CPU1 APB2 GRP1 STOP IP
383 * @{
384 */
385 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
386 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
387 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
388 /**
389 * @}
390 */
391
392 /** @defgroup SYSTEM_LL_EC_C2_APB2_GRP1_STOP_IP DBGMCU CPU2 APB2 GRP1 STOP IP
393 * @{
394 */
395 #define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
396 #define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
397 #define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
398 /**
399 * @}
400 */
401
402 #if defined(VREFBUF)
403 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
404 * @{
405 */
406 #define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREF_OUT1) */
407 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
408 /**
409 * @}
410 */
411 #endif /* VREFBUF */
412
413 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
414 * @{
415 */
416 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
417 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
418 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
419 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
420
421 /**
422 * @}
423 */
424
425 /**
426 * @}
427 */
428
429 /* Exported macro ------------------------------------------------------------*/
430
431 /* Exported functions --------------------------------------------------------*/
432 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
433 * @{
434 */
435
436 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
437 * @{
438 */
439
440 /**
441 * @brief Set memory mapping at address 0x00000000
442 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
443 * @param Memory This parameter can be one of the following values:
444 * @arg @ref LL_SYSCFG_REMAP_FLASH
445 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
446 * @arg @ref LL_SYSCFG_REMAP_SRAM
447 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
448 * @retval None
449 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)450 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
451 {
452 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
453 }
454
455 /**
456 * @brief Get memory mapping at address 0x00000000
457 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
458 * @retval Returned value can be one of the following values:
459 * @arg @ref LL_SYSCFG_REMAP_FLASH
460 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
461 * @arg @ref LL_SYSCFG_REMAP_SRAM
462 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
463 */
LL_SYSCFG_GetRemapMemory(void)464 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
465 {
466 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
467 }
468
469 /**
470 * @brief Enable I/O analog switch voltage booster.
471 * @note When voltage booster is enabled, I/O analog switches are supplied
472 * by a dedicated voltage booster, from VDD power domain. This is
473 * the recommended configuration with low VDDA voltage operation.
474 * @note The I/O analog switch voltage booster is relevant for peripherals
475 * using I/O in analog input: ADC and COMP.
476 * However, COMP inputs have a high impedance and
477 * voltage booster do not impact performance significantly.
478 * Therefore, the voltage booster is mainly intended for
479 * usage with ADC.
480 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
481 * @retval None
482 */
LL_SYSCFG_EnableAnalogBooster(void)483 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
484 {
485 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
486 }
487
488 /**
489 * @brief Disable I/O analog switch voltage booster.
490 * @note When voltage booster is enabled, I/O analog switches are supplied
491 * by a dedicated voltage booster, from VDD power domain. This is
492 * the recommended configuration with low VDDA voltage operation.
493 * @note The I/O analog switch voltage booster is relevant for peripherals
494 * using I/O in analog input: ADC and COMP.
495 * However, COMP inputs have a high impedance and
496 * voltage booster do not impact performance significantly.
497 * Therefore, the voltage booster is mainly intended for
498 * usage with ADC.
499 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
500 * @retval None
501 */
LL_SYSCFG_DisableAnalogBooster(void)502 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
503 {
504 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
505 }
506
507 /**
508 * @brief Enable the Analog GPIO switch to control voltage selection
509 * when the supply voltage is supplied by VDDA
510 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogGpioSwitch
511 * @note Activating the gpio switch enable IOs analog switches supplied by VDDA
512 * @retval None
513 */
LL_SYSCFG_EnableAnalogGpioSwitch(void)514 __STATIC_INLINE void LL_SYSCFG_EnableAnalogGpioSwitch(void)
515 {
516 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
517 }
518
519 /**
520 * @brief Disable the Analog GPIO switch to control voltage selection
521 * when the supply voltage is supplied by VDDA
522 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogGpioSwitch
523 * @note Activating the gpio switch enable IOs analog switches supplied by VDDA
524 * @retval None
525 */
LL_SYSCFG_DisableAnalogGpioSwitch(void)526 __STATIC_INLINE void LL_SYSCFG_DisableAnalogGpioSwitch(void)
527 {
528 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
529 }
530
531 /**
532 * @brief Enable the I2C fast mode plus driving capability.
533 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
534 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
535 * @param ConfigFastModePlus This parameter can be a combination of the following values:
536 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
537 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
540 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
541 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
542 * @retval None
543 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)544 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
545 {
546 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
547 }
548
549 /**
550 * @brief Disable the I2C fast mode plus driving capability.
551 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
552 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
553 * @param ConfigFastModePlus This parameter can be a combination of the following values:
554 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
555 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
556 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
557 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
558 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
559 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
560 * @retval None
561 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)562 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
563 {
564 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
565 }
566
567 /**
568 * @brief Enable Floating Point Unit Invalid operation Interrupt
569 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
570 * @retval None
571 */
LL_SYSCFG_EnableIT_FPU_IOC(void)572 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
573 {
574 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
575 }
576
577 /**
578 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
579 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
580 * @retval None
581 */
LL_SYSCFG_EnableIT_FPU_DZC(void)582 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
583 {
584 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
585 }
586
587 /**
588 * @brief Enable Floating Point Unit Underflow Interrupt
589 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
590 * @retval None
591 */
LL_SYSCFG_EnableIT_FPU_UFC(void)592 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
593 {
594 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
595 }
596
597 /**
598 * @brief Enable Floating Point Unit Overflow Interrupt
599 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
600 * @retval None
601 */
LL_SYSCFG_EnableIT_FPU_OFC(void)602 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
603 {
604 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
605 }
606
607 /**
608 * @brief Enable Floating Point Unit Input denormal Interrupt
609 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
610 * @retval None
611 */
LL_SYSCFG_EnableIT_FPU_IDC(void)612 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
613 {
614 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
615 }
616
617 /**
618 * @brief Enable Floating Point Unit Inexact Interrupt
619 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
620 * @retval None
621 */
LL_SYSCFG_EnableIT_FPU_IXC(void)622 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
623 {
624 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
625 }
626
627 /**
628 * @brief Disable Floating Point Unit Invalid operation Interrupt
629 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
630 * @retval None
631 */
LL_SYSCFG_DisableIT_FPU_IOC(void)632 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
633 {
634 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
635 }
636
637 /**
638 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
639 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
640 * @retval None
641 */
LL_SYSCFG_DisableIT_FPU_DZC(void)642 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
643 {
644 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
645 }
646
647 /**
648 * @brief Disable Floating Point Unit Underflow Interrupt
649 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
650 * @retval None
651 */
LL_SYSCFG_DisableIT_FPU_UFC(void)652 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
653 {
654 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
655 }
656
657 /**
658 * @brief Disable Floating Point Unit Overflow Interrupt
659 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
660 * @retval None
661 */
LL_SYSCFG_DisableIT_FPU_OFC(void)662 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
663 {
664 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
665 }
666
667 /**
668 * @brief Disable Floating Point Unit Input denormal Interrupt
669 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
670 * @retval None
671 */
LL_SYSCFG_DisableIT_FPU_IDC(void)672 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
673 {
674 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
675 }
676
677 /**
678 * @brief Disable Floating Point Unit Inexact Interrupt
679 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
680 * @retval None
681 */
LL_SYSCFG_DisableIT_FPU_IXC(void)682 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
683 {
684 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
685 }
686
687 /**
688 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
689 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
690 * @retval State of bit (1 or 0).
691 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)692 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
693 {
694 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
695 }
696
697 /**
698 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
699 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
700 * @retval State of bit (1 or 0).
701 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)702 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
703 {
704 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
705 }
706
707 /**
708 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
709 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
710 * @retval State of bit (1 or 0).
711 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)712 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
713 {
714 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
715 }
716
717 /**
718 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
719 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
720 * @retval State of bit (1 or 0).
721 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)722 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
723 {
724 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
725 }
726
727 /**
728 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
729 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
730 * @retval State of bit (1 or 0).
731 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)732 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
733 {
734 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
735 }
736
737 /**
738 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
739 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
740 * @retval State of bit (1 or 0).
741 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)742 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
743 {
744 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
745 }
746
747 /**
748 * @brief Configure source input for the EXTI external interrupt.
749 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
750 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
751 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
752 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
753 * @param Port This parameter can be one of the following values:
754 * @arg @ref LL_SYSCFG_EXTI_PORTA
755 * @arg @ref LL_SYSCFG_EXTI_PORTB
756 * @arg @ref LL_SYSCFG_EXTI_PORTC
757 * @arg @ref LL_SYSCFG_EXTI_PORTD
758 * @arg @ref LL_SYSCFG_EXTI_PORTE
759 * @arg @ref LL_SYSCFG_EXTI_PORTH
760 *
761 * @param Line This parameter can be one of the following values:
762 * @arg @ref LL_SYSCFG_EXTI_LINE0
763 * @arg @ref LL_SYSCFG_EXTI_LINE1
764 * @arg @ref LL_SYSCFG_EXTI_LINE2
765 * @arg @ref LL_SYSCFG_EXTI_LINE3
766 * @arg @ref LL_SYSCFG_EXTI_LINE4
767 * @arg @ref LL_SYSCFG_EXTI_LINE5
768 * @arg @ref LL_SYSCFG_EXTI_LINE6
769 * @arg @ref LL_SYSCFG_EXTI_LINE7
770 * @arg @ref LL_SYSCFG_EXTI_LINE8
771 * @arg @ref LL_SYSCFG_EXTI_LINE9
772 * @arg @ref LL_SYSCFG_EXTI_LINE10
773 * @arg @ref LL_SYSCFG_EXTI_LINE11
774 * @arg @ref LL_SYSCFG_EXTI_LINE12
775 * @arg @ref LL_SYSCFG_EXTI_LINE13
776 * @arg @ref LL_SYSCFG_EXTI_LINE14
777 * @arg @ref LL_SYSCFG_EXTI_LINE15
778 * @retval None
779 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)780 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
781 {
782 MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U), (Port << ((POSITION_VAL((Line >> 16U))) & 0x0000000FUL)));
783 }
784
785 /**
786 * @brief Get the configured defined for specific EXTI Line
787 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
788 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
789 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
790 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
791 * @param Line This parameter can be one of the following values:
792 * @arg @ref LL_SYSCFG_EXTI_LINE0
793 * @arg @ref LL_SYSCFG_EXTI_LINE1
794 * @arg @ref LL_SYSCFG_EXTI_LINE2
795 * @arg @ref LL_SYSCFG_EXTI_LINE3
796 * @arg @ref LL_SYSCFG_EXTI_LINE4
797 * @arg @ref LL_SYSCFG_EXTI_LINE5
798 * @arg @ref LL_SYSCFG_EXTI_LINE6
799 * @arg @ref LL_SYSCFG_EXTI_LINE7
800 * @arg @ref LL_SYSCFG_EXTI_LINE8
801 * @arg @ref LL_SYSCFG_EXTI_LINE9
802 * @arg @ref LL_SYSCFG_EXTI_LINE10
803 * @arg @ref LL_SYSCFG_EXTI_LINE11
804 * @arg @ref LL_SYSCFG_EXTI_LINE12
805 * @arg @ref LL_SYSCFG_EXTI_LINE13
806 * @arg @ref LL_SYSCFG_EXTI_LINE14
807 * @arg @ref LL_SYSCFG_EXTI_LINE15
808 * @retval Returned value can be one of the following values:
809 * @arg @ref LL_SYSCFG_EXTI_PORTA
810 * @arg @ref LL_SYSCFG_EXTI_PORTB
811 * @arg @ref LL_SYSCFG_EXTI_PORTC
812 * @arg @ref LL_SYSCFG_EXTI_PORTD
813 * @arg @ref LL_SYSCFG_EXTI_PORTE
814 * @arg @ref LL_SYSCFG_EXTI_PORTH
815 */
LL_SYSCFG_GetEXTISource(uint32_t Line)816 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
817 {
818 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x0000000FUL) );
819 }
820
821 /**
822 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
823 * automatically cleared at the end of the SRAM2 erase operation.)
824 * @note This bit is write-protected: setting this bit is possible only after the
825 * correct key sequence is written in the SYSCFG_SKR register.
826 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
827 * @retval None
828 */
LL_SYSCFG_EnableSRAM2Erase(void)829 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
830 {
831 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
832 }
833
834 /**
835 * @brief Check if SRAM2 erase operation is on going
836 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
837 * @retval State of bit (1 or 0).
838 */
LL_SYSCFG_IsSRAM2EraseOngoing(void)839 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
840 {
841 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)) ? 1UL : 0UL);
842 }
843
844 /**
845 * @brief Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware
846 * and will only be reset by a Hardware reset, including a reset after Standby.)
847 * @note Firmware writing 0 has no effect.
848 * @rmtoll SYSCFG_SCSR C2RFD LL_SYSCFG_DisableSRAMFetch
849 * @retval None
850 */
LL_SYSCFG_DisableSRAMFetch(void)851 __STATIC_INLINE void LL_SYSCFG_DisableSRAMFetch(void)
852 {
853 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_C2RFD);
854 }
855
856 /**
857 * @brief Check if CPU2 SRAM fetch is enabled
858 * @rmtoll SYSCFG_SCSR C2RFD LL_SYSCFG_IsEnabledSRAMFetch
859 * @retval State of bit (1 or 0).
860 */
LL_SYSCFG_IsEnabledSRAMFetch(void)861 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMFetch(void)
862 {
863 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_C2RFD) != (SYSCFG_SCSR_C2RFD)) ? 1UL : 0UL);
864 }
865
866 /**
867 * @brief Set connections to TIM1/16/17 Break inputs
868 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
869 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
870 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
871 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
872 * @param Break This parameter can be a combination of the following values:
873 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
874 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
875 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
876 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
877 * @retval None
878 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)879 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
880 {
881 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
882 }
883
884 /**
885 * @brief Get connections to TIM1/16/17 Break inputs
886 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
887 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
888 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
889 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
890 * @retval Returned value can be can be a combination of the following values:
891 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
892 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
893 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
894 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
895 */
LL_SYSCFG_GetTIMBreakInputs(void)896 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
897 {
898 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
899 }
900
901 /**
902 * @brief Check if SRAM2 parity error detected
903 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
904 * @retval State of bit (1 or 0).
905 */
LL_SYSCFG_IsActiveFlag_SP(void)906 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
907 {
908 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
909 }
910
911 /**
912 * @brief Clear SRAM2 parity error flag
913 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
914 * @retval None
915 */
LL_SYSCFG_ClearFlag_SP(void)916 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
917 {
918 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
919 }
920
921 /**
922 * @brief Enable SRAM2 page write protection for Pages in range 0 to 31
923 * @note Write protection is cleared only by a system reset
924 * @rmtoll SYSCFG_SWPR1 PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
925 * @param SRAM2WRP This parameter can be a combination of the following values:
926 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
927 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
928 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
929 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
930 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
931 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
932 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
933 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
934 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
935 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
936 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
937 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
938 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
939 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
940 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
941 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
942 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16
943 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17
944 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18
945 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19
946 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20
947 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21
948 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22
949 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23
950 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24
951 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25
952 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26
953 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27
954 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28
955 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29
956 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30
957 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31
958 * @retval None
959 */
960 /* Legacy define */
961 #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)962 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
963 {
964 SET_BIT(SYSCFG->SWPR1, SRAM2WRP);
965 }
966
967 /**
968 * @brief Enable SRAM2 page write protection for Pages in range 32 to 63
969 * @note Write protection is cleared only by a system reset
970 * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
971 * @param SRAM2WRP This parameter can be a combination of the following values:
972 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32
973 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33
974 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34
975 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35
976 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36
977 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37
978 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38
979 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39
980 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40
981 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41
982 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42
983 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43
984 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44
985 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45
986 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46
987 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47
988 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48
989 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49
990 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50
991 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51
992 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52
993 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53
994 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54
995 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55
996 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56
997 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57
998 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58
999 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59
1000 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60
1001 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61
1002 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62
1003 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63
1004 * @retval None
1005 */
LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)1006 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
1007 {
1008 SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
1009 }
1010
1011 /**
1012 * @brief SRAM2 page write protection lock prior to erase
1013 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
1014 * @retval None
1015 */
LL_SYSCFG_LockSRAM2WRP(void)1016 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
1017 {
1018 /* Writing a wrong key reactivates the write protection */
1019 WRITE_REG(SYSCFG->SKR, 0x00U);
1020 }
1021
1022 /**
1023 * @brief SRAM2 page write protection unlock prior to erase
1024 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
1025 * @retval None
1026 */
LL_SYSCFG_UnlockSRAM2WRP(void)1027 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
1028 {
1029 /* unlock the write protection of the SRAM2ER bit */
1030 WRITE_REG(SYSCFG->SKR, 0xCAU);
1031 WRITE_REG(SYSCFG->SKR, 0x53U);
1032 }
1033
1034 /**
1035 * @brief Enable CPU1 Interrupt Mask
1036 * @rmtoll SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_EnableIT\n
1037 * SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_EnableIT\n
1038 * SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_EnableIT\n
1039 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_EnableIT
1040 * @param Interrupt This parameter can be a combination of the following values:
1041 * @arg @ref LL_SYSCFG_GRP1_TIM1
1042 * @arg @ref LL_SYSCFG_GRP1_TIM16
1043 * @arg @ref LL_SYSCFG_GRP1_TIM17
1044 * @arg @ref LL_SYSCFG_GRP1_EXTI5
1045 * @arg @ref LL_SYSCFG_GRP1_EXTI6
1046 * @arg @ref LL_SYSCFG_GRP1_EXTI7
1047 * @arg @ref LL_SYSCFG_GRP1_EXTI8
1048 * @arg @ref LL_SYSCFG_GRP1_EXTI9
1049 * @arg @ref LL_SYSCFG_GRP1_EXTI10
1050 * @arg @ref LL_SYSCFG_GRP1_EXTI11
1051 * @arg @ref LL_SYSCFG_GRP1_EXTI12
1052 * @arg @ref LL_SYSCFG_GRP1_EXTI13
1053 * @arg @ref LL_SYSCFG_GRP1_EXTI14
1054 * @arg @ref LL_SYSCFG_GRP1_EXTI15
1055 * @retval None
1056 */
LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)1057 __STATIC_INLINE void LL_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
1058 {
1059 CLEAR_BIT(SYSCFG->IMR1, Interrupt);
1060 }
1061
1062 /**
1063 * @brief Enable CPU1 Interrupt Mask
1064 * @rmtoll SYSCFG_IMR1 PVM1IM LL_SYSCFG_GRP2_EnableIT\n
1065 * SYSCFG_IMR1 PVM3IM LL_SYSCFG_GRP2_EnableIT\n
1066 * SYSCFG_IMR1 PVDIM LL_SYSCFG_GRP2_EnableIT
1067 * @param Interrupt This parameter can be a combination of the following values:
1068 * @arg @ref LL_SYSCFG_GRP2_PVM1
1069 * @arg @ref LL_SYSCFG_GRP2_PVM3
1070 * @arg @ref LL_SYSCFG_GRP2_PVD
1071 * @retval None
1072 */
LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)1073 __STATIC_INLINE void LL_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
1074 {
1075 CLEAR_BIT(SYSCFG->IMR2, Interrupt);
1076 }
1077
1078 /**
1079 * @brief Disable CPU1 Interrupt Mask
1080 * @rmtoll SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_DisableIT\n
1081 * SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_DisableIT\n
1082 * SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_DisableIT\n
1083 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_DisableIT
1084 * @param Interrupt This parameter can be a combination of the following values:
1085 * @arg @ref LL_SYSCFG_GRP1_TIM1
1086 * @arg @ref LL_SYSCFG_GRP1_TIM16
1087 * @arg @ref LL_SYSCFG_GRP1_TIM17
1088 * @arg @ref LL_SYSCFG_GRP1_EXTI5
1089 * @arg @ref LL_SYSCFG_GRP1_EXTI6
1090 * @arg @ref LL_SYSCFG_GRP1_EXTI7
1091 * @arg @ref LL_SYSCFG_GRP1_EXTI8
1092 * @arg @ref LL_SYSCFG_GRP1_EXTI9
1093 * @arg @ref LL_SYSCFG_GRP1_EXTI10
1094 * @arg @ref LL_SYSCFG_GRP1_EXTI11
1095 * @arg @ref LL_SYSCFG_GRP1_EXTI12
1096 * @arg @ref LL_SYSCFG_GRP1_EXTI13
1097 * @arg @ref LL_SYSCFG_GRP1_EXTI14
1098 * @arg @ref LL_SYSCFG_GRP1_EXTI15
1099 * @retval None
1100 */
LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)1101 __STATIC_INLINE void LL_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
1102 {
1103 SET_BIT(SYSCFG->IMR1, Interrupt);
1104 }
1105
1106 /**
1107 * @brief Disable CPU1 Interrupt Mask
1108 * @rmtoll SYSCFG_IMR2 PVM1IM LL_SYSCFG_GRP2_DisableIT\n
1109 * SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_DisableIT\n
1110 * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_DisableIT
1111 * @param Interrupt This parameter can be a combination of the following values:
1112 * @arg @ref LL_SYSCFG_GRP2_PVM1
1113 * @arg @ref LL_SYSCFG_GRP2_PVM3
1114 * @arg @ref LL_SYSCFG_GRP2_PVD
1115 * @retval None
1116 */
LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)1117 __STATIC_INLINE void LL_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
1118 {
1119 SET_BIT(SYSCFG->IMR2, Interrupt);
1120 }
1121
1122 /**
1123 * @brief Indicate if CPU1 Interrupt Mask is enabled
1124 * @rmtoll SYSCFG_IMR1 TIM1IM LL_SYSCFG_GRP1_IsEnabledIT\n
1125 * SYSCFG_IMR1 TIM16IM LL_SYSCFG_GRP1_IsEnabledIT\n
1126 * SYSCFG_IMR1 TIM17IM LL_SYSCFG_GRP1_IsEnabledIT\n
1127 * SYSCFG_IMR1 EXTIxIM LL_SYSCFG_GRP1_IsEnabledIT
1128 * @param Interrupt This parameter can be one of the following values:
1129 * @arg @ref LL_SYSCFG_GRP1_TIM1
1130 * @arg @ref LL_SYSCFG_GRP1_TIM16
1131 * @arg @ref LL_SYSCFG_GRP1_TIM17
1132 * @arg @ref LL_SYSCFG_GRP1_EXTI5
1133 * @arg @ref LL_SYSCFG_GRP1_EXTI6
1134 * @arg @ref LL_SYSCFG_GRP1_EXTI7
1135 * @arg @ref LL_SYSCFG_GRP1_EXTI8
1136 * @arg @ref LL_SYSCFG_GRP1_EXTI9
1137 * @arg @ref LL_SYSCFG_GRP1_EXTI10
1138 * @arg @ref LL_SYSCFG_GRP1_EXTI11
1139 * @arg @ref LL_SYSCFG_GRP1_EXTI12
1140 * @arg @ref LL_SYSCFG_GRP1_EXTI13
1141 * @arg @ref LL_SYSCFG_GRP1_EXTI14
1142 * @arg @ref LL_SYSCFG_GRP1_EXTI15
1143 * @retval State of bit (1 or 0).
1144 */
LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)1145 __STATIC_INLINE uint32_t LL_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
1146 {
1147 return ((READ_BIT(SYSCFG->IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1148 }
1149
1150 /**
1151 * @brief Indicate if CPU1 Interrupt Mask is enabled
1152 * @rmtoll SYSCFG_IMR2 PVM1IM LL_SYSCFG_GRP2_IsEnabledIT\n
1153 * SYSCFG_IMR2 PVM3IM LL_SYSCFG_GRP2_IsEnabledIT\n
1154 * SYSCFG_IMR2 PVDIM LL_SYSCFG_GRP2_IsEnabledIT
1155 * @param Interrupt This parameter can be one of the following values:
1156 * @arg @ref LL_SYSCFG_GRP2_PVM1
1157 * @arg @ref LL_SYSCFG_GRP2_PVM3
1158 * @arg @ref LL_SYSCFG_GRP2_PVD
1159 * @retval State of bit (1 or 0).
1160 */
LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)1161 __STATIC_INLINE uint32_t LL_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
1162 {
1163 return ((READ_BIT(SYSCFG->IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1164 }
1165
1166 /**
1167 * @brief Enable CPU2 Interrupt Mask
1168 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT\n
1169 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_EnableIT\n
1170 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_EnableIT\n
1171 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_EnableIT\n
1172 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_EnableIT\n
1173 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_EnableIT\n
1174 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_EnableIT\n
1175 * SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_EnableIT\n
1176 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_EnableIT\n
1177 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_EnableIT\n
1178 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_EnableIT
1179 * @param Interrupt This parameter can be a combination of the following values:
1180 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
1181 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
1182 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
1183 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
1184 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
1185 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
1186 * @arg @ref LL_C2_SYSCFG_GRP1_RNG
1187 * @arg @ref LL_C2_SYSCFG_GRP1_AES1
1188 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
1189 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
1190 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
1191 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
1192 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
1193 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
1194 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
1195 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
1196 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
1197 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
1198 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
1199 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
1200 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
1201 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
1202 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
1203 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
1204 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
1205 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
1206 * @retval None
1207 */
LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)1208 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_EnableIT(uint32_t Interrupt)
1209 {
1210 CLEAR_BIT(SYSCFG->C2IMR1, Interrupt);
1211 }
1212
1213 /**
1214 * @brief Enable CPU2 Interrupt Mask
1215 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n
1216 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_EnableIT\n
1217 * SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_EnableIT\n
1218 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_EnableIT\n
1219 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_EnableIT\n
1220 * SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_EnableIT\n
1221 * SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_EnableIT
1222 * @param Interrupt This parameter can be a combination of the following values:
1223 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1224 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1225 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1226 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1227 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1228 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1229 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1230 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1231 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1232 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1233 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1234 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1235 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1236 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1237 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1238 * @arg @ref LL_C2_SYSCFG_GRP2_PVM1
1239 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1240 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1241 * @arg @ref LL_C2_SYSCFG_GRP2_TSC
1242 * @arg @ref LL_C2_SYSCFG_GRP2_LCD
1243 * @retval None
1244 */
LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)1245 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_EnableIT(uint32_t Interrupt)
1246 {
1247 CLEAR_BIT(SYSCFG->C2IMR2, Interrupt);
1248 }
1249
1250 /**
1251 * @brief Disable CPU2 Interrupt Mask
1252 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_DisableIT\n
1253 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_DisableIT\n
1254 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_DisableIT\n
1255 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_DisableIT\n
1256 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_DisableIT\n
1257 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_DisableIT\n
1258 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_DisableIT\n
1259 * SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_DisableIT\n
1260 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_DisableIT\n
1261 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_DisableIT\n
1262 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_DisableIT
1263 * @param Interrupt This parameter can be a combination of the following values:
1264 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
1265 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
1266 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
1267 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
1268 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
1269 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
1270 * @arg @ref LL_C2_SYSCFG_GRP1_RNG
1271 * @arg @ref LL_C2_SYSCFG_GRP1_AES1
1272 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
1273 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
1274 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
1275 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
1276 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
1277 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
1278 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
1279 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
1280 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
1281 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
1282 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
1283 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
1284 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
1285 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
1286 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
1287 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
1288 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
1289 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
1290 * @retval None
1291 */
LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)1292 __STATIC_INLINE void LL_C2_SYSCFG_GRP1_DisableIT(uint32_t Interrupt)
1293 {
1294 SET_BIT(SYSCFG->C2IMR1, Interrupt);
1295 }
1296
1297 /**
1298 * @brief Disable CPU2 Interrupt Mask
1299 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n
1300 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_DisableIT\n
1301 * SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_DisableIT\n
1302 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_DisableIT\n
1303 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_DisableIT\n
1304 * SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_DisableIT\n
1305 * SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_DisableIT
1306 * @param Interrupt This parameter can be a combination of the following values:
1307 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1308 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1309 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1310 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1311 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1312 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1313 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1314 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1315 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1316 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1317 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1318 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1319 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1320 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1321 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1322 * @arg @ref LL_C2_SYSCFG_GRP2_PVM1
1323 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1324 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1325 * @arg @ref LL_C2_SYSCFG_GRP2_TSC
1326 * @arg @ref LL_C2_SYSCFG_GRP2_LCD
1327 * @retval None
1328 */
LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)1329 __STATIC_INLINE void LL_C2_SYSCFG_GRP2_DisableIT(uint32_t Interrupt)
1330 {
1331 SET_BIT(SYSCFG->C2IMR2, Interrupt);
1332 }
1333
1334 /**
1335 * @brief Indicate if CPU2 Interrupt Mask is enabled
1336 * @rmtoll SYSCFG_C2IMR1 RTCSTAMPTAMPLSECSSIM LL_C2_SYSCFG_GRP1_EnableIT\n
1337 * SYSCFG_C2IMR1 RTCWKUPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1338 * SYSCFG_C2IMR1 RTCALARMIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1339 * SYSCFG_C2IMR1 RCCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1340 * SYSCFG_C2IMR1 FLASHIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1341 * SYSCFG_C2IMR1 PKAIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1342 * SYSCFG_C2IMR1 RNGIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1343 * SYSCFG_C2IMR1 AES1IM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1344 * SYSCFG_C2IMR1 COMPIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1345 * SYSCFG_C2IMR1 ADCIM LL_C2_SYSCFG_GRP1_IsEnabledIT\n
1346 * SYSCFG_C2IMR1 EXTIxIM LL_C2_SYSCFG_GRP1_IsEnabledIT
1347 * @param Interrupt This parameter can be one of the following values:
1348 * @arg @ref LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS
1349 * @arg @ref LL_C2_SYSCFG_GRP1_RTCWKUP
1350 * @arg @ref LL_C2_SYSCFG_GRP1_RTCALARM
1351 * @arg @ref LL_C2_SYSCFG_GRP1_RCC
1352 * @arg @ref LL_C2_SYSCFG_GRP1_FLASH
1353 * @arg @ref LL_C2_SYSCFG_GRP1_PKA
1354 * @arg @ref LL_C2_SYSCFG_GRP1_RNG
1355 * @arg @ref LL_C2_SYSCFG_GRP1_AES1
1356 * @arg @ref LL_C2_SYSCFG_GRP1_COMP
1357 * @arg @ref LL_C2_SYSCFG_GRP1_ADC
1358 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI0
1359 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI1
1360 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI2
1361 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI3
1362 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI4
1363 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI5
1364 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI6
1365 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI7
1366 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI8
1367 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI9
1368 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI10
1369 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI11
1370 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI12
1371 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI13
1372 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI14
1373 * @arg @ref LL_C2_SYSCFG_GRP1_EXTI15
1374 * @retval State of bit (1 or 0).
1375 */
LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)1376 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP1_IsEnabledIT(uint32_t Interrupt)
1377 {
1378 return ((READ_BIT(SYSCFG->C2IMR1, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1379 }
1380
1381 /**
1382 * @brief Indicate if CPU2 Interrupt Mask is enabled
1383 * @rmtoll SYSCFG_C2IMR2 DMA1CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1384 * SYSCFG_C2IMR2 DMA2CHxIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1385 * SYSCFG_C2IMR2 PVM1IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1386 * SYSCFG_C2IMR2 PVM3IM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1387 * SYSCFG_C2IMR2 PVDIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1388 * SYSCFG_C2IMR2 TSCIM LL_C2_SYSCFG_GRP2_IsEnabledIT\n
1389 * SYSCFG_C2IMR2 LCDIM LL_C2_SYSCFG_GRP2_IsEnabledIT
1390 * @param Interrupt This parameter can be one of the following values:
1391 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH1
1392 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH2
1393 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH3
1394 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH4
1395 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH5
1396 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH6
1397 * @arg @ref LL_C2_SYSCFG_GRP2_DMA1CH7
1398 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH1
1399 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH2
1400 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH3
1401 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH4
1402 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH5
1403 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH6
1404 * @arg @ref LL_C2_SYSCFG_GRP2_DMA2CH7
1405 * @arg @ref LL_C2_SYSCFG_GRP2_DMAMUX1
1406 * @arg @ref LL_C2_SYSCFG_GRP2_PVM1
1407 * @arg @ref LL_C2_SYSCFG_GRP2_PVM3
1408 * @arg @ref LL_C2_SYSCFG_GRP2_PVD
1409 * @arg @ref LL_C2_SYSCFG_GRP2_TSC
1410 * @arg @ref LL_C2_SYSCFG_GRP2_LCD
1411 * @retval State of bit (1 or 0).
1412 */
LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)1413 __STATIC_INLINE uint32_t LL_C2_SYSCFG_GRP2_IsEnabledIT(uint32_t Interrupt)
1414 {
1415 return ((READ_BIT(SYSCFG->C2IMR2, Interrupt) != (Interrupt)) ? 1UL : 0UL);
1416 }
1417
1418 /**
1419 * @brief Enable the access for security IP
1420 * @rmtoll SYSCFG_SIPCR SAES1 LL_SYSCFG_EnableSecurityAccess\n
1421 * SYSCFG_CFGR1 SAES2 LL_SYSCFG_EnableSecurityAccess\n
1422 * SYSCFG_CFGR1 SPKA LL_SYSCFG_EnableSecurityAccess\n
1423 * SYSCFG_CFGR1 SRNG LL_SYSCFG_EnableSecurityAccess
1424 * @param SecurityAccess This parameter can be a combination of the following values:
1425 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
1426 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
1427 * @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
1428 * @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
1429 * @retval None
1430 */
LL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess)1431 __STATIC_INLINE void LL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess)
1432 {
1433 SET_BIT(SYSCFG->SIPCR, SecurityAccess);
1434 }
1435
1436 /**
1437 * @brief Disable the access for security IP
1438 * @rmtoll SYSCFG_SIPCR SAES1 LL_SYSCFG_DisableSecurityAccess\n
1439 * SYSCFG_CFGR1 SAES2 LL_SYSCFG_DisableSecurityAccess\n
1440 * SYSCFG_CFGR1 SPKA LL_SYSCFG_DisableSecurityAccess\n
1441 * SYSCFG_CFGR1 SRNG LL_SYSCFG_DisableSecurityAccess
1442 * @param SecurityAccess This parameter can be a combination of the following values:
1443 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
1444 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
1445 * @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
1446 * @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
1447 * @retval None
1448 */
LL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess)1449 __STATIC_INLINE void LL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess)
1450 {
1451 CLEAR_BIT(SYSCFG->SIPCR, SecurityAccess);
1452 }
1453
1454 /**
1455 * @brief Indicate if access for security IP is enabled
1456 * @rmtoll SYSCFG_SIPCR SAES1 LL_SYSCFG_IsEnabledSecurityAccess\n
1457 * SYSCFG_CFGR1 SAES2 LL_SYSCFG_IsEnabledSecurityAccess\n
1458 * SYSCFG_CFGR1 SPKA LL_SYSCFG_IsEnabledSecurityAccess\n
1459 * SYSCFG_CFGR1 SRNG LL_SYSCFG_IsEnabledSecurityAccess
1460 * @param SecurityAccess This parameter can be one of the following values:
1461 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES1
1462 * @arg @ref LL_SYSCFG_SECURE_ACCESS_AES2
1463 * @arg @ref LL_SYSCFG_SECURE_ACCESS_PKA
1464 * @arg @ref LL_SYSCFG_SECURE_ACCESS_RNG
1465 * @retval State of bit (1 or 0).
1466 */
LL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess)1467 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess)
1468 {
1469 return ((READ_BIT(SYSCFG->SIPCR, SecurityAccess) == (SecurityAccess)) ? 1UL : 0UL);
1470 }
1471
1472 /**
1473 * @}
1474 */
1475
1476 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1477 * @note DBGMCU is only accessible by Cortex M4
1478 * To access on DBGMCU, Cortex M0+ need to request to the Cortex M4
1479 * the action.
1480 * @{
1481 */
1482
1483 /**
1484 * @brief Return the device identifier
1485 * @note For STM32WBxxxx devices, the device ID is 0x495
1486 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1487 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF (ex: device ID is 0x495)
1488 */
LL_DBGMCU_GetDeviceID(void)1489 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1490 {
1491 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1492 }
1493
1494 /**
1495 * @brief Return the device revision identifier
1496 * @note This field indicates the revision of the device.
1497 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1498 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1499 */
LL_DBGMCU_GetRevisionID(void)1500 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1501 {
1502 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1503 }
1504
1505 /**
1506 * @brief Enable the Debug Module during SLEEP mode
1507 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1508 * @retval None
1509 */
LL_DBGMCU_EnableDBGSleepMode(void)1510 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1511 {
1512 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1513 }
1514
1515 /**
1516 * @brief Disable the Debug Module during SLEEP mode
1517 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1518 * @retval None
1519 */
LL_DBGMCU_DisableDBGSleepMode(void)1520 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1521 {
1522 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1523 }
1524
1525 /**
1526 * @brief Enable the Debug Module during STOP mode
1527 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1528 * @retval None
1529 */
LL_DBGMCU_EnableDBGStopMode(void)1530 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1531 {
1532 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1533 }
1534
1535 /**
1536 * @brief Disable the Debug Module during STOP mode
1537 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1538 * @retval None
1539 */
LL_DBGMCU_DisableDBGStopMode(void)1540 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1541 {
1542 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1543 }
1544
1545 /**
1546 * @brief Enable the Debug Module during STANDBY mode
1547 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1548 * @retval None
1549 */
LL_DBGMCU_EnableDBGStandbyMode(void)1550 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1551 {
1552 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1553 }
1554
1555 /**
1556 * @brief Disable the Debug Module during STANDBY mode
1557 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1558 * @retval None
1559 */
LL_DBGMCU_DisableDBGStandbyMode(void)1560 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1561 {
1562 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1563 }
1564
1565 /**
1566 * @brief Enable the clock for Trace port
1567 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock\n
1568 */
LL_DBGMCU_EnableTraceClock(void)1569 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
1570 {
1571 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN);
1572 }
1573
1574 /**
1575 * @brief Disable the clock for Trace port
1576 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock\n
1577 * @retval None
1578 */
LL_DBGMCU_DisableTraceClock(void)1579 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
1580 {
1581 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN);
1582 }
1583
1584 /**
1585 * @brief Indicate if the clock for Trace port is enabled
1586 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock\n
1587 * @retval State of bit (1 or 0).
1588 */
LL_DBGMCU_IsEnabledTraceClock(void)1589 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
1590 {
1591 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN) == (DBGMCU_CR_TRACE_IOEN)) ? 1UL : 0UL);
1592 }
1593
1594 /**
1595 * @brief Enable the external trigger ouput
1596 * @note When enable the external trigger is output (state of bit 1),
1597 * TRGIO pin is connected to TRGOUT.
1598 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_EnableTriggerOutput\n
1599 */
LL_DBGMCU_EnableTriggerOutput(void)1600 __STATIC_INLINE void LL_DBGMCU_EnableTriggerOutput(void)
1601 {
1602 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
1603 }
1604
1605 /**
1606 * @brief Disable the external trigger ouput
1607 * @note When disable external trigger is input (state of bit 0),
1608 * TRGIO pin is connected to TRGIN.
1609 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_DisableTriggerOutput\n
1610 * @retval None
1611 */
LL_DBGMCU_DisableTriggerOutput(void)1612 __STATIC_INLINE void LL_DBGMCU_DisableTriggerOutput(void)
1613 {
1614 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
1615 }
1616
1617 /**
1618 * @brief Indicate if the external trigger is output or input direction
1619 * @note When the external trigger is output (state of bit 1),
1620 * TRGIO pin is connected to TRGOUT.
1621 * When the external trigger is input (state of bit 0),
1622 * TRGIO pin is connected to TRGIN.
1623 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_EnableTriggerOutput\n
1624 * @retval State of bit (1 or 0).
1625 */
LL_DBGMCU_IsEnabledTriggerOutput(void)1626 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTriggerOutput(void)
1627 {
1628 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN) == (DBGMCU_CR_TRGOEN)) ? 1UL : 0UL);
1629 }
1630
1631 /**
1632 * @brief Freeze CPU1 APB1 peripherals (group1 peripherals)
1633 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1634 * @param Periphs This parameter can be a combination of the following values:
1635 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1636 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1637 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1638 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1639 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1640 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1641 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1642 * @retval None
1643 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1644 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1645 {
1646 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1647 }
1648
1649 /**
1650 * @brief Freeze CPU2 APB1 peripherals (group1 peripherals)
1651 * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_FreezePeriph
1652 * @param Periphs This parameter can be a combination of the following values:
1653 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
1654 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
1655 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
1656 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
1657 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
1658 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
1659 * @retval None
1660 */
LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1661 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1662 {
1663 SET_BIT(DBGMCU->C2APB1FZR1, Periphs);
1664 }
1665
1666 /**
1667 * @brief Freeze CPU1 APB1 peripherals (group2 peripherals)
1668 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1669 * @param Periphs This parameter can be a combination of the following values:
1670 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1671 * @retval None
1672 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1673 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1674 {
1675 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1676 }
1677
1678 /**
1679 * @brief Freeze CPU2 APB1 peripherals (group2 peripherals)
1680 * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_FreezePeriph
1681 * @param Periphs This parameter can be a combination of the following values:
1682 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
1683 * @retval None
1684 */
LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1685 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1686 {
1687 SET_BIT(DBGMCU->C2APB1FZR2, Periphs);
1688 }
1689
1690 /**
1691 * @brief Unfreeze CPU1 APB1 peripherals (group1 peripherals)
1692 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1693 * @param Periphs This parameter can be a combination of the following values:
1694 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1695 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1696 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1697 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1698 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1699 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1700 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1701 * @retval None
1702 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1703 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1704 {
1705 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1706 }
1707
1708 /**
1709 * @brief Unfreeze CPU2 APB1 peripherals (group1 peripherals)
1710 * @rmtoll DBGMCU_C2APB1FZR1 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph
1711 * @param Periphs This parameter can be a combination of the following values:
1712 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP
1713 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_RTC_STOP
1714 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP
1715 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP
1716 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP
1717 * @arg @ref LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP
1718 * @retval None
1719 */
LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1720 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1721 {
1722 CLEAR_BIT(DBGMCU->C2APB1FZR1, Periphs);
1723 }
1724
1725 /**
1726 * @brief Unfreeze CPU1 APB1 peripherals (group2 peripherals)
1727 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1728 * @param Periphs This parameter can be a combination of the following values:
1729 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1730 * @retval None
1731 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1732 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1733 {
1734 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1735 }
1736
1737 /**
1738 * @brief Unfreeze CPU2 APB1 peripherals (group2 peripherals)
1739 * @rmtoll DBGMCU_C2APB1FZR2 DBG_xxxx_STOP LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph
1740 * @param Periphs This parameter can be a combination of the following values:
1741 * @arg @ref LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP
1742 * @retval None
1743 */
LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1744 __STATIC_INLINE void LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1745 {
1746 CLEAR_BIT(DBGMCU->C2APB1FZR2, Periphs);
1747 }
1748
1749 /**
1750 * @brief Freeze CPU1 APB2 peripherals
1751 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1752 * @param Periphs This parameter can be a combination of the following values:
1753 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1754 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1755 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1756 * @retval None
1757 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1758 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1759 {
1760 SET_BIT(DBGMCU->APB2FZR, Periphs);
1761 }
1762
1763 /**
1764 * @brief Freeze CPU2 APB2 peripherals
1765 * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_FreezePeriph
1766 * @param Periphs This parameter can be a combination of the following values:
1767 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
1768 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
1769 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
1770 * @retval None
1771 */
LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1772 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1773 {
1774 SET_BIT(DBGMCU->C2APB2FZR, Periphs);
1775 }
1776
1777 /**
1778 * @brief Unfreeze CPU1 APB2 peripherals
1779 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1780 * @param Periphs This parameter can be a combination of the following values:
1781 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1782 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1783 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1784 * @retval None
1785 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1786 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1787 {
1788 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1789 }
1790
1791 /**
1792 * @brief Unfreeze CPU2 APB2 peripherals
1793 * @rmtoll DBGMCU_C2APB2FZR DBG_TIMx_STOP LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph
1794 * @param Periphs This parameter can be a combination of the following values:
1795 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP
1796 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP
1797 * @arg @ref LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP
1798 * @retval None
1799 */
LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1800 __STATIC_INLINE void LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1801 {
1802 CLEAR_BIT(DBGMCU->C2APB2FZR, Periphs);
1803 }
1804
1805 /**
1806 * @}
1807 */
1808
1809 #if defined(VREFBUF)
1810 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1811 * @{
1812 */
1813
1814 /**
1815 * @brief Enable Internal voltage reference
1816 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1817 * @retval None
1818 */
LL_VREFBUF_Enable(void)1819 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1820 {
1821 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1822 }
1823
1824 /**
1825 * @brief Disable Internal voltage reference
1826 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1827 * @retval None
1828 */
LL_VREFBUF_Disable(void)1829 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1830 {
1831 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1832 }
1833
1834 /**
1835 * @brief Enable high impedance (VREF+pin is high impedance)
1836 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1837 * @retval None
1838 */
LL_VREFBUF_EnableHIZ(void)1839 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1840 {
1841 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1842 }
1843
1844 /**
1845 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1846 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1847 * @retval None
1848 */
LL_VREFBUF_DisableHIZ(void)1849 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1850 {
1851 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1852 }
1853
1854 /**
1855 * @brief Set the Voltage reference scale
1856 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1857 * @param Scale This parameter can be one of the following values:
1858 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1859 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1860 * @retval None
1861 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1862 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1863 {
1864 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1865 }
1866
1867 /**
1868 * @brief Get the Voltage reference scale
1869 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1870 * @retval Returned value can be one of the following values:
1871 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1872 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1873 */
LL_VREFBUF_GetVoltageScaling(void)1874 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1875 {
1876 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1877 }
1878
1879 /**
1880 * @brief Check if Voltage reference buffer is ready
1881 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1882 * @retval State of bit (1 or 0).
1883 */
LL_VREFBUF_IsVREFReady(void)1884 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1885 {
1886 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
1887 }
1888
1889 /**
1890 * @brief Get the trimming code for VREFBUF calibration
1891 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1892 * @retval Between 0 and 0x3F
1893 */
LL_VREFBUF_GetTrimming(void)1894 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1895 {
1896 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1897 }
1898
1899 /**
1900 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1901 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1902 * @param Value Between 0 and 0x3F
1903 * @retval None
1904 */
LL_VREFBUF_SetTrimming(uint32_t Value)1905 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1906 {
1907 WRITE_REG(VREFBUF->CCR, Value);
1908 }
1909
1910 /**
1911 * @}
1912 */
1913 #endif /* VREFBUF */
1914
1915 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1916 * @{
1917 */
1918
1919 /**
1920 * @brief Set FLASH Latency
1921 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1922 * @param Latency This parameter can be one of the following values:
1923 * @arg @ref LL_FLASH_LATENCY_0
1924 * @arg @ref LL_FLASH_LATENCY_1
1925 * @arg @ref LL_FLASH_LATENCY_2
1926 * @arg @ref LL_FLASH_LATENCY_3
1927 * @retval None
1928 */
LL_FLASH_SetLatency(uint32_t Latency)1929 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1930 {
1931 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1932 }
1933
1934 /**
1935 * @brief Get FLASH Latency
1936 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1937 * @retval Returned value can be one of the following values:
1938 * @arg @ref LL_FLASH_LATENCY_0
1939 * @arg @ref LL_FLASH_LATENCY_1
1940 * @arg @ref LL_FLASH_LATENCY_2
1941 * @arg @ref LL_FLASH_LATENCY_3
1942 */
LL_FLASH_GetLatency(void)1943 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1944 {
1945 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1946 }
1947
1948 /**
1949 * @brief Enable Prefetch
1950 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1951 * @retval None
1952 */
LL_FLASH_EnablePrefetch(void)1953 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1954 {
1955 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1956 }
1957
1958 /**
1959 * @brief Disable Prefetch
1960 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1961 * @rmtoll FLASH_C2ACR PRFTEN LL_FLASH_DisablePrefetch
1962 * @retval None
1963 */
LL_FLASH_DisablePrefetch(void)1964 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1965 {
1966 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1967 }
1968
1969 /**
1970 * @brief Check if Prefetch buffer is enabled
1971 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1972 * @rmtoll FLASH_C2ACR C2PRFTEN LL_FLASH_IsPrefetchEnabled
1973 * @retval State of bit (1 or 0).
1974 */
LL_FLASH_IsPrefetchEnabled(void)1975 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1976 {
1977 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
1978 }
1979
1980 /**
1981 * @brief Enable Instruction cache
1982 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1983 * @rmtoll FLASH_C2ACR ICEN LL_FLASH_EnableInstCache
1984 * @retval None
1985 */
LL_FLASH_EnableInstCache(void)1986 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1987 {
1988 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1989 }
1990
1991 /**
1992 * @brief Disable Instruction cache
1993 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1994 * @rmtoll FLASH_C2ACR ICEN LL_FLASH_DisableInstCache
1995 * @retval None
1996 */
LL_FLASH_DisableInstCache(void)1997 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1998 {
1999 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
2000 }
2001
2002 /**
2003 * @brief Enable Data cache
2004 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
2005 * @retval None
2006 */
LL_FLASH_EnableDataCache(void)2007 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
2008 {
2009 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
2010 }
2011
2012 /**
2013 * @brief Disable Data cache
2014 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
2015 * @retval None
2016 */
LL_FLASH_DisableDataCache(void)2017 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
2018 {
2019 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
2020 }
2021
2022 /**
2023 * @brief Enable Instruction cache reset
2024 * @note bit can be written only when the instruction cache is disabled
2025 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
2026 * @rmtoll FLASH_C2ACR ICRST LL_FLASH_EnableInstCacheReset
2027 * @retval None
2028 */
LL_FLASH_EnableInstCacheReset(void)2029 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
2030 {
2031 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
2032 }
2033
2034 /**
2035 * @brief Disable Instruction cache reset
2036 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
2037 * @rmtoll FLASH_C2ACR ICRST LL_FLASH_DisableInstCacheReset
2038 * @retval None
2039 */
LL_FLASH_DisableInstCacheReset(void)2040 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
2041 {
2042 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
2043 }
2044
2045 /**
2046 * @brief Enable Data cache reset
2047 * @note bit can be written only when the data cache is disabled
2048 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
2049 * @retval None
2050 */
LL_FLASH_EnableDataCacheReset(void)2051 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
2052 {
2053 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
2054 }
2055
2056 /**
2057 * @brief Disable Data cache reset
2058 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
2059 * @retval None
2060 */
LL_FLASH_DisableDataCacheReset(void)2061 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
2062 {
2063 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
2064 }
2065
2066 /**
2067 * @brief Suspend new program or erase operation request
2068 * @note Any new Flash program and erase operation on both CPU side will be suspended
2069 * until this bit and the same bit in Flash CPU2 access control register (FLASH_C2ACR) are
2070 * cleared. The PESD bit in both the Flash status register (FLASH_SR) and Flash
2071 * CPU2 status register (FLASH_C2SR) register will be set when at least one PES
2072 * bit in FLASH_ACR or FLASH_C2ACR is set.
2073 * @rmtoll FLASH_ACR PES LL_FLASH_SuspendOperation
2074 * @rmtoll FLASH_C2ACR PES LL_FLASH_SuspendOperation
2075 * @retval None
2076 */
LL_FLASH_SuspendOperation(void)2077 __STATIC_INLINE void LL_FLASH_SuspendOperation(void)
2078 {
2079 SET_BIT(FLASH->ACR, FLASH_ACR_PES);
2080 }
2081
2082 /**
2083 * @brief Allow new program or erase operation request
2084 * @note Any new Flash program and erase operation on both CPU side will be allowed
2085 * until one of this bit or the same bit in Flash CPU2 access control register (FLASH_C2ACR) is
2086 * set. The PESD bit in both the Flash status register (FLASH_SR) and Flash
2087 * CPU2 status register (FLASH_C2SR) register will be clear when both PES
2088 * bit in FLASH_ACR or FLASH_C2ACR is cleared.
2089 * @rmtoll FLASH_ACR PES LL_FLASH_AllowOperation
2090 * @rmtoll FLASH_C2ACR PES LL_FLASH_AllowOperation
2091 * @retval None
2092 */
LL_FLASH_AllowOperation(void)2093 __STATIC_INLINE void LL_FLASH_AllowOperation(void)
2094 {
2095 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PES);
2096 }
2097
2098 /**
2099 * @brief Check if new program or erase operation request from CPU2 is suspended
2100 * @rmtoll FLASH_ACR PES LL_FLASH_IsOperationSuspended
2101 * @rmtoll FLASH_C2ACR PES LL_FLASH_IsOperationSuspended
2102 * @retval State of bit (1 or 0).
2103 */
LL_FLASH_IsOperationSuspended(void)2104 __STATIC_INLINE uint32_t LL_FLASH_IsOperationSuspended(void)
2105 {
2106 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PES) == (FLASH_ACR_PES)) ? 1UL : 0UL);
2107 }
2108
2109 /**
2110 * @brief Check if new program or erase operation request from CPU1 or CPU2 is suspended
2111 * @rmtoll FLASH_SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
2112 * @rmtoll FLASH_C2SR PESD LL_FLASH_IsActiveFlag_OperationSuspended
2113 * @retval State of bit (1 or 0).
2114 */
LL_FLASH_IsActiveFlag_OperationSuspended(void)2115 __STATIC_INLINE uint32_t LL_FLASH_IsActiveFlag_OperationSuspended(void)
2116 {
2117 return ((READ_BIT(FLASH->SR, FLASH_SR_PESD) == (FLASH_SR_PESD)) ? 1UL : 0UL);
2118 }
2119
2120 /**
2121 * @brief Set EMPTY flag information as Flash User area empty
2122 * @rmtoll FLASH_ACR EMPTY LL_FLASH_SetEmptyFlag
2123 * @retval None
2124 */
LL_FLASH_SetEmptyFlag(void)2125 __STATIC_INLINE void LL_FLASH_SetEmptyFlag(void)
2126 {
2127 SET_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
2128 }
2129
2130 /**
2131 * @brief Clear EMPTY flag information as Flash User area programmed
2132 * @rmtoll FLASH_ACR EMPTY LL_FLASH_ClearEmptyFlag
2133 * @retval None
2134 */
LL_FLASH_ClearEmptyFlag(void)2135 __STATIC_INLINE void LL_FLASH_ClearEmptyFlag(void)
2136 {
2137 CLEAR_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
2138 }
2139
2140 /**
2141 * @brief Check if the EMPTY flag is set or reset
2142 * @rmtoll FLASH_ACR EMPTY LL_FLASH_IsEmptyFlag
2143 * @retval State of bit (1 or 0).
2144 */
LL_FLASH_IsEmptyFlag(void)2145 __STATIC_INLINE uint32_t LL_FLASH_IsEmptyFlag(void)
2146 {
2147 return ((READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY) == FLASH_ACR_EMPTY) ? 1UL : 0UL);
2148 }
2149
2150 /**
2151 * @brief Get IPCC buffer base address
2152 * @rmtoll FLASH_IPCCBR IPCCDBA LL_FLASH_GetIPCCBufferAddr
2153 * @retval IPCC data buffer base address offset
2154 */
LL_FLASH_GetIPCCBufferAddr(void)2155 __STATIC_INLINE uint32_t LL_FLASH_GetIPCCBufferAddr(void)
2156 {
2157 return (uint32_t)(READ_BIT(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA));
2158 }
2159
2160 /**
2161 * @brief Get CPU2 boot reset vector
2162 * @rmtoll FLASH_SRRVR SBRV LL_FLASH_GetC2BootResetVect
2163 * @retval CPU2 boot reset vector
2164 */
LL_FLASH_GetC2BootResetVect(void)2165 __STATIC_INLINE uint32_t LL_FLASH_GetC2BootResetVect(void)
2166 {
2167 return (uint32_t)(READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRV));
2168 }
2169
2170 /**
2171 * @brief Return the Unique Device Number
2172 * @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
2173 * 802.15.4 64-bit Device Address EUI-64.
2174 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
2175 */
LL_FLASH_GetUDN(void)2176 __STATIC_INLINE uint32_t LL_FLASH_GetUDN(void)
2177 {
2178 return (uint32_t)(READ_REG(*((uint32_t *)UID64_BASE)));
2179 }
2180
2181 /**
2182 * @brief Return the Device ID
2183 * @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
2184 * 802.15.4 64-bit Device Address EUI-64.
2185 * For STM32WBxxxx devices, the device ID is 0x26
2186 * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x26 fo STM32WB55x)
2187 */
LL_FLASH_GetDeviceID(void)2188 __STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void)
2189 {
2190 return (uint32_t)((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU);
2191 }
2192
2193 /**
2194 * @brief Return the ST Company ID
2195 * @note The 64-bit UID64 may be used by Firmware to derive BLE 48-bit Device Address EUI-48 or
2196 * 802.15.4 64-bit Device Address EUI-64.
2197 * For STM32WBxxxx devices, the ST Compagny ID is 0x0080E1
2198 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Compagny ID is 0x0080E1)
2199 */
LL_FLASH_GetSTCompanyID(void)2200 __STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void)
2201 {
2202 return (uint32_t)(((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U ) & 0x00FFFFFFU);
2203 }
2204 /**
2205 * @}
2206 */
2207
2208 /**
2209 * @}
2210 */
2211
2212 /**
2213 * @}
2214 */
2215
2216 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
2217
2218 /**
2219 * @}
2220 */
2221
2222 #ifdef __cplusplus
2223 }
2224 #endif
2225
2226 #endif /* STM32WBxx_LL_SYSTEM_H */
2227
2228 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2229