1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32WBxx_LL_RCC_H
22 #define STM32WBxx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32wbxx.h"
30
31 /** @addtogroup STM32WBxx_LL_Driver
32 * @{
33 */
34
35 #if defined(RCC)
36
37 /** @defgroup RCC_LL RCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
44 * @{
45 */
46
47 #define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU
48
49 /**
50 * @}
51 */
52
53 /* Private constants ---------------------------------------------------------*/
54 /* Private macros ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
57 * @{
58 */
59 /**
60 * @}
61 */
62 #endif /*USE_FULL_LL_DRIVER*/
63
64 /* Exported types ------------------------------------------------------------*/
65 #if defined(USE_FULL_LL_DRIVER)
66 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
67 * @{
68 */
69
70 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
71 * @{
72 */
73
74 /**
75 * @brief RCC Clocks Frequency Structure
76 */
77 typedef struct
78 {
79 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
80 uint32_t HCLK1_Frequency; /*!< HCLK1 clock frequency */
81 uint32_t HCLK2_Frequency; /*!< HCLK2 clock frequency */
82 uint32_t HCLK4_Frequency; /*!< HCLK4 clock frequency */
83 uint32_t HCLK5_Frequency; /*!< HCLK5 clock frequency */
84 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
85 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
86 } LL_RCC_ClocksTypeDef;
87
88 /**
89 * @}
90 */
91
92 /**
93 * @}
94 */
95 #endif /* USE_FULL_LL_DRIVER */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
99 * @{
100 */
101
102 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
103 * @brief Defines used to adapt values of different oscillators
104 * @note These values could be modified in the user environment according to
105 * HW set-up.
106 * @{
107 */
108 #if !defined (HSE_VALUE)
109 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
110 #endif /* HSE_VALUE */
111
112 #if !defined (HSI_VALUE)
113 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
114 #endif /* HSI_VALUE */
115
116 #if !defined (LSE_VALUE)
117 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
118 #endif /* LSE_VALUE */
119
120 #if !defined (LSI_VALUE)
121 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
122 #endif /* LSI_VALUE */
123
124 #if !defined (HSI48_VALUE)
125 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
126 #endif /* HSI48_VALUE */
127 /**
128 * @}
129 */
130
131 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
132 * @brief Flags defines which can be used with LL_RCC_WriteReg function
133 * @{
134 */
135 #define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
136 #define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI1 Ready Interrupt Clear */
137 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
138 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
139 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
140 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
141 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
142 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
143 #if defined(SAI1)
144 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
145 #endif
146 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
147 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
148 /**
149 * @}
150 */
151
152 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
153 * @brief Flags defines which can be used with LL_RCC_ReadReg function
154 * @{
155 */
156 #define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
157 #define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
158 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
159 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
160 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
161 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
162 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
163 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
164 #if defined(SAI1)
165 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
166 #endif
167 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
168 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
169 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
170 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
171 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
172 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
173 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
174 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
175 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
176 /**
177 * @}
178 */
179
180 /** @defgroup RCC_LL_EC_IT IT Defines
181 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
182 * @{
183 */
184 #define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
185 #define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI Ready Interrupt Enable */
186 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
187 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
188 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
189 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
190 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
191 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
192 #if defined(SAI1)
193 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
194 #endif
195 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
196 /**
197 * @}
198 */
199
200 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
201 * @{
202 */
203 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
204 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
205 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
206 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
207 /**
208 * @}
209 */
210
211 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
212 * @{
213 */
214 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
215 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
216 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
217 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
218 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
219 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
220 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
221 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
222 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
223 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
224 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
225 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
226 /**
227 * @}
228 */
229
230
231 /** @defgroup RCC_LL_EC_HSE_CURRENT_CONTROL HSE current control max limits
232 * @{
233 */
234 #define LL_RCC_HSE_CURRENTMAX_0 0x000000000U /*!< HSE current control max limit = 0.18 ma/V*/
235 #define LL_RCC_HSE_CURRENTMAX_1 RCC_HSECR_HSEGMC0 /*!< HSE current control max limit = 0.57 ma/V*/
236 #define LL_RCC_HSE_CURRENTMAX_2 RCC_HSECR_HSEGMC1 /*!< HSE current control max limit = 0.78 ma/V*/
237 #define LL_RCC_HSE_CURRENTMAX_3 (RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.13 ma/V*/
238 #define LL_RCC_HSE_CURRENTMAX_4 RCC_HSECR_HSEGMC2 /*!< HSE current control max limit = 0.61 ma/V*/
239 #define LL_RCC_HSE_CURRENTMAX_5 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 1.65 ma/V*/
240 #define LL_RCC_HSE_CURRENTMAX_6 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1) /*!< HSE current control max limit = 2.12 ma/V*/
241 #define LL_RCC_HSE_CURRENTMAX_7 (RCC_HSECR_HSEGMC2|RCC_HSECR_HSEGMC1|RCC_HSECR_HSEGMC0) /*!< HSE current control max limit = 2.84 ma/V*/
242 /**
243 * @}
244 */
245
246 /** @defgroup RCC_LL_EC_HSE_SENSE_AMPLIFIER HSE sense amplifier threshold
247 * @{
248 */
249 #define LL_RCC_HSEAMPTHRESHOLD_1_2 (0x000000000U) /*!< HSE sense amplifier bias current factor = 1/2*/
250 #define LL_RCC_HSEAMPTHRESHOLD_3_4 RCC_HSECR_HSES /*!< HSE sense amplifier bias current factor = 3/4*/
251 /**
252 * @}
253 */
254
255 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
256 * @{
257 */
258 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
259 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
260 /**
261 * @}
262 */
263
264 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
265 * @{
266 */
267 #define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */
268 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
269 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
270 #define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */
271 /**
272 * @}
273 */
274
275 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
276 * @{
277 */
278 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */
279 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
280 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
281 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */
282 /**
283 * @}
284 */
285
286 /** @defgroup RCC_LL_EC_RF_CLKSOURCE_STATUS RF system clock switch status
287 * @{
288 */
289 #define LL_RCC_RF_CLKSOURCE_HSI 0x00000000U /*!< HSI used as RF system clock */
290 #define LL_RCC_RF_CLKSOURCE_HSE_DIV2 RCC_EXTCFGR_RFCSS /*!< HSE divided by 2 used as RF system clock */
291 /**
292 * @}
293 */
294
295
296 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
297 * @{
298 */
299 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
300 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
301 #define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */
302 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
303 #define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */
304 #define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */
305 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
306 #define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */
307 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
308 #define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */
309 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
310 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
311 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
312 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
313 /**
314 * @}
315 */
316
317 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
318 * @{
319 */
320 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */
321 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */
322 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */
323 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */
324 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */
325 /**
326 * @}
327 */
328
329 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
330 * @{
331 */
332 #define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */
333 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */
334 #define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */
335 #define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */
336 #define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */
337 /**
338 * @}
339 */
340
341 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
342 * @{
343 */
344 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
345 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
346 /**
347 * @}
348 */
349
350 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
351 * @{
352 */
353 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
354 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
355 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
356 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
357 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */
358 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
359 #define LL_RCC_MCO1SOURCE_LSI1 (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI1 selection as MCO1 source */
360 #define LL_RCC_MCO1SOURCE_LSI2 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI2 selection as MCO1 source */
361 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */
362 #define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */
363 #define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */
364 /**
365 * @}
366 */
367
368 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
369 * @{
370 */
371 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
372 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
373 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
374 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
375 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
376 /**
377 * @}
378 */
379
380 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE SMPS clock switch
381 * @{
382 */
383 #define LL_RCC_SMPS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as SMPS clock */
384 #define LL_RCC_SMPS_CLKSOURCE_MSI RCC_SMPSCR_SMPSSEL_0 /*!< MSI selection as SMPS clock */
385 #define LL_RCC_SMPS_CLKSOURCE_HSE RCC_SMPSCR_SMPSSEL_1 /*!< HSE selection as SMPS clock */
386
387 /**
388 * @}
389 */
390
391 /** @defgroup RCC_LL_EC_SMPS_CLKSOURCE_STATUS SMPS clock switch status
392 * @{
393 */
394 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as SMPS clock */
395 #define LL_RCC_SMPS_CLKSOURCE_STATUS_MSI RCC_SMPSCR_SMPSSWS_0 /*!< MSI used as SMPS clock */
396 #define LL_RCC_SMPS_CLKSOURCE_STATUS_HSE RCC_SMPSCR_SMPSSWS_1 /*!< HSE used as SMPS clock */
397 #define LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK (RCC_SMPSCR_SMPSSWS_0|RCC_SMPSCR_SMPSSWS_1) /*!< No Clock used as SMPS clock */
398
399 /**
400 * @}
401 */
402
403 /** @defgroup RCC_LL_EC_SMPS_DIV SMPS prescaler
404 * @{
405 */
406 #define LL_RCC_SMPS_DIV_0 (0x00000000U) /*!< SMPS clock division 0 */
407 #define LL_RCC_SMPS_DIV_1 RCC_SMPSCR_SMPSDIV_0 /*!< SMPS clock division 1 */
408 #define LL_RCC_SMPS_DIV_2 RCC_SMPSCR_SMPSDIV_1 /*!< SMPS clock division 2 */
409 #define LL_RCC_SMPS_DIV_3 (RCC_SMPSCR_SMPSDIV_0|RCC_SMPSCR_SMPSDIV_1) /*!< SMPS clock division 3 */
410
411 /**
412 * @}
413 */
414
415
416
417
418 #if defined(USE_FULL_LL_DRIVER)
419 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
420 * @{
421 */
422 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
423 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
424 /**
425 * @}
426 */
427 #endif /* USE_FULL_LL_DRIVER */
428
429 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE USART1 CLKSOURCE
430 * @{
431 */
432 #define LL_RCC_USART1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 selected as USART1 clock */
433 #define LL_RCC_USART1_CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK selected as USART1 clock */
434 #define LL_RCC_USART1_CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI selected as USART1 clock */
435 #define LL_RCC_USART1_CLKSOURCE_LSE RCC_CCIPR_USART1SEL /*!< LSE selected as USART1 clock */
436 /**
437 * @}
438 */
439
440 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE
441 * @{
442 */
443 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */
444 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYCLK selected as LPUART1 clock */
445 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */
446 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */
447 /**
448 * @}
449 */
450
451 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE
452 * @{
453 */
454 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */
455 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */
456 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */
457 #if defined(I2C3)
458 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */
459 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */
460 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */
461 #endif
462 /**
463 * @}
464 */
465
466 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE LPTIMx CLKSOURCE
467 * @{
468 */
469 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM1 clock */
470 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */
471 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */
472 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */
473 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM2 clock */
474 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */
475 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */
476 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */
477 /**
478 * @}
479 */
480
481 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE SAI1 CLKSOURCE
482 * @{
483 */
484 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 0x00000000U /*!< PLLSAI1 selected as SAI1 clock */
485 #define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL selected as SAI1 clock */
486 #define LL_RCC_SAI1_CLKSOURCE_HSI RCC_CCIPR_SAI1SEL_1 /*!< HSI selected as SAI1 clock */
487 #define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL /*!< External input selected as SAI1 clock */
488 /**
489 * @}
490 */
491
492 /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE
493 * @{
494 */
495 #define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock*/
496 #if defined(SAI1)
497 #define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock*/
498 #endif
499 #define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock*/
500 #define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock*/
501 /**
502 * @}
503 */
504
505 /** @defgroup RCC_LL_EC_USB_CLKSOURCE USB CLKSOURCE
506 * @{
507 */
508 #define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock*/
509 #if defined(SAI1)
510 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock*/
511 #endif
512 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock*/
513 #define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock*/
514 /**
515 * @}
516 */
517
518 /** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC
519 * @{
520 */
521 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock*/
522 #if defined(SAI1)
523 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/
524 #endif
525 #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock*/
526 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock*/
527 /**
528 * @}
529 */
530
531 /** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC
532 * @{
533 */
534 #define LL_RCC_RNG_CLKSOURCE_CLK48 0x00000000U /*!< CLK48 divided by 3 selected as RNG Clock */
535 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as ADC clock*/
536 #define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as ADC clock*/
537 /**
538 * @}
539 */
540
541 /** @defgroup RCC_LL_EC_USART1 USART1
542 * @{
543 */
544 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */
545 /**
546 * @}
547 */
548
549 #if defined(LPUART1)
550 /** @defgroup RCC_LL_EC_LPUART1 LPUART1
551 * @{
552 */
553 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */
554 /**
555 * @}
556 */
557 #endif
558
559 /** @defgroup RCC_LL_EC_I2C1 I2C1
560 * @{
561 */
562 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */
563 #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */
564 /**
565 * @}
566 */
567
568 /** @defgroup RCC_LL_EC_LPTIM1 LPTIM1
569 * @{
570 */
571 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */
572 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 clock source selection bits */
573 /**
574 * @}
575 */
576
577 #if defined(SAI1)
578 /** @defgroup RCC_LL_EC_SAI1 SAI1
579 * @{
580 */
581 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 clock source selection bits */
582 /**
583 * @}
584 */
585 #endif
586
587 /** @defgroup RCC_LL_EC_CLK48 CLK48
588 * @{
589 */
590 #define LL_RCC_CLK48_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB clock source selection bits */
591 /**
592 * @}
593 */
594
595 /** @defgroup RCC_LL_EC_USB USB
596 * @{
597 */
598 #define LL_RCC_USB_CLKSOURCE LL_RCC_CLK48_CLKSOURCE /*!< USB clock source selection bits */
599 /**
600 * @}
601 */
602
603 /** @defgroup RCC_LL_EC_RNG RNG
604 * @{
605 */
606 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG clock source selection bits */
607 /**
608 * @}
609 */
610
611 /** @defgroup RCC_LL_EC_ADC ADC
612 * @{
613 */
614 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC clock source selection bits */
615 /**
616 * @}
617 */
618
619 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
620 * @{
621 */
622 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
623 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
624 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
625 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
626
627 /**
628 * @}
629 */
630
631 /** @defgroup RCC_LL_EC_RFWKP_CLKSOURCE RF Wakeup clock source selection
632 * @{
633 */
634 #define LL_RCC_RFWKP_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RF Wakeup clock */
635 #define LL_RCC_RFWKP_CLKSOURCE_LSE RCC_CSR_RFWKPSEL_0 /*!< LSE oscillator clock used as RF Wakeup clock */
636 #define LL_RCC_RFWKP_CLKSOURCE_LSI RCC_CSR_RFWKPSEL_1 /*!< LSI oscillator clock used as RF Wakeup clock */
637 #define LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 RCC_CSR_RFWKPSEL /*!< HSE oscillator clock divided by 1024 used as RF Wakeup clock */
638
639 /**
640 * @}
641 */
642
643
644 /** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLSAI1 entry clock source
645 * @{
646 */
647 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
648 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
649 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
650 #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */
651 /**
652 * @}
653 */
654
655 /** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLSAI1 division factor
656 * @{
657 */
658 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL and PLLSAI1 division factor by 1 */
659 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLSAI1 division factor by 2 */
660 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLSAI1 division factor by 3 */
661 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 4 */
662 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLSAI1 division factor by 5 */
663 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL and PLLSAI1 division factor by 6 */
664 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL and PLLSAI1 division factor by 7 */
665 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL and PLLSAI1 division factor by 8 */
666 /**
667 * @}
668 */
669
670 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
671 * @{
672 */
673 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
674 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
675 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
676 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
677 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
678 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
679 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
680 /**
681 * @}
682 */
683
684 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
685 * @{
686 */
687 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
688 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
689 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
690 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
691 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
692 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
693 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
694 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
695 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
696 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
697 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
698 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
699 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
700 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
701 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
702 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
703 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
704 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
705 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
706 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
707 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
708 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
709 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
710 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
711 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
712 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
713 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
714 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
715 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
716 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
717 #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
718 /**
719 * @}
720 */
721
722 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
723 * @{
724 */
725 #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */
726 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */
727 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
728 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */
729 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
730 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
731 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
732 /**
733 * @}
734 */
735
736
737 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLQ)
738 * @{
739 */
740 #define LL_RCC_PLLSAI1Q_DIV_2 (RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
741 #define LL_RCC_PLLSAI1Q_DIV_3 (RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 3 */
742 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
743 #define LL_RCC_PLLSAI1Q_DIV_5 (RCC_PLLSAI1CFGR_PLLQ_2) /*!< PLLSAI1 division factor for PLLSAI1Q output by 5 */
744 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
745 #define LL_RCC_PLLSAI1Q_DIV_7 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 7 */
746 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLQ_2 | RCC_PLLSAI1CFGR_PLLQ_1 | RCC_PLLSAI1CFGR_PLLQ_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
747 /**
748 * @}
749 */
750
751 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLP)
752 * @{
753 */
754 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
755 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
756 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
757 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
758 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
759 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
760 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2)/*!< Main PLL division factor for PLLP output by 8 */
761 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
762 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
763 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
764 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 12 */
765 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
766 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 14 */
767 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 15 */
768 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
769 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
770 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
771 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
772 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 20 */
773 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
774 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 22 */
775 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 23 */
776 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
777 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
778 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 26 */
779 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 27*/
780 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
781 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 29 */
782 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
783 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
784 #define LL_RCC_PLLSAI1P_DIV_32 (RCC_PLLSAI1CFGR_PLLP_0|RCC_PLLSAI1CFGR_PLLP_1|RCC_PLLSAI1CFGR_PLLP_2|RCC_PLLSAI1CFGR_PLLP_3|RCC_PLLSAI1CFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
785 /**
786 * @}
787 */
788
789 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLR)
790 * @{
791 */
792 #define LL_RCC_PLLSAI1R_DIV_2 (RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
793 #define LL_RCC_PLLSAI1R_DIV_3 (RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 3 */
794 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
795 #define LL_RCC_PLLSAI1R_DIV_5 (RCC_PLLSAI1CFGR_PLLR_2) /*!< PLLSAI1 division factor for PLLSAI1R output by 5 */
796 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
797 #define LL_RCC_PLLSAI1R_DIV_7 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 7 */
798 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLR_2 | RCC_PLLSAI1CFGR_PLLR_1 | RCC_PLLSAI1CFGR_PLLR_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
799 /**
800 * @}
801 */
802
803 /**
804 * @}
805 */
806
807 /* Exported macro ------------------------------------------------------------*/
808 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
809 * @{
810 */
811
812 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
813 * @{
814 */
815
816 /**
817 * @brief Write a value in RCC register
818 * @param __REG__ Register to be written
819 * @param __VALUE__ Value to be written in the register
820 * @retval None
821 */
822 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
823
824 /**
825 * @brief Read a value in RCC register
826 * @param __REG__ Register to be read
827 * @retval Register value
828 */
829 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
830 /**
831 * @}
832 */
833
834 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
835 * @{
836 */
837
838 /**
839 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
840 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
841 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
842 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
843 * @param __PLLM__ This parameter can be one of the following values:
844 * @arg @ref LL_RCC_PLLM_DIV_1
845 * @arg @ref LL_RCC_PLLM_DIV_2
846 * @arg @ref LL_RCC_PLLM_DIV_3
847 * @arg @ref LL_RCC_PLLM_DIV_4
848 * @arg @ref LL_RCC_PLLM_DIV_5
849 * @arg @ref LL_RCC_PLLM_DIV_6
850 * @arg @ref LL_RCC_PLLM_DIV_7
851 * @arg @ref LL_RCC_PLLM_DIV_8
852 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
853 * @param __PLLR__ This parameter can be one of the following values:
854 * @arg @ref LL_RCC_PLLR_DIV_2
855 * @arg @ref LL_RCC_PLLR_DIV_3
856 * @arg @ref LL_RCC_PLLR_DIV_4
857 * @arg @ref LL_RCC_PLLR_DIV_5
858 * @arg @ref LL_RCC_PLLR_DIV_6
859 * @arg @ref LL_RCC_PLLR_DIV_7
860 * @arg @ref LL_RCC_PLLR_DIV_8
861 * @retval PLL clock frequency (in Hz)
862 */
863 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
864 (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
865
866 #if defined(SAI1)
867 /**
868 * @brief Helper macro to calculate the PLLPCLK frequency used on SAI domain
869 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
870 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
871 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
872 * @param __PLLM__ This parameter can be one of the following values:
873 * @arg @ref LL_RCC_PLLM_DIV_1
874 * @arg @ref LL_RCC_PLLM_DIV_2
875 * @arg @ref LL_RCC_PLLM_DIV_3
876 * @arg @ref LL_RCC_PLLM_DIV_4
877 * @arg @ref LL_RCC_PLLM_DIV_5
878 * @arg @ref LL_RCC_PLLM_DIV_6
879 * @arg @ref LL_RCC_PLLM_DIV_7
880 * @arg @ref LL_RCC_PLLM_DIV_8
881 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
882 * @param __PLLP__ This parameter can be one of the following values:
883 * @arg @ref LL_RCC_PLLP_DIV_2
884 * @arg @ref LL_RCC_PLLP_DIV_3
885 * @arg @ref LL_RCC_PLLP_DIV_4
886 * @arg @ref LL_RCC_PLLP_DIV_5
887 * @arg @ref LL_RCC_PLLP_DIV_6
888 * @arg @ref LL_RCC_PLLP_DIV_7
889 * @arg @ref LL_RCC_PLLP_DIV_8
890 * @arg @ref LL_RCC_PLLP_DIV_9
891 * @arg @ref LL_RCC_PLLP_DIV_10
892 * @arg @ref LL_RCC_PLLP_DIV_11
893 * @arg @ref LL_RCC_PLLP_DIV_12
894 * @arg @ref LL_RCC_PLLP_DIV_13
895 * @arg @ref LL_RCC_PLLP_DIV_14
896 * @arg @ref LL_RCC_PLLP_DIV_15
897 * @arg @ref LL_RCC_PLLP_DIV_16
898 * @arg @ref LL_RCC_PLLP_DIV_17
899 * @arg @ref LL_RCC_PLLP_DIV_18
900 * @arg @ref LL_RCC_PLLP_DIV_19
901 * @arg @ref LL_RCC_PLLP_DIV_20
902 * @arg @ref LL_RCC_PLLP_DIV_21
903 * @arg @ref LL_RCC_PLLP_DIV_22
904 * @arg @ref LL_RCC_PLLP_DIV_23
905 * @arg @ref LL_RCC_PLLP_DIV_24
906 * @arg @ref LL_RCC_PLLP_DIV_25
907 * @arg @ref LL_RCC_PLLP_DIV_26
908 * @arg @ref LL_RCC_PLLP_DIV_27
909 * @arg @ref LL_RCC_PLLP_DIV_28
910 * @arg @ref LL_RCC_PLLP_DIV_29
911 * @arg @ref LL_RCC_PLLP_DIV_30
912 * @arg @ref LL_RCC_PLLP_DIV_31
913 * @retval PLL clock frequency (in Hz)
914 */
915 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U))/ \
916 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
917 #endif
918
919 /**
920 * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain
921 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
922 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
923 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
924 * @param __PLLM__ This parameter can be one of the following values:
925 * @arg @ref LL_RCC_PLLM_DIV_1
926 * @arg @ref LL_RCC_PLLM_DIV_2
927 * @arg @ref LL_RCC_PLLM_DIV_3
928 * @arg @ref LL_RCC_PLLM_DIV_4
929 * @arg @ref LL_RCC_PLLM_DIV_5
930 * @arg @ref LL_RCC_PLLM_DIV_6
931 * @arg @ref LL_RCC_PLLM_DIV_7
932 * @arg @ref LL_RCC_PLLM_DIV_8
933 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
934 * @param __PLLP__ This parameter can be one of the following values:
935 * @arg @ref LL_RCC_PLLP_DIV_2
936 * @arg @ref LL_RCC_PLLP_DIV_3
937 * @arg @ref LL_RCC_PLLP_DIV_4
938 * @arg @ref LL_RCC_PLLP_DIV_5
939 * @arg @ref LL_RCC_PLLP_DIV_6
940 * @arg @ref LL_RCC_PLLP_DIV_7
941 * @arg @ref LL_RCC_PLLP_DIV_8
942 * @arg @ref LL_RCC_PLLP_DIV_9
943 * @arg @ref LL_RCC_PLLP_DIV_10
944 * @arg @ref LL_RCC_PLLP_DIV_11
945 * @arg @ref LL_RCC_PLLP_DIV_12
946 * @arg @ref LL_RCC_PLLP_DIV_13
947 * @arg @ref LL_RCC_PLLP_DIV_14
948 * @arg @ref LL_RCC_PLLP_DIV_15
949 * @arg @ref LL_RCC_PLLP_DIV_16
950 * @arg @ref LL_RCC_PLLP_DIV_17
951 * @arg @ref LL_RCC_PLLP_DIV_18
952 * @arg @ref LL_RCC_PLLP_DIV_19
953 * @arg @ref LL_RCC_PLLP_DIV_20
954 * @arg @ref LL_RCC_PLLP_DIV_21
955 * @arg @ref LL_RCC_PLLP_DIV_22
956 * @arg @ref LL_RCC_PLLP_DIV_23
957 * @arg @ref LL_RCC_PLLP_DIV_24
958 * @arg @ref LL_RCC_PLLP_DIV_25
959 * @arg @ref LL_RCC_PLLP_DIV_26
960 * @arg @ref LL_RCC_PLLP_DIV_27
961 * @arg @ref LL_RCC_PLLP_DIV_28
962 * @arg @ref LL_RCC_PLLP_DIV_29
963 * @arg @ref LL_RCC_PLLP_DIV_30
964 * @arg @ref LL_RCC_PLLP_DIV_31
965 * @arg @ref LL_RCC_PLLP_DIV_32
966 * @retval PLL clock frequency (in Hz)
967 */
968 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
969 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
970
971 /**
972 * @brief Helper macro to calculate the PLLQCLK frequency used on 48M domain
973 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
974 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
975 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
976 * @param __PLLM__ This parameter can be one of the following values:
977 * @arg @ref LL_RCC_PLLM_DIV_1
978 * @arg @ref LL_RCC_PLLM_DIV_2
979 * @arg @ref LL_RCC_PLLM_DIV_3
980 * @arg @ref LL_RCC_PLLM_DIV_4
981 * @arg @ref LL_RCC_PLLM_DIV_5
982 * @arg @ref LL_RCC_PLLM_DIV_6
983 * @arg @ref LL_RCC_PLLM_DIV_7
984 * @arg @ref LL_RCC_PLLM_DIV_8
985 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
986 * @param __PLLQ__ This parameter can be one of the following values:
987 * @arg @ref LL_RCC_PLLQ_DIV_2
988 * @arg @ref LL_RCC_PLLQ_DIV_3
989 * @arg @ref LL_RCC_PLLQ_DIV_4
990 * @arg @ref LL_RCC_PLLQ_DIV_5
991 * @arg @ref LL_RCC_PLLQ_DIV_6
992 * @arg @ref LL_RCC_PLLQ_DIV_7
993 * @arg @ref LL_RCC_PLLQ_DIV_8
994 * @retval PLL clock frequency (in Hz)
995 */
996 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
997 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
998
999 #if defined(SAI1)
1000 /**
1001 * @brief Helper macro to calculate the PLLSAI1PCLK frequency used for SAI domain
1002 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1003 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1004 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1005 * @param __PLLM__ This parameter can be one of the following values:
1006 * @arg @ref LL_RCC_PLLM_DIV_1
1007 * @arg @ref LL_RCC_PLLM_DIV_2
1008 * @arg @ref LL_RCC_PLLM_DIV_3
1009 * @arg @ref LL_RCC_PLLM_DIV_4
1010 * @arg @ref LL_RCC_PLLM_DIV_5
1011 * @arg @ref LL_RCC_PLLM_DIV_6
1012 * @arg @ref LL_RCC_PLLM_DIV_7
1013 * @arg @ref LL_RCC_PLLM_DIV_8
1014 * @param __PLLSAI1N__ Between 6 and 127
1015 * @param __PLLSAI1P__ This parameter can be one of the following values:
1016 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1017 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1018 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1019 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1020 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1021 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1022 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1023 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1024 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1025 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1026 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1027 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1028 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1029 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1030 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1031 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1032 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1033 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1034 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1035 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1036 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1037 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1038 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1039 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1040 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1041 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1042 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1043 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1044 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1045 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1046 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
1047 * @retval PLLSAI1 clock frequency (in Hz)
1048 */
1049 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1050 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1051 (((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLP_Pos) + 1U))
1052
1053 /**
1054 * @brief Helper macro to calculate the PLLSAI1QCLK frequency used on 48M domain
1055 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1056 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1057 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1058 * @param __PLLM__ This parameter can be one of the following values:
1059 * @arg @ref LL_RCC_PLLM_DIV_1
1060 * @arg @ref LL_RCC_PLLM_DIV_2
1061 * @arg @ref LL_RCC_PLLM_DIV_3
1062 * @arg @ref LL_RCC_PLLM_DIV_4
1063 * @arg @ref LL_RCC_PLLM_DIV_5
1064 * @arg @ref LL_RCC_PLLM_DIV_6
1065 * @arg @ref LL_RCC_PLLM_DIV_7
1066 * @arg @ref LL_RCC_PLLM_DIV_8
1067 * @param __PLLSAI1N__ Between 6 and 127
1068 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1069 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1070 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
1071 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1072 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
1073 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1074 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
1075 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1076 * @retval PLLSAI1 clock frequency (in Hz)
1077 */
1078 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
1079 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1080 (((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLQ_Pos) + 1U))
1081
1082 /**
1083 * @brief Helper macro to calculate the PLLSAI1RCLK frequency used on ADC domain
1084 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1085 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1086 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1087 * @param __PLLM__ This parameter can be one of the following values:
1088 * @arg @ref LL_RCC_PLLM_DIV_1
1089 * @arg @ref LL_RCC_PLLM_DIV_2
1090 * @arg @ref LL_RCC_PLLM_DIV_3
1091 * @arg @ref LL_RCC_PLLM_DIV_4
1092 * @arg @ref LL_RCC_PLLM_DIV_5
1093 * @arg @ref LL_RCC_PLLM_DIV_6
1094 * @arg @ref LL_RCC_PLLM_DIV_7
1095 * @arg @ref LL_RCC_PLLM_DIV_8
1096 * @param __PLLSAI1N__ Between 6 and 127
1097 * @param __PLLSAI1R__ This parameter can be one of the following values:
1098 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1099 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
1100 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1101 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
1102 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1103 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
1104 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1105 * @retval PLLSAI1 clock frequency (in Hz)
1106 */
1107 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
1108 ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
1109 (((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLR_Pos) + 1U))
1110 #endif
1111
1112 /**
1113 * @brief Helper macro to calculate the HCLK1 frequency
1114 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1115 * @param __CPU1PRESCALER__ This parameter can be one of the following values:
1116 * @arg @ref LL_RCC_SYSCLK_DIV_1
1117 * @arg @ref LL_RCC_SYSCLK_DIV_2
1118 * @arg @ref LL_RCC_SYSCLK_DIV_3
1119 * @arg @ref LL_RCC_SYSCLK_DIV_4
1120 * @arg @ref LL_RCC_SYSCLK_DIV_5
1121 * @arg @ref LL_RCC_SYSCLK_DIV_6
1122 * @arg @ref LL_RCC_SYSCLK_DIV_8
1123 * @arg @ref LL_RCC_SYSCLK_DIV_10
1124 * @arg @ref LL_RCC_SYSCLK_DIV_16
1125 * @arg @ref LL_RCC_SYSCLK_DIV_32
1126 * @arg @ref LL_RCC_SYSCLK_DIV_64
1127 * @arg @ref LL_RCC_SYSCLK_DIV_128
1128 * @arg @ref LL_RCC_SYSCLK_DIV_256
1129 * @arg @ref LL_RCC_SYSCLK_DIV_512
1130 * @retval HCLK1 clock frequency (in Hz)
1131 */
1132 #define __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__,__CPU1PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1133
1134 /**
1135 * @brief Helper macro to calculate the HCLK2 frequency
1136 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1137 * @param __CPU2PRESCALER__ This parameter can be one of the following values:
1138 * @arg @ref LL_RCC_SYSCLK_DIV_1
1139 * @arg @ref LL_RCC_SYSCLK_DIV_2
1140 * @arg @ref LL_RCC_SYSCLK_DIV_3
1141 * @arg @ref LL_RCC_SYSCLK_DIV_4
1142 * @arg @ref LL_RCC_SYSCLK_DIV_5
1143 * @arg @ref LL_RCC_SYSCLK_DIV_6
1144 * @arg @ref LL_RCC_SYSCLK_DIV_8
1145 * @arg @ref LL_RCC_SYSCLK_DIV_10
1146 * @arg @ref LL_RCC_SYSCLK_DIV_16
1147 * @arg @ref LL_RCC_SYSCLK_DIV_32
1148 * @arg @ref LL_RCC_SYSCLK_DIV_64
1149 * @arg @ref LL_RCC_SYSCLK_DIV_128
1150 * @arg @ref LL_RCC_SYSCLK_DIV_256
1151 * @arg @ref LL_RCC_SYSCLK_DIV_512
1152 * @retval HCLK2 clock frequency (in Hz)
1153 */
1154 #define __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos])
1155
1156 /**
1157 * @brief Helper macro to calculate the HCLK4 frequency
1158 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1159 * @param __AHB4PRESCALER__ This parameter can be one of the following values:
1160 * @arg @ref LL_RCC_SYSCLK_DIV_1
1161 * @arg @ref LL_RCC_SYSCLK_DIV_2
1162 * @arg @ref LL_RCC_SYSCLK_DIV_3
1163 * @arg @ref LL_RCC_SYSCLK_DIV_4
1164 * @arg @ref LL_RCC_SYSCLK_DIV_5
1165 * @arg @ref LL_RCC_SYSCLK_DIV_6
1166 * @arg @ref LL_RCC_SYSCLK_DIV_8
1167 * @arg @ref LL_RCC_SYSCLK_DIV_10
1168 * @arg @ref LL_RCC_SYSCLK_DIV_16
1169 * @arg @ref LL_RCC_SYSCLK_DIV_32
1170 * @arg @ref LL_RCC_SYSCLK_DIV_64
1171 * @arg @ref LL_RCC_SYSCLK_DIV_128
1172 * @arg @ref LL_RCC_SYSCLK_DIV_256
1173 * @arg @ref LL_RCC_SYSCLK_DIV_512
1174 * @retval HCLK4 clock frequency (in Hz)
1175 */
1176 #define __LL_RCC_CALC_HCLK4_FREQ(__SYSCLKFREQ__, __AHB4PRESCALER__) ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB4PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos])
1177
1178
1179 /**
1180 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1181 * @param __HCLKFREQ__ HCLK frequency
1182 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1183 * @arg @ref LL_RCC_APB1_DIV_1
1184 * @arg @ref LL_RCC_APB1_DIV_2
1185 * @arg @ref LL_RCC_APB1_DIV_4
1186 * @arg @ref LL_RCC_APB1_DIV_8
1187 * @arg @ref LL_RCC_APB1_DIV_16
1188 * @retval PCLK1 clock frequency (in Hz)
1189 */
1190 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB1PRESCALER__) & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos)] & 31U))
1191
1192 /**
1193 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1194 * @param __HCLKFREQ__ HCLK frequency
1195 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1196 * @arg @ref LL_RCC_APB2_DIV_1
1197 * @arg @ref LL_RCC_APB2_DIV_2
1198 * @arg @ref LL_RCC_APB2_DIV_4
1199 * @arg @ref LL_RCC_APB2_DIV_8
1200 * @arg @ref LL_RCC_APB2_DIV_16
1201 * @retval PCLK2 clock frequency (in Hz)
1202 */
1203 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(((__APB2PRESCALER__) & RCC_CFGR_PPRE2_Msk) >> RCC_CFGR_PPRE2_Pos)] & 31U))
1204
1205 /**
1206 * @brief Helper macro to calculate the MSI frequency (in Hz)
1207 * @note __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange()
1208 * @param __MSIRANGE__ This parameter can be one of the following values:
1209 * @arg @ref LL_RCC_MSIRANGE_0
1210 * @arg @ref LL_RCC_MSIRANGE_1
1211 * @arg @ref LL_RCC_MSIRANGE_2
1212 * @arg @ref LL_RCC_MSIRANGE_3
1213 * @arg @ref LL_RCC_MSIRANGE_4
1214 * @arg @ref LL_RCC_MSIRANGE_5
1215 * @arg @ref LL_RCC_MSIRANGE_6
1216 * @arg @ref LL_RCC_MSIRANGE_7
1217 * @arg @ref LL_RCC_MSIRANGE_8
1218 * @arg @ref LL_RCC_MSIRANGE_9
1219 * @arg @ref LL_RCC_MSIRANGE_10
1220 * @arg @ref LL_RCC_MSIRANGE_11
1221 * @retval MSI clock frequency (in Hz)
1222 */
1223 #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]
1224 /**
1225 * @}
1226 */
1227
1228 /**
1229 * @}
1230 */
1231
1232 /* Exported functions --------------------------------------------------------*/
1233 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1234 * @{
1235 */
1236
1237 /** @defgroup RCC_LL_EF_HSE HSE
1238 * @{
1239 */
1240
1241 /**
1242 * @brief Enable HSE sysclk and pll prescaler division by 2
1243 * @rmtoll CR HSEPRE LL_RCC_HSE_EnableDiv2
1244 * @retval None
1245 */
LL_RCC_HSE_EnableDiv2(void)1246 __STATIC_INLINE void LL_RCC_HSE_EnableDiv2(void)
1247 {
1248 SET_BIT(RCC->CR, RCC_CR_HSEPRE);
1249 }
1250
1251 /**
1252 * @brief Disable HSE sysclk and pll prescaler
1253 * @rmtoll CR HSEPRE LL_RCC_HSE_DisableDiv2
1254 * @retval None
1255 */
LL_RCC_HSE_DisableDiv2(void)1256 __STATIC_INLINE void LL_RCC_HSE_DisableDiv2(void)
1257 {
1258 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
1259 }
1260
1261 /**
1262 * @brief Get HSE sysclk and pll prescaler
1263 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledDiv2
1264 * @retval None
1265 */
LL_RCC_HSE_IsEnabledDiv2(void)1266 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2(void)
1267 {
1268 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
1269 }
1270
1271 /**
1272 * @brief Enable the Clock Security System.
1273 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1274 * @retval None
1275 */
LL_RCC_HSE_EnableCSS(void)1276 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1277 {
1278 SET_BIT(RCC->CR, RCC_CR_CSSON);
1279 }
1280
1281 /**
1282 * @brief Enable HSE external oscillator (HSE Bypass)
1283 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1284 * @retval None
1285 */
LL_RCC_HSE_EnableBypass(void)1286 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1287 {
1288 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1289 }
1290
1291 /**
1292 * @brief Disable HSE external oscillator (HSE Bypass)
1293 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1294 * @retval None
1295 */
LL_RCC_HSE_DisableBypass(void)1296 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1297 {
1298 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1299 }
1300
1301 /**
1302 * @brief Enable HSE crystal oscillator (HSE ON)
1303 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1304 * @retval None
1305 */
LL_RCC_HSE_Enable(void)1306 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1307 {
1308 SET_BIT(RCC->CR, RCC_CR_HSEON);
1309 }
1310
1311 /**
1312 * @brief Disable HSE crystal oscillator (HSE ON)
1313 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1314 * @retval None
1315 */
LL_RCC_HSE_Disable(void)1316 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1317 {
1318 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1319 }
1320
1321 /**
1322 * @brief Check if HSE oscillator Ready
1323 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1324 * @retval State of bit (1 or 0).
1325 */
LL_RCC_HSE_IsReady(void)1326 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1327 {
1328 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1329 }
1330
1331 /**
1332 * @brief Check if HSE clock control register is locked or not
1333 * @rmtoll HSECR UNLOCKED LL_RCC_HSE_IsClockControlLocked
1334 * @retval State of bit (1 or 0).
1335 */
LL_RCC_HSE_IsClockControlLocked(void)1336 __STATIC_INLINE uint32_t LL_RCC_HSE_IsClockControlLocked(void)
1337 {
1338 return ((READ_BIT(RCC->HSECR, RCC_HSECR_UNLOCKED) != (RCC_HSECR_UNLOCKED)) ? 1UL : 0UL);
1339 }
1340
1341 /**
1342 * @brief Set HSE capacitor tuning
1343 * @rmtoll HSECR HSETUNE LL_RCC_HSE_SetCapacitorTuning
1344 * @param Value Between Min_Data = 0 and Max_Data = 63
1345 * @retval None
1346 */
LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)1347 __STATIC_INLINE void LL_RCC_HSE_SetCapacitorTuning(uint32_t Value)
1348 {
1349 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1350 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSETUNE, Value << RCC_HSECR_HSETUNE_Pos);
1351 }
1352
1353 /**
1354 * @brief Get HSE capacitor tuning
1355 * @rmtoll HSECR HSETUNE LL_RCC_HSE_GetCapacitorTuning
1356 * @retval Between Min_Data = 0 and Max_Data = 63
1357 */
LL_RCC_HSE_GetCapacitorTuning(void)1358 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCapacitorTuning(void)
1359 {
1360 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSETUNE) >> RCC_HSECR_HSETUNE_Pos);
1361 }
1362
1363 /**
1364 * @brief Set HSE current control
1365 * @rmtoll HSECR HSEGMC LL_RCC_HSE_SetCurrentControl
1366 * @param CurrentMax This parameter can be one of the following values:
1367 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
1368 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
1369 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
1370 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
1371 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
1372 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
1373 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
1374 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
1375 */
LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)1376 __STATIC_INLINE void LL_RCC_HSE_SetCurrentControl(uint32_t CurrentMax)
1377 {
1378 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1379 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSEGMC, CurrentMax);
1380 }
1381
1382 /**
1383 * @brief Get HSE current control
1384 * @rmtoll HSECR HSEGMC LL_RCC_HSE_GetCurrentControl
1385 * @retval Returned value can be one of the following values:
1386 * @arg @ref LL_RCC_HSE_CURRENTMAX_0
1387 * @arg @ref LL_RCC_HSE_CURRENTMAX_1
1388 * @arg @ref LL_RCC_HSE_CURRENTMAX_2
1389 * @arg @ref LL_RCC_HSE_CURRENTMAX_3
1390 * @arg @ref LL_RCC_HSE_CURRENTMAX_4
1391 * @arg @ref LL_RCC_HSE_CURRENTMAX_5
1392 * @arg @ref LL_RCC_HSE_CURRENTMAX_6
1393 * @arg @ref LL_RCC_HSE_CURRENTMAX_7
1394 */
LL_RCC_HSE_GetCurrentControl(void)1395 __STATIC_INLINE uint32_t LL_RCC_HSE_GetCurrentControl(void)
1396 {
1397 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSEGMC));
1398 }
1399
1400 /**
1401 * @brief Set HSE sense amplifier threshold
1402 * @rmtoll HSECR HSES LL_RCC_HSE_SetSenseAmplifier
1403 * @param SenseAmplifier This parameter can be one of the following values:
1404 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
1405 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
1406 */
LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)1407 __STATIC_INLINE void LL_RCC_HSE_SetSenseAmplifier(uint32_t SenseAmplifier)
1408 {
1409 WRITE_REG(RCC->HSECR, HSE_CONTROL_UNLOCK_KEY);
1410 MODIFY_REG(RCC->HSECR, RCC_HSECR_HSES, SenseAmplifier);
1411 }
1412
1413 /**
1414 * @brief Get HSE current control
1415 * @rmtoll HSECR HSES LL_RCC_HSE_GetSenseAmplifier
1416 * @retval Returned value can be one of the following values:
1417 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_1_2
1418 * @arg @ref LL_RCC_HSEAMPTHRESHOLD_3_4
1419 */
LL_RCC_HSE_GetSenseAmplifier(void)1420 __STATIC_INLINE uint32_t LL_RCC_HSE_GetSenseAmplifier(void)
1421 {
1422 return (uint32_t)(READ_BIT(RCC->HSECR, RCC_HSECR_HSES));
1423 }
1424 /**
1425 * @}
1426 */
1427
1428 /** @defgroup RCC_LL_EF_HSI HSI
1429 * @{
1430 */
1431
1432 /**
1433 * @brief Enable HSI even in stop mode
1434 * @note HSI oscillator is forced ON even in Stop mode
1435 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1436 * @retval None
1437 */
LL_RCC_HSI_EnableInStopMode(void)1438 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1439 {
1440 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1441 }
1442
1443 /**
1444 * @brief Disable HSI in stop mode
1445 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1446 * @retval None
1447 */
LL_RCC_HSI_DisableInStopMode(void)1448 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1449 {
1450 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1451 }
1452
1453 /**
1454 * @brief Check if HSI in stop mode is ready
1455 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1456 * @retval State of bit (1 or 0).
1457 */
LL_RCC_HSI_IsEnabledInStopMode(void)1458 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1459 {
1460 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
1461 }
1462
1463 /**
1464 * @brief Enable HSI oscillator
1465 * @rmtoll CR HSION LL_RCC_HSI_Enable
1466 * @retval None
1467 */
LL_RCC_HSI_Enable(void)1468 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1469 {
1470 SET_BIT(RCC->CR, RCC_CR_HSION);
1471 }
1472
1473 /**
1474 * @brief Disable HSI oscillator
1475 * @rmtoll CR HSION LL_RCC_HSI_Disable
1476 * @retval None
1477 */
LL_RCC_HSI_Disable(void)1478 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1479 {
1480 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1481 }
1482
1483 /**
1484 * @brief Check if HSI clock is ready
1485 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1486 * @retval State of bit (1 or 0).
1487 */
LL_RCC_HSI_IsReady(void)1488 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1489 {
1490 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1491 }
1492
1493 /**
1494 * @brief Enable HSI Automatic from stop mode
1495 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
1496 * @retval None
1497 */
LL_RCC_HSI_EnableAutoFromStop(void)1498 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
1499 {
1500 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
1501 }
1502
1503 /**
1504 * @brief Disable HSI Automatic from stop mode
1505 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
1506 * @retval None
1507 */
LL_RCC_HSI_DisableAutoFromStop(void)1508 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
1509 {
1510 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
1511 }
1512 /**
1513 * @brief Get HSI Calibration value
1514 * @note When HSITRIM is written, HSICAL is updated with the sum of
1515 * HSITRIM and the factory trim value
1516 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1517 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1518 */
LL_RCC_HSI_GetCalibration(void)1519 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1520 {
1521 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1522 }
1523
1524 /**
1525 * @brief Set HSI Calibration trimming
1526 * @note user-programmable trimming value that is added to the HSICAL
1527 * @note Default value is 64, which, when added to the HSICAL value,
1528 * should trim the HSI to 16 MHz +/- 1 %
1529 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1530 * @param Value Between Min_Data = 0 and Max_Data = 127
1531 * @retval None
1532 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1533 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1534 {
1535 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1536 }
1537
1538 /**
1539 * @brief Get HSI Calibration trimming
1540 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1541 * @retval Between Min_Data = 0 and Max_Data = 127
1542 */
LL_RCC_HSI_GetCalibTrimming(void)1543 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1544 {
1545 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1546 }
1547
1548 /**
1549 * @}
1550 */
1551
1552 /** @defgroup RCC_LL_EF_HSI48 HSI48
1553 * @{
1554 */
1555
1556 /**
1557 * @brief Enable HSI48
1558 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
1559 * @retval None
1560 */
LL_RCC_HSI48_Enable(void)1561 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1562 {
1563 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1564 }
1565
1566 /**
1567 * @brief Disable HSI48
1568 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
1569 * @retval None
1570 */
LL_RCC_HSI48_Disable(void)1571 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1572 {
1573 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1574 }
1575
1576 /**
1577 * @brief Check if HSI48 oscillator Ready
1578 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
1579 * @retval State of bit (1 or 0).
1580 */
LL_RCC_HSI48_IsReady(void)1581 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1582 {
1583 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
1584 }
1585
1586 /**
1587 * @brief Get HSI48 Calibration value
1588 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1589 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1590 */
LL_RCC_HSI48_GetCalibration(void)1591 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1592 {
1593 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1594 }
1595
1596 /**
1597 * @}
1598 */
1599
1600 /** @defgroup RCC_LL_EF_LSE LSE
1601 * @{
1602 */
1603
1604 /**
1605 * @brief Enable Low Speed External (LSE) crystal.
1606 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1607 * @retval None
1608 */
LL_RCC_LSE_Enable(void)1609 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1610 {
1611 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1612 }
1613
1614 /**
1615 * @brief Disable Low Speed External (LSE) crystal.
1616 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1617 * @retval None
1618 */
LL_RCC_LSE_Disable(void)1619 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1620 {
1621 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1622 }
1623
1624 /**
1625 * @brief Check if Low Speed External (LSE) crystal has been enabled or not
1626 * @rmtoll BDCR LSEON LL_RCC_LSE_IsEnabled
1627 * @retval State of bit (1 or 0).
1628 */
LL_RCC_LSE_IsEnabled(void)1629 __STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void)
1630 {
1631 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL);
1632 }
1633
1634 /**
1635 * @brief Enable external clock source (LSE bypass).
1636 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1637 * @retval None
1638 */
LL_RCC_LSE_EnableBypass(void)1639 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1640 {
1641 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1642 }
1643
1644 /**
1645 * @brief Disable external clock source (LSE bypass).
1646 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1647 * @retval None
1648 */
LL_RCC_LSE_DisableBypass(void)1649 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1650 {
1651 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1652 }
1653
1654 /**
1655 * @brief Set LSE oscillator drive capability
1656 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1657 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1658 * @param LSEDrive This parameter can be one of the following values:
1659 * @arg @ref LL_RCC_LSEDRIVE_LOW
1660 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1661 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1662 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1663 * @retval None
1664 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1665 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1666 {
1667 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1668 }
1669
1670 /**
1671 * @brief Get LSE oscillator drive capability
1672 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1673 * @retval Returned value can be one of the following values:
1674 * @arg @ref LL_RCC_LSEDRIVE_LOW
1675 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1676 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1677 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1678 */
LL_RCC_LSE_GetDriveCapability(void)1679 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1680 {
1681 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1682 }
1683
1684 /**
1685 * @brief Enable Clock security system on LSE.
1686 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1687 * @retval None
1688 */
LL_RCC_LSE_EnableCSS(void)1689 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1690 {
1691 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1692 }
1693
1694 /**
1695 * @brief Disable Clock security system on LSE.
1696 * @note Clock security system can be disabled only after a LSE
1697 * failure detection. In that case it MUST be disabled by software.
1698 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1699 * @retval None
1700 */
LL_RCC_LSE_DisableCSS(void)1701 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1702 {
1703 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1704 }
1705
1706 /**
1707 * @brief Check if LSE oscillator Ready
1708 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1709 * @retval State of bit (1 or 0).
1710 */
LL_RCC_LSE_IsReady(void)1711 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1712 {
1713 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1714 }
1715
1716 /**
1717 * @brief Check if CSS on LSE failure Detection
1718 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1719 * @retval State of bit (1 or 0).
1720 */
LL_RCC_LSE_IsCSSDetected(void)1721 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1722 {
1723 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1724 }
1725
1726 /**
1727 * @}
1728 */
1729
1730 /** @defgroup RCC_LL_EF_LSI1 LSI1
1731 * @{
1732 */
1733
1734 /**
1735 * @brief Enable LSI1 Oscillator
1736 * @rmtoll CSR LSI1ON LL_RCC_LSI1_Enable
1737 * @retval None
1738 */
LL_RCC_LSI1_Enable(void)1739 __STATIC_INLINE void LL_RCC_LSI1_Enable(void)
1740 {
1741 SET_BIT(RCC->CSR, RCC_CSR_LSI1ON);
1742 }
1743
1744 /**
1745 * @brief Disable LSI1 Oscillator
1746 * @rmtoll CSR LSI1ON LL_RCC_LSI1_Disable
1747 * @retval None
1748 */
LL_RCC_LSI1_Disable(void)1749 __STATIC_INLINE void LL_RCC_LSI1_Disable(void)
1750 {
1751 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI1ON);
1752 }
1753
1754 /**
1755 * @brief Check if LSI1 is Ready
1756 * @rmtoll CSR LSI1RDY LL_RCC_LSI1_IsReady
1757 * @retval State of bit (1 or 0).
1758 */
LL_RCC_LSI1_IsReady(void)1759 __STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void)
1760 {
1761 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI1RDY) == (RCC_CSR_LSI1RDY)) ? 1UL : 0UL);
1762 }
1763
1764 /**
1765 * @}
1766 */
1767
1768 /** @defgroup RCC_LL_EF_LSI2 LSI2
1769 * @{
1770 */
1771
1772 /**
1773 * @brief Enable LSI2 Oscillator
1774 * @rmtoll CSR LSI2ON LL_RCC_LSI2_Enable
1775 * @retval None
1776 */
LL_RCC_LSI2_Enable(void)1777 __STATIC_INLINE void LL_RCC_LSI2_Enable(void)
1778 {
1779 SET_BIT(RCC->CSR, RCC_CSR_LSI2ON);
1780 }
1781
1782 /**
1783 * @brief Disable LSI2 Oscillator
1784 * @rmtoll CSR LSI2ON LL_RCC_LSI2_Disable
1785 * @retval None
1786 */
LL_RCC_LSI2_Disable(void)1787 __STATIC_INLINE void LL_RCC_LSI2_Disable(void)
1788 {
1789 CLEAR_BIT(RCC->CSR, RCC_CSR_LSI2ON);
1790 }
1791
1792 /**
1793 * @brief Check if LSI2 is Ready
1794 * @rmtoll CSR LSI2RDY LL_RCC_LSI2_IsReady
1795 * @retval State of bit (1 or 0).
1796 */
LL_RCC_LSI2_IsReady(void)1797 __STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void)
1798 {
1799 return ((READ_BIT(RCC->CSR, RCC_CSR_LSI2RDY) == (RCC_CSR_LSI2RDY)) ? 1UL : 0UL);
1800 }
1801
1802 /**
1803 * @brief Set LSI2 trimming value
1804 * @rmtoll CSR LSI2TRIM LL_RCC_LSI2_SetTrimming
1805 * @param Value Between Min_Data = 0 and Max_Data = 15
1806 * @retval None
1807 */
LL_RCC_LSI2_SetTrimming(uint32_t Value)1808 __STATIC_INLINE void LL_RCC_LSI2_SetTrimming(uint32_t Value)
1809 {
1810 MODIFY_REG(RCC->CSR, RCC_CSR_LSI2TRIM, Value << RCC_CSR_LSI2TRIM_Pos);
1811 }
1812
1813 /**
1814 * @brief Get LSI2 trimming value
1815 * @rmtoll CSR LSI2TRIM LL_RCC_LSI2_GetTrimming
1816 * @retval Between Min_Data = 0 and Max_Data = 12
1817 */
LL_RCC_LSI2_GetTrimming(void)1818 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetTrimming(void)
1819 {
1820 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSI2TRIM) >> RCC_CSR_LSI2TRIM_Pos);
1821 }
1822
1823 /**
1824 * @}
1825 */
1826
1827 /** @defgroup RCC_LL_EF_MSI MSI
1828 * @{
1829 */
1830
1831 /**
1832 * @brief Enable MSI oscillator
1833 * @rmtoll CR MSION LL_RCC_MSI_Enable
1834 * @retval None
1835 */
LL_RCC_MSI_Enable(void)1836 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1837 {
1838 SET_BIT(RCC->CR, RCC_CR_MSION);
1839 }
1840
1841 /**
1842 * @brief Disable MSI oscillator
1843 * @rmtoll CR MSION LL_RCC_MSI_Disable
1844 * @retval None
1845 */
LL_RCC_MSI_Disable(void)1846 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1847 {
1848 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
1849 }
1850
1851 /**
1852 * @brief Check if MSI oscillator Ready
1853 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
1854 * @retval State of bit (1 or 0).
1855 */
LL_RCC_MSI_IsReady(void)1856 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1857 {
1858 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
1859 }
1860
1861 /**
1862 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
1863 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
1864 * and ready (LSERDY set by hardware)
1865 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
1866 * ready
1867 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
1868 * @retval None
1869 */
LL_RCC_MSI_EnablePLLMode(void)1870 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
1871 {
1872 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1873 }
1874
1875 /**
1876 * @brief Disable MSI-PLL mode
1877 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
1878 * the Clock Security System on LSE detects a LSE failure
1879 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
1880 * @retval None
1881 */
LL_RCC_MSI_DisablePLLMode(void)1882 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
1883 {
1884 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1885 }
1886
1887
1888 /**
1889 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
1890 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
1891 * @param Range This parameter can be one of the following values:
1892 * @arg @ref LL_RCC_MSIRANGE_0
1893 * @arg @ref LL_RCC_MSIRANGE_1
1894 * @arg @ref LL_RCC_MSIRANGE_2
1895 * @arg @ref LL_RCC_MSIRANGE_3
1896 * @arg @ref LL_RCC_MSIRANGE_4
1897 * @arg @ref LL_RCC_MSIRANGE_5
1898 * @arg @ref LL_RCC_MSIRANGE_6
1899 * @arg @ref LL_RCC_MSIRANGE_7
1900 * @arg @ref LL_RCC_MSIRANGE_8
1901 * @arg @ref LL_RCC_MSIRANGE_9
1902 * @arg @ref LL_RCC_MSIRANGE_10
1903 * @arg @ref LL_RCC_MSIRANGE_11
1904 * @retval None
1905 */
LL_RCC_MSI_SetRange(uint32_t Range)1906 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
1907 {
1908 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
1909 }
1910
1911 /**
1912 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
1913 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
1914 * @retval Returned value can be one of the following values:
1915 * @arg @ref LL_RCC_MSIRANGE_0
1916 * @arg @ref LL_RCC_MSIRANGE_1
1917 * @arg @ref LL_RCC_MSIRANGE_2
1918 * @arg @ref LL_RCC_MSIRANGE_3
1919 * @arg @ref LL_RCC_MSIRANGE_4
1920 * @arg @ref LL_RCC_MSIRANGE_5
1921 * @arg @ref LL_RCC_MSIRANGE_6
1922 * @arg @ref LL_RCC_MSIRANGE_7
1923 * @arg @ref LL_RCC_MSIRANGE_8
1924 * @arg @ref LL_RCC_MSIRANGE_9
1925 * @arg @ref LL_RCC_MSIRANGE_10
1926 * @arg @ref LL_RCC_MSIRANGE_11
1927 */
LL_RCC_MSI_GetRange(void)1928 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
1929 {
1930 uint32_t msiRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
1931 if (msiRange > LL_RCC_MSIRANGE_11)
1932 {
1933 msiRange = LL_RCC_MSIRANGE_11;
1934 }
1935 return msiRange;
1936 }
1937
1938
1939 /**
1940 * @brief Get MSI Calibration value
1941 * @note When MSITRIM is written, MSICAL is updated with the sum of
1942 * MSITRIM and the factory trim value
1943 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
1944 * @retval Between Min_Data = 0 and Max_Data = 255
1945 */
LL_RCC_MSI_GetCalibration(void)1946 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
1947 {
1948 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
1949 }
1950
1951 /**
1952 * @brief Set MSI Calibration trimming
1953 * @note user-programmable trimming value that is added to the MSICAL
1954 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
1955 * @param Value Between Min_Data = 0 and Max_Data = 255
1956 * @retval None
1957 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)1958 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
1959 {
1960 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
1961 }
1962
1963 /**
1964 * @brief Get MSI Calibration trimming
1965 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
1966 * @retval Between 0 and 255
1967 */
LL_RCC_MSI_GetCalibTrimming(void)1968 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
1969 {
1970 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
1971 }
1972
1973 /**
1974 * @}
1975 */
1976
1977 /** @defgroup RCC_LL_EF_LSCO LSCO
1978 * @{
1979 */
1980
1981 /**
1982 * @brief Enable Low speed clock
1983 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1984 * @retval None
1985 */
LL_RCC_LSCO_Enable(void)1986 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1987 {
1988 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1989 }
1990
1991 /**
1992 * @brief Disable Low speed clock
1993 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1994 * @retval None
1995 */
LL_RCC_LSCO_Disable(void)1996 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1997 {
1998 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1999 }
2000
2001 /**
2002 * @brief Configure Low speed clock selection
2003 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2004 * @param Source This parameter can be one of the following values:
2005 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2006 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2007 * @retval None
2008 */
LL_RCC_LSCO_SetSource(uint32_t Source)2009 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2010 {
2011 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2012 }
2013
2014 /**
2015 * @brief Get Low speed clock selection
2016 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2017 * @retval Returned value can be one of the following values:
2018 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2019 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2020 */
LL_RCC_LSCO_GetSource(void)2021 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2022 {
2023 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2024 }
2025
2026 /**
2027 * @}
2028 */
2029
2030 /** @defgroup RCC_LL_EF_System System
2031 * @{
2032 */
2033
2034 /**
2035 * @brief Configure the system clock source
2036 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2037 * @param Source This parameter can be one of the following values:
2038 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
2039 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2040 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2041 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2042 * @retval None
2043 */
LL_RCC_SetSysClkSource(uint32_t Source)2044 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2045 {
2046 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2047 }
2048
2049 /**
2050 * @brief Get the system clock source
2051 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2052 * @retval Returned value can be one of the following values:
2053 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
2054 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2055 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2056 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2057 */
LL_RCC_GetSysClkSource(void)2058 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2059 {
2060 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2061 }
2062
2063 /**
2064 * @brief Get the RF clock source
2065 * @rmtoll EXTCFGR RFCSS LL_RCC_GetRFClockSource
2066 * @retval Returned value can be one of the following values:
2067 * @arg @ref LL_RCC_RF_CLKSOURCE_HSI
2068 * @arg @ref LL_RCC_RF_CLKSOURCE_HSE_DIV2
2069 */
LL_RCC_GetRFClockSource(void)2070 __STATIC_INLINE uint32_t LL_RCC_GetRFClockSource(void)
2071 {
2072 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_RFCSS));
2073 }
2074
2075 /**
2076 * @brief Set RF Wakeup Clock Source
2077 * @rmtoll CSR RFWKPSEL LL_RCC_SetRFWKPClockSource
2078 * @param Source This parameter can be one of the following values:
2079 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
2080 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
2081 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI
2082 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
2083 * @retval None
2084 */
LL_RCC_SetRFWKPClockSource(uint32_t Source)2085 __STATIC_INLINE void LL_RCC_SetRFWKPClockSource(uint32_t Source)
2086 {
2087 MODIFY_REG(RCC->CSR, RCC_CSR_RFWKPSEL, Source);
2088 }
2089
2090 /**
2091 * @brief Get RF Wakeup Clock Source
2092 * @rmtoll CSR RFWKPSEL LL_RCC_GetRFWKPClockSource
2093 * @retval Returned value can be one of the following values:
2094 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_NONE
2095 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSE
2096 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_LSI
2097 * @arg @ref LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024
2098 */
LL_RCC_GetRFWKPClockSource(void)2099 __STATIC_INLINE uint32_t LL_RCC_GetRFWKPClockSource(void)
2100 {
2101 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RFWKPSEL));
2102 }
2103
2104 /**
2105 * @brief Check if Radio System is reset.
2106 * @rmtoll CSR RFRSTS LL_RCC_IsRFUnderReset
2107 * @retval State of bit (1 or 0).
2108 */
LL_RCC_IsRFUnderReset(void)2109 __STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void)
2110 {
2111 return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTS) == (RCC_CSR_RFRSTS)) ? 1UL : 0UL);
2112 }
2113
2114 /**
2115 * @brief Set AHB prescaler
2116 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2117 * @param Prescaler This parameter can be one of the following values:
2118 * @arg @ref LL_RCC_SYSCLK_DIV_1
2119 * @arg @ref LL_RCC_SYSCLK_DIV_2
2120 * @arg @ref LL_RCC_SYSCLK_DIV_3
2121 * @arg @ref LL_RCC_SYSCLK_DIV_4
2122 * @arg @ref LL_RCC_SYSCLK_DIV_5
2123 * @arg @ref LL_RCC_SYSCLK_DIV_6
2124 * @arg @ref LL_RCC_SYSCLK_DIV_8
2125 * @arg @ref LL_RCC_SYSCLK_DIV_10
2126 * @arg @ref LL_RCC_SYSCLK_DIV_16
2127 * @arg @ref LL_RCC_SYSCLK_DIV_32
2128 * @arg @ref LL_RCC_SYSCLK_DIV_64
2129 * @arg @ref LL_RCC_SYSCLK_DIV_128
2130 * @arg @ref LL_RCC_SYSCLK_DIV_256
2131 * @arg @ref LL_RCC_SYSCLK_DIV_512
2132 * @retval None
2133 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2134 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2135 {
2136 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2137 }
2138
2139 /**
2140 * @brief Set CPU2 AHB prescaler
2141 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_SetAHBPrescaler
2142 * @param Prescaler This parameter can be one of the following values:
2143 * @arg @ref LL_RCC_SYSCLK_DIV_1
2144 * @arg @ref LL_RCC_SYSCLK_DIV_2
2145 * @arg @ref LL_RCC_SYSCLK_DIV_3
2146 * @arg @ref LL_RCC_SYSCLK_DIV_4
2147 * @arg @ref LL_RCC_SYSCLK_DIV_5
2148 * @arg @ref LL_RCC_SYSCLK_DIV_6
2149 * @arg @ref LL_RCC_SYSCLK_DIV_8
2150 * @arg @ref LL_RCC_SYSCLK_DIV_10
2151 * @arg @ref LL_RCC_SYSCLK_DIV_16
2152 * @arg @ref LL_RCC_SYSCLK_DIV_32
2153 * @arg @ref LL_RCC_SYSCLK_DIV_64
2154 * @arg @ref LL_RCC_SYSCLK_DIV_128
2155 * @arg @ref LL_RCC_SYSCLK_DIV_256
2156 * @arg @ref LL_RCC_SYSCLK_DIV_512
2157 * @retval None
2158 */
LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)2159 __STATIC_INLINE void LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)
2160 {
2161 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
2162 }
2163
2164 /**
2165 * @brief Set AHB4 prescaler
2166 * @rmtoll EXTCFGR SHDHPRE LL_RCC_SetAHB4Prescaler
2167 * @param Prescaler This parameter can be one of the following values:
2168 * @arg @ref LL_RCC_SYSCLK_DIV_1
2169 * @arg @ref LL_RCC_SYSCLK_DIV_2
2170 * @arg @ref LL_RCC_SYSCLK_DIV_3
2171 * @arg @ref LL_RCC_SYSCLK_DIV_4
2172 * @arg @ref LL_RCC_SYSCLK_DIV_5
2173 * @arg @ref LL_RCC_SYSCLK_DIV_6
2174 * @arg @ref LL_RCC_SYSCLK_DIV_8
2175 * @arg @ref LL_RCC_SYSCLK_DIV_10
2176 * @arg @ref LL_RCC_SYSCLK_DIV_16
2177 * @arg @ref LL_RCC_SYSCLK_DIV_32
2178 * @arg @ref LL_RCC_SYSCLK_DIV_64
2179 * @arg @ref LL_RCC_SYSCLK_DIV_128
2180 * @arg @ref LL_RCC_SYSCLK_DIV_256
2181 * @arg @ref LL_RCC_SYSCLK_DIV_512
2182 * @retval None
2183 */
LL_RCC_SetAHB4Prescaler(uint32_t Prescaler)2184 __STATIC_INLINE void LL_RCC_SetAHB4Prescaler(uint32_t Prescaler)
2185 {
2186 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
2187 }
2188
2189 /**
2190 * @brief Set APB1 prescaler
2191 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2192 * @param Prescaler This parameter can be one of the following values:
2193 * @arg @ref LL_RCC_APB1_DIV_1
2194 * @arg @ref LL_RCC_APB1_DIV_2
2195 * @arg @ref LL_RCC_APB1_DIV_4
2196 * @arg @ref LL_RCC_APB1_DIV_8
2197 * @arg @ref LL_RCC_APB1_DIV_16
2198 * @retval None
2199 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2200 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2201 {
2202 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2203 }
2204
2205 /**
2206 * @brief Set APB2 prescaler
2207 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2208 * @param Prescaler This parameter can be one of the following values:
2209 * @arg @ref LL_RCC_APB2_DIV_1
2210 * @arg @ref LL_RCC_APB2_DIV_2
2211 * @arg @ref LL_RCC_APB2_DIV_4
2212 * @arg @ref LL_RCC_APB2_DIV_8
2213 * @arg @ref LL_RCC_APB2_DIV_16
2214 * @retval None
2215 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2216 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2217 {
2218 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2219 }
2220
2221 /**
2222 * @brief Get AHB prescaler
2223 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2224 * @retval Returned value can be one of the following values:
2225 * @arg @ref LL_RCC_SYSCLK_DIV_1
2226 * @arg @ref LL_RCC_SYSCLK_DIV_2
2227 * @arg @ref LL_RCC_SYSCLK_DIV_3
2228 * @arg @ref LL_RCC_SYSCLK_DIV_4
2229 * @arg @ref LL_RCC_SYSCLK_DIV_5
2230 * @arg @ref LL_RCC_SYSCLK_DIV_6
2231 * @arg @ref LL_RCC_SYSCLK_DIV_8
2232 * @arg @ref LL_RCC_SYSCLK_DIV_10
2233 * @arg @ref LL_RCC_SYSCLK_DIV_16
2234 * @arg @ref LL_RCC_SYSCLK_DIV_32
2235 * @arg @ref LL_RCC_SYSCLK_DIV_64
2236 * @arg @ref LL_RCC_SYSCLK_DIV_128
2237 * @arg @ref LL_RCC_SYSCLK_DIV_256
2238 * @arg @ref LL_RCC_SYSCLK_DIV_512
2239 */
LL_RCC_GetAHBPrescaler(void)2240 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2241 {
2242 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2243 }
2244
2245 /**
2246 * @brief Get C2 AHB prescaler
2247 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_GetAHBPrescaler
2248 * @retval Returned value can be one of the following values:
2249 * @arg @ref LL_RCC_SYSCLK_DIV_1
2250 * @arg @ref LL_RCC_SYSCLK_DIV_2
2251 * @arg @ref LL_RCC_SYSCLK_DIV_3
2252 * @arg @ref LL_RCC_SYSCLK_DIV_4
2253 * @arg @ref LL_RCC_SYSCLK_DIV_5
2254 * @arg @ref LL_RCC_SYSCLK_DIV_6
2255 * @arg @ref LL_RCC_SYSCLK_DIV_8
2256 * @arg @ref LL_RCC_SYSCLK_DIV_10
2257 * @arg @ref LL_RCC_SYSCLK_DIV_16
2258 * @arg @ref LL_RCC_SYSCLK_DIV_32
2259 * @arg @ref LL_RCC_SYSCLK_DIV_64
2260 * @arg @ref LL_RCC_SYSCLK_DIV_128
2261 * @arg @ref LL_RCC_SYSCLK_DIV_256
2262 * @arg @ref LL_RCC_SYSCLK_DIV_512
2263 */
LL_C2_RCC_GetAHBPrescaler(void)2264 __STATIC_INLINE uint32_t LL_C2_RCC_GetAHBPrescaler(void)
2265 {
2266 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE));
2267 }
2268
2269 /**
2270 * @brief Get AHB4 prescaler
2271 * @rmtoll EXTCFGR SHDHPRE LL_RCC_GetAHB4Prescaler
2272 * @retval Returned value can be one of the following values:
2273 * @arg @ref LL_RCC_SYSCLK_DIV_1
2274 * @arg @ref LL_RCC_SYSCLK_DIV_2
2275 * @arg @ref LL_RCC_SYSCLK_DIV_3
2276 * @arg @ref LL_RCC_SYSCLK_DIV_4
2277 * @arg @ref LL_RCC_SYSCLK_DIV_5
2278 * @arg @ref LL_RCC_SYSCLK_DIV_6
2279 * @arg @ref LL_RCC_SYSCLK_DIV_8
2280 * @arg @ref LL_RCC_SYSCLK_DIV_10
2281 * @arg @ref LL_RCC_SYSCLK_DIV_16
2282 * @arg @ref LL_RCC_SYSCLK_DIV_32
2283 * @arg @ref LL_RCC_SYSCLK_DIV_64
2284 * @arg @ref LL_RCC_SYSCLK_DIV_128
2285 * @arg @ref LL_RCC_SYSCLK_DIV_256
2286 * @arg @ref LL_RCC_SYSCLK_DIV_512
2287 */
LL_RCC_GetAHB4Prescaler(void)2288 __STATIC_INLINE uint32_t LL_RCC_GetAHB4Prescaler(void)
2289 {
2290 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
2291 }
2292
2293 /**
2294 * @brief Get APB1 prescaler
2295 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2296 * @retval Returned value can be one of the following values:
2297 * @arg @ref LL_RCC_APB1_DIV_1
2298 * @arg @ref LL_RCC_APB1_DIV_2
2299 * @arg @ref LL_RCC_APB1_DIV_4
2300 * @arg @ref LL_RCC_APB1_DIV_8
2301 * @arg @ref LL_RCC_APB1_DIV_16
2302 */
LL_RCC_GetAPB1Prescaler(void)2303 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2304 {
2305 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2306 }
2307
2308 /**
2309 * @brief Get APB2 prescaler
2310 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2311 * @retval Returned value can be one of the following values:
2312 * @arg @ref LL_RCC_APB2_DIV_1
2313 * @arg @ref LL_RCC_APB2_DIV_2
2314 * @arg @ref LL_RCC_APB2_DIV_4
2315 * @arg @ref LL_RCC_APB2_DIV_8
2316 * @arg @ref LL_RCC_APB2_DIV_16
2317 */
LL_RCC_GetAPB2Prescaler(void)2318 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2319 {
2320 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2321 }
2322
2323 /**
2324 * @brief Set Clock After Wake-Up From Stop mode
2325 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2326 * @param Clock This parameter can be one of the following values:
2327 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2328 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2329 * @retval None
2330 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2331 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2332 {
2333 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
2334 }
2335
2336 /**
2337 * @brief Get Clock After Wake-Up From Stop mode
2338 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2339 * @retval Returned value can be one of the following values:
2340 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2341 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2342 */
LL_RCC_GetClkAfterWakeFromStop(void)2343 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2344 {
2345 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2346 }
2347
2348 /**
2349 * @}
2350 */
2351
2352 #if defined(RCC_SMPS_SUPPORT)
2353 /** @defgroup RCC_LL_EF_SMPS SMPS
2354 * @{
2355 */
2356 /**
2357 * @brief Configure SMPS step down converter clock source
2358 * @rmtoll SMPSCR SMPSSEL LL_RCC_SetSMPSClockSource
2359 * @param SMPSSource This parameter can be one of the following values:
2360 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
2361 * @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI (*)
2362 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
2363 * @note The system must always be configured so as to get a SMPS Step Down
2364 * converter clock frequency between 2 MHz and 8 MHz
2365 * @note (*) The MSI shall only be selected as SMPS Step Down converter
2366 * clock source when a supported SMPS Step Down converter clock
2367 * MSIRANGE is set (LL_RCC_MSIRANGE_8 to LL_RCC_MSIRANGE_11)
2368 * @retval None
2369 */
LL_RCC_SetSMPSClockSource(uint32_t SMPSSource)2370 __STATIC_INLINE void LL_RCC_SetSMPSClockSource(uint32_t SMPSSource)
2371 {
2372 MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL, SMPSSource);
2373 }
2374
2375 /**
2376 * @brief Get the SMPS clock source selection
2377 * @rmtoll SMPSCR SMPSSEL LL_RCC_GetSMPSClockSelection
2378 * @retval Returned value can be one of the following values:
2379 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSI
2380 * @arg @ref LL_RCC_SMPS_CLKSOURCE_MSI
2381 * @arg @ref LL_RCC_SMPS_CLKSOURCE_HSE
2382 */
LL_RCC_GetSMPSClockSelection(void)2383 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSelection(void)
2384 {
2385 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSEL));
2386 }
2387
2388
2389 /**
2390 * @brief Get the SMPS clock source
2391 * @rmtoll SMPSCR SMPSSWS LL_RCC_GetSMPSClockSource
2392 * @retval Returned value can be one of the following values:
2393 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSI
2394 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_MSI
2395 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_HSE
2396 * @arg @ref LL_RCC_SMPS_CLKSOURCE_STATUS_NO_CLOCK
2397 */
LL_RCC_GetSMPSClockSource(void)2398 __STATIC_INLINE uint32_t LL_RCC_GetSMPSClockSource(void)
2399 {
2400 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSSWS));
2401 }
2402
2403 /**
2404 * @brief Set SMPS prescaler
2405 * @rmtoll SMPSCR SMPSDIV LL_RCC_SetSMPSPrescaler
2406 * @param Prescaler This parameter can be one of the following values:
2407 * @arg @ref LL_RCC_SMPS_DIV_0
2408 * @arg @ref LL_RCC_SMPS_DIV_1
2409 * @arg @ref LL_RCC_SMPS_DIV_2
2410 * @arg @ref LL_RCC_SMPS_DIV_3
2411 * @retval None
2412 */
LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)2413 __STATIC_INLINE void LL_RCC_SetSMPSPrescaler(uint32_t Prescaler)
2414 {
2415 MODIFY_REG(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV, Prescaler);
2416 }
2417
2418 /**
2419 * @brief Get SMPS prescaler
2420 * @rmtoll SMPSCR SMPSDIV LL_RCC_GetSMPSPrescaler
2421 * @retval Returned value can be one of the following values:
2422 * @arg @ref LL_RCC_SMPS_DIV_0
2423 * @arg @ref LL_RCC_SMPS_DIV_1
2424 * @arg @ref LL_RCC_SMPS_DIV_2
2425 * @arg @ref LL_RCC_SMPS_DIV_3
2426 */
LL_RCC_GetSMPSPrescaler(void)2427 __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void)
2428 {
2429 return (uint32_t)(READ_BIT(RCC->SMPSCR, RCC_SMPSCR_SMPSDIV));
2430 }
2431
2432 /**
2433 * @}
2434 */
2435 #endif
2436
2437 /** @defgroup RCC_LL_EF_MCO MCO
2438 * @{
2439 */
2440
2441 /**
2442 * @brief Configure MCOx
2443 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
2444 * CFGR MCOPRE LL_RCC_ConfigMCO
2445 * @param MCOxSource This parameter can be one of the following values:
2446 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
2447 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
2448 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2449 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2450 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2451 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2452 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2453 * @arg @ref LL_RCC_MCO1SOURCE_LSI1
2454 * @arg @ref LL_RCC_MCO1SOURCE_LSI2
2455 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2456 * @arg @ref LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB
2457 * @param MCOxPrescaler This parameter can be one of the following values:
2458 * @arg @ref LL_RCC_MCO1_DIV_1
2459 * @arg @ref LL_RCC_MCO1_DIV_2
2460 * @arg @ref LL_RCC_MCO1_DIV_4
2461 * @arg @ref LL_RCC_MCO1_DIV_8
2462 * @arg @ref LL_RCC_MCO1_DIV_16
2463 * @retval None
2464 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2465 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2466 {
2467 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2468 }
2469
2470 /**
2471 * @}
2472 */
2473
2474 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2475 * @{
2476 */
2477
2478 /**
2479 * @brief Configure USARTx clock source
2480 * @rmtoll CCIPR USART1SEL LL_RCC_SetUSARTClockSource
2481 * @param USARTxSource This parameter can be one of the following values:
2482 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2483 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2484 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2485 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2486 * @retval None
2487 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2488 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2489 {
2490 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, USARTxSource);
2491 }
2492
2493 #if defined(LPUART1)
2494 /**
2495 * @brief Configure LPUART1x clock source
2496 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2497 * @param LPUARTxSource This parameter can be one of the following values:
2498 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2499 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2500 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2501 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2502 * @retval None
2503 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2504 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2505 {
2506 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
2507 }
2508 #endif
2509
2510 /**
2511 * @brief Configure I2Cx clock source
2512 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
2513 * @param I2CxSource This parameter can be one of the following values:
2514 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2515 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2516 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2517 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2518 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2519 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2520 * @retval None
2521 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2522 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2523 {
2524 MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
2525 }
2526
2527 /**
2528 * @brief Configure LPTIMx clock source
2529 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
2530 * @param LPTIMxSource This parameter can be one of the following values:
2531 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2532 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2533 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2534 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2535 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2536 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2537 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2538 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2539 * @retval None
2540 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2541 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2542 {
2543 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
2544 }
2545
2546 #if defined(SAI1)
2547 /**
2548 * @brief Configure SAIx clock source
2549 * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
2550 * @param SAIxSource This parameter can be one of the following values:
2551 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2552 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2553 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
2554 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2555 * @retval None
2556 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)2557 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2558 {
2559 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
2560 }
2561 #endif
2562
2563 /**
2564 * @brief Configure RNG clock source
2565 * @note In case of CLK48 clock selected, it must be configured first thanks to LL_RCC_SetCLK48ClockSource
2566 * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource
2567 * @param RNGxSource This parameter can be one of the following values:
2568 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2569 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2570 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2571 * @retval None
2572 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2573 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2574 {
2575 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
2576 }
2577
2578 /**
2579 * @brief Configure CLK48 clock source
2580 * @rmtoll CCIPR CLK48SEL LL_RCC_SetCLK48ClockSource
2581 * @param CLK48xSource This parameter can be one of the following values:
2582 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
2583 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1
2584 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2585 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2586 * @retval None
2587 */
LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)2588 __STATIC_INLINE void LL_RCC_SetCLK48ClockSource(uint32_t CLK48xSource)
2589 {
2590 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, CLK48xSource);
2591 }
2592
2593 /**
2594 * @brief Configure USB clock source
2595 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
2596 * @param USBxSource This parameter can be one of the following values:
2597 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2598 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2599 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2600 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2601 * @retval None
2602 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)2603 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2604 {
2605 LL_RCC_SetCLK48ClockSource(USBxSource);
2606 }
2607
2608 /**
2609 * @brief Configure RNG clock source
2610 * @note Allow to configure the overall RNG Clock source, if CLK48 is selected as RNG
2611 Clock source, the CLK48xSource has to be configured
2612 * @rmtoll CCIPR RNGSEL LL_RCC_ConfigRNGClockSource
2613 * @rmtoll CCIPR CLK48SEL LL_RCC_ConfigRNGClockSource
2614 * @param RNGxSource This parameter can be one of the following values:
2615 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2616 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2617 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2618 * @param CLK48xSource This parameter can be one of the following values:
2619 * @arg @ref LL_RCC_CLK48_CLKSOURCE_HSI48
2620 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLLSAI1
2621 * @arg @ref LL_RCC_CLK48_CLKSOURCE_PLL
2622 * @arg @ref LL_RCC_CLK48_CLKSOURCE_MSI
2623
2624 * @retval None
2625 */
LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource,uint32_t CLK48xSource)2626 __STATIC_INLINE void LL_RCC_ConfigRNGClockSource(uint32_t RNGxSource, uint32_t CLK48xSource)
2627 {
2628 if (RNGxSource == LL_RCC_RNG_CLKSOURCE_CLK48)
2629 {
2630 LL_RCC_SetCLK48ClockSource(CLK48xSource);
2631 }
2632 LL_RCC_SetRNGClockSource(RNGxSource);
2633 }
2634
2635
2636 /**
2637 * @brief Configure ADC clock source
2638 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
2639 * @param ADCxSource This parameter can be one of the following values:
2640 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2641 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
2642 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2643 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2644 * @retval None
2645 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2646 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2647 {
2648 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
2649 }
2650
2651 /**
2652 * @brief Get USARTx clock source
2653 * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource
2654 * @param USARTx This parameter can be one of the following values:
2655 * @arg @ref LL_RCC_USART1_CLKSOURCE
2656 * @retval Returned value can be one of the following values:
2657 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2658 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2659 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2660 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2661 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2662 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2663 {
2664 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx));
2665 }
2666
2667 #if defined(LPUART1)
2668 /**
2669 * @brief Get LPUARTx clock source
2670 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
2671 * @param LPUARTx This parameter can be one of the following values:
2672 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2673 * @retval Returned value can be one of the following values:
2674 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2675 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2676 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2677 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2678 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2679 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2680 {
2681 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
2682 }
2683 #endif
2684
2685 /**
2686 * @brief Get I2Cx clock source
2687 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
2688 * @param I2Cx This parameter can be one of the following values:
2689 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2690 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2691 * @retval Returned value can be one of the following values:
2692 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2693 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2694 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2695 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2696 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2697 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2698 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2699 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2700 {
2701 return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
2702 }
2703
2704 /**
2705 * @brief Get LPTIMx clock source
2706 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
2707 * @param LPTIMx This parameter can be one of the following values:
2708 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2709 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2710 * @retval Returned value can be one of the following values:
2711 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2712 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2713 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2714 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2715 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2716 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2717 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2718 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2719 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2720 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2721 {
2722 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16) | LPTIMx);
2723 }
2724
2725 #if defined(SAI1)
2726 /**
2727 * @brief Get SAIx clock source
2728 * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
2729 * @param SAIx This parameter can be one of the following values:
2730 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2731 * @retval Returned value can be one of the following values:
2732 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
2733 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
2734 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
2735 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2736 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2737 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2738 {
2739 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
2740 }
2741 #endif
2742
2743 /**
2744 * @brief Get RNGx clock source
2745 * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource
2746 * @param RNGx This parameter can be one of the following values:
2747 * @arg @ref LL_RCC_RNG_CLKSOURCE
2748 * @retval Returned value can be one of the following values:
2749 * @arg @ref LL_RCC_RNG_CLKSOURCE_CLK48
2750 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2751 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2752 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2753 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2754 {
2755 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
2756 }
2757
2758 /**
2759 * @brief Get CLK48x clock source
2760 * @rmtoll CCIPR CLK48SEL LL_RCC_GetCLK48ClockSource
2761 * @param CLK48x This parameter can be one of the following values:
2762 * @arg @ref LL_RCC_CLK48_CLKSOURCE
2763 * @retval Returned value can be one of the following values:
2764 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2765 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2766 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2767 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2768 */
LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)2769 __STATIC_INLINE uint32_t LL_RCC_GetCLK48ClockSource(uint32_t CLK48x)
2770 {
2771 return (uint32_t)(READ_BIT(RCC->CCIPR, CLK48x));
2772 }
2773
2774 /**
2775 * @brief Get USBx clock source
2776 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
2777 * @param USBx This parameter can be one of the following values:
2778 * @arg @ref LL_RCC_USB_CLKSOURCE
2779 * @retval Returned value can be one of the following values:
2780 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
2781 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
2782 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2783 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
2784 */
LL_RCC_GetUSBClockSource(uint32_t USBx)2785 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2786 {
2787 return LL_RCC_GetCLK48ClockSource(USBx);
2788 }
2789
2790 /**
2791 * @brief Get ADCx clock source
2792 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
2793 * @param ADCx This parameter can be one of the following values:
2794 * @arg @ref LL_RCC_ADC_CLKSOURCE
2795 * @retval Returned value can be one of the following values:
2796 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2797 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
2798 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2799 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2800 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2801 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2802 {
2803 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
2804 }
2805
2806 /**
2807 * @}
2808 */
2809
2810 /** @defgroup RCC_LL_EF_RTC RTC
2811 * @{
2812 */
2813
2814 /**
2815 * @brief Set RTC Clock Source
2816 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2817 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2818 * set). The BDRST bit can be used to reset them.
2819 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2820 * @param Source This parameter can be one of the following values:
2821 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2822 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2823 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2824 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2825 * @retval None
2826 */
LL_RCC_SetRTCClockSource(uint32_t Source)2827 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2828 {
2829 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2830 }
2831
2832 /**
2833 * @brief Get RTC Clock Source
2834 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2835 * @retval Returned value can be one of the following values:
2836 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2837 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2838 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2839 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2840 */
LL_RCC_GetRTCClockSource(void)2841 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2842 {
2843 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2844 }
2845
2846 /**
2847 * @brief Enable RTC
2848 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2849 * @retval None
2850 */
LL_RCC_EnableRTC(void)2851 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2852 {
2853 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2854 }
2855
2856 /**
2857 * @brief Disable RTC
2858 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2859 * @retval None
2860 */
LL_RCC_DisableRTC(void)2861 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2862 {
2863 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2864 }
2865
2866 /**
2867 * @brief Check if RTC has been enabled or not
2868 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2869 * @retval State of bit (1 or 0).
2870 */
LL_RCC_IsEnabledRTC(void)2871 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2872 {
2873 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2874 }
2875
2876 /**
2877 * @brief Force the Backup domain reset
2878 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2879 * @retval None
2880 */
LL_RCC_ForceBackupDomainReset(void)2881 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2882 {
2883 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2884 }
2885
2886 /**
2887 * @brief Release the Backup domain reset
2888 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2889 * @retval None
2890 */
LL_RCC_ReleaseBackupDomainReset(void)2891 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2892 {
2893 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2894 }
2895
2896 /**
2897 * @}
2898 */
2899
2900
2901 /** @defgroup RCC_LL_EF_PLL PLL
2902 * @{
2903 */
2904
2905 /**
2906 * @brief Enable PLL
2907 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2908 * @retval None
2909 */
LL_RCC_PLL_Enable(void)2910 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2911 {
2912 SET_BIT(RCC->CR, RCC_CR_PLLON);
2913 }
2914
2915 /**
2916 * @brief Disable PLL
2917 * @note Cannot be disabled if the PLL clock is used as the system clock
2918 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2919 * @retval None
2920 */
LL_RCC_PLL_Disable(void)2921 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2922 {
2923 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2924 }
2925
2926 /**
2927 * @brief Check if PLL Ready
2928 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2929 * @retval State of bit (1 or 0).
2930 */
LL_RCC_PLL_IsReady(void)2931 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2932 {
2933 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2934 }
2935
2936 /**
2937 * @brief Configure PLL used for SYSCLK Domain
2938 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2939 * PLLSAI1 are disabled
2940 * @note PLLN/PLLR can be written only when PLL is disabled
2941 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2942 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2943 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2944 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2945 * @param Source This parameter can be one of the following values:
2946 * @arg @ref LL_RCC_PLLSOURCE_NONE
2947 * @arg @ref LL_RCC_PLLSOURCE_MSI
2948 * @arg @ref LL_RCC_PLLSOURCE_HSI
2949 * @arg @ref LL_RCC_PLLSOURCE_HSE
2950 * @param PLLM This parameter can be one of the following values:
2951 * @arg @ref LL_RCC_PLLM_DIV_1
2952 * @arg @ref LL_RCC_PLLM_DIV_2
2953 * @arg @ref LL_RCC_PLLM_DIV_3
2954 * @arg @ref LL_RCC_PLLM_DIV_4
2955 * @arg @ref LL_RCC_PLLM_DIV_5
2956 * @arg @ref LL_RCC_PLLM_DIV_6
2957 * @arg @ref LL_RCC_PLLM_DIV_7
2958 * @arg @ref LL_RCC_PLLM_DIV_8
2959 * @param PLLN Between 6 and 127
2960 * @param PLLR This parameter can be one of the following values:
2961 * @arg @ref LL_RCC_PLLR_DIV_2
2962 * @arg @ref LL_RCC_PLLR_DIV_4
2963 * @arg @ref LL_RCC_PLLR_DIV_6
2964 * @arg @ref LL_RCC_PLLR_DIV_8
2965 * @retval None
2966 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2967 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2968 {
2969 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2970 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2971 }
2972
2973 #if defined(SAI1)
2974 /**
2975 * @brief Configure PLL used for SAI domain clock
2976 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2977 * PLLSAI1 are disabled
2978 * @note PLLN/PLLP can be written only when PLL is disabled
2979 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
2980 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
2981 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
2982 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
2983 * @param Source This parameter can be one of the following values:
2984 * @arg @ref LL_RCC_PLLSOURCE_NONE
2985 * @arg @ref LL_RCC_PLLSOURCE_MSI
2986 * @arg @ref LL_RCC_PLLSOURCE_HSI
2987 * @arg @ref LL_RCC_PLLSOURCE_HSE
2988 * @param PLLM This parameter can be one of the following values:
2989 * @arg @ref LL_RCC_PLLM_DIV_1
2990 * @arg @ref LL_RCC_PLLM_DIV_2
2991 * @arg @ref LL_RCC_PLLM_DIV_3
2992 * @arg @ref LL_RCC_PLLM_DIV_4
2993 * @arg @ref LL_RCC_PLLM_DIV_5
2994 * @arg @ref LL_RCC_PLLM_DIV_6
2995 * @arg @ref LL_RCC_PLLM_DIV_7
2996 * @arg @ref LL_RCC_PLLM_DIV_8
2997 * @param PLLN Between 6 and 127
2998 * @param PLLP This parameter can be one of the following values:
2999 * @arg @ref LL_RCC_PLLP_DIV_2
3000 * @arg @ref LL_RCC_PLLP_DIV_3
3001 * @arg @ref LL_RCC_PLLP_DIV_4
3002 * @arg @ref LL_RCC_PLLP_DIV_5
3003 * @arg @ref LL_RCC_PLLP_DIV_6
3004 * @arg @ref LL_RCC_PLLP_DIV_7
3005 * @arg @ref LL_RCC_PLLP_DIV_8
3006 * @arg @ref LL_RCC_PLLP_DIV_9
3007 * @arg @ref LL_RCC_PLLP_DIV_10
3008 * @arg @ref LL_RCC_PLLP_DIV_11
3009 * @arg @ref LL_RCC_PLLP_DIV_12
3010 * @arg @ref LL_RCC_PLLP_DIV_13
3011 * @arg @ref LL_RCC_PLLP_DIV_14
3012 * @arg @ref LL_RCC_PLLP_DIV_15
3013 * @arg @ref LL_RCC_PLLP_DIV_16
3014 * @arg @ref LL_RCC_PLLP_DIV_17
3015 * @arg @ref LL_RCC_PLLP_DIV_18
3016 * @arg @ref LL_RCC_PLLP_DIV_19
3017 * @arg @ref LL_RCC_PLLP_DIV_20
3018 * @arg @ref LL_RCC_PLLP_DIV_21
3019 * @arg @ref LL_RCC_PLLP_DIV_22
3020 * @arg @ref LL_RCC_PLLP_DIV_23
3021 * @arg @ref LL_RCC_PLLP_DIV_24
3022 * @arg @ref LL_RCC_PLLP_DIV_25
3023 * @arg @ref LL_RCC_PLLP_DIV_26
3024 * @arg @ref LL_RCC_PLLP_DIV_27
3025 * @arg @ref LL_RCC_PLLP_DIV_28
3026 * @arg @ref LL_RCC_PLLP_DIV_29
3027 * @arg @ref LL_RCC_PLLP_DIV_30
3028 * @arg @ref LL_RCC_PLLP_DIV_31
3029 * @arg @ref LL_RCC_PLLP_DIV_32
3030 * @retval None
3031 */
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3032 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3033 {
3034 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3035 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3036 }
3037 #endif
3038
3039 /**
3040 * @brief Configure PLL used for ADC domain clock
3041 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3042 * PLLSAI1 are disabled
3043 * @note PLLN/PLLP can be written only when PLL is disabled
3044 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
3045 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
3046 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
3047 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
3048 * @param Source This parameter can be one of the following values:
3049 * @arg @ref LL_RCC_PLLSOURCE_NONE
3050 * @arg @ref LL_RCC_PLLSOURCE_MSI
3051 * @arg @ref LL_RCC_PLLSOURCE_HSI
3052 * @arg @ref LL_RCC_PLLSOURCE_HSE
3053 * @param PLLM This parameter can be one of the following values:
3054 * @arg @ref LL_RCC_PLLM_DIV_1
3055 * @arg @ref LL_RCC_PLLM_DIV_2
3056 * @arg @ref LL_RCC_PLLM_DIV_3
3057 * @arg @ref LL_RCC_PLLM_DIV_4
3058 * @arg @ref LL_RCC_PLLM_DIV_5
3059 * @arg @ref LL_RCC_PLLM_DIV_6
3060 * @arg @ref LL_RCC_PLLM_DIV_7
3061 * @arg @ref LL_RCC_PLLM_DIV_8
3062 * @param PLLN Between 6 and 127
3063 * @param PLLP This parameter can be one of the following values:
3064 * @arg @ref LL_RCC_PLLP_DIV_2
3065 * @arg @ref LL_RCC_PLLP_DIV_3
3066 * @arg @ref LL_RCC_PLLP_DIV_4
3067 * @arg @ref LL_RCC_PLLP_DIV_5
3068 * @arg @ref LL_RCC_PLLP_DIV_6
3069 * @arg @ref LL_RCC_PLLP_DIV_7
3070 * @arg @ref LL_RCC_PLLP_DIV_8
3071 * @arg @ref LL_RCC_PLLP_DIV_9
3072 * @arg @ref LL_RCC_PLLP_DIV_10
3073 * @arg @ref LL_RCC_PLLP_DIV_11
3074 * @arg @ref LL_RCC_PLLP_DIV_12
3075 * @arg @ref LL_RCC_PLLP_DIV_13
3076 * @arg @ref LL_RCC_PLLP_DIV_14
3077 * @arg @ref LL_RCC_PLLP_DIV_15
3078 * @arg @ref LL_RCC_PLLP_DIV_16
3079 * @arg @ref LL_RCC_PLLP_DIV_17
3080 * @arg @ref LL_RCC_PLLP_DIV_18
3081 * @arg @ref LL_RCC_PLLP_DIV_19
3082 * @arg @ref LL_RCC_PLLP_DIV_20
3083 * @arg @ref LL_RCC_PLLP_DIV_21
3084 * @arg @ref LL_RCC_PLLP_DIV_22
3085 * @arg @ref LL_RCC_PLLP_DIV_23
3086 * @arg @ref LL_RCC_PLLP_DIV_24
3087 * @arg @ref LL_RCC_PLLP_DIV_25
3088 * @arg @ref LL_RCC_PLLP_DIV_26
3089 * @arg @ref LL_RCC_PLLP_DIV_27
3090 * @arg @ref LL_RCC_PLLP_DIV_28
3091 * @arg @ref LL_RCC_PLLP_DIV_29
3092 * @arg @ref LL_RCC_PLLP_DIV_30
3093 * @arg @ref LL_RCC_PLLP_DIV_31
3094 * @arg @ref LL_RCC_PLLP_DIV_32
3095 * @retval None
3096 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3097 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3098 {
3099 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3100 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3101 }
3102
3103 /**
3104 * @brief Configure PLL used for 48Mhz domain clock
3105 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3106 * PLLSAI1 are disabled
3107 * @note PLLN/PLLQ can be written only when PLL is disabled
3108 * @note This can be selected for USB, RNG
3109 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3110 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3111 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3112 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3113 * @param Source This parameter can be one of the following values:
3114 * @arg @ref LL_RCC_PLLSOURCE_NONE
3115 * @arg @ref LL_RCC_PLLSOURCE_MSI
3116 * @arg @ref LL_RCC_PLLSOURCE_HSI
3117 * @arg @ref LL_RCC_PLLSOURCE_HSE
3118 * @param PLLM This parameter can be one of the following values:
3119 * @arg @ref LL_RCC_PLLM_DIV_1
3120 * @arg @ref LL_RCC_PLLM_DIV_2
3121 * @arg @ref LL_RCC_PLLM_DIV_3
3122 * @arg @ref LL_RCC_PLLM_DIV_4
3123 * @arg @ref LL_RCC_PLLM_DIV_5
3124 * @arg @ref LL_RCC_PLLM_DIV_6
3125 * @arg @ref LL_RCC_PLLM_DIV_7
3126 * @arg @ref LL_RCC_PLLM_DIV_8
3127 * @param PLLN Between 6 and 127
3128 * @param PLLQ This parameter can be one of the following values:
3129 * @arg @ref LL_RCC_PLLQ_DIV_2
3130 * @arg @ref LL_RCC_PLLQ_DIV_3
3131 * @arg @ref LL_RCC_PLLQ_DIV_4
3132 * @arg @ref LL_RCC_PLLQ_DIV_5
3133 * @arg @ref LL_RCC_PLLQ_DIV_6
3134 * @arg @ref LL_RCC_PLLQ_DIV_7
3135 * @arg @ref LL_RCC_PLLQ_DIV_8
3136 * @retval None
3137 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3138 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3139 {
3140 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3141 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
3142 }
3143
3144 /**
3145 * @brief Get Main PLL multiplication factor for VCO
3146 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3147 * @retval Between 6 and 127
3148 */
LL_RCC_PLL_GetN(void)3149 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
3150 {
3151 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
3152 }
3153
3154 /**
3155 * @brief Get Main PLL division factor for PLLP
3156 * @note used for PLLSAI1CLK (SAI1 clock)
3157 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
3158 * @retval Returned value can be one of the following values:
3159 * @arg @ref LL_RCC_PLLP_DIV_2
3160 * @arg @ref LL_RCC_PLLP_DIV_3
3161 * @arg @ref LL_RCC_PLLP_DIV_4
3162 * @arg @ref LL_RCC_PLLP_DIV_5
3163 * @arg @ref LL_RCC_PLLP_DIV_6
3164 * @arg @ref LL_RCC_PLLP_DIV_7
3165 * @arg @ref LL_RCC_PLLP_DIV_8
3166 * @arg @ref LL_RCC_PLLP_DIV_9
3167 * @arg @ref LL_RCC_PLLP_DIV_10
3168 * @arg @ref LL_RCC_PLLP_DIV_11
3169 * @arg @ref LL_RCC_PLLP_DIV_12
3170 * @arg @ref LL_RCC_PLLP_DIV_13
3171 * @arg @ref LL_RCC_PLLP_DIV_14
3172 * @arg @ref LL_RCC_PLLP_DIV_15
3173 * @arg @ref LL_RCC_PLLP_DIV_16
3174 * @arg @ref LL_RCC_PLLP_DIV_17
3175 * @arg @ref LL_RCC_PLLP_DIV_18
3176 * @arg @ref LL_RCC_PLLP_DIV_19
3177 * @arg @ref LL_RCC_PLLP_DIV_20
3178 * @arg @ref LL_RCC_PLLP_DIV_21
3179 * @arg @ref LL_RCC_PLLP_DIV_22
3180 * @arg @ref LL_RCC_PLLP_DIV_23
3181 * @arg @ref LL_RCC_PLLP_DIV_24
3182 * @arg @ref LL_RCC_PLLP_DIV_25
3183 * @arg @ref LL_RCC_PLLP_DIV_26
3184 * @arg @ref LL_RCC_PLLP_DIV_27
3185 * @arg @ref LL_RCC_PLLP_DIV_28
3186 * @arg @ref LL_RCC_PLLP_DIV_29
3187 * @arg @ref LL_RCC_PLLP_DIV_30
3188 * @arg @ref LL_RCC_PLLP_DIV_31
3189 * @arg @ref LL_RCC_PLLP_DIV_32
3190 */
LL_RCC_PLL_GetP(void)3191 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3192 {
3193 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3194 }
3195
3196 /**
3197 * @brief Get Main PLL division factor for PLLQ
3198 * @note used for PLL48MCLK selected for USB, RNG (48 MHz clock)
3199 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3200 * @retval Returned value can be one of the following values:
3201 * @arg @ref LL_RCC_PLLQ_DIV_2
3202 * @arg @ref LL_RCC_PLLQ_DIV_3
3203 * @arg @ref LL_RCC_PLLQ_DIV_4
3204 * @arg @ref LL_RCC_PLLQ_DIV_5
3205 * @arg @ref LL_RCC_PLLQ_DIV_6
3206 * @arg @ref LL_RCC_PLLQ_DIV_7
3207 * @arg @ref LL_RCC_PLLQ_DIV_8
3208 */
LL_RCC_PLL_GetQ(void)3209 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3210 {
3211 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3212 }
3213
3214 /**
3215 * @brief Get Main PLL division factor for PLLR
3216 * @note used for PLLCLK (system clock)
3217 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3218 * @retval Returned value can be one of the following values:
3219 * @arg @ref LL_RCC_PLLR_DIV_2
3220 * @arg @ref LL_RCC_PLLR_DIV_3
3221 * @arg @ref LL_RCC_PLLR_DIV_4
3222 * @arg @ref LL_RCC_PLLR_DIV_5
3223 * @arg @ref LL_RCC_PLLR_DIV_6
3224 * @arg @ref LL_RCC_PLLR_DIV_7
3225 * @arg @ref LL_RCC_PLLR_DIV_8
3226 */
LL_RCC_PLL_GetR(void)3227 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3228 {
3229 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3230 }
3231
3232 /**
3233 * @brief Get Division factor for the main PLL and other PLL
3234 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3235 * @retval Returned value can be one of the following values:
3236 * @arg @ref LL_RCC_PLLM_DIV_1
3237 * @arg @ref LL_RCC_PLLM_DIV_2
3238 * @arg @ref LL_RCC_PLLM_DIV_3
3239 * @arg @ref LL_RCC_PLLM_DIV_4
3240 * @arg @ref LL_RCC_PLLM_DIV_5
3241 * @arg @ref LL_RCC_PLLM_DIV_6
3242 * @arg @ref LL_RCC_PLLM_DIV_7
3243 * @arg @ref LL_RCC_PLLM_DIV_8
3244 */
LL_RCC_PLL_GetDivider(void)3245 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3246 {
3247 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3248 }
3249
3250 #if defined(SAI1)
3251 /**
3252 * @brief Enable PLL output mapped on SAI domain clock
3253 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
3254 * @retval None
3255 */
LL_RCC_PLL_EnableDomain_SAI(void)3256 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
3257 {
3258 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3259 }
3260
3261 /**
3262 * @brief Disable PLL output mapped on SAI domain clock
3263 * @note In order to save power, when the PLLCLK of the PLL is
3264 * not used, should be 0
3265 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
3266 * @retval None
3267 */
LL_RCC_PLL_DisableDomain_SAI(void)3268 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
3269 {
3270 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3271 }
3272 #endif
3273
3274 /**
3275 * @brief Enable PLL output mapped on ADC domain clock
3276 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
3277 * @retval None
3278 */
LL_RCC_PLL_EnableDomain_ADC(void)3279 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
3280 {
3281 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3282 }
3283
3284 /**
3285 * @brief Disable PLL output mapped on ADC domain clock
3286 * @note In order to save power, when the PLLCLK of the PLL is
3287 * not used, should be 0
3288 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
3289 * @retval None
3290 */
LL_RCC_PLL_DisableDomain_ADC(void)3291 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
3292 {
3293 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
3294 }
3295
3296
3297 /**
3298 * @brief Enable PLL output mapped on 48MHz domain clock
3299 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
3300 * @retval None
3301 */
LL_RCC_PLL_EnableDomain_48M(void)3302 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
3303 {
3304 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3305 }
3306
3307 /**
3308 * @brief Disable PLL output mapped on 48MHz domain clock
3309 * @note In order to save power, when the PLLCLK of the PLL is
3310 * not used, should be 0
3311 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
3312 * @retval None
3313 */
LL_RCC_PLL_DisableDomain_48M(void)3314 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
3315 {
3316 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
3317 }
3318
3319 /**
3320 * @brief Enable PLL output mapped on SYSCLK domain
3321 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
3322 * @retval None
3323 */
LL_RCC_PLL_EnableDomain_SYS(void)3324 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
3325 {
3326 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3327 }
3328
3329 /**
3330 * @brief Disable PLL output mapped on SYSCLK domain
3331 * @note Cannot be disabled if the PLL clock is used as the system clock
3332 * @note In order to save power, when the PLLCLK of the PLL is
3333 * not used, Main PLL should be 0
3334 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
3335 * @retval None
3336 */
LL_RCC_PLL_DisableDomain_SYS(void)3337 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
3338 {
3339 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
3340 }
3341
3342 /**
3343 * @}
3344 */
3345
3346 #if defined(SAI1)
3347 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
3348 * @{
3349 */
3350
3351 /**
3352 * @brief Enable PLLSAI1
3353 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
3354 * @retval None
3355 */
LL_RCC_PLLSAI1_Enable(void)3356 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
3357 {
3358 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3359 }
3360
3361 /**
3362 * @brief Disable PLLSAI1
3363 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
3364 * @retval None
3365 */
LL_RCC_PLLSAI1_Disable(void)3366 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
3367 {
3368 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
3369 }
3370
3371 /**
3372 * @brief Check if PLLSAI1 Ready
3373 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
3374 * @retval State of bit (1 or 0).
3375 */
LL_RCC_PLLSAI1_IsReady(void)3376 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
3377 {
3378 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) ? 1UL : 0UL);
3379 }
3380
3381 /**
3382 * @brief Configure PLLSAI1 used for 48Mhz domain clock
3383 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3384 * PLLSAI1 are disabled
3385 * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
3386 * @note This can be selected for USB, RNG
3387 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
3388 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
3389 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_48M\n
3390 * PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_ConfigDomain_48M
3391 * @param Source This parameter can be one of the following values:
3392 * @arg @ref LL_RCC_PLLSOURCE_NONE
3393 * @arg @ref LL_RCC_PLLSOURCE_MSI
3394 * @arg @ref LL_RCC_PLLSOURCE_HSI
3395 * @arg @ref LL_RCC_PLLSOURCE_HSE
3396 * @param PLLM This parameter can be one of the following values:
3397 * @arg @ref LL_RCC_PLLM_DIV_1
3398 * @arg @ref LL_RCC_PLLM_DIV_2
3399 * @arg @ref LL_RCC_PLLM_DIV_3
3400 * @arg @ref LL_RCC_PLLM_DIV_4
3401 * @arg @ref LL_RCC_PLLM_DIV_5
3402 * @arg @ref LL_RCC_PLLM_DIV_6
3403 * @arg @ref LL_RCC_PLLM_DIV_7
3404 * @arg @ref LL_RCC_PLLM_DIV_8
3405 * @param PLLN Between 6 and 127
3406 * @param PLLQ This parameter can be one of the following values:
3407 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3408 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
3409 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3410 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
3411 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3412 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
3413 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3414 * @retval None
3415 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3416 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3417 {
3418 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3419 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLQ, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLQ);
3420 }
3421
3422 /**
3423 * @brief Configure PLLSAI1 used for SAI domain clock
3424 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3425 * PLLSAI1 are disabled
3426 * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
3427 * @note This can be selected for SAI1 or SAI2 (*)
3428 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3429 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3430 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_SAI\n
3431 * PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_ConfigDomain_SAI
3432 * @param Source This parameter can be one of the following values:
3433 * @arg @ref LL_RCC_PLLSOURCE_NONE
3434 * @arg @ref LL_RCC_PLLSOURCE_MSI
3435 * @arg @ref LL_RCC_PLLSOURCE_HSI
3436 * @arg @ref LL_RCC_PLLSOURCE_HSE
3437 * @param PLLM This parameter can be one of the following values:
3438 * @arg @ref LL_RCC_PLLM_DIV_1
3439 * @arg @ref LL_RCC_PLLM_DIV_2
3440 * @arg @ref LL_RCC_PLLM_DIV_3
3441 * @arg @ref LL_RCC_PLLM_DIV_4
3442 * @arg @ref LL_RCC_PLLM_DIV_5
3443 * @arg @ref LL_RCC_PLLM_DIV_6
3444 * @arg @ref LL_RCC_PLLM_DIV_7
3445 * @arg @ref LL_RCC_PLLM_DIV_8
3446 * @param PLLN Between 6 and 127
3447 * @param PLLP This parameter can be one of the following values:
3448 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3449 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3450 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3451 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3452 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3453 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3454 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3455 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3456 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3457 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3458 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3459 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3460 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3461 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3462 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3463 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3464 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3465 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3466 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3467 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3468 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3469 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3470 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3471 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3472 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3473 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3474 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3475 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3476 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3477 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3478 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
3479 * @retval None
3480 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3481 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3482 {
3483 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3484 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP,
3485 (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLP);
3486 }
3487
3488 /**
3489 * @brief Configure PLLSAI1 used for ADC domain clock
3490 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
3491 * PLLSAI1 are disabled
3492 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
3493 * @note This can be selected for ADC
3494 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3495 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3496 * PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_ConfigDomain_ADC\n
3497 * PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_ConfigDomain_ADC
3498 * @param Source This parameter can be one of the following values:
3499 * @arg @ref LL_RCC_PLLSOURCE_NONE
3500 * @arg @ref LL_RCC_PLLSOURCE_MSI
3501 * @arg @ref LL_RCC_PLLSOURCE_HSI
3502 * @arg @ref LL_RCC_PLLSOURCE_HSE
3503 * @param PLLM This parameter can be one of the following values:
3504 * @arg @ref LL_RCC_PLLM_DIV_1
3505 * @arg @ref LL_RCC_PLLM_DIV_2
3506 * @arg @ref LL_RCC_PLLM_DIV_3
3507 * @arg @ref LL_RCC_PLLM_DIV_4
3508 * @arg @ref LL_RCC_PLLM_DIV_5
3509 * @arg @ref LL_RCC_PLLM_DIV_6
3510 * @arg @ref LL_RCC_PLLM_DIV_7
3511 * @arg @ref LL_RCC_PLLM_DIV_8
3512 * @param PLLN Between 6 and 127
3513 * @param PLLR This parameter can be one of the following values:
3514 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3515 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
3516 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3517 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
3518 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3519 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
3520 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3521 * @retval None
3522 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3523 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3524 {
3525 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3526 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLR, (PLLN << RCC_PLLSAI1CFGR_PLLN_Pos) | PLLR);
3527 }
3528
3529 /**
3530 * @brief Get SAI1PLL multiplication factor for VCO
3531 * @rmtoll PLLSAI1CFGR PLLN LL_RCC_PLLSAI1_GetN
3532 * @retval Between 6 and 127
3533 */
LL_RCC_PLLSAI1_GetN(void)3534 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
3535 {
3536 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN) >> RCC_PLLSAI1CFGR_PLLN_Pos);
3537 }
3538
3539 /**
3540 * @brief Get SAI1PLL division factor for PLLSAI1P
3541 * @note used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
3542 * @rmtoll PLLSAI1CFGR PLLP LL_RCC_PLLSAI1_GetP
3543 * @retval Returned value can be one of the following values:
3544 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
3545 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
3546 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
3547 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
3548 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
3549 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
3550 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
3551 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
3552 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
3553 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
3554 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
3555 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
3556 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
3557 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
3558 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
3559 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
3560 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
3561 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
3562 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
3563 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
3564 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
3565 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
3566 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
3567 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
3568 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
3569 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
3570 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
3571 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
3572 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
3573 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
3574 * @arg @ref LL_RCC_PLLSAI1P_DIV_32
3575 */
LL_RCC_PLLSAI1_GetP(void)3576 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
3577 {
3578 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP));
3579 }
3580
3581 /**
3582 * @brief Get SAI1PLL division factor for PLLQ
3583 * @note used PLL48M2CLK selected for USB, RNG (48 MHz clock)
3584 * @rmtoll PLLSAI1CFGR PLLQ LL_RCC_PLLSAI1_GetQ
3585 * @retval Returned value can be one of the following values:
3586 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
3587 * @arg @ref LL_RCC_PLLSAI1Q_DIV_3
3588 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
3589 * @arg @ref LL_RCC_PLLSAI1Q_DIV_5
3590 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
3591 * @arg @ref LL_RCC_PLLSAI1Q_DIV_7
3592 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
3593 */
LL_RCC_PLLSAI1_GetQ(void)3594 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
3595 {
3596 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ));
3597 }
3598
3599 /**
3600 * @brief Get PLLSAI1 division factor for PLLSAIR
3601 * @note used for PLLADC1CLK (ADC clock)
3602 * @rmtoll PLLSAI1CFGR PLLR LL_RCC_PLLSAI1_GetR
3603 * @retval Returned value can be one of the following values:
3604 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
3605 * @arg @ref LL_RCC_PLLSAI1R_DIV_3
3606 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
3607 * @arg @ref LL_RCC_PLLSAI1R_DIV_5
3608 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
3609 * @arg @ref LL_RCC_PLLSAI1R_DIV_7
3610 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
3611 */
LL_RCC_PLLSAI1_GetR(void)3612 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
3613 {
3614 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR));
3615 }
3616
3617
3618 /**
3619 * @brief Enable PLLSAI1 output mapped on SAI domain clock
3620 * @rmtoll PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_EnableDomain_SAI
3621 * @retval None
3622 */
LL_RCC_PLLSAI1_EnableDomain_SAI(void)3623 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
3624 {
3625 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
3626 }
3627
3628 /**
3629 * @brief Disable PLLSAI1 output mapped on SAI domain clock
3630 * @note In order to save power, when of the PLLSAI1 is
3631 * not used, should be 0
3632 * @rmtoll PLLSAI1CFGR PLLPEN LL_RCC_PLLSAI1_DisableDomain_SAI
3633 * @retval None
3634 */
LL_RCC_PLLSAI1_DisableDomain_SAI(void)3635 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
3636 {
3637 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLPEN);
3638 }
3639
3640 /**
3641 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
3642 * @rmtoll PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_EnableDomain_48M
3643 * @retval None
3644 */
LL_RCC_PLLSAI1_EnableDomain_48M(void)3645 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
3646 {
3647 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
3648 }
3649
3650 /**
3651 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
3652 * @note In order to save power, when of the PLLSAI1 is
3653 * not used, should be 0
3654 * @rmtoll PLLSAI1CFGR PLLQEN LL_RCC_PLLSAI1_DisableDomain_48M
3655 * @retval None
3656 */
LL_RCC_PLLSAI1_DisableDomain_48M(void)3657 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
3658 {
3659 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQEN);
3660 }
3661
3662 /**
3663 * @brief Enable PLLSAI1 output mapped on ADC domain clock
3664 * @rmtoll PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_EnableDomain_ADC
3665 * @retval None
3666 */
LL_RCC_PLLSAI1_EnableDomain_ADC(void)3667 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
3668 {
3669 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
3670 }
3671
3672 /**
3673 * @brief Disable PLLSAI1 output mapped on ADC domain clock
3674 * @note In order to save power, when of the PLLSAI1 is
3675 * not used, Main PLLSAI1 should be 0
3676 * @rmtoll PLLSAI1CFGR PLLREN LL_RCC_PLLSAI1_DisableDomain_ADC
3677 * @retval None
3678 */
LL_RCC_PLLSAI1_DisableDomain_ADC(void)3679 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
3680 {
3681 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN);
3682 }
3683 #endif
3684
3685 /**
3686 * @}
3687 */
3688
3689
3690
3691 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
3692 * @{
3693 */
3694
3695 /**
3696 * @brief Clear LSI1 ready interrupt flag
3697 * @rmtoll CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY
3698 * @retval None
3699 */
LL_RCC_ClearFlag_LSI1RDY(void)3700 __STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void)
3701 {
3702 SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC);
3703 }
3704
3705 /**
3706 * @brief Clear LSI2 ready interrupt flag
3707 * @rmtoll CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY
3708 * @retval None
3709 */
LL_RCC_ClearFlag_LSI2RDY(void)3710 __STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void)
3711 {
3712 SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC);
3713 }
3714
3715 /**
3716 * @brief Clear LSE ready interrupt flag
3717 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
3718 * @retval None
3719 */
LL_RCC_ClearFlag_LSERDY(void)3720 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
3721 {
3722 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
3723 }
3724
3725 /**
3726 * @brief Clear MSI ready interrupt flag
3727 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
3728 * @retval None
3729 */
LL_RCC_ClearFlag_MSIRDY(void)3730 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
3731 {
3732 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
3733 }
3734
3735 /**
3736 * @brief Clear HSI ready interrupt flag
3737 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
3738 * @retval None
3739 */
LL_RCC_ClearFlag_HSIRDY(void)3740 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
3741 {
3742 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
3743 }
3744
3745 /**
3746 * @brief Clear HSE ready interrupt flag
3747 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
3748 * @retval None
3749 */
LL_RCC_ClearFlag_HSERDY(void)3750 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
3751 {
3752 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
3753 }
3754
3755 /**
3756 * @brief Configure PLL clock source
3757 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3758 * @param PLLSource This parameter can be one of the following values:
3759 * @arg @ref LL_RCC_PLLSOURCE_MSI
3760 * @arg @ref LL_RCC_PLLSOURCE_HSI
3761 * @arg @ref LL_RCC_PLLSOURCE_HSE
3762 * @retval None
3763 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3764 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3765 {
3766 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3767 }
3768
3769 /**
3770 * @brief Get the oscillator used as PLL clock source.
3771 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3772 * @retval Returned value can be one of the following values:
3773 * @arg @ref LL_RCC_PLLSOURCE_NONE
3774 * @arg @ref LL_RCC_PLLSOURCE_MSI
3775 * @arg @ref LL_RCC_PLLSOURCE_HSI
3776 * @arg @ref LL_RCC_PLLSOURCE_HSE
3777 */
LL_RCC_PLL_GetMainSource(void)3778 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3779 {
3780 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3781 }
3782
3783 /**
3784 * @brief Clear PLL ready interrupt flag
3785 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
3786 * @retval None
3787 */
LL_RCC_ClearFlag_PLLRDY(void)3788 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
3789 {
3790 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
3791 }
3792
3793 /**
3794 * @brief Clear HSI48 ready interrupt flag
3795 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
3796 * @retval None
3797 */
LL_RCC_ClearFlag_HSI48RDY(void)3798 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
3799 {
3800 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
3801 }
3802
3803 #if defined(SAI1)
3804 /**
3805 * @brief Clear PLLSAI1 ready interrupt flag
3806 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
3807 * @retval None
3808 */
LL_RCC_ClearFlag_PLLSAI1RDY(void)3809 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
3810 {
3811 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
3812 }
3813 #endif
3814
3815 /**
3816 * @brief Clear Clock security system interrupt flag
3817 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
3818 * @retval None
3819 */
LL_RCC_ClearFlag_HSECSS(void)3820 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
3821 {
3822 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
3823 }
3824
3825 /**
3826 * @brief Clear LSE Clock security system interrupt flag
3827 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
3828 * @retval None
3829 */
LL_RCC_ClearFlag_LSECSS(void)3830 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
3831 {
3832 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
3833 }
3834
3835 /**
3836 * @brief Check if LSI1 ready interrupt occurred or not
3837 * @rmtoll CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY
3838 * @retval State of bit (1 or 0).
3839 */
LL_RCC_IsActiveFlag_LSI1RDY(void)3840 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void)
3841 {
3842 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == (RCC_CIFR_LSI1RDYF)) ? 1UL : 0UL);
3843 }
3844
3845 /**
3846 * @brief Check if LSI2 ready interrupt occurred or not
3847 * @rmtoll CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY
3848 * @retval State of bit (1 or 0).
3849 */
LL_RCC_IsActiveFlag_LSI2RDY(void)3850 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void)
3851 {
3852 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == (RCC_CIFR_LSI2RDYF)) ? 1UL : 0UL);
3853 }
3854
3855 /**
3856 * @brief Check if LSE ready interrupt occurred or not
3857 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
3858 * @retval State of bit (1 or 0).
3859 */
LL_RCC_IsActiveFlag_LSERDY(void)3860 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
3861 {
3862 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
3863 }
3864
3865 /**
3866 * @brief Check if MSI ready interrupt occurred or not
3867 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
3868 * @retval State of bit (1 or 0).
3869 */
LL_RCC_IsActiveFlag_MSIRDY(void)3870 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
3871 {
3872 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)) ? 1UL : 0UL);
3873 }
3874
3875 /**
3876 * @brief Check if HSI ready interrupt occurred or not
3877 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
3878 * @retval State of bit (1 or 0).
3879 */
LL_RCC_IsActiveFlag_HSIRDY(void)3880 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
3881 {
3882 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
3883 }
3884
3885 /**
3886 * @brief Check if HSE ready interrupt occurred or not
3887 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
3888 * @retval State of bit (1 or 0).
3889 */
LL_RCC_IsActiveFlag_HSERDY(void)3890 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
3891 {
3892 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
3893 }
3894
3895 /**
3896 * @brief Check if PLL ready interrupt occurred or not
3897 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
3898 * @retval State of bit (1 or 0).
3899 */
LL_RCC_IsActiveFlag_PLLRDY(void)3900 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
3901 {
3902 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
3903 }
3904
3905 /**
3906 * @brief Check if HSI48 ready interrupt occurred or not
3907 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
3908 * @retval State of bit (1 or 0).
3909 */
LL_RCC_IsActiveFlag_HSI48RDY(void)3910 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
3911 {
3912 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
3913 }
3914
3915 #if defined(SAI1)
3916 /**
3917 * @brief Check if PLLSAI1 ready interrupt occurred or not
3918 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
3919 * @retval State of bit (1 or 0).
3920 */
LL_RCC_IsActiveFlag_PLLSAI1RDY(void)3921 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
3922 {
3923 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)) ? 1UL : 0UL);
3924 }
3925 #endif
3926
3927 /**
3928 * @brief Check if Clock security system interrupt occurred or not
3929 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
3930 * @retval State of bit (1 or 0).
3931 */
LL_RCC_IsActiveFlag_HSECSS(void)3932 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
3933 {
3934 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
3935 }
3936
3937 /**
3938 * @brief Check if LSE Clock security system interrupt occurred or not
3939 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
3940 * @retval State of bit (1 or 0).
3941 */
LL_RCC_IsActiveFlag_LSECSS(void)3942 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
3943 {
3944 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
3945 }
3946
3947 /**
3948 * @brief Check if HCLK1 prescaler flag value has been applied or not
3949 * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE
3950 * @retval State of bit (1 or 0).
3951 */
LL_RCC_IsActiveFlag_HPRE(void)3952 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
3953 {
3954 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
3955 }
3956
3957 /**
3958 * @brief Check if HCLK2 prescaler flag value has been applied or not
3959 * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
3960 * @retval State of bit (1 or 0).
3961 */
LL_RCC_IsActiveFlag_C2HPRE(void)3962 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
3963 {
3964 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
3965 }
3966
3967 /**
3968 * @brief Check if HCLK4 prescaler flag value has been applied or not
3969 * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
3970 * @retval State of bit (1 or 0).
3971 */
LL_RCC_IsActiveFlag_SHDHPRE(void)3972 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
3973 {
3974 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
3975 }
3976
3977
3978 /**
3979 * @brief Check if PLCK1 prescaler flag value has been applied or not
3980 * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
3981 * @retval State of bit (1 or 0).
3982 */
LL_RCC_IsActiveFlag_PPRE1(void)3983 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
3984 {
3985 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
3986 }
3987
3988 /**
3989 * @brief Check if PLCK2 prescaler flag value has been applied or not
3990 * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
3991 * @retval State of bit (1 or 0).
3992 */
LL_RCC_IsActiveFlag_PPRE2(void)3993 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
3994 {
3995 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
3996 }
3997
3998 /**
3999 * @brief Check if RCC flag Independent Watchdog reset is set or not.
4000 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
4001 * @retval State of bit (1 or 0).
4002 */
LL_RCC_IsActiveFlag_IWDGRST(void)4003 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
4004 {
4005 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
4006 }
4007
4008 /**
4009 * @brief Check if RCC flag Low Power reset is set or not.
4010 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
4011 * @retval State of bit (1 or 0).
4012 */
LL_RCC_IsActiveFlag_LPWRRST(void)4013 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
4014 {
4015 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
4016 }
4017
4018 /**
4019 * @brief Check if RCC flag Option byte reset is set or not.
4020 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
4021 * @retval State of bit (1 or 0).
4022 */
LL_RCC_IsActiveFlag_OBLRST(void)4023 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
4024 {
4025 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
4026 }
4027
4028 /**
4029 * @brief Check if RCC flag Pin reset is set or not.
4030 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
4031 * @retval State of bit (1 or 0).
4032 */
LL_RCC_IsActiveFlag_PINRST(void)4033 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
4034 {
4035 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
4036 }
4037
4038 /**
4039 * @brief Check if RCC flag Software reset is set or not.
4040 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
4041 * @retval State of bit (1 or 0).
4042 */
LL_RCC_IsActiveFlag_SFTRST(void)4043 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
4044 {
4045 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
4046 }
4047
4048 /**
4049 * @brief Check if RCC flag Window Watchdog reset is set or not.
4050 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
4051 * @retval State of bit (1 or 0).
4052 */
LL_RCC_IsActiveFlag_WWDGRST(void)4053 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
4054 {
4055 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
4056 }
4057
4058 /**
4059 * @brief Check if RCC flag BOR reset is set or not.
4060 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
4061 * @retval State of bit (1 or 0).
4062 */
LL_RCC_IsActiveFlag_BORRST(void)4063 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
4064 {
4065 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
4066 }
4067
4068 /**
4069 * @brief Set RMVF bit to clear the reset flags.
4070 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
4071 * @retval None
4072 */
LL_RCC_ClearResetFlags(void)4073 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
4074 {
4075 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
4076 }
4077
4078 /**
4079 * @}
4080 */
4081
4082 /** @defgroup RCC_LL_EF_IT_Management IT Management
4083 * @{
4084 */
4085
4086 /**
4087 * @brief Enable LSI1 ready interrupt
4088 * @rmtoll CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY
4089 * @retval None
4090 */
LL_RCC_EnableIT_LSI1RDY(void)4091 __STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void)
4092 {
4093 SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
4094 }
4095
4096 /**
4097 * @brief Enable LSI2 ready interrupt
4098 * @rmtoll CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY
4099 * @retval None
4100 */
LL_RCC_EnableIT_LSI2RDY(void)4101 __STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void)
4102 {
4103 SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
4104 }
4105 /**
4106 * @brief Enable LSE ready interrupt
4107 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
4108 * @retval None
4109 */
LL_RCC_EnableIT_LSERDY(void)4110 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
4111 {
4112 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4113 }
4114
4115 /**
4116 * @brief Enable MSI ready interrupt
4117 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
4118 * @retval None
4119 */
LL_RCC_EnableIT_MSIRDY(void)4120 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
4121 {
4122 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4123 }
4124
4125 /**
4126 * @brief Enable HSI ready interrupt
4127 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
4128 * @retval None
4129 */
LL_RCC_EnableIT_HSIRDY(void)4130 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
4131 {
4132 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4133 }
4134
4135 /**
4136 * @brief Enable HSE ready interrupt
4137 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
4138 * @retval None
4139 */
LL_RCC_EnableIT_HSERDY(void)4140 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
4141 {
4142 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4143 }
4144
4145 /**
4146 * @brief Enable PLL ready interrupt
4147 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
4148 * @retval None
4149 */
LL_RCC_EnableIT_PLLRDY(void)4150 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
4151 {
4152 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4153 }
4154
4155 /**
4156 * @brief Enable HSI48 ready interrupt
4157 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
4158 * @retval None
4159 */
LL_RCC_EnableIT_HSI48RDY(void)4160 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
4161 {
4162 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4163 }
4164
4165 #if defined(SAI1)
4166 /**
4167 * @brief Enable PLLSAI1 ready interrupt
4168 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
4169 * @retval None
4170 */
LL_RCC_EnableIT_PLLSAI1RDY(void)4171 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
4172 {
4173 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4174 }
4175 #endif
4176
4177 /**
4178 * @brief Enable LSE clock security system interrupt
4179 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
4180 * @retval None
4181 */
LL_RCC_EnableIT_LSECSS(void)4182 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
4183 {
4184 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
4185 }
4186
4187 /**
4188 * @brief Disable LSI1 ready interrupt
4189 * @rmtoll CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY
4190 * @retval None
4191 */
LL_RCC_DisableIT_LSI1RDY(void)4192 __STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void)
4193 {
4194 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
4195 }
4196
4197 /**
4198 * @brief Disable LSI2 ready interrupt
4199 * @rmtoll CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY
4200 * @retval None
4201 */
LL_RCC_DisableIT_LSI2RDY(void)4202 __STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void)
4203 {
4204 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
4205 }
4206 /**
4207 * @brief Disable LSE ready interrupt
4208 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
4209 * @retval None
4210 */
LL_RCC_DisableIT_LSERDY(void)4211 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
4212 {
4213 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
4214 }
4215
4216 /**
4217 * @brief Disable MSI ready interrupt
4218 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
4219 * @retval None
4220 */
LL_RCC_DisableIT_MSIRDY(void)4221 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
4222 {
4223 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
4224 }
4225
4226 /**
4227 * @brief Disable HSI ready interrupt
4228 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
4229 * @retval None
4230 */
LL_RCC_DisableIT_HSIRDY(void)4231 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
4232 {
4233 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
4234 }
4235
4236 /**
4237 * @brief Disable HSE ready interrupt
4238 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
4239 * @retval None
4240 */
LL_RCC_DisableIT_HSERDY(void)4241 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
4242 {
4243 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
4244 }
4245
4246 /**
4247 * @brief Disable PLL ready interrupt
4248 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
4249 * @retval None
4250 */
LL_RCC_DisableIT_PLLRDY(void)4251 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
4252 {
4253 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
4254 }
4255
4256 /**
4257 * @brief Disable HSI48 ready interrupt
4258 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
4259 * @retval None
4260 */
LL_RCC_DisableIT_HSI48RDY(void)4261 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
4262 {
4263 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
4264 }
4265
4266 #if defined(SAI1)
4267 /**
4268 * @brief Disable PLLSAI1 ready interrupt
4269 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
4270 * @retval None
4271 */
LL_RCC_DisableIT_PLLSAI1RDY(void)4272 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
4273 {
4274 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
4275 }
4276 #endif
4277
4278 /**
4279 * @brief Disable LSE clock security system interrupt
4280 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
4281 * @retval None
4282 */
LL_RCC_DisableIT_LSECSS(void)4283 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
4284 {
4285 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
4286 }
4287
4288 /**
4289 * @brief Checks if LSI1 ready interrupt source is enabled or disabled.
4290 * @rmtoll CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY
4291 * @retval State of bit (1 or 0).
4292 */
LL_RCC_IsEnabledIT_LSI1RDY(void)4293 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void)
4294 {
4295 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == (RCC_CIER_LSI1RDYIE)) ? 1UL : 0UL);
4296 }
4297
4298 /**
4299 * @brief Checks if LSI2 ready interrupt source is enabled or disabled.
4300 * @rmtoll CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY
4301 * @retval State of bit (1 or 0).
4302 */
LL_RCC_IsEnabledIT_LSI2RDY(void)4303 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void)
4304 {
4305 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == (RCC_CIER_LSI2RDYIE)) ? 1UL : 0UL);
4306 }
4307 /**
4308 * @brief Checks if LSE ready interrupt source is enabled or disabled.
4309 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
4310 * @retval State of bit (1 or 0).
4311 */
LL_RCC_IsEnabledIT_LSERDY(void)4312 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
4313 {
4314 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
4315 }
4316
4317 /**
4318 * @brief Checks if MSI ready interrupt source is enabled or disabled.
4319 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
4320 * @retval State of bit (1 or 0).
4321 */
LL_RCC_IsEnabledIT_MSIRDY(void)4322 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
4323 {
4324 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)) ? 1UL : 0UL);
4325 }
4326
4327 /**
4328 * @brief Checks if HSI ready interrupt source is enabled or disabled.
4329 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
4330 * @retval State of bit (1 or 0).
4331 */
LL_RCC_IsEnabledIT_HSIRDY(void)4332 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
4333 {
4334 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
4335 }
4336
4337 /**
4338 * @brief Checks if HSE ready interrupt source is enabled or disabled.
4339 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
4340 * @retval State of bit (1 or 0).
4341 */
LL_RCC_IsEnabledIT_HSERDY(void)4342 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
4343 {
4344 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
4345 }
4346
4347 /**
4348 * @brief Checks if PLL ready interrupt source is enabled or disabled.
4349 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
4350 * @retval State of bit (1 or 0).
4351 */
LL_RCC_IsEnabledIT_PLLRDY(void)4352 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
4353 {
4354 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
4355 }
4356
4357 /**
4358 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
4359 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
4360 * @retval State of bit (1 or 0).
4361 */
LL_RCC_IsEnabledIT_HSI48RDY(void)4362 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
4363 {
4364 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
4365 }
4366
4367 #if defined(SAI1)
4368 /**
4369 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
4370 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
4371 * @retval State of bit (1 or 0).
4372 */
LL_RCC_IsEnabledIT_PLLSAI1RDY(void)4373 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
4374 {
4375 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)) ? 1UL : 0UL);
4376 }
4377 #endif
4378
4379 /**
4380 * @brief Checks if LSECSS interrupt source is enabled or disabled.
4381 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
4382 * @retval State of bit (1 or 0).
4383 */
LL_RCC_IsEnabledIT_LSECSS(void)4384 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
4385 {
4386 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
4387 }
4388
4389 /**
4390 * @}
4391 */
4392
4393 #if defined(USE_FULL_LL_DRIVER)
4394 /** @defgroup RCC_LL_EF_Init De-initialization function
4395 * @{
4396 */
4397 ErrorStatus LL_RCC_DeInit(void);
4398 /**
4399 * @}
4400 */
4401
4402 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
4403 * @{
4404 */
4405 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
4406 uint32_t LL_RCC_GetSMPSClockFreq(void);
4407 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
4408 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
4409 #if defined(LPUART1)
4410 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
4411 #endif
4412 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
4413 #if defined(SAI1)
4414 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
4415 #endif
4416 uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource);
4417 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
4418 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
4419 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
4420 uint32_t LL_RCC_GetRTCClockFreq(void);
4421 uint32_t LL_RCC_GetRFWKPClockFreq(void);
4422 /**
4423 * @}
4424 */
4425 #endif /* USE_FULL_LL_DRIVER */
4426
4427 /**
4428 * @}
4429 */
4430
4431 /**
4432 * @}
4433 */
4434
4435 #endif /* defined(RCC) */
4436
4437 /**
4438 * @}
4439 */
4440
4441 #ifdef __cplusplus
4442 }
4443 #endif
4444
4445 #endif /* STM32WBxx_LL_RCC_H */
4446
4447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4448