1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32WBxx_LL_PWR_H
22 #define STM32WBxx_LL_PWR_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32wbxx.h"
30
31 /** @addtogroup STM32WBxx_LL_Driver
32 * @{
33 */
34
35 #if defined(PWR)
36
37 /** @defgroup PWR_LL PWR
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
46 * @{
47 */
48
49 #if defined(PWR_CR5_SMPSEN)
50 /** @defgroup PWR_SMPS_Calibration PWR SMPS calibration
51 * @{
52 */
53 #define SMPS_VOLTAGE_CAL_ADDR ((uint32_t*) (0x1FFF7558UL)) /* SMPS output voltage calibration level corresponding to voltage "SMPS_VOLTAGE_CAL_VOLTAGE_MV" */
54 #define SMPS_VOLTAGE_CAL_POS (8UL) /* SMPS output voltage calibration level bitfield position */
55 #define SMPS_VOLTAGE_CAL (0xFUL << SMPS_VOLTAGE_CAL_POS) /* SMPS output voltage calibration level bitfield mask */
56 #define SMPS_VOLTAGE_CAL_VOLTAGE_MV (1500UL) /* SMPS output voltage calibration value (unit: mV) */
57 #define SMPS_VOLTAGE_BASE_MV (1200UL) /* SMPS output voltage base value (unit: mV) */
58 #define SMPS_VOLTAGE_STEP_MV ( 50UL) /* SMPS output voltage step (unit: mV) */
59 /**
60 * @}
61 */
62 #endif
63
64 /**
65 * @}
66 */
67
68 /* Private macros ------------------------------------------------------------*/
69
70 /* Exported types ------------------------------------------------------------*/
71 /* Exported constants --------------------------------------------------------*/
72 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
73 * @{
74 */
75
76 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
77 * @brief Flags defines which can be used with LL_PWR_WriteReg function
78 * @{
79 */
80 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
81 #if defined(PWR_CR3_EWUP2)
82 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
83 #endif
84 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
85 #if defined(PWR_CR3_EWUP3)
86 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
87 #endif
88 #if defined(PWR_CR3_EWUP2)
89 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
90 #endif
91 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
92 #define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF
93 #define LL_PWR_SCR_C802AF PWR_SCR_C802AF
94 #define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF
95 #define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF
96 #define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF
97 #define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF
98 #if defined(PWR_CR5_SMPSEN)
99 #define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF
100 #define LL_PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF
101 #endif
102 #define LL_PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF
103 #define LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF
104 #define LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF
105 /**
106 * @}
107 */
108
109 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
110 * @brief Flags defines which can be used with LL_PWR_ReadReg function
111 * @{
112 */
113 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
114 #if defined(PWR_CR3_EWUP5)
115 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
116 #endif
117 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
118 #if defined(PWR_CR3_EWUP3)
119 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
120 #endif
121 #if defined(PWR_CR3_EWUP2)
122 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
123 #endif
124 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
125 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
126 #if defined(PWR_CR2_PVME1)
127 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
128 #endif
129 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
130 #if defined(PWR_CR1_VOS)
131 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
132 #endif
133 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
134 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
135
136 /* BOR flags */
137 #define LL_PWR_FLAG_BORH PWR_SR1_BORHF /* BORH interrupt flag */
138
139 #if defined(PWR_CR5_SMPSEN)
140 /* SMPS flags */
141 #define LL_PWR_FLAG_SMPS PWR_SR2_SMPSF /* SMPS step down converter ready flag */
142 #define LL_PWR_FLAG_SMPSB PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */
143 #define LL_PWR_FLAG_SMPSFB PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */
144 #endif
145
146 /* Radio (BLE or 802.15.4) flags */
147 #define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */
148 #define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
149 #define LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */
150 #define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */
151 #define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */
152 #define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */
153
154 /* Multicore flags */
155 #define LL_PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF /* System standby flag for CPU1 */
156 #define LL_PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF /* System stop flag for CPU1 */
157 #define LL_PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS /* CPU1 deepsleep mode */
158 #define LL_PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF /* System standby flag for CPU2 */
159 #define LL_PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF /* System stop flag for CPU2 */
160 #define LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */
161 #define LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */
162 /**
163 * @}
164 */
165
166 #if defined(PWR_CR1_VOS)
167 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
168 * @{
169 */
170 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */
171 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */
172 /**
173 * @}
174 */
175 #endif
176
177 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
178 * @{
179 */
180 #define LL_PWR_MODE_STOP0 (0x000000000U)
181 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
182 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)
183 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
184 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
185 /**
186 * @}
187 */
188
189 /** @defgroup PWR_LL_EC_FLASH_LPRUN_POWER_DOWN_MODE Flash power-down mode during low-power run mode
190 * @{
191 */
192 #define LL_PWR_FLASH_LPRUN_MODE_IDLE (0x000000000U)
193 #define LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR)
194 /**
195 * @}
196 */
197
198 /** @defgroup PWR_LL_EC_FLASH_SLEEP_POWER_DOWN_MODE Flash power-down mode during sleep mode
199 * @{
200 */
201 #define LL_PWR_FLASH_SLEEP_MODE_IDLE (0x000000000U)
202 #define LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS)
203 /**
204 * @}
205 */
206
207 /** @defgroup PWR_LL_EC_PVM Peripheral voltage monitoring
208 * @{
209 */
210 #if defined(PWR_CR2_PVME1)
211 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
212 #endif
213 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
214 /**
215 * @}
216 */
217
218 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
219 * @{
220 */
221 #define LL_PWR_PVDLEVEL_0 (0x00000000U) /* VPVD0 around 2.0 V */
222 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_0) /* VPVD1 around 2.2 V */
223 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_1) /* VPVD2 around 2.4 V */
224 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */
225 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_2) /* VPVD4 around 2.6 V */
226 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */
227 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */
228 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage (Compare internally to VREFINT) */
229 /**
230 * @}
231 */
232
233 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
234 * @{
235 */
236 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
237 #if defined(PWR_CR3_EWUP2)
238 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
239 #endif
240 #if defined(PWR_CR3_EWUP3)
241 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
242 #endif
243 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
244 #if defined(PWR_CR3_EWUP5)
245 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
246 #endif
247 /**
248 * @}
249 */
250
251 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
252 * @{
253 */
254 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
255 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
256 /**
257 * @}
258 */
259
260 /** @defgroup PWR_LL_EC_GPIO GPIO
261 * @{
262 */
263 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
264 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
265 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
266 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
267 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
268 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
269 /**
270 * @}
271 */
272
273 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
274 * @{
275 */
276 #if defined(PWR_PUCRC_PC0)
277 /* Note: LL_PWR_GPIO_BIT_x defined from port C because all pins are available */
278 /* for PWR pull-up and pull-down. */
279 #define LL_PWR_GPIO_BIT_0 (PWR_PUCRC_PC0)
280 #define LL_PWR_GPIO_BIT_1 (PWR_PUCRC_PC1)
281 #define LL_PWR_GPIO_BIT_2 (PWR_PUCRC_PC2)
282 #define LL_PWR_GPIO_BIT_3 (PWR_PUCRC_PC3)
283 #define LL_PWR_GPIO_BIT_4 (PWR_PUCRC_PC4)
284 #define LL_PWR_GPIO_BIT_5 (PWR_PUCRC_PC5)
285 #define LL_PWR_GPIO_BIT_6 (PWR_PUCRC_PC6)
286 #define LL_PWR_GPIO_BIT_7 (PWR_PUCRC_PC7)
287 #define LL_PWR_GPIO_BIT_8 (PWR_PUCRC_PC8)
288 #define LL_PWR_GPIO_BIT_9 (PWR_PUCRC_PC9)
289 #define LL_PWR_GPIO_BIT_10 (PWR_PUCRC_PC10)
290 #define LL_PWR_GPIO_BIT_11 (PWR_PUCRC_PC11)
291 #define LL_PWR_GPIO_BIT_12 (PWR_PUCRC_PC12)
292 #define LL_PWR_GPIO_BIT_13 (PWR_PUCRC_PC13)
293 #define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14)
294 #define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15)
295 #else
296 #define LL_PWR_GPIO_BIT_0 (PWR_PUCRA_PA0)
297 #define LL_PWR_GPIO_BIT_1 (PWR_PUCRA_PA1)
298 #define LL_PWR_GPIO_BIT_2 (PWR_PUCRA_PA2)
299 #define LL_PWR_GPIO_BIT_3 (PWR_PUCRA_PA3)
300 #define LL_PWR_GPIO_BIT_4 (PWR_PUCRA_PA4)
301 #define LL_PWR_GPIO_BIT_5 (PWR_PUCRA_PA5)
302 #define LL_PWR_GPIO_BIT_6 (PWR_PUCRA_PA6)
303 #define LL_PWR_GPIO_BIT_7 (PWR_PUCRA_PA7)
304 #define LL_PWR_GPIO_BIT_8 (PWR_PUCRA_PA8)
305 #define LL_PWR_GPIO_BIT_9 (PWR_PUCRA_PA9)
306 #define LL_PWR_GPIO_BIT_10 (PWR_PUCRA_PA10)
307 #define LL_PWR_GPIO_BIT_11 (PWR_PUCRA_PA11)
308 #define LL_PWR_GPIO_BIT_12 (PWR_PUCRA_PA12)
309 #define LL_PWR_GPIO_BIT_13 (PWR_PUCRA_PA13)
310 #define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14)
311 #define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15)
312 #endif
313 /**
314 * @}
315 */
316
317 #if defined(PWR_CR5_SMPSEN)
318 /** @defgroup PWR_LL_EC_BOR_CONFIGURATION BOR configuration
319 * @{
320 */
321 #define LL_PWR_BOR_SYSTEM_RESET (0x00000000U) /*!< BOR will generate a system reset */
322 #define LL_PWR_BOR_SMPS_FORCE_BYPASS (PWR_CR5_BORHC) /*!< BOR will for SMPS step down converter in bypass mode */
323 /**
324 * @}
325 */
326
327 /** @defgroup PWR_LL_EC_SMPS_OPERATING_MODES SMPS step down converter operating modes
328 * @{
329 */
330 /* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF */
331 /* but they are also used as register CR5 bits SMPSEN and SMPSBEN, */
332 /* as used by all SMPS operating mode functions targetting different */
333 /* registers: */
334 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
335 /* and "LL_PWR_SMPS_GetEffectiveMode()". */
336 #define LL_PWR_SMPS_BYPASS (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode. */
337 #define LL_PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */
338 /**
339 * @}
340 */
341
342 /** @defgroup PWR_LL_EC_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection
343 * @{
344 */
345 #define LL_PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U) /*!< SMPS step down converter supply startup current 80mA */
346 #define LL_PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */
347 #define LL_PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 120mA */
348 #define LL_PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */
349 #define LL_PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 ) /*!< SMPS step down converter supply startup current 160mA */
350 #define LL_PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */
351 #define LL_PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 200mA */
352 #define LL_PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */
353 /**
354 * @}
355 */
356
357 /** @defgroup PWR_LL_EC_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level
358 * @{
359 */
360 /* Note: SMPS voltage is trimmed during device production to control
361 the actual voltage level variation from device to device. */
362 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U) /*!< SMPS step down converter supply output voltage 1.20V */
363 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */
364 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.30V */
365 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */
366 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.40V */
367 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */
368 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.50V */
369 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */
370 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 ) /*!< SMPS step down converter supply output voltage 1.60V */
371 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */
372 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.70V */
373 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */
374 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.80V */
375 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */
376 #define LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.90V */
377 /**
378 * @}
379 */
380 #endif
381
382 /**
383 * @}
384 */
385
386 /* Exported macro ------------------------------------------------------------*/
387 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
388 * @{
389 */
390
391 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
392 * @{
393 */
394
395 /**
396 * @brief Write a value in PWR register
397 * @param __REG__ Register to be written
398 * @param __VALUE__ Value to be written in the register
399 * @retval None
400 */
401 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
402
403 /**
404 * @brief Read a value in PWR register
405 * @param __REG__ Register to be read
406 * @retval Register value
407 */
408 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
409 /**
410 * @}
411 */
412
413 /**
414 * @}
415 */
416
417
418 /* Exported functions --------------------------------------------------------*/
419 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
420 * @{
421 */
422
423 /** @defgroup PWR_LL_EF_Configuration Configuration
424 * @{
425 */
426
427 /**
428 * @brief Switch from run main mode to run low-power mode.
429 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
430 * @retval None
431 */
LL_PWR_EnterLowPowerRunMode(void)432 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
433 {
434 SET_BIT(PWR->CR1, PWR_CR1_LPR);
435 }
436
437 /**
438 * @brief Switch from run main mode to low-power mode.
439 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
440 * @retval None
441 */
LL_PWR_ExitLowPowerRunMode(void)442 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
443 {
444 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
445 }
446
447 /**
448 * @brief Check if the regulator is in low-power mode
449 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
450 * @retval State of bit (1 or 0).
451 */
LL_PWR_IsEnabledLowPowerRunMode(void)452 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
453 {
454 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
455 }
456
457 #if defined(PWR_CR1_VOS)
458 /**
459 * @brief Set the main internal regulator output voltage
460 * @note A delay is required for the internal regulator to be ready
461 * after the voltage scaling has been changed.
462 * Check whether regulator reached the selected voltage level
463 * can be done using function @ref LL_PWR_IsActiveFlag_VOS().
464 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
465 * @param VoltageScaling This parameter can be one of the following values:
466 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
467 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
468 * @retval None
469 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)470 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
471 {
472 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
473 }
474
475 /**
476 * @brief Get the main internal regulator output voltage
477 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
478 * @retval Returned value can be one of the following values:
479 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
480 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
481 */
LL_PWR_GetRegulVoltageScaling(void)482 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
483 {
484 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
485 }
486 #endif
487
488 /**
489 * @brief Enable access to the backup domain
490 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
491 * @retval None
492 */
LL_PWR_EnableBkUpAccess(void)493 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
494 {
495 SET_BIT(PWR->CR1, PWR_CR1_DBP);
496 }
497
498 /**
499 * @brief Disable access to the backup domain
500 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
501 * @retval None
502 */
LL_PWR_DisableBkUpAccess(void)503 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
504 {
505 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
506 }
507
508 /**
509 * @brief Check if the backup domain is enabled
510 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
511 * @retval State of bit (1 or 0).
512 */
LL_PWR_IsEnabledBkUpAccess(void)513 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
514 {
515 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
516 }
517
518 /**
519 * @brief Set Low-Power mode
520 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
521 * @param LowPowerMode This parameter can be one of the following values:
522 * @arg @ref LL_PWR_MODE_STOP0
523 * @arg @ref LL_PWR_MODE_STOP1
524 * @arg @ref LL_PWR_MODE_STOP2
525 * @arg @ref LL_PWR_MODE_STANDBY
526 * @arg @ref LL_PWR_MODE_SHUTDOWN
527 * @retval None
528 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)529 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
530 {
531 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
532 }
533
534 /**
535 * @brief Get Low-Power mode
536 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
537 * @retval Returned value can be one of the following values:
538 * @arg @ref LL_PWR_MODE_STOP0
539 * @arg @ref LL_PWR_MODE_STOP1
540 * @arg @ref LL_PWR_MODE_STOP2
541 * @arg @ref LL_PWR_MODE_STANDBY
542 * @arg @ref LL_PWR_MODE_SHUTDOWN
543 */
LL_PWR_GetPowerMode(void)544 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
545 {
546 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
547 }
548
549 /**
550 * @brief Set flash power-down mode during low-power run mode
551 * @rmtoll CR1 FPDR LL_PWR_SetFlashPowerModeLPRun
552 * @param FlashLowPowerMode This parameter can be one of the following values:
553 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
554 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
555 * @retval None
556 */
LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)557 __STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
558 {
559 /* Unlock bit FPDR */
560 WRITE_REG(PWR->CR1, 0x0000C1B0U);
561
562 /* Update bit FPDR */
563 MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode);
564 }
565
566 /**
567 * @brief Get flash power-down mode during low-power run mode
568 * @rmtoll CR1 FPDR LL_PWR_GetFlashPowerModeLPRun
569 * @retval Returned value can be one of the following values:
570 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
571 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
572 */
LL_PWR_GetFlashPowerModeLPRun(void)573 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeLPRun(void)
574 {
575 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDR));
576 }
577
578 /**
579 * @brief Set flash power-down mode during sleep mode
580 * @rmtoll CR1 FPDS LL_PWR_SetFlashPowerModeSleep
581 * @param FlashLowPowerMode This parameter can be one of the following values:
582 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
583 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
584 * @retval None
585 */
LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)586 __STATIC_INLINE void LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
587 {
588 MODIFY_REG(PWR->CR1, PWR_CR1_FPDS, FlashLowPowerMode);
589 }
590
591 /**
592 * @brief Get flash power-down mode during sleep mode
593 * @rmtoll CR1 FPDS LL_PWR_GetFlashPowerModeSleep
594 * @retval Returned value can be one of the following values:
595 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
596 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
597 */
LL_PWR_GetFlashPowerModeSleep(void)598 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeSleep(void)
599 {
600 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS));
601 }
602
603 #if defined(PWR_CR2_PVME1)
604 /**
605 * @brief Enable VDDUSB supply
606 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
607 * @retval None
608 */
LL_PWR_EnableVddUSB(void)609 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
610 {
611 SET_BIT(PWR->CR2, PWR_CR2_USV);
612 }
613
614 /**
615 * @brief Disable VDDUSB supply
616 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
617 * @retval None
618 */
LL_PWR_DisableVddUSB(void)619 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
620 {
621 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
622 }
623
624 /**
625 * @brief Check if VDDUSB supply is enabled
626 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
627 * @retval State of bit (1 or 0).
628 */
LL_PWR_IsEnabledVddUSB(void)629 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
630 {
631 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
632 }
633 #endif
634
635 /**
636 * @brief Enable the Power Voltage Monitoring on a peripheral
637 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
638 * CR2 PVME3 LL_PWR_EnablePVM
639 * @param PeriphVoltage This parameter can be one of the following values:
640 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
641 * @arg @ref LL_PWR_PVM_VDDA_1_62V
642 *
643 * (*) Not available on devices STM32WB50xx
644 * @retval None
645 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)646 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
647 {
648 SET_BIT(PWR->CR2, PeriphVoltage);
649 }
650
651 /**
652 * @brief Disable the Power Voltage Monitoring on a peripheral
653 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
654 * CR2 PVME3 LL_PWR_DisablePVM
655 * @param PeriphVoltage This parameter can be one of the following values:
656 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
657 * @arg @ref LL_PWR_PVM_VDDA_1_62V
658 *
659 * (*) Not available on devices STM32WB50xx
660 * @retval None
661 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)662 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
663 {
664 CLEAR_BIT(PWR->CR2, PeriphVoltage);
665 }
666
667 /**
668 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
669 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
670 * CR2 PVME3 LL_PWR_IsEnabledPVM
671 * @param PeriphVoltage This parameter can be one of the following values:
672 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
673 * @arg @ref LL_PWR_PVM_VDDA_1_62V
674 *
675 * (*) Not available on devices STM32WB50xx
676 * @retval State of bit (1 or 0).
677 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)678 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
679 {
680 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
681 }
682
683 /**
684 * @brief Configure the voltage threshold detected by the Power Voltage Detector
685 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
686 * @param PVDLevel This parameter can be one of the following values:
687 * @arg @ref LL_PWR_PVDLEVEL_0
688 * @arg @ref LL_PWR_PVDLEVEL_1
689 * @arg @ref LL_PWR_PVDLEVEL_2
690 * @arg @ref LL_PWR_PVDLEVEL_3
691 * @arg @ref LL_PWR_PVDLEVEL_4
692 * @arg @ref LL_PWR_PVDLEVEL_5
693 * @arg @ref LL_PWR_PVDLEVEL_6
694 * @arg @ref LL_PWR_PVDLEVEL_7
695 * @retval None
696 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)697 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
698 {
699 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
700 }
701
702 /**
703 * @brief Get the voltage threshold detection
704 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
705 * @retval Returned value can be one of the following values:
706 * @arg @ref LL_PWR_PVDLEVEL_0
707 * @arg @ref LL_PWR_PVDLEVEL_1
708 * @arg @ref LL_PWR_PVDLEVEL_2
709 * @arg @ref LL_PWR_PVDLEVEL_3
710 * @arg @ref LL_PWR_PVDLEVEL_4
711 * @arg @ref LL_PWR_PVDLEVEL_5
712 * @arg @ref LL_PWR_PVDLEVEL_6
713 * @arg @ref LL_PWR_PVDLEVEL_7
714 */
LL_PWR_GetPVDLevel(void)715 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
716 {
717 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
718 }
719
720 /**
721 * @brief Enable Power Voltage Detector
722 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
723 * @retval None
724 */
LL_PWR_EnablePVD(void)725 __STATIC_INLINE void LL_PWR_EnablePVD(void)
726 {
727 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
728 }
729
730 /**
731 * @brief Disable Power Voltage Detector
732 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
733 * @retval None
734 */
LL_PWR_DisablePVD(void)735 __STATIC_INLINE void LL_PWR_DisablePVD(void)
736 {
737 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
738 }
739
740 /**
741 * @brief Check if Power Voltage Detector is enabled
742 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
743 * @retval State of bit (1 or 0).
744 */
LL_PWR_IsEnabledPVD(void)745 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
746 {
747 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
748 }
749
750 /**
751 * @brief Enable Internal Wake-up line
752 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
753 * @retval None
754 */
LL_PWR_EnableInternWU(void)755 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
756 {
757 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
758 }
759
760 /**
761 * @brief Disable Internal Wake-up line
762 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
763 * @retval None
764 */
LL_PWR_DisableInternWU(void)765 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
766 {
767 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
768 }
769
770 /**
771 * @brief Check if Internal Wake-up line is enabled
772 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
773 * @retval State of bit (1 or 0).
774 */
LL_PWR_IsEnabledInternWU(void)775 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
776 {
777 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
778 }
779
780 /**
781 * @brief Enable pull-up and pull-down configuration
782 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
783 * @retval None
784 */
LL_PWR_EnablePUPDCfg(void)785 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
786 {
787 SET_BIT(PWR->CR3, PWR_CR3_APC);
788 }
789
790 /**
791 * @brief Disable pull-up and pull-down configuration
792 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
793 * @retval None
794 */
LL_PWR_DisablePUPDCfg(void)795 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
796 {
797 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
798 }
799
800 /**
801 * @brief Check if pull-up and pull-down configuration is enabled
802 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
803 * @retval State of bit (1 or 0).
804 */
LL_PWR_IsEnabledPUPDCfg(void)805 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
806 {
807 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
808 }
809
810 /**
811 * @brief Enable SRAM2 content retention in Standby mode
812 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
813 * @retval None
814 */
LL_PWR_EnableSRAM2Retention(void)815 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
816 {
817 SET_BIT(PWR->CR3, PWR_CR3_RRS);
818 }
819
820 /**
821 * @brief Disable SRAM2 content retention in Standby mode
822 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
823 * @retval None
824 */
LL_PWR_DisableSRAM2Retention(void)825 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
826 {
827 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
828 }
829
830 /**
831 * @brief Check if SRAM2 content retention in Standby mode is enabled
832 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
833 * @retval State of bit (1 or 0).
834 */
LL_PWR_IsEnabledSRAM2Retention(void)835 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
836 {
837 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
838 }
839
840 /**
841 * @brief Enable the WakeUp PINx functionality
842 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
843 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
844 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
845 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
846 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
847 * @param WakeUpPin This parameter can be one of the following values:
848 * @arg @ref LL_PWR_WAKEUP_PIN1
849 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
850 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
851 * @arg @ref LL_PWR_WAKEUP_PIN4
852 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
853 *
854 * (*) Not available on devices STM32WB50xx
855 * @retval None
856 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)857 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
858 {
859 SET_BIT(PWR->CR3, WakeUpPin);
860 }
861
862 /**
863 * @brief Disable the WakeUp PINx functionality
864 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
865 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
866 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
867 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
868 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
869 * @param WakeUpPin This parameter can be one of the following values:
870 * @arg @ref LL_PWR_WAKEUP_PIN1
871 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
872 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
873 * @arg @ref LL_PWR_WAKEUP_PIN4
874 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
875 *
876 * (*) Not available on devices STM32WB50xx
877 * @retval None
878 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)879 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
880 {
881 CLEAR_BIT(PWR->CR3, WakeUpPin);
882 }
883
884 /**
885 * @brief Check if the WakeUp PINx functionality is enabled
886 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
887 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
888 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
889 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
890 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
891 * @param WakeUpPin This parameter can be one of the following values:
892 * @arg @ref LL_PWR_WAKEUP_PIN1
893 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
894 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
895 * @arg @ref LL_PWR_WAKEUP_PIN4
896 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
897 *
898 * (*) Not available on devices STM32WB50xx
899 * @retval State of bit (1 or 0).
900 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)901 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
902 {
903 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
904 }
905
906 /**
907 * @brief Set the resistor impedance
908 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
909 * @param Resistor This parameter can be one of the following values:
910 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
911 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
912 * @retval None
913 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)914 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
915 {
916 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
917 }
918
919 /**
920 * @brief Get the resistor impedance
921 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
922 * @retval Returned value can be one of the following values:
923 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
924 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
925 */
LL_PWR_GetBattChargResistor(void)926 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
927 {
928 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
929 }
930
931 /**
932 * @brief Enable battery charging
933 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
934 * @retval None
935 */
LL_PWR_EnableBatteryCharging(void)936 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
937 {
938 SET_BIT(PWR->CR4, PWR_CR4_VBE);
939 }
940
941 /**
942 * @brief Disable battery charging
943 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
944 * @retval None
945 */
LL_PWR_DisableBatteryCharging(void)946 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
947 {
948 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
949 }
950
951 /**
952 * @brief Check if battery charging is enabled
953 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
954 * @retval State of bit (1 or 0).
955 */
LL_PWR_IsEnabledBatteryCharging(void)956 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
957 {
958 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
959 }
960
961 /**
962 * @brief Set the Wake-Up pin polarity low for the event detection
963 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
964 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
965 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
966 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
967 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
968 * @param WakeUpPin This parameter can be one of the following values:
969 * @arg @ref LL_PWR_WAKEUP_PIN1
970 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
971 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
972 * @arg @ref LL_PWR_WAKEUP_PIN4
973 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
974 *
975 * (*) Not available on devices STM32WB50xx
976 * @retval None
977 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)978 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
979 {
980 SET_BIT(PWR->CR4, WakeUpPin);
981 }
982
983 /**
984 * @brief Set the Wake-Up pin polarity high for the event detection
985 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
986 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
987 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
988 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
989 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
990 * @param WakeUpPin This parameter can be one of the following values:
991 * @arg @ref LL_PWR_WAKEUP_PIN1
992 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
993 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
994 * @arg @ref LL_PWR_WAKEUP_PIN4
995 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
996 *
997 * (*) Not available on devices STM32WB50xx
998 * @retval None
999 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1000 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1001 {
1002 CLEAR_BIT(PWR->CR4, WakeUpPin);
1003 }
1004
1005 /**
1006 * @brief Get the Wake-Up pin polarity for the event detection
1007 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
1008 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
1009 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
1010 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
1011 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
1012 * @param WakeUpPin This parameter can be one of the following values:
1013 * @arg @ref LL_PWR_WAKEUP_PIN1
1014 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1015 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1016 * @arg @ref LL_PWR_WAKEUP_PIN4
1017 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1018 *
1019 * (*) Not available on devices STM32WB50xx
1020 * @retval State of bit (1 or 0).
1021 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1022 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1023 {
1024 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1025 }
1026
1027 /**
1028 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1029 * @note Some pins are not configurable for pulling in Standby and Shutdown
1030 * modes. Refer to reference manual for available pins and ports.
1031 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1032 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1033 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1034 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1035 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1036 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp
1037 * @param GPIO This parameter can be one of the following values:
1038 * @arg @ref LL_PWR_GPIO_A
1039 * @arg @ref LL_PWR_GPIO_B
1040 * @arg @ref LL_PWR_GPIO_C
1041 * @arg @ref LL_PWR_GPIO_D
1042 * @arg @ref LL_PWR_GPIO_E
1043 * @arg @ref LL_PWR_GPIO_H
1044 * @param GPIONumber This parameter can be one of the following values:
1045 * @arg @ref LL_PWR_GPIO_BIT_0
1046 * @arg @ref LL_PWR_GPIO_BIT_1
1047 * @arg @ref LL_PWR_GPIO_BIT_2
1048 * @arg @ref LL_PWR_GPIO_BIT_3
1049 * @arg @ref LL_PWR_GPIO_BIT_4
1050 * @arg @ref LL_PWR_GPIO_BIT_5
1051 * @arg @ref LL_PWR_GPIO_BIT_6
1052 * @arg @ref LL_PWR_GPIO_BIT_7
1053 * @arg @ref LL_PWR_GPIO_BIT_8
1054 * @arg @ref LL_PWR_GPIO_BIT_9
1055 * @arg @ref LL_PWR_GPIO_BIT_10
1056 * @arg @ref LL_PWR_GPIO_BIT_11
1057 * @arg @ref LL_PWR_GPIO_BIT_12
1058 * @arg @ref LL_PWR_GPIO_BIT_13
1059 * @arg @ref LL_PWR_GPIO_BIT_14
1060 * @arg @ref LL_PWR_GPIO_BIT_15
1061 * @retval None
1062 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1063 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1064 {
1065 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1066 }
1067
1068 /**
1069 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1070 * @note Some pins are not configurable for pulling in Standby and Shutdown
1071 * modes. Refer to reference manual for available pins and ports.
1072 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1073 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1074 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1075 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1076 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1077 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp
1078 * @param GPIO This parameter can be one of the following values:
1079 * @arg @ref LL_PWR_GPIO_A
1080 * @arg @ref LL_PWR_GPIO_B
1081 * @arg @ref LL_PWR_GPIO_C
1082 * @arg @ref LL_PWR_GPIO_D
1083 * @arg @ref LL_PWR_GPIO_E
1084 * @arg @ref LL_PWR_GPIO_H
1085 * @param GPIONumber This parameter can be one of the following values:
1086 * @arg @ref LL_PWR_GPIO_BIT_0
1087 * @arg @ref LL_PWR_GPIO_BIT_1
1088 * @arg @ref LL_PWR_GPIO_BIT_2
1089 * @arg @ref LL_PWR_GPIO_BIT_3
1090 * @arg @ref LL_PWR_GPIO_BIT_4
1091 * @arg @ref LL_PWR_GPIO_BIT_5
1092 * @arg @ref LL_PWR_GPIO_BIT_6
1093 * @arg @ref LL_PWR_GPIO_BIT_7
1094 * @arg @ref LL_PWR_GPIO_BIT_8
1095 * @arg @ref LL_PWR_GPIO_BIT_9
1096 * @arg @ref LL_PWR_GPIO_BIT_10
1097 * @arg @ref LL_PWR_GPIO_BIT_11
1098 * @arg @ref LL_PWR_GPIO_BIT_12
1099 * @arg @ref LL_PWR_GPIO_BIT_13
1100 * @arg @ref LL_PWR_GPIO_BIT_14
1101 * @arg @ref LL_PWR_GPIO_BIT_15
1102 * @retval None
1103 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1104 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1105 {
1106 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1107 }
1108
1109 /**
1110 * @brief Check if GPIO pull-up state is enabled
1111 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1112 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1113 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1114 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1115 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1116 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp
1117 * @param GPIO This parameter can be one of the following values:
1118 * @arg @ref LL_PWR_GPIO_A
1119 * @arg @ref LL_PWR_GPIO_B
1120 * @arg @ref LL_PWR_GPIO_C
1121 * @arg @ref LL_PWR_GPIO_D
1122 * @arg @ref LL_PWR_GPIO_E
1123 * @arg @ref LL_PWR_GPIO_H
1124 * @param GPIONumber This parameter can be one of the following values:
1125 * @arg @ref LL_PWR_GPIO_BIT_0
1126 * @arg @ref LL_PWR_GPIO_BIT_1
1127 * @arg @ref LL_PWR_GPIO_BIT_2
1128 * @arg @ref LL_PWR_GPIO_BIT_3
1129 * @arg @ref LL_PWR_GPIO_BIT_4
1130 * @arg @ref LL_PWR_GPIO_BIT_5
1131 * @arg @ref LL_PWR_GPIO_BIT_6
1132 * @arg @ref LL_PWR_GPIO_BIT_7
1133 * @arg @ref LL_PWR_GPIO_BIT_8
1134 * @arg @ref LL_PWR_GPIO_BIT_9
1135 * @arg @ref LL_PWR_GPIO_BIT_10
1136 * @arg @ref LL_PWR_GPIO_BIT_11
1137 * @arg @ref LL_PWR_GPIO_BIT_12
1138 * @arg @ref LL_PWR_GPIO_BIT_13
1139 * @arg @ref LL_PWR_GPIO_BIT_14
1140 * @arg @ref LL_PWR_GPIO_BIT_15
1141 * @retval State of bit (1 or 0).
1142 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1143 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1144 {
1145 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1146 }
1147
1148 /**
1149 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1150 * @note Some pins are not configurable for pulling in Standby and Shutdown
1151 * modes. Refer to reference manual for available pins and ports.
1152 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1153 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1154 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1155 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1156 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1157 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown
1158 * @param GPIO This parameter can be one of the following values:
1159 * @arg @ref LL_PWR_GPIO_A
1160 * @arg @ref LL_PWR_GPIO_B
1161 * @arg @ref LL_PWR_GPIO_C
1162 * @arg @ref LL_PWR_GPIO_D
1163 * @arg @ref LL_PWR_GPIO_E
1164 * @arg @ref LL_PWR_GPIO_H
1165 * @param GPIONumber This parameter can be one of the following values:
1166 * @arg @ref LL_PWR_GPIO_BIT_0
1167 * @arg @ref LL_PWR_GPIO_BIT_1
1168 * @arg @ref LL_PWR_GPIO_BIT_2
1169 * @arg @ref LL_PWR_GPIO_BIT_3
1170 * @arg @ref LL_PWR_GPIO_BIT_4
1171 * @arg @ref LL_PWR_GPIO_BIT_5
1172 * @arg @ref LL_PWR_GPIO_BIT_6
1173 * @arg @ref LL_PWR_GPIO_BIT_7
1174 * @arg @ref LL_PWR_GPIO_BIT_8
1175 * @arg @ref LL_PWR_GPIO_BIT_9
1176 * @arg @ref LL_PWR_GPIO_BIT_10
1177 * @arg @ref LL_PWR_GPIO_BIT_11
1178 * @arg @ref LL_PWR_GPIO_BIT_12
1179 * @arg @ref LL_PWR_GPIO_BIT_13
1180 * @arg @ref LL_PWR_GPIO_BIT_14
1181 * @arg @ref LL_PWR_GPIO_BIT_15
1182 * @retval None
1183 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1184 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1185 {
1186 SET_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
1187 }
1188
1189 /**
1190 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1191 * @note Some pins are not configurable for pulling in Standby and Shutdown
1192 * modes. Refer to reference manual for available pins and ports.
1193 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1194 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1195 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1196 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1197 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1198 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown
1199 * @param GPIO This parameter can be one of the following values:
1200 * @arg @ref LL_PWR_GPIO_A
1201 * @arg @ref LL_PWR_GPIO_B
1202 * @arg @ref LL_PWR_GPIO_C
1203 * @arg @ref LL_PWR_GPIO_D
1204 * @arg @ref LL_PWR_GPIO_E
1205 * @arg @ref LL_PWR_GPIO_H
1206 * @param GPIONumber This parameter can be one of the following values:
1207 * @arg @ref LL_PWR_GPIO_BIT_0
1208 * @arg @ref LL_PWR_GPIO_BIT_1
1209 * @arg @ref LL_PWR_GPIO_BIT_2
1210 * @arg @ref LL_PWR_GPIO_BIT_3
1211 * @arg @ref LL_PWR_GPIO_BIT_4
1212 * @arg @ref LL_PWR_GPIO_BIT_5
1213 * @arg @ref LL_PWR_GPIO_BIT_6
1214 * @arg @ref LL_PWR_GPIO_BIT_7
1215 * @arg @ref LL_PWR_GPIO_BIT_8
1216 * @arg @ref LL_PWR_GPIO_BIT_9
1217 * @arg @ref LL_PWR_GPIO_BIT_10
1218 * @arg @ref LL_PWR_GPIO_BIT_11
1219 * @arg @ref LL_PWR_GPIO_BIT_12
1220 * @arg @ref LL_PWR_GPIO_BIT_13
1221 * @arg @ref LL_PWR_GPIO_BIT_14
1222 * @arg @ref LL_PWR_GPIO_BIT_15
1223 * @retval None
1224 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1225 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1226 {
1227 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber);
1228 }
1229
1230 /**
1231 * @brief Check if GPIO pull-down state is enabled
1232 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1233 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1234 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1235 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1236 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1237 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown
1238 * @param GPIO This parameter can be one of the following values:
1239 * @arg @ref LL_PWR_GPIO_A
1240 * @arg @ref LL_PWR_GPIO_B
1241 * @arg @ref LL_PWR_GPIO_C
1242 * @arg @ref LL_PWR_GPIO_D
1243 * @arg @ref LL_PWR_GPIO_E
1244 * @arg @ref LL_PWR_GPIO_H
1245 * @param GPIONumber This parameter can be one of the following values:
1246 * @arg @ref LL_PWR_GPIO_BIT_0
1247 * @arg @ref LL_PWR_GPIO_BIT_1
1248 * @arg @ref LL_PWR_GPIO_BIT_2
1249 * @arg @ref LL_PWR_GPIO_BIT_3
1250 * @arg @ref LL_PWR_GPIO_BIT_4
1251 * @arg @ref LL_PWR_GPIO_BIT_5
1252 * @arg @ref LL_PWR_GPIO_BIT_6
1253 * @arg @ref LL_PWR_GPIO_BIT_7
1254 * @arg @ref LL_PWR_GPIO_BIT_8
1255 * @arg @ref LL_PWR_GPIO_BIT_9
1256 * @arg @ref LL_PWR_GPIO_BIT_10
1257 * @arg @ref LL_PWR_GPIO_BIT_11
1258 * @arg @ref LL_PWR_GPIO_BIT_12
1259 * @arg @ref LL_PWR_GPIO_BIT_13
1260 * @arg @ref LL_PWR_GPIO_BIT_14
1261 * @arg @ref LL_PWR_GPIO_BIT_15
1262 * @retval State of bit (1 or 0).
1263 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1264 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1265 {
1266 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4UL)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1267 }
1268
1269 #if defined(PWR_CR5_SMPSEN)
1270 /**
1271 * @brief Set BOR configuration
1272 * @rmtoll CR5 BORHC LL_PWR_SetBORConfig
1273 * @param BORConfiguration This parameter can be one of the following values:
1274 * @arg @ref LL_PWR_BOR_SYSTEM_RESET
1275 * @arg @ref LL_PWR_BOR_SMPS_FORCE_BYPASS
1276 */
LL_PWR_SetBORConfig(uint32_t BORConfiguration)1277 __STATIC_INLINE void LL_PWR_SetBORConfig(uint32_t BORConfiguration)
1278 {
1279 MODIFY_REG(PWR->CR5, PWR_CR5_BORHC, BORConfiguration);
1280 }
1281
1282 /**
1283 * @brief Get BOR configuration
1284 * @rmtoll CR5 BORHC LL_PWR_GetBORConfig
1285 * @retval Returned value can be one of the following values:
1286 * @arg @ref LL_PWR_BOR_SYSTEM_RESET
1287 * @arg @ref LL_PWR_BOR_SMPS_FORCE_BYPASS
1288 */
LL_PWR_GetBORConfig(void)1289 __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void)
1290 {
1291 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_BORHC));
1292 }
1293 #endif
1294
1295 /**
1296 * @}
1297 */
1298
1299 #if defined(PWR_CR5_SMPSEN)
1300 /** @defgroup PWR_LL_EF_Configuration_SMPS Configuration of SMPS
1301 * @{
1302 */
1303
1304 /**
1305 * @brief Set SMPS operating mode
1306 * @note When SMPS step down converter SMPS mode is enabled,
1307 * it is good practice to enable the BORH to monitor the supply:
1308 * in this case, when the supply drops below the SMPS step down
1309 * converter SMPS mode operating supply level,
1310 * switching on the fly is performed automaticcaly
1311 * and interruption is generated.
1312 * Refer to function @ref LL_PWR_SetBORConfig().
1313 * @note Occurence of SMPS step down converter forced in bypass mode
1314 * can be monitored by flag and interruption.
1315 * Refer to functions
1316 * @ref LL_PWR_IsActiveFlag_SMPSFB(), @ref LL_PWR_ClearFlag_SMPSFB(),
1317 * @ref LL_PWR_EnableIT_BORH_SMPSFB().
1318 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_SetMode \n
1319 * CR5 SMPSBEN LL_PWR_SMPS_SetMode
1320 * @param OperatingMode This parameter can be one of the following values:
1321 * @arg @ref LL_PWR_SMPS_BYPASS
1322 * @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
1323 *
1324 * (1) SMPS operating mode step down or open depends on system low-power mode:
1325 * - step down mode if system low power mode is run, LP run or stop0,
1326 * - open mode if system low power mode is stop1, stop2, standby or shutdown
1327 * @retval None
1328 */
LL_PWR_SMPS_SetMode(uint32_t OperatingMode)1329 __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode)
1330 {
1331 /* Note: Operation on bits performed to keep compatibility of literals */
1332 /* for all SMPS operating mode functions: */
1333 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
1334 /* and "LL_PWR_SMPS_GetEffectiveMode()". */
1335 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, (OperatingMode & PWR_SR2_SMPSF) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos));
1336 }
1337
1338 /**
1339 * @brief Get SMPS operating mode
1340 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_GetMode \n
1341 * CR5 SMPSBEN LL_PWR_SMPS_GetMode
1342 * @retval Returned value can be one of the following values:
1343 * @arg @ref LL_PWR_SMPS_BYPASS
1344 * @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
1345 *
1346 * (1) SMPS operating mode step down or open depends on system low-power mode:
1347 * - step down mode if system low power mode is run, LP run or stop0,
1348 * - open mode if system low power mode is stop1, stop2, standby or shutdown
1349 */
LL_PWR_SMPS_GetMode(void)1350 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
1351 {
1352 /* Note: Operation on bits performed to keep compatibility of literals */
1353 /* for all SMPS operating mode functions: */
1354 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
1355 /* and "LL_PWR_SMPS_GetEffectiveMode()". */
1356 register uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos));
1357
1358 OperatingMode = (OperatingMode | ((~OperatingMode >> 1U) & PWR_SR2_SMPSBF));
1359
1360 return OperatingMode;
1361 }
1362
1363 /**
1364 * @brief Get SMPS effective operating mode
1365 * @note SMPS operating mode can be changed by hardware, therefore
1366 * requested operating mode can differ from effective low power mode.
1367 * - dependency on system low-power mode:
1368 * - step down mode if system low power mode is run, LP run or stop0,
1369 * - open mode if system low power mode is stop1, stop2, standby or shutdown
1370 * - dependency on BOR level:
1371 * - bypass mode if supply voltage drops below BOR level
1372 * @note This functions check flags of SMPS operating modes step down
1373 * and bypass. If the SMPS is not among these 2 operating modes,
1374 * then it can be in mode off or open.
1375 * @rmtoll SR2 SMPSF LL_PWR_SMPS_GetEffectiveMode \n
1376 * SR2 SMPSBF LL_PWR_SMPS_GetEffectiveMode
1377 * @retval Returned value can be one of the following values:
1378 * @arg @ref LL_PWR_SMPS_BYPASS
1379 * @arg @ref LL_PWR_SMPS_STEP_DOWN (1)
1380 *
1381 * (1) SMPS operating mode step down or open depends on system low-power mode:
1382 * - step down mode if system low power mode is run, LP run or stop0,
1383 * - open mode if system low power mode is stop1, stop2, standby or shutdown
1384 */
LL_PWR_SMPS_GetEffectiveMode(void)1385 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void)
1386 {
1387 return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF)));
1388 }
1389
1390 /**
1391 * @brief SMPS step down converter enable
1392 * @note This function can be used for specific usage of the SMPS,
1393 * for general usage of the SMPS the function
1394 * @ref LL_PWR_SMPS_SetMode() should be used instead.
1395 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Enable
1396 * @retval None
1397 */
LL_PWR_SMPS_Enable(void)1398 __STATIC_INLINE void LL_PWR_SMPS_Enable(void)
1399 {
1400 SET_BIT(PWR->CR5, PWR_CR5_SMPSEN);
1401 }
1402
1403 /**
1404 * @brief SMPS step down converter enable
1405 * @note This function can be used for specific usage of the SMPS,
1406 * for general usage of the SMPS the function
1407 * @ref LL_PWR_SMPS_SetMode() should be used instead.
1408 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Disable
1409 * @retval None
1410 */
LL_PWR_SMPS_Disable(void)1411 __STATIC_INLINE void LL_PWR_SMPS_Disable(void)
1412 {
1413 CLEAR_BIT(PWR->CR5, PWR_CR5_SMPSEN);
1414 }
1415
1416 /**
1417 * @brief Check if the SMPS step down converter is enabled
1418 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_IsEnabled
1419 * @retval State of bit (1 or 0).
1420 */
LL_PWR_SMPS_IsEnabled(void)1421 __STATIC_INLINE uint32_t LL_PWR_SMPS_IsEnabled(void)
1422 {
1423 return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) == (PWR_CR5_SMPSEN)) ? 1UL : 0UL);
1424 }
1425
1426 /**
1427 * @brief Set SMPS step down converter supply startup current selection
1428 * @rmtoll CR5 SMPSSC LL_PWR_SMPS_SetStartupCurrent
1429 * @param StartupCurrent This parameter can be one of the following values:
1430 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_80MA
1431 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_100MA
1432 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_120MA
1433 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_140MA
1434 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_160MA
1435 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_180MA
1436 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_200MA
1437 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_220MA
1438 * @retval None
1439 */
LL_PWR_SMPS_SetStartupCurrent(uint32_t StartupCurrent)1440 __STATIC_INLINE void LL_PWR_SMPS_SetStartupCurrent(uint32_t StartupCurrent)
1441 {
1442 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSSC, StartupCurrent);
1443 }
1444
1445 /**
1446 * @brief Get SMPS step down converter supply startup current selection
1447 * @rmtoll CR5 SMPSSC LL_PWR_SMPS_GetStartupCurrent
1448 * @retval Returned value can be one of the following values:
1449 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_80MA
1450 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_100MA
1451 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_120MA
1452 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_140MA
1453 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_160MA
1454 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_180MA
1455 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_200MA
1456 * @arg @ref LL_PWR_SMPS_STARTUP_CURRENT_220MA
1457 */
LL_PWR_SMPS_GetStartupCurrent(void)1458 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetStartupCurrent(void)
1459 {
1460 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSSC));
1461 }
1462
1463 /**
1464 * @brief Set SMPS step down converter output voltage scaling
1465 * @note SMPS output voltage is calibrated in production,
1466 * calibration parameters are applied to the voltage level parameter
1467 * to reach the requested voltage value.
1468 * @rmtoll CR5 SMPSVOS LL_PWR_SMPS_SetOutputVoltageLevel
1469 * @param OutputVoltageLevel This parameter can be one of the following values:
1470 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
1471 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
1472 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
1473 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
1474 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
1475 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
1476 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
1477 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
1478 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
1479 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
1480 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
1481 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
1482 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
1483 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
1484 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
1485 * @retval None
1486 */
LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel)1487 __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLevel)
1488 {
1489 register __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */
1490 register int32_t TrimmingSteps; /* Trimming steps between theorical output voltage and calibrated output voltage */
1491 register int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */
1492
1493 if(OutputVoltageLevel_calibration == 0UL)
1494 {
1495 /* Device with SMPS output voltage not calibrated in production: Apply output voltage value directly */
1496
1497 /* Update register */
1498 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, OutputVoltageLevel);
1499 }
1500 else
1501 {
1502 /* Device with SMPS output voltage calibrated in production: Apply output voltage value after correction by calibration value */
1503
1504 TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos));
1505 OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)(OutputVoltageLevel >> PWR_CR5_SMPSVOS_Pos)) + (int32_t)TrimmingSteps);
1506
1507 /* Clamp value to voltage trimming bitfield range */
1508 if(OutputVoltageLevelTrimmed < 0)
1509 {
1510 OutputVoltageLevelTrimmed = 0;
1511 }
1512 else
1513 {
1514 if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
1515 {
1516 OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS;
1517 }
1518 }
1519
1520 /* Update register */
1521 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, (uint32_t)OutputVoltageLevelTrimmed);
1522 }
1523 }
1524
1525 /**
1526 * @brief Get SMPS step down converter output voltage scaling
1527 * @note SMPS output voltage is calibrated in production,
1528 * calibration parameters are applied to the voltage level parameter
1529 * to return the effective voltage value.
1530 * @rmtoll CR5 SMPSVOS LL_PWR_SMPS_GetOutputVoltageLevel
1531 * @retval Returned value can be one of the following values:
1532 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20
1533 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V25
1534 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V30
1535 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V35
1536 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40
1537 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V45
1538 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50
1539 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V55
1540 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V60
1541 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V65
1542 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V70
1543 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V75
1544 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V80
1545 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V85
1546 * @arg @ref LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90
1547 */
LL_PWR_SMPS_GetOutputVoltageLevel(void)1548 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void)
1549 {
1550 register __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */
1551 register int32_t TrimmingSteps; /* Trimming steps between theorical output voltage and calibrated output voltage */
1552 register int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */
1553
1554 if(OutputVoltageLevel_calibration == 0UL)
1555 {
1556 /* Device with SMPS output voltage not calibrated in production: Return output voltage value directly */
1557
1558 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS));
1559 }
1560 else
1561 {
1562 /* Device with SMPS output voltage calibrated in production: Return output voltage value after correction by calibration value */
1563
1564 TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos)); /* Trimming steps between theorical output voltage and calibrated output voltage */
1565
1566 OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS)) - TrimmingSteps);
1567
1568 /* Clamp value to voltage range */
1569 if(OutputVoltageLevelTrimmed < 0)
1570 {
1571 OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20;
1572 }
1573 else
1574 {
1575 if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
1576 {
1577 OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90;
1578 }
1579 }
1580
1581 return (uint32_t)OutputVoltageLevelTrimmed;
1582 }
1583 }
1584
1585 /**
1586 * @}
1587 */
1588 #endif
1589
1590 /** @defgroup PWR_LL_EF_Configuration_Multicore Configuration of multicore, intended to be executed by CPU1
1591 * @{
1592 */
1593
1594 /**
1595 * @brief Boot CPU2 after reset or wakeup from stop or standby modes
1596 * @rmtoll CR4 C2BOOT LL_PWR_EnableBootC2
1597 * @retval None
1598 */
LL_PWR_EnableBootC2(void)1599 __STATIC_INLINE void LL_PWR_EnableBootC2(void)
1600 {
1601 SET_BIT(PWR->CR4, PWR_CR4_C2BOOT);
1602 }
1603
1604 /**
1605 * @brief Release bit to boot CPU2 after reset or wakeup from stop or standby
1606 * modes
1607 * @rmtoll CR4 C2BOOT LL_PWR_DisableBootC2
1608 * @retval None
1609 */
LL_PWR_DisableBootC2(void)1610 __STATIC_INLINE void LL_PWR_DisableBootC2(void)
1611 {
1612 CLEAR_BIT(PWR->CR4, PWR_CR4_C2BOOT);
1613 }
1614
1615 /**
1616 * @brief Check if bit to boot CPU2 after reset or wakeup from stop or standby
1617 * modes is set
1618 * @rmtoll CR4 C2BOOT LL_PWR_IsEnabledBootC2
1619 * @retval State of bit (1 or 0)
1620 */
LL_PWR_IsEnabledBootC2(void)1621 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void)
1622 {
1623 return ((READ_BIT(PWR->CR4, PWR_CR4_C2BOOT) == (PWR_CR4_C2BOOT)) ? 1UL : 0UL);
1624 }
1625
1626 /**
1627 * @}
1628 */
1629
1630 /** @defgroup PWR_LL_EF_Configuration_CPU2 Configuration of CPU2, intended to be executed by CPU2
1631 * @{
1632 */
1633
1634 /**
1635 * @brief Set Low-Power mode for CPU2
1636 * @rmtoll C2CR1 LPMS LL_C2_PWR_SetPowerMode
1637 * @param LowPowerMode This parameter can be one of the following values:
1638 * @arg @ref LL_PWR_MODE_STOP0
1639 * @arg @ref LL_PWR_MODE_STOP1
1640 * @arg @ref LL_PWR_MODE_STOP2
1641 * @arg @ref LL_PWR_MODE_STANDBY
1642 * @arg @ref LL_PWR_MODE_SHUTDOWN
1643 * @retval None
1644 */
LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)1645 __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
1646 {
1647 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode);
1648 }
1649
1650 /**
1651 * @brief Get Low-Power mode for CPU2
1652 * @rmtoll C2CR1 LPMS LL_C2_PWR_GetPowerMode
1653 * @retval Returned value can be one of the following values:
1654 * @arg @ref LL_PWR_MODE_STOP0
1655 * @arg @ref LL_PWR_MODE_STOP1
1656 * @arg @ref LL_PWR_MODE_STOP2
1657 * @arg @ref LL_PWR_MODE_STANDBY
1658 * @arg @ref LL_PWR_MODE_SHUTDOWN
1659 */
LL_C2_PWR_GetPowerMode(void)1660 __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void)
1661 {
1662 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_LPMS));
1663 }
1664
1665 /**
1666 * @brief Set flash power-down mode during low-power run mode for CPU2
1667 * @rmtoll C2CR1 FPDR LL_C2_PWR_SetFlashPowerModeLPRun
1668 * @param FlashLowPowerMode This parameter can be one of the following values:
1669 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
1670 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
1671 * @retval None
1672 */
LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)1673 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
1674 {
1675 /* Unlock bit FPDR */
1676 WRITE_REG(PWR->C2CR1, 0x0000C1B0U);
1677
1678 /* Update bit FPDR */
1679 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode);
1680 }
1681
1682 /**
1683 * @brief Get flash power-down mode during low-power run mode for CPU2
1684 * @rmtoll C2CR1 FPDR LL_C2_PWR_GetFlashPowerModeLPRun
1685 * @retval Returned value can be one of the following values:
1686 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
1687 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
1688 */
LL_C2_PWR_GetFlashPowerModeLPRun(void)1689 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeLPRun(void)
1690 {
1691 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDR));
1692 }
1693
1694 /**
1695 * @brief Set flash power-down mode during sleep mode for CPU2
1696 * @rmtoll C2CR1 FPDS LL_C2_PWR_SetFlashPowerModeSleep
1697 * @param FlashLowPowerMode This parameter can be one of the following values:
1698 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
1699 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
1700 * @retval None
1701 */
LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)1702 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
1703 {
1704 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDS, FlashLowPowerMode);
1705 }
1706
1707 /**
1708 * @brief Get flash power-down mode during sleep mode for CPU2
1709 * @rmtoll C2CR1 FPDS LL_C2_PWR_GetFlashPowerModeSleep
1710 * @retval Returned value can be one of the following values:
1711 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
1712 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
1713 */
LL_C2_PWR_GetFlashPowerModeSleep(void)1714 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeSleep(void)
1715 {
1716 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDS));
1717 }
1718
1719
1720 /**
1721 * @brief Enable Internal Wake-up line for CPU2
1722 * @rmtoll C2CR3 EIWUL LL_C2_PWR_EnableInternWU
1723 * @retval None
1724 */
LL_C2_PWR_EnableInternWU(void)1725 __STATIC_INLINE void LL_C2_PWR_EnableInternWU(void)
1726 {
1727 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
1728 }
1729
1730 /**
1731 * @brief Disable Internal Wake-up line for CPU2
1732 * @rmtoll C2CR3 EIWUL LL_C2_PWR_DisableInternWU
1733 * @retval None
1734 */
LL_C2_PWR_DisableInternWU(void)1735 __STATIC_INLINE void LL_C2_PWR_DisableInternWU(void)
1736 {
1737 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
1738 }
1739
1740 /**
1741 * @brief Check if Internal Wake-up line is enabled for CPU2
1742 * @rmtoll C2CR3 EIWUL LL_C2_PWR_IsEnabledInternWU
1743 * @retval State of bit (1 or 0).
1744 */
LL_C2_PWR_IsEnabledInternWU(void)1745 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void)
1746 {
1747 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL);
1748 }
1749
1750 /**
1751 * @brief Enable the WakeUp PINx functionality
1752 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n
1753 * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n
1754 * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin\n
1755 * C2CR3 EWUP4 LL_C2_PWR_EnableWakeUpPin\n
1756 * C2CR3 EWUP5 LL_C2_PWR_EnableWakeUpPin
1757 * @param WakeUpPin This parameter can be one of the following values:
1758 * @arg @ref LL_PWR_WAKEUP_PIN1
1759 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1760 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1761 * @arg @ref LL_PWR_WAKEUP_PIN4
1762 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1763 *
1764 * (*) Not available on devices STM32WB50xx
1765 * @retval None
1766 */
LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1767 __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1768 {
1769 SET_BIT(PWR->C2CR3, WakeUpPin);
1770 }
1771
1772 /**
1773 * @brief Disable the WakeUp PINx functionality
1774 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_DisableWakeUpPin\n
1775 * C2CR3 EWUP2 LL_C2_PWR_DisableWakeUpPin\n
1776 * C2CR3 EWUP3 LL_C2_PWR_DisableWakeUpPin\n
1777 * C2CR3 EWUP4 LL_C2_PWR_DisableWakeUpPin\n
1778 * C2CR3 EWUP5 LL_C2_PWR_DisableWakeUpPin
1779 * @param WakeUpPin This parameter can be one of the following values:
1780 * @arg @ref LL_PWR_WAKEUP_PIN1
1781 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1782 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1783 * @arg @ref LL_PWR_WAKEUP_PIN4
1784 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1785 *
1786 * (*) Not available on devices STM32WB50xx
1787 * @retval None
1788 */
LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1789 __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1790 {
1791 CLEAR_BIT(PWR->C2CR3, WakeUpPin);
1792 }
1793
1794 /**
1795 * @brief Check if the WakeUp PINx functionality is enabled
1796 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_IsEnabledWakeUpPin\n
1797 * C2CR3 EWUP2 LL_C2_PWR_IsEnabledWakeUpPin\n
1798 * C2CR3 EWUP3 LL_C2_PWR_IsEnabledWakeUpPin\n
1799 * C2CR3 EWUP4 LL_C2_PWR_IsEnabledWakeUpPin\n
1800 * C2CR3 EWUP5 LL_C2_PWR_IsEnabledWakeUpPin
1801 * @param WakeUpPin This parameter can be one of the following values:
1802 * @arg @ref LL_PWR_WAKEUP_PIN1
1803 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
1804 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
1805 * @arg @ref LL_PWR_WAKEUP_PIN4
1806 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
1807 *
1808 * (*) Not available on devices STM32WB50xx
1809 * @retval None
1810 */
LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1811 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1812 {
1813 return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1814 }
1815
1816 /**
1817 * @brief Enable pull-up and pull-down configuration for CPU2
1818 * @rmtoll C2CR3 APC LL_C2_PWR_EnablePUPDCfg
1819 * @retval None
1820 */
LL_C2_PWR_EnablePUPDCfg(void)1821 __STATIC_INLINE void LL_C2_PWR_EnablePUPDCfg(void)
1822 {
1823 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC);
1824 }
1825
1826 /**
1827 * @brief Disable pull-up and pull-down configuration for CPU2
1828 * @rmtoll C2CR3 APC LL_C2_PWR_DisablePUPDCfg
1829 * @retval None
1830 */
LL_C2_PWR_DisablePUPDCfg(void)1831 __STATIC_INLINE void LL_C2_PWR_DisablePUPDCfg(void)
1832 {
1833 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC);
1834 }
1835
1836 /**
1837 * @brief Check if pull-up and pull-down configuration is enabled for CPU2
1838 * @rmtoll C2CR3 APC LL_C2_PWR_IsEnabledPUPDCfg
1839 * @retval State of bit (1 or 0).
1840 */
LL_C2_PWR_IsEnabledPUPDCfg(void)1841 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledPUPDCfg(void)
1842 {
1843 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL);
1844 }
1845
1846 /**
1847 * @}
1848 */
1849
1850 /** @defgroup PWR_LL_EF_Configuration_CPU2_Radio Configuration of radio (BLE or 802.15.4) of CPU2, intended to be executed by CPU2
1851 * @{
1852 */
1853
1854 /**
1855 * @brief Wakeup BLE controller from its sleep mode
1856 * @note This bit is automatically reset when BLE controller
1857 * exit its sleep mode.
1858 * @rmtoll C2CR1 BLEEWKUP LL_C2_PWR_WakeUp_BLE
1859 * @retval None
1860 */
LL_C2_PWR_WakeUp_BLE(void)1861 __STATIC_INLINE void LL_C2_PWR_WakeUp_BLE(void)
1862 {
1863 SET_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP);
1864 }
1865
1866 /**
1867 * @brief Check if the BLE controller is woken-up from
1868 * low-power mode.
1869 * @rmtoll C2CR1 BLEEWKUP LL_C2_PWR_IsWokenUp_BLE
1870 * @retval State of bit (1 or 0) (value "0": BLE is not woken-up)
1871 */
LL_C2_PWR_IsWokenUp_BLE(void)1872 __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_BLE(void)
1873 {
1874 return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL);
1875 }
1876
1877 /**
1878 * @brief Wakeup 802.15.4 controller from its sleep mode
1879 * @note This bit is automatically reset when 802.15.4 controller
1880 * exit its sleep mode.
1881 * @rmtoll C2CR1 802EWKUP LL_C2_PWR_WakeUp_802_15_4
1882 * @retval None
1883 */
LL_C2_PWR_WakeUp_802_15_4(void)1884 __STATIC_INLINE void LL_C2_PWR_WakeUp_802_15_4(void)
1885 {
1886 SET_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP);
1887 }
1888
1889 /**
1890 * @brief Check if the 802.15.4 controller is woken-up from
1891 * low-power mode.
1892 * @rmtoll C2CR1 802EWKUP LL_C2_PWR_IsWokenUp_802_15_4
1893 * @retval State of bit (1 or 0) (value "0": 802.15.4 is not woken-up)
1894 */
LL_C2_PWR_IsWokenUp_802_15_4(void)1895 __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4(void)
1896 {
1897 return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL);
1898 }
1899
1900 /**
1901 * @}
1902 */
1903
1904 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1905 * @{
1906 */
1907
1908 /**
1909 * @brief Get Internal Wake-up line Flag
1910 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1911 * @retval State of bit (1 or 0).
1912 */
LL_PWR_IsActiveFlag_InternWU(void)1913 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1914 {
1915 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1916 }
1917
1918 #if defined(PWR_CR3_EWUP5)
1919 /**
1920 * @brief Get Wake-up Flag 5
1921 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1922 * @retval State of bit (1 or 0).
1923 */
LL_PWR_IsActiveFlag_WU5(void)1924 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1925 {
1926 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1927 }
1928 #endif
1929
1930 /**
1931 * @brief Get Wake-up Flag 4
1932 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1933 * @retval State of bit (1 or 0).
1934 */
LL_PWR_IsActiveFlag_WU4(void)1935 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1936 {
1937 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1938 }
1939
1940 #if defined(PWR_CR3_EWUP3)
1941 /**
1942 * @brief Get Wake-up Flag 3
1943 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1944 * @retval State of bit (1 or 0).
1945 */
LL_PWR_IsActiveFlag_WU3(void)1946 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1947 {
1948 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1949 }
1950 #endif
1951
1952 #if defined(PWR_CR3_EWUP2)
1953 /**
1954 * @brief Get Wake-up Flag 2
1955 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1956 * @retval State of bit (1 or 0).
1957 */
LL_PWR_IsActiveFlag_WU2(void)1958 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1959 {
1960 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1961 }
1962 #endif
1963
1964 /**
1965 * @brief Get Wake-up Flag 1
1966 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1967 * @retval State of bit (1 or 0).
1968 */
LL_PWR_IsActiveFlag_WU1(void)1969 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1970 {
1971 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1972 }
1973
1974 /**
1975 * @brief Clear Wake-up Flags
1976 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1977 * @retval None
1978 */
LL_PWR_ClearFlag_WU(void)1979 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1980 {
1981 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1982 }
1983
1984 #if defined(PWR_CR3_EWUP5)
1985 /**
1986 * @brief Clear Wake-up Flag 5
1987 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1988 * @retval None
1989 */
LL_PWR_ClearFlag_WU5(void)1990 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1991 {
1992 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1993 }
1994 #endif
1995
1996 /**
1997 * @brief Clear Wake-up Flag 4
1998 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1999 * @retval None
2000 */
LL_PWR_ClearFlag_WU4(void)2001 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
2002 {
2003 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
2004 }
2005
2006 #if defined(PWR_CR3_EWUP3)
2007 /**
2008 * @brief Clear Wake-up Flag 3
2009 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
2010 * @retval None
2011 */
LL_PWR_ClearFlag_WU3(void)2012 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
2013 {
2014 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
2015 }
2016 #endif
2017
2018 #if defined(PWR_CR3_EWUP2)
2019 /**
2020 * @brief Clear Wake-up Flag 2
2021 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
2022 * @retval None
2023 */
LL_PWR_ClearFlag_WU2(void)2024 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
2025 {
2026 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
2027 }
2028 #endif
2029
2030 /**
2031 * @brief Clear Wake-up Flag 1
2032 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
2033 * @retval None
2034 */
LL_PWR_ClearFlag_WU1(void)2035 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
2036 {
2037 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
2038 }
2039
2040
2041 /**
2042 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
2043 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
2044 * @retval State of bit (1 or 0).
2045 */
LL_PWR_IsActiveFlag_PVMO3(void)2046 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
2047 {
2048 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
2049 }
2050
2051 #if defined(PWR_CR2_PVME1)
2052 /**
2053 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
2054 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
2055 * @retval State of bit (1 or 0).
2056 */
LL_PWR_IsActiveFlag_PVMO1(void)2057 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
2058 {
2059 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
2060 }
2061 #endif
2062
2063 /**
2064 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
2065 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
2066 * @retval State of bit (1 or 0).
2067 */
LL_PWR_IsActiveFlag_PVDO(void)2068 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
2069 {
2070 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
2071 }
2072
2073 #if defined(PWR_CR1_VOS)
2074 /**
2075 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
2076 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
2077 * @retval State of bit (1 or 0).
2078 */
LL_PWR_IsActiveFlag_VOS(void)2079 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
2080 {
2081 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
2082 }
2083 #endif
2084
2085 /**
2086 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
2087 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
2088 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
2089 * @retval State of bit (1 or 0).
2090 */
LL_PWR_IsActiveFlag_REGLPF(void)2091 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
2092 {
2093 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
2094 }
2095
2096 /**
2097 * @brief Indicate whether or not the low-power regulator is ready
2098 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
2099 * @retval State of bit (1 or 0).
2100 */
LL_PWR_IsActiveFlag_REGLPS(void)2101 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
2102 {
2103 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
2104 }
2105
2106 /**
2107 * @brief Get BORH interrupt flag
2108 * @rmtoll SR1 BORHF LL_PWR_IsActiveFlag_BORH
2109 * @retval State of bit (1 or 0).
2110 */
LL_PWR_IsActiveFlag_BORH(void)2111 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BORH(void)
2112 {
2113 return ((READ_BIT(PWR->SR1, PWR_SR1_BORHF) == (PWR_SR1_BORHF)) ? 1UL : 0UL);
2114 }
2115
2116 /**
2117 * @brief Clear BORH interrupt flag
2118 * @rmtoll SCR CBORHF LL_PWR_ClearFlag_BORH
2119 * @retval None
2120 */
LL_PWR_ClearFlag_BORH(void)2121 __STATIC_INLINE void LL_PWR_ClearFlag_BORH(void)
2122 {
2123 WRITE_REG(PWR->SCR, PWR_SCR_CBORHF);
2124 }
2125
2126 /**
2127 * @}
2128 */
2129
2130 #if defined(PWR_CR5_SMPSEN)
2131 /** @defgroup PWR_LL_EF_FLAG_Management_SMPS FLAG management for SMPS
2132 * @{
2133 */
2134
2135 /**
2136 * @brief Get SMPS step down converter forced in bypass mode interrupt flag
2137 * @note To activate flag of SMPS step down converter forced in bypass mode
2138 * by BORH, BOR must be preliminarily configured to control SMPS
2139 * operating mode.
2140 * Refer to function @ref LL_PWR_SetBORConfig().
2141 * @rmtoll SR1 SMPSFBF LL_PWR_IsActiveFlag_SMPSFB
2142 * @retval State of bit (1 or 0).
2143 */
LL_PWR_IsActiveFlag_SMPSFB(void)2144 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSFB(void)
2145 {
2146 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSFBF) == (PWR_SR1_SMPSFBF)) ? 1UL : 0UL);
2147 }
2148
2149 /**
2150 * @brief Clear SMPS step down converter forced in bypass mode interrupt flag
2151 * @note To activate flag of SMPS step down converter forced in bypass mode
2152 * by BORH, BOR must be preliminarily configured to control SMPS
2153 * operating mode.
2154 * Refer to function @ref LL_PWR_SetBORConfig().
2155 * @rmtoll SCR CSMPSFBF LL_PWR_ClearFlag_SMPSFB
2156 * @retval None
2157 */
LL_PWR_ClearFlag_SMPSFB(void)2158 __STATIC_INLINE void LL_PWR_ClearFlag_SMPSFB(void)
2159 {
2160 WRITE_REG(PWR->SCR, PWR_SCR_CSMPSFBF);
2161 }
2162
2163 /**
2164 * @}
2165 */
2166 #endif
2167
2168 /** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio (BLE or 802.15.4)
2169 * @{
2170 */
2171
2172 /**
2173 * @brief Get BLE wakeup interrupt flag
2174 * @rmtoll SR1 BLEWUF LL_PWR_IsActiveFlag_BLEWU
2175 * @retval State of bit (1 or 0).
2176 */
LL_PWR_IsActiveFlag_BLEWU(void)2177 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEWU(void)
2178 {
2179 return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL);
2180 }
2181
2182 /**
2183 * @brief Get 802.15.4 wakeup interrupt flag
2184 * @rmtoll SR1 802WUF LL_PWR_IsActiveFlag_802WU
2185 * @retval State of bit (1 or 0).
2186 */
LL_PWR_IsActiveFlag_802WU(void)2187 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU(void)
2188 {
2189 return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL);
2190 }
2191
2192 /**
2193 * @brief Get BLE end of activity interrupt flag
2194 * @rmtoll SR1 BLEAF LL_PWR_IsActiveFlag_BLEA
2195 * @retval State of bit (1 or 0).
2196 */
LL_PWR_IsActiveFlag_BLEA(void)2197 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEA(void)
2198 {
2199 return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL);
2200 }
2201
2202 /**
2203 * @brief Get 802.15.4 end of activity interrupt flag
2204 * @rmtoll SR1 802AF LL_PWR_IsActiveFlag_802A
2205 * @retval State of bit (1 or 0).
2206 */
LL_PWR_IsActiveFlag_802A(void)2207 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A(void)
2208 {
2209 return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL);
2210 }
2211
2212 /**
2213 * @brief Get critical radio phase end of activity interrupt flag
2214 * @rmtoll SR1 CRPEF LL_PWR_IsActiveFlag_CRPE
2215 * @retval State of bit (1 or 0).
2216 */
LL_PWR_IsActiveFlag_CRPE(void)2217 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRPE(void)
2218 {
2219 return ((READ_BIT(PWR->SR1, PWR_SR1_CRPEF) == (PWR_SR1_CRPEF)) ? 1UL : 0UL);
2220 }
2221
2222 /**
2223 * @brief Get critical radio system phase flag
2224 * @rmtoll EXTSCR CRPF LL_PWR_IsActiveFlag_CRP
2225 * @retval State of bit (1 or 0).
2226 */
LL_PWR_IsActiveFlag_CRP(void)2227 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_CRP(void)
2228 {
2229 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_CRPF) == (PWR_EXTSCR_CRPF)) ? 1UL : 0UL);
2230 }
2231
2232 /**
2233 * @brief Clear BLE wakeup interrupt flag
2234 * @rmtoll SCR BLEWU LL_PWR_ClearFlag_BLEWU
2235 * @retval None
2236 */
LL_PWR_ClearFlag_BLEWU(void)2237 __STATIC_INLINE void LL_PWR_ClearFlag_BLEWU(void)
2238 {
2239 WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF);
2240 }
2241
2242 /**
2243 * @brief Clear 802.15.4 wakeup interrupt flag
2244 * @rmtoll SCR 802WU LL_PWR_ClearFlag_802WU
2245 * @retval None
2246 */
LL_PWR_ClearFlag_802WU(void)2247 __STATIC_INLINE void LL_PWR_ClearFlag_802WU(void)
2248 {
2249 WRITE_REG(PWR->SCR, PWR_SCR_C802WUF);
2250 }
2251
2252 /**
2253 * @brief Clear BLE end of activity interrupt flag
2254 * @rmtoll SCR BLEAF LL_PWR_ClearFlag_BLEA
2255 * @retval None
2256 */
LL_PWR_ClearFlag_BLEA(void)2257 __STATIC_INLINE void LL_PWR_ClearFlag_BLEA(void)
2258 {
2259 WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF);
2260 }
2261
2262 /**
2263 * @brief Clear 802.15.4 end of activity interrupt flag
2264 * @rmtoll SCR 802AF LL_PWR_ClearFlag_802A
2265 * @retval None
2266 */
LL_PWR_ClearFlag_802A(void)2267 __STATIC_INLINE void LL_PWR_ClearFlag_802A(void)
2268 {
2269 WRITE_REG(PWR->SCR, PWR_SCR_C802AF);
2270 }
2271
2272 /**
2273 * @brief Clear critical radio phase end of activity interrupt flag
2274 * @rmtoll SCR CCRPEF LL_PWR_ClearFlag_CRPE
2275 * @retval None
2276 */
LL_PWR_ClearFlag_CRPE(void)2277 __STATIC_INLINE void LL_PWR_ClearFlag_CRPE(void)
2278 {
2279 WRITE_REG(PWR->SCR, PWR_SCR_CCRPEF);
2280 }
2281
2282 /**
2283 * @brief Clear critical radio system phase flag
2284 * @rmtoll EXTSCR CCRP LL_PWR_ClearFlag_CRP
2285 * @retval None
2286 */
LL_PWR_ClearFlag_CRP(void)2287 __STATIC_INLINE void LL_PWR_ClearFlag_CRP(void)
2288 {
2289 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_CCRPF);
2290 }
2291
2292 /**
2293 * @}
2294 */
2295
2296 /** @defgroup PWR_LL_EF_FLAG_Management_Multicore FLAG management for multicore
2297 * @{
2298 */
2299
2300 /**
2301 * @brief Get CPU2 hold interrupt flag
2302 * @rmtoll SCR CC2HF LL_PWR_IsActiveFlag_C2H
2303 * @retval State of bit (1 or 0).
2304 */
LL_PWR_IsActiveFlag_C2H(void)2305 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2H(void)
2306 {
2307 return ((READ_BIT(PWR->SR1, PWR_SR1_C2HF) == (PWR_SR1_C2HF)) ? 1UL : 0UL);
2308 }
2309
2310 /**
2311 * @brief Get system stop flag for CPU1
2312 * @rmtoll EXTSCR C1STOPF LL_PWR_IsActiveFlag_C1STOP
2313 * @retval State of bit (1 or 0).
2314 */
LL_PWR_IsActiveFlag_C1STOP(void)2315 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP(void)
2316 {
2317 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOPF) == (PWR_EXTSCR_C1STOPF)) ? 1UL : 0UL);
2318 }
2319
2320 /**
2321 * @brief Get system standby flag for CPU1
2322 * @rmtoll EXTSCR C1SBF LL_PWR_IsActiveFlag_C1SB
2323 * @retval State of bit (1 or 0).
2324 */
LL_PWR_IsActiveFlag_C1SB(void)2325 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1SB(void)
2326 {
2327 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1SBF) == (PWR_EXTSCR_C1SBF)) ? 1UL : 0UL);
2328 }
2329
2330 /**
2331 * @brief Get deepsleep mode for CPU1
2332 * @rmtoll EXTSCR C1DS LL_PWR_IsActiveFlag_C1DS
2333 * @retval State of bit (1 or 0).
2334 */
LL_PWR_IsActiveFlag_C1DS(void)2335 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1DS(void)
2336 {
2337 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1DS) == (PWR_EXTSCR_C1DS)) ? 1UL : 0UL);
2338 }
2339
2340 /**
2341 * @brief System stop flag for CPU2
2342 * @rmtoll EXTSCR C2STOPF LL_PWR_IsActiveFlag_C2STOP
2343 * @retval State of bit (1 or 0).
2344 */
LL_PWR_IsActiveFlag_C2STOP(void)2345 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP(void)
2346 {
2347 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOPF) == (PWR_EXTSCR_C2STOPF)) ? 1UL : 0UL);
2348 }
2349
2350 /**
2351 * @brief System standby flag for CPU2
2352 * @rmtoll EXTSCR C2SBF LL_PWR_IsActiveFlag_C2SB
2353 * @retval State of bit (1 or 0).
2354 */
LL_PWR_IsActiveFlag_C2SB(void)2355 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2SB(void)
2356 {
2357 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2SBF) == (PWR_EXTSCR_C2SBF)) ? 1UL : 0UL);
2358 }
2359
2360 /**
2361 * @brief Get deepsleep mode for CPU2
2362 * @rmtoll EXTSCR C2DS LL_PWR_IsActiveFlag_C2DS
2363 * @retval State of bit (1 or 0).
2364 */
LL_PWR_IsActiveFlag_C2DS(void)2365 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2DS(void)
2366 {
2367 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2DS) == (PWR_EXTSCR_C2DS)) ? 1UL : 0UL);
2368 }
2369
2370 /**
2371 * @brief Clear CPU2 hold interrupt flag
2372 * @rmtoll SCR CC2HF LL_PWR_ClearFlag_C2H
2373 * @retval None
2374 */
LL_PWR_ClearFlag_C2H(void)2375 __STATIC_INLINE void LL_PWR_ClearFlag_C2H(void)
2376 {
2377 WRITE_REG(PWR->SCR, PWR_SCR_CC2HF);
2378 }
2379 /**
2380 * @brief Clear standby and stop flags for CPU1
2381 * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB
2382 * @retval None
2383 */
LL_PWR_ClearFlag_C1STOP_C1STB(void)2384 __STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void)
2385 {
2386 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF);
2387 }
2388
2389 /**
2390 * @brief Clear standby and stop flags for CPU2
2391 * @rmtoll EXTSCR C2CSSF LL_PWR_ClearFlag_C2STOP_C2STB
2392 * @retval None
2393 */
LL_PWR_ClearFlag_C2STOP_C2STB(void)2394 __STATIC_INLINE void LL_PWR_ClearFlag_C2STOP_C2STB(void)
2395 {
2396 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF);
2397 }
2398
2399 /**
2400 * @}
2401 */
2402
2403 #if defined(PWR_CR5_SMPSEN)
2404 /** @defgroup PWR_LL_EF_IT_Management_SMPS PWR IT management for SMPS
2405 * @{
2406 */
2407
2408 /**
2409 * @brief Enable SMPS step down converter forced in bypass mode by BORH
2410 * interrupt for CPU1
2411 * @note To activate flag of SMPS step down converter forced in bypass mode
2412 * by BORH, BOR must be preliminarily configured to control SMPS
2413 * operating mode.
2414 * Refer to function @ref LL_PWR_SetBORConfig().
2415 * @rmtoll CR3 EBORHSMPSFB LL_PWR_EnableIT_BORH_SMPSFB
2416 * @retval None
2417 */
LL_PWR_EnableIT_BORH_SMPSFB(void)2418 __STATIC_INLINE void LL_PWR_EnableIT_BORH_SMPSFB(void)
2419 {
2420 SET_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
2421 }
2422
2423 /**
2424 * @brief Disable SMPS step down converter forced in bypass mode by BORH
2425 * interrupt for CPU1
2426 * @rmtoll CR3 EBORHSMPSFB LL_PWR_DisableIT_BORH_SMPSFB
2427 * @retval None
2428 */
LL_PWR_DisableIT_BORH_SMPSFB(void)2429 __STATIC_INLINE void LL_PWR_DisableIT_BORH_SMPSFB(void)
2430 {
2431 CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
2432 }
2433
2434 /**
2435 * @brief Check if SMPS step down converter forced in bypass mode by BORH
2436 * interrupt is enabled for CPU1
2437 * @rmtoll CR3 EBORHSMPSFB LL_PWR_IsEnabledIT_BORH_SMPSFB
2438 * @retval State of bit (1 or 0).
2439 */
LL_PWR_IsEnabledIT_BORH_SMPSFB(void)2440 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BORH_SMPSFB(void)
2441 {
2442 return ((READ_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB) == (PWR_CR3_EBORHSMPSFB)) ? 1UL : 0UL);
2443 }
2444
2445 /**
2446 * @}
2447 */
2448 #endif
2449
2450 /** @defgroup PWR_LL_EF_IT_Management_Radio PWR IT management for radio (BLE or 802.15.4)
2451 * @{
2452 */
2453
2454 /**
2455 * @brief Enable BLE end of activity interrupt for CPU1
2456 * @rmtoll CR3 EBLEA LL_PWR_EnableIT_BLEA
2457 * @retval None
2458 */
LL_PWR_EnableIT_BLEA(void)2459 __STATIC_INLINE void LL_PWR_EnableIT_BLEA(void)
2460 {
2461 SET_BIT(PWR->CR3, PWR_CR3_EBLEA);
2462 }
2463
2464 /**
2465 * @brief Enable 802.15.4 end of activity interrupt for CPU1
2466 * @rmtoll CR3 E802A LL_PWR_EnableIT_802A
2467 * @retval None
2468 */
LL_PWR_EnableIT_802A(void)2469 __STATIC_INLINE void LL_PWR_EnableIT_802A(void)
2470 {
2471 SET_BIT(PWR->CR3, PWR_CR3_E802A);
2472 }
2473
2474
2475 /**
2476 * @brief Disable BLE end of activity interrupt for CPU1
2477 * @rmtoll CR3 EBLEA LL_PWR_DisableIT_BLEA
2478 * @retval None
2479 */
LL_PWR_DisableIT_BLEA(void)2480 __STATIC_INLINE void LL_PWR_DisableIT_BLEA(void)
2481 {
2482 CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
2483 }
2484
2485 /**
2486 * @brief Disable 802.15.4 end of activity interrupt for CPU1
2487 * @rmtoll CR3 E802A LL_PWR_DisableIT_802A
2488 * @retval None
2489 */
LL_PWR_DisableIT_802A(void)2490 __STATIC_INLINE void LL_PWR_DisableIT_802A(void)
2491 {
2492 CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
2493 }
2494
2495 /**
2496 * @brief Check if BLE end of activity interrupt is enabled for CPU1
2497 * @rmtoll CR3 EBLEA LL_PWR_IsEnabledIT_BLEA
2498 * @retval State of bit (1 or 0).
2499 */
LL_PWR_IsEnabledIT_BLEA(void)2500 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BLEA(void)
2501 {
2502 return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL);
2503 }
2504
2505 /**
2506 * @brief Check if 802.15.4 end of activity interrupt is enabled for CPU1
2507 * @rmtoll CR3 E802A LL_PWR_IsEnabledIT_802A
2508 * @retval State of bit (1 or 0).
2509 */
LL_PWR_IsEnabledIT_802A(void)2510 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A(void)
2511 {
2512 return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL);
2513 }
2514
2515 /**
2516 * @brief Enable critical radio phase end of activity interrupt for CPU1
2517 * @rmtoll CR3 ECRPE LL_PWR_EnableIT_802A
2518 * @retval None
2519 */
LL_PWR_EnableIT_CRPE(void)2520 __STATIC_INLINE void LL_PWR_EnableIT_CRPE(void)
2521 {
2522 SET_BIT(PWR->CR3, PWR_CR3_ECRPE);
2523 }
2524
2525 /**
2526 * @brief Disable critical radio phase end of activity interrupt for CPU1
2527 * @rmtoll CR3 ECRPE LL_PWR_DisableIT_802A
2528 * @retval None
2529 */
LL_PWR_DisableIT_CRPE(void)2530 __STATIC_INLINE void LL_PWR_DisableIT_CRPE(void)
2531 {
2532 CLEAR_BIT(PWR->CR3, PWR_CR3_ECRPE);
2533 }
2534
2535 /**
2536 * @brief Check if critical radio phase end of activity interrupt is enabled for CPU1
2537 * @rmtoll CR3 ECRPE LL_PWR_IsEnabledIT_802A
2538 * @retval State of bit (1 or 0).
2539 */
LL_PWR_IsEnabledIT_CRPE(void)2540 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_CRPE(void)
2541 {
2542 return ((READ_BIT(PWR->CR3, PWR_CR3_ECRPE) == (PWR_CR3_ECRPE)) ? 1UL : 0UL);
2543 }
2544
2545 /**
2546 * @}
2547 */
2548
2549 /** @defgroup PWR_LL_EF_IT_Management_Multicore PWR IT management for multicore
2550 * @{
2551 */
2552
2553 /**
2554 * @brief Enable CPU2 hold interrupt for CPU1
2555 * @rmtoll CR3 EC2H LL_PWR_EnableIT_HoldCPU2
2556 * @retval None
2557 */
LL_PWR_EnableIT_HoldCPU2(void)2558 __STATIC_INLINE void LL_PWR_EnableIT_HoldCPU2(void)
2559 {
2560 SET_BIT(PWR->CR3, PWR_CR3_EC2H);
2561 }
2562
2563 /**
2564 * @brief Disable 802.15.4 host wakeup interrupt for CPU2
2565 * @rmtoll CR3 EC2H LL_PWR_DisableIT_HoldCPU2
2566 * @retval None
2567 */
LL_PWR_DisableIT_HoldCPU2(void)2568 __STATIC_INLINE void LL_PWR_DisableIT_HoldCPU2(void)
2569 {
2570 CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H);
2571 }
2572
2573 /**
2574 * @brief Check if BLE host wakeup interrupt is enabled for CPU2
2575 * @rmtoll CR3 EC2H LL_PWR_IsEnabledIT_HoldCPU2
2576 * @retval State of bit (1 or 0).
2577 */
LL_PWR_IsEnabledIT_HoldCPU2(void)2578 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_HoldCPU2(void)
2579 {
2580 return ((READ_BIT(PWR->CR3, PWR_CR3_EC2H) == (PWR_CR3_EC2H)) ? 1UL : 0UL);
2581 }
2582
2583 /**
2584 * @}
2585 */
2586
2587 /** @defgroup PWR_LL_EF_IT_Management_CPU2 PWR IT management of CPU2, intended to be executed by CPU2
2588 * @{
2589 */
2590
2591 /**
2592 * @brief Enable BLE host wakeup interrupt for CPU2
2593 * @rmtoll C2CR3 EBLEWUP LL_C2_PWR_EnableIT_BLEWU
2594 * @retval None
2595 */
LL_C2_PWR_EnableIT_BLEWU(void)2596 __STATIC_INLINE void LL_C2_PWR_EnableIT_BLEWU(void)
2597 {
2598 SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
2599 }
2600
2601 /**
2602 * @brief Enable 802.15.4 host wakeup interrupt for CPU2
2603 * @rmtoll C2CR3 E802WUP LL_C2_PWR_EnableIT_802WU
2604 * @retval None
2605 */
LL_C2_PWR_EnableIT_802WU(void)2606 __STATIC_INLINE void LL_C2_PWR_EnableIT_802WU(void)
2607 {
2608 SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
2609 }
2610
2611 /**
2612 * @brief Disable BLE host wakeup interrupt for CPU2
2613 * @rmtoll C2CR3 EBLEWUP LL_C2_PWR_DisableIT_BLEWU
2614 * @retval None
2615 */
LL_C2_PWR_DisableIT_BLEWU(void)2616 __STATIC_INLINE void LL_C2_PWR_DisableIT_BLEWU(void)
2617 {
2618 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
2619 }
2620
2621 /**
2622 * @brief Disable 802.15.4 host wakeup interrupt for CPU2
2623 * @rmtoll C2CR3 E802WUP LL_C2_PWR_DisableIT_802WU
2624 * @retval None
2625 */
LL_C2_PWR_DisableIT_802WU(void)2626 __STATIC_INLINE void LL_C2_PWR_DisableIT_802WU(void)
2627 {
2628 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
2629 }
2630
2631 /**
2632 * @brief Check if BLE host wakeup interrupt is enabled for CPU2
2633 * @rmtoll C2CR3 EBLEWUP LL_C2_PWR_IsEnabledIT_BLEWU
2634 * @retval State of bit (1 or 0).
2635 */
LL_C2_PWR_IsEnabledIT_BLEWU(void)2636 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_BLEWU(void)
2637 {
2638 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL);
2639 }
2640
2641 /**
2642 * @brief Check if 802.15.4 host wakeup interrupt is enabled for CPU2
2643 * @rmtoll C2CR3 E802WUP LL_C2_PWR_IsEnabledIT_802WU
2644 * @retval State of bit (1 or 0).
2645 */
LL_C2_PWR_IsEnabledIT_802WU(void)2646 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU(void)
2647 {
2648 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL);
2649 }
2650
2651 /**
2652 * @}
2653 */
2654
2655 #if defined(USE_FULL_LL_DRIVER)
2656 /** @defgroup PWR_LL_EF_Init De-initialization function
2657 * @{
2658 */
2659 ErrorStatus LL_PWR_DeInit(void);
2660 /**
2661 * @}
2662 */
2663 #endif /* USE_FULL_LL_DRIVER */
2664
2665 /**
2666 * @}
2667 */
2668
2669 /**
2670 * @}
2671 */
2672
2673 #endif /* defined(PWR) */
2674
2675 /**
2676 * @}
2677 */
2678
2679 #ifdef __cplusplus
2680 }
2681 #endif
2682
2683 #endif /* STM32WBxx_LL_PWR_H */
2684
2685 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2686