1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32WBxx_LL_DMA_H
22 #define STM32WBxx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32wbxx.h"
30 #include "stm32wbxx_ll_dmamux.h"
31
32 /** @addtogroup STM32WBxx_LL_Driver
33 * @{
34 */
35
36 #if defined (DMA1) || defined (DMA2)
37
38 /** @defgroup DMA_LL DMA
39 * @{
40 */
41
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /* Private constants ---------------------------------------------------------*/
45 /* Private macros ------------------------------------------------------------*/
46 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
47 * @{
48 */
49
50 /**
51 * @brief Helper macro to convert DMA Instance and index into DMA channel
52 * @param __DMA_INSTANCE__ DMAx
53 * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
54 * @retval Pointer to the DMA channel
55 */
56 #if defined (DMA2)
57 #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \
58 (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__)))
59 #else
60 #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \
61 (DMA1_Channel1 + (__CHANNEL_INDEX__))
62 #endif
63
64 /**
65 * @brief Helper macro to convert DMA Instance and index into DMAMUX channel
66 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
67 #if defined (DMA2)
68 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
69 #endif
70 * @param __DMA_INSTANCE__ DMAx
71 * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
72 * @retval Pointer to the DMA channel
73 */
74 #if defined (DMA2)
75 #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
76 (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__)))
77 #else
78 #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
79 (DMAMUX1_Channel0 + (__CHANNEL_INDEX__))
80 #endif
81 /**
82 * @}
83 */
84
85 /* Exported types ------------------------------------------------------------*/
86 #if defined(USE_FULL_LL_DRIVER)
87 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
88 * @{
89 */
90 typedef struct
91 {
92 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
93 or as Source base address in case of memory to memory transfer direction.
94
95 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
96
97 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
98 or as Destination base address in case of memory to memory transfer direction.
99
100 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
101
102 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
103 from memory to memory or from peripheral to memory.
104 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
105
106 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
107
108 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
109 This parameter can be a value of @ref DMA_LL_EC_MODE
110 @note: The circular buffer mode cannot be used if the memory to memory
111 data transfer direction is configured on the selected Channel
112
113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
114
115 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
116 is incremented or not.
117 This parameter can be a value of @ref DMA_LL_EC_PERIPH
118
119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
120
121 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
122 is incremented or not.
123 This parameter can be a value of @ref DMA_LL_EC_MEMORY
124
125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
126
127 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
128 in case of memory to memory transfer direction.
129 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
132
133 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
134 in case of memory to memory transfer direction.
135 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
136
137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
138
139 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
140 The data unit is equal to the source buffer configuration set in PeripheralSize
141 or MemorySize parameters depending in the transfer direction.
142 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
143
144 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
145
146 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
147 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
148
149 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
150
151 uint32_t Priority; /*!< Specifies the channel priority level.
152 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
153
154 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
155
156 } LL_DMA_InitTypeDef;
157 /**
158 * @}
159 */
160 #endif /*USE_FULL_LL_DRIVER*/
161
162 /* Exported constants --------------------------------------------------------*/
163 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
164 * @{
165 */
166 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
167 * @brief Flags defines which can be used with LL_DMA_WriteReg function
168 * @{
169 */
170 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
171 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
172 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
173 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
174 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
175 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
176 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
177 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
178 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
179 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
180 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
181 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
182 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
183 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
184 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
185 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
186 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
187 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
188 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
189 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
190 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
191 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
192 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
193 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
194 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
195 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
196 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
197 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
198 /**
199 * @}
200 */
201
202 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
203 * @brief Flags defines which can be used with LL_DMA_ReadReg function
204 * @{
205 */
206 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
207 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
208 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
209 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
210 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
211 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
212 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
213 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
214 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
215 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
216 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
217 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
218 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
219 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
220 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
221 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
222 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
223 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
224 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
225 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
226 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
227 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
228 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
229 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
230 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
231 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
232 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
233 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
234 /**
235 * @}
236 */
237
238 /** @defgroup DMA_LL_EC_IT IT Defines
239 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
240 * @{
241 */
242 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
243 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
244 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
245 /**
246 * @}
247 */
248
249 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
250 * @{
251 */
252 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
253 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
254 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
255 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
256 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
257 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
258 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
259 #if defined(USE_FULL_LL_DRIVER)
260 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
261 #endif /*USE_FULL_LL_DRIVER*/
262 /**
263 * @}
264 */
265
266 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
267 * @{
268 */
269 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
270 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
271 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
272 /**
273 * @}
274 */
275
276 /** @defgroup DMA_LL_EC_MODE Transfer mode
277 * @{
278 */
279 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
280 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
281 /**
282 * @}
283 */
284
285 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
286 * @{
287 */
288 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
289 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
290 /**
291 * @}
292 */
293
294 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
295 * @{
296 */
297 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
298 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
299 /**
300 * @}
301 */
302
303 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
304 * @{
305 */
306 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
307 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
308 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
309 /**
310 * @}
311 */
312
313 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
314 * @{
315 */
316 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
317 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
318 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
319 /**
320 * @}
321 */
322
323 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
324 * @{
325 */
326 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
327 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
328 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
329 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
330 /**
331 * @}
332 */
333
334 /**
335 * @}
336 */
337
338 /* Exported macro ------------------------------------------------------------*/
339 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
340 * @{
341 */
342
343 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
344 * @{
345 */
346 /**
347 * @brief Write a value in DMA register
348 * @param __INSTANCE__ DMA Instance
349 * @param __REG__ Register to be written
350 * @param __VALUE__ Value to be written in the register
351 * @retval None
352 */
353 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
354
355 /**
356 * @brief Read a value in DMA register
357 * @param __INSTANCE__ DMA Instance
358 * @param __REG__ Register to be read
359 * @retval Register value
360 */
361 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
362 /**
363 * @}
364 */
365
366 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
367 * @{
368 */
369 /**
370 * @brief Convert DMAx_Channely into DMAx
371 * @param __CHANNEL_INSTANCE__ DMAx_Channely
372 * @retval DMAx
373 */
374 #if defined(DMA2)
375 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
376 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
377 #else
378 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
379 #endif
380
381 /**
382 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
383 * @param __CHANNEL_INSTANCE__ DMAx_Channely
384 * @retval LL_DMA_CHANNEL_y
385 */
386 #if defined (DMA2)
387 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
388 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
389 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
400 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
401 LL_DMA_CHANNEL_7)
402 #else
403 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
404 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
413 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
414 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
415 LL_DMA_CHANNEL_7)
416 #endif
417 #else
418 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
419 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
425 LL_DMA_CHANNEL_7)
426 #endif
427
428 /**
429 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
430 * @param __DMA_INSTANCE__ DMAx
431 * @param __CHANNEL__ LL_DMA_CHANNEL_y
432 * @retval DMAx_Channely
433 */
434 #if defined (DMA2)
435 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
436 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
437 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
450 DMA2_Channel7)
451 #else
452 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
453 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
464 DMA1_Channel7)
465 #endif
466 #else
467 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
468 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
474 DMA1_Channel7)
475 #endif
476
477 /**
478 * @}
479 */
480
481 /**
482 * @}
483 */
484
485 /* Exported functions --------------------------------------------------------*/
486 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
487 * @{
488 */
489
490 /** @defgroup DMA_LL_EF_Configuration Configuration
491 * @{
492 */
493 /**
494 * @brief Enable DMA channel.
495 * @rmtoll CCR EN LL_DMA_EnableChannel
496 * @param DMAx DMAx Instance
497 * @param Channel This parameter can be one of the following values:
498 * @arg @ref LL_DMA_CHANNEL_1
499 * @arg @ref LL_DMA_CHANNEL_2
500 * @arg @ref LL_DMA_CHANNEL_3
501 * @arg @ref LL_DMA_CHANNEL_4
502 * @arg @ref LL_DMA_CHANNEL_5
503 * @arg @ref LL_DMA_CHANNEL_6
504 * @arg @ref LL_DMA_CHANNEL_7
505 * @retval None
506 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)507 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
508 {
509 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
510 }
511
512 /**
513 * @brief Disable DMA channel.
514 * @rmtoll CCR EN LL_DMA_DisableChannel
515 * @param DMAx DMAx Instance
516 * @param Channel This parameter can be one of the following values:
517 * @arg @ref LL_DMA_CHANNEL_1
518 * @arg @ref LL_DMA_CHANNEL_2
519 * @arg @ref LL_DMA_CHANNEL_3
520 * @arg @ref LL_DMA_CHANNEL_4
521 * @arg @ref LL_DMA_CHANNEL_5
522 * @arg @ref LL_DMA_CHANNEL_6
523 * @arg @ref LL_DMA_CHANNEL_7
524 * @retval None
525 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)526 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
527 {
528 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
529 }
530
531 /**
532 * @brief Check if DMA channel is enabled or disabled.
533 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
534 * @param DMAx DMAx Instance
535 * @param Channel This parameter can be one of the following values:
536 * @arg @ref LL_DMA_CHANNEL_1
537 * @arg @ref LL_DMA_CHANNEL_2
538 * @arg @ref LL_DMA_CHANNEL_3
539 * @arg @ref LL_DMA_CHANNEL_4
540 * @arg @ref LL_DMA_CHANNEL_5
541 * @arg @ref LL_DMA_CHANNEL_6
542 * @arg @ref LL_DMA_CHANNEL_7
543 * @retval State of bit (1 or 0).
544 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)545 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
546 {
547 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
548 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
549 }
550
551 /**
552 * @brief Configure all parameters link to DMA transfer.
553 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
554 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
555 * CCR CIRC LL_DMA_ConfigTransfer\n
556 * CCR PINC LL_DMA_ConfigTransfer\n
557 * CCR MINC LL_DMA_ConfigTransfer\n
558 * CCR PSIZE LL_DMA_ConfigTransfer\n
559 * CCR MSIZE LL_DMA_ConfigTransfer\n
560 * CCR PL LL_DMA_ConfigTransfer
561 * @param DMAx DMAx Instance
562 * @param Channel This parameter can be one of the following values:
563 * @arg @ref LL_DMA_CHANNEL_1
564 * @arg @ref LL_DMA_CHANNEL_2
565 * @arg @ref LL_DMA_CHANNEL_3
566 * @arg @ref LL_DMA_CHANNEL_4
567 * @arg @ref LL_DMA_CHANNEL_5
568 * @arg @ref LL_DMA_CHANNEL_6
569 * @arg @ref LL_DMA_CHANNEL_7
570 * @param Configuration This parameter must be a combination of all the following values:
571 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
572 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
573 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
574 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
575 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
576 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
577 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
578 * @retval None
579 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)580 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
581 {
582 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
583 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
584 Configuration);
585 }
586
587 /**
588 * @brief Set Data transfer direction (read from peripheral or from memory).
589 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
590 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
591 * @param DMAx DMAx Instance
592 * @param Channel This parameter can be one of the following values:
593 * @arg @ref LL_DMA_CHANNEL_1
594 * @arg @ref LL_DMA_CHANNEL_2
595 * @arg @ref LL_DMA_CHANNEL_3
596 * @arg @ref LL_DMA_CHANNEL_4
597 * @arg @ref LL_DMA_CHANNEL_5
598 * @arg @ref LL_DMA_CHANNEL_6
599 * @arg @ref LL_DMA_CHANNEL_7
600 * @param Direction This parameter can be one of the following values:
601 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
602 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
603 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
604 * @retval None
605 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)606 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
607 {
608 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
609 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
610 }
611
612 /**
613 * @brief Get Data transfer direction (read from peripheral or from memory).
614 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
615 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
616 * @param DMAx DMAx Instance
617 * @param Channel This parameter can be one of the following values:
618 * @arg @ref LL_DMA_CHANNEL_1
619 * @arg @ref LL_DMA_CHANNEL_2
620 * @arg @ref LL_DMA_CHANNEL_3
621 * @arg @ref LL_DMA_CHANNEL_4
622 * @arg @ref LL_DMA_CHANNEL_5
623 * @arg @ref LL_DMA_CHANNEL_6
624 * @arg @ref LL_DMA_CHANNEL_7
625 * @retval Returned value can be one of the following values:
626 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
627 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
628 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
629 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)630 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
631 {
632 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
633 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
634 }
635
636 /**
637 * @brief Set DMA mode circular or normal.
638 * @note The circular buffer mode cannot be used if the memory-to-memory
639 * data transfer is configured on the selected Channel.
640 * @rmtoll CCR CIRC LL_DMA_SetMode
641 * @param DMAx DMAx Instance
642 * @param Channel This parameter can be one of the following values:
643 * @arg @ref LL_DMA_CHANNEL_1
644 * @arg @ref LL_DMA_CHANNEL_2
645 * @arg @ref LL_DMA_CHANNEL_3
646 * @arg @ref LL_DMA_CHANNEL_4
647 * @arg @ref LL_DMA_CHANNEL_5
648 * @arg @ref LL_DMA_CHANNEL_6
649 * @arg @ref LL_DMA_CHANNEL_7
650 * @param Mode This parameter can be one of the following values:
651 * @arg @ref LL_DMA_MODE_NORMAL
652 * @arg @ref LL_DMA_MODE_CIRCULAR
653 * @retval None
654 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)655 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
656 {
657 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC,
658 Mode);
659 }
660
661 /**
662 * @brief Get DMA mode circular or normal.
663 * @rmtoll CCR CIRC LL_DMA_GetMode
664 * @param DMAx DMAx Instance
665 * @param Channel This parameter can be one of the following values:
666 * @arg @ref LL_DMA_CHANNEL_1
667 * @arg @ref LL_DMA_CHANNEL_2
668 * @arg @ref LL_DMA_CHANNEL_3
669 * @arg @ref LL_DMA_CHANNEL_4
670 * @arg @ref LL_DMA_CHANNEL_5
671 * @arg @ref LL_DMA_CHANNEL_6
672 * @arg @ref LL_DMA_CHANNEL_7
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_DMA_MODE_NORMAL
675 * @arg @ref LL_DMA_MODE_CIRCULAR
676 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)677 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
678 {
679 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
680 DMA_CCR_CIRC));
681 }
682
683 /**
684 * @brief Set Peripheral increment mode.
685 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
686 * @param DMAx DMAx Instance
687 * @param Channel This parameter can be one of the following values:
688 * @arg @ref LL_DMA_CHANNEL_1
689 * @arg @ref LL_DMA_CHANNEL_2
690 * @arg @ref LL_DMA_CHANNEL_3
691 * @arg @ref LL_DMA_CHANNEL_4
692 * @arg @ref LL_DMA_CHANNEL_5
693 * @arg @ref LL_DMA_CHANNEL_6
694 * @arg @ref LL_DMA_CHANNEL_7
695 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
696 * @arg @ref LL_DMA_PERIPH_INCREMENT
697 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
698 * @retval None
699 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)700 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
701 {
702 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC,
703 PeriphOrM2MSrcIncMode);
704 }
705
706 /**
707 * @brief Get Peripheral increment mode.
708 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
709 * @param DMAx DMAx Instance
710 * @param Channel This parameter can be one of the following values:
711 * @arg @ref LL_DMA_CHANNEL_1
712 * @arg @ref LL_DMA_CHANNEL_2
713 * @arg @ref LL_DMA_CHANNEL_3
714 * @arg @ref LL_DMA_CHANNEL_4
715 * @arg @ref LL_DMA_CHANNEL_5
716 * @arg @ref LL_DMA_CHANNEL_6
717 * @arg @ref LL_DMA_CHANNEL_7
718 * @retval Returned value can be one of the following values:
719 * @arg @ref LL_DMA_PERIPH_INCREMENT
720 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
721 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)722 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
723 {
724 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
725 DMA_CCR_PINC));
726 }
727
728 /**
729 * @brief Set Memory increment mode.
730 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
731 * @param DMAx DMAx Instance
732 * @param Channel This parameter can be one of the following values:
733 * @arg @ref LL_DMA_CHANNEL_1
734 * @arg @ref LL_DMA_CHANNEL_2
735 * @arg @ref LL_DMA_CHANNEL_3
736 * @arg @ref LL_DMA_CHANNEL_4
737 * @arg @ref LL_DMA_CHANNEL_5
738 * @arg @ref LL_DMA_CHANNEL_6
739 * @arg @ref LL_DMA_CHANNEL_7
740 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
741 * @arg @ref LL_DMA_MEMORY_INCREMENT
742 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
743 * @retval None
744 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)745 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
746 {
747 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC,
748 MemoryOrM2MDstIncMode);
749 }
750
751 /**
752 * @brief Get Memory increment mode.
753 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
754 * @param DMAx DMAx Instance
755 * @param Channel This parameter can be one of the following values:
756 * @arg @ref LL_DMA_CHANNEL_1
757 * @arg @ref LL_DMA_CHANNEL_2
758 * @arg @ref LL_DMA_CHANNEL_3
759 * @arg @ref LL_DMA_CHANNEL_4
760 * @arg @ref LL_DMA_CHANNEL_5
761 * @arg @ref LL_DMA_CHANNEL_6
762 * @arg @ref LL_DMA_CHANNEL_7
763 * @retval Returned value can be one of the following values:
764 * @arg @ref LL_DMA_MEMORY_INCREMENT
765 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
766 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)767 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
768 {
769 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
770 DMA_CCR_MINC));
771 }
772
773 /**
774 * @brief Set Peripheral size.
775 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
776 * @param DMAx DMAx Instance
777 * @param Channel This parameter can be one of the following values:
778 * @arg @ref LL_DMA_CHANNEL_1
779 * @arg @ref LL_DMA_CHANNEL_2
780 * @arg @ref LL_DMA_CHANNEL_3
781 * @arg @ref LL_DMA_CHANNEL_4
782 * @arg @ref LL_DMA_CHANNEL_5
783 * @arg @ref LL_DMA_CHANNEL_6
784 * @arg @ref LL_DMA_CHANNEL_7
785 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
786 * @arg @ref LL_DMA_PDATAALIGN_BYTE
787 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
788 * @arg @ref LL_DMA_PDATAALIGN_WORD
789 * @retval None
790 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)791 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
792 {
793 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE,
794 PeriphOrM2MSrcDataSize);
795 }
796
797 /**
798 * @brief Get Peripheral size.
799 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
800 * @param DMAx DMAx Instance
801 * @param Channel This parameter can be one of the following values:
802 * @arg @ref LL_DMA_CHANNEL_1
803 * @arg @ref LL_DMA_CHANNEL_2
804 * @arg @ref LL_DMA_CHANNEL_3
805 * @arg @ref LL_DMA_CHANNEL_4
806 * @arg @ref LL_DMA_CHANNEL_5
807 * @arg @ref LL_DMA_CHANNEL_6
808 * @arg @ref LL_DMA_CHANNEL_7
809 * @retval Returned value can be one of the following values:
810 * @arg @ref LL_DMA_PDATAALIGN_BYTE
811 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
812 * @arg @ref LL_DMA_PDATAALIGN_WORD
813 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)814 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
815 {
816 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
817 DMA_CCR_PSIZE));
818 }
819
820 /**
821 * @brief Set Memory size.
822 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
823 * @param DMAx DMAx Instance
824 * @param Channel This parameter can be one of the following values:
825 * @arg @ref LL_DMA_CHANNEL_1
826 * @arg @ref LL_DMA_CHANNEL_2
827 * @arg @ref LL_DMA_CHANNEL_3
828 * @arg @ref LL_DMA_CHANNEL_4
829 * @arg @ref LL_DMA_CHANNEL_5
830 * @arg @ref LL_DMA_CHANNEL_6
831 * @arg @ref LL_DMA_CHANNEL_7
832 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
833 * @arg @ref LL_DMA_MDATAALIGN_BYTE
834 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
835 * @arg @ref LL_DMA_MDATAALIGN_WORD
836 * @retval None
837 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)838 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
839 {
840 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE,
841 MemoryOrM2MDstDataSize);
842 }
843
844 /**
845 * @brief Get Memory size.
846 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
847 * @param DMAx DMAx Instance
848 * @param Channel This parameter can be one of the following values:
849 * @arg @ref LL_DMA_CHANNEL_1
850 * @arg @ref LL_DMA_CHANNEL_2
851 * @arg @ref LL_DMA_CHANNEL_3
852 * @arg @ref LL_DMA_CHANNEL_4
853 * @arg @ref LL_DMA_CHANNEL_5
854 * @arg @ref LL_DMA_CHANNEL_6
855 * @arg @ref LL_DMA_CHANNEL_7
856 * @retval Returned value can be one of the following values:
857 * @arg @ref LL_DMA_MDATAALIGN_BYTE
858 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
859 * @arg @ref LL_DMA_MDATAALIGN_WORD
860 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)861 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
862 {
863 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
864 DMA_CCR_MSIZE));
865 }
866
867 /**
868 * @brief Set Channel priority level.
869 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
870 * @param DMAx DMAx Instance
871 * @param Channel This parameter can be one of the following values:
872 * @arg @ref LL_DMA_CHANNEL_1
873 * @arg @ref LL_DMA_CHANNEL_2
874 * @arg @ref LL_DMA_CHANNEL_3
875 * @arg @ref LL_DMA_CHANNEL_4
876 * @arg @ref LL_DMA_CHANNEL_5
877 * @arg @ref LL_DMA_CHANNEL_6
878 * @arg @ref LL_DMA_CHANNEL_7
879 * @param Priority This parameter can be one of the following values:
880 * @arg @ref LL_DMA_PRIORITY_LOW
881 * @arg @ref LL_DMA_PRIORITY_MEDIUM
882 * @arg @ref LL_DMA_PRIORITY_HIGH
883 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
884 * @retval None
885 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)886 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
887 {
888 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL,
889 Priority);
890 }
891
892 /**
893 * @brief Get Channel priority level.
894 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
895 * @param DMAx DMAx Instance
896 * @param Channel This parameter can be one of the following values:
897 * @arg @ref LL_DMA_CHANNEL_1
898 * @arg @ref LL_DMA_CHANNEL_2
899 * @arg @ref LL_DMA_CHANNEL_3
900 * @arg @ref LL_DMA_CHANNEL_4
901 * @arg @ref LL_DMA_CHANNEL_5
902 * @arg @ref LL_DMA_CHANNEL_6
903 * @arg @ref LL_DMA_CHANNEL_7
904 * @retval Returned value can be one of the following values:
905 * @arg @ref LL_DMA_PRIORITY_LOW
906 * @arg @ref LL_DMA_PRIORITY_MEDIUM
907 * @arg @ref LL_DMA_PRIORITY_HIGH
908 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
909 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)910 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
911 {
912 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
913 DMA_CCR_PL));
914 }
915
916 /**
917 * @brief Set Number of data to transfer.
918 * @note This action has no effect if
919 * channel is enabled.
920 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
921 * @param DMAx DMAx Instance
922 * @param Channel This parameter can be one of the following values:
923 * @arg @ref LL_DMA_CHANNEL_1
924 * @arg @ref LL_DMA_CHANNEL_2
925 * @arg @ref LL_DMA_CHANNEL_3
926 * @arg @ref LL_DMA_CHANNEL_4
927 * @arg @ref LL_DMA_CHANNEL_5
928 * @arg @ref LL_DMA_CHANNEL_6
929 * @arg @ref LL_DMA_CHANNEL_7
930 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
931 * @retval None
932 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)933 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
934 {
935 MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
936 DMA_CNDTR_NDT, NbData);
937 }
938
939 /**
940 * @brief Get Number of data to transfer.
941 * @note Once the channel is enabled, the return value indicate the
942 * remaining bytes to be transmitted.
943 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
944 * @param DMAx DMAx Instance
945 * @param Channel This parameter can be one of the following values:
946 * @arg @ref LL_DMA_CHANNEL_1
947 * @arg @ref LL_DMA_CHANNEL_2
948 * @arg @ref LL_DMA_CHANNEL_3
949 * @arg @ref LL_DMA_CHANNEL_4
950 * @arg @ref LL_DMA_CHANNEL_5
951 * @arg @ref LL_DMA_CHANNEL_6
952 * @arg @ref LL_DMA_CHANNEL_7
953 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
954 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)955 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
956 {
957 return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
958 DMA_CNDTR_NDT));
959 }
960
961 /**
962 * @brief Configure the Source and Destination addresses.
963 * @note This API must not be called when the DMA channel is enabled.
964 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
965 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
966 * CMAR MA LL_DMA_ConfigAddresses
967 * @param DMAx DMAx Instance
968 * @param Channel This parameter can be one of the following values:
969 * @arg @ref LL_DMA_CHANNEL_1
970 * @arg @ref LL_DMA_CHANNEL_2
971 * @arg @ref LL_DMA_CHANNEL_3
972 * @arg @ref LL_DMA_CHANNEL_4
973 * @arg @ref LL_DMA_CHANNEL_5
974 * @arg @ref LL_DMA_CHANNEL_6
975 * @arg @ref LL_DMA_CHANNEL_7
976 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
977 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
978 * @param Direction This parameter can be one of the following values:
979 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
980 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
981 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
982 * @retval None
983 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)984 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
985 uint32_t DstAddress, uint32_t Direction)
986 {
987 /* Direction Memory to Periph */
988 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
989 {
990 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, SrcAddress);
991 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, DstAddress);
992 }
993 /* Direction Periph to Memory and Memory to Memory */
994 else
995 {
996 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, SrcAddress);
997 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, DstAddress);
998 }
999 }
1000
1001 /**
1002 * @brief Set the Memory address.
1003 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1004 * @note This API must not be called when the DMA channel is enabled.
1005 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1006 * @param DMAx DMAx Instance
1007 * @param Channel This parameter can be one of the following values:
1008 * @arg @ref LL_DMA_CHANNEL_1
1009 * @arg @ref LL_DMA_CHANNEL_2
1010 * @arg @ref LL_DMA_CHANNEL_3
1011 * @arg @ref LL_DMA_CHANNEL_4
1012 * @arg @ref LL_DMA_CHANNEL_5
1013 * @arg @ref LL_DMA_CHANNEL_6
1014 * @arg @ref LL_DMA_CHANNEL_7
1015 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1016 * @retval None
1017 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1018 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1019 {
1020 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
1021 }
1022
1023 /**
1024 * @brief Set the Peripheral address.
1025 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1026 * @note This API must not be called when the DMA channel is enabled.
1027 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1028 * @param DMAx DMAx Instance
1029 * @param Channel This parameter can be one of the following values:
1030 * @arg @ref LL_DMA_CHANNEL_1
1031 * @arg @ref LL_DMA_CHANNEL_2
1032 * @arg @ref LL_DMA_CHANNEL_3
1033 * @arg @ref LL_DMA_CHANNEL_4
1034 * @arg @ref LL_DMA_CHANNEL_5
1035 * @arg @ref LL_DMA_CHANNEL_6
1036 * @arg @ref LL_DMA_CHANNEL_7
1037 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1038 * @retval None
1039 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1040 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1041 {
1042 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress);
1043 }
1044
1045 /**
1046 * @brief Get Memory address.
1047 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1048 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1049 * @param DMAx DMAx Instance
1050 * @param Channel This parameter can be one of the following values:
1051 * @arg @ref LL_DMA_CHANNEL_1
1052 * @arg @ref LL_DMA_CHANNEL_2
1053 * @arg @ref LL_DMA_CHANNEL_3
1054 * @arg @ref LL_DMA_CHANNEL_4
1055 * @arg @ref LL_DMA_CHANNEL_5
1056 * @arg @ref LL_DMA_CHANNEL_6
1057 * @arg @ref LL_DMA_CHANNEL_7
1058 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1059 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1060 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1061 {
1062 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
1063 }
1064
1065 /**
1066 * @brief Get Peripheral address.
1067 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1068 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1069 * @param DMAx DMAx Instance
1070 * @param Channel This parameter can be one of the following values:
1071 * @arg @ref LL_DMA_CHANNEL_1
1072 * @arg @ref LL_DMA_CHANNEL_2
1073 * @arg @ref LL_DMA_CHANNEL_3
1074 * @arg @ref LL_DMA_CHANNEL_4
1075 * @arg @ref LL_DMA_CHANNEL_5
1076 * @arg @ref LL_DMA_CHANNEL_6
1077 * @arg @ref LL_DMA_CHANNEL_7
1078 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1079 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1080 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1081 {
1082 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
1083 }
1084
1085 /**
1086 * @brief Set the Memory to Memory Source address.
1087 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1088 * @note This API must not be called when the DMA channel is enabled.
1089 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1090 * @param DMAx DMAx Instance
1091 * @param Channel This parameter can be one of the following values:
1092 * @arg @ref LL_DMA_CHANNEL_1
1093 * @arg @ref LL_DMA_CHANNEL_2
1094 * @arg @ref LL_DMA_CHANNEL_3
1095 * @arg @ref LL_DMA_CHANNEL_4
1096 * @arg @ref LL_DMA_CHANNEL_5
1097 * @arg @ref LL_DMA_CHANNEL_6
1098 * @arg @ref LL_DMA_CHANNEL_7
1099 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1100 * @retval None
1101 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1102 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1103 {
1104 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress);
1105 }
1106
1107 /**
1108 * @brief Set the Memory to Memory Destination address.
1109 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1110 * @note This API must not be called when the DMA channel is enabled.
1111 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1112 * @param DMAx DMAx Instance
1113 * @param Channel This parameter can be one of the following values:
1114 * @arg @ref LL_DMA_CHANNEL_1
1115 * @arg @ref LL_DMA_CHANNEL_2
1116 * @arg @ref LL_DMA_CHANNEL_3
1117 * @arg @ref LL_DMA_CHANNEL_4
1118 * @arg @ref LL_DMA_CHANNEL_5
1119 * @arg @ref LL_DMA_CHANNEL_6
1120 * @arg @ref LL_DMA_CHANNEL_7
1121 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1122 * @retval None
1123 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1124 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1125 {
1126 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
1127 }
1128
1129 /**
1130 * @brief Get the Memory to Memory Source address.
1131 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1132 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1133 * @param DMAx DMAx Instance
1134 * @param Channel This parameter can be one of the following values:
1135 * @arg @ref LL_DMA_CHANNEL_1
1136 * @arg @ref LL_DMA_CHANNEL_2
1137 * @arg @ref LL_DMA_CHANNEL_3
1138 * @arg @ref LL_DMA_CHANNEL_4
1139 * @arg @ref LL_DMA_CHANNEL_5
1140 * @arg @ref LL_DMA_CHANNEL_6
1141 * @arg @ref LL_DMA_CHANNEL_7
1142 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1143 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1144 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1145 {
1146 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
1147 }
1148
1149 /**
1150 * @brief Get the Memory to Memory Destination address.
1151 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1152 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1153 * @param DMAx DMAx Instance
1154 * @param Channel This parameter can be one of the following values:
1155 * @arg @ref LL_DMA_CHANNEL_1
1156 * @arg @ref LL_DMA_CHANNEL_2
1157 * @arg @ref LL_DMA_CHANNEL_3
1158 * @arg @ref LL_DMA_CHANNEL_4
1159 * @arg @ref LL_DMA_CHANNEL_5
1160 * @arg @ref LL_DMA_CHANNEL_6
1161 * @arg @ref LL_DMA_CHANNEL_7
1162 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1163 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1164 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1165 {
1166 return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
1167 }
1168
1169 /**
1170 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1171 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1172 #if defined(DMA2)
1173 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1174 #endif
1175 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1176 * @param DMAx DMAx Instance
1177 * @param Channel This parameter can be one of the following values:
1178 * @arg @ref LL_DMA_CHANNEL_1
1179 * @arg @ref LL_DMA_CHANNEL_2
1180 * @arg @ref LL_DMA_CHANNEL_3
1181 * @arg @ref LL_DMA_CHANNEL_4
1182 * @arg @ref LL_DMA_CHANNEL_5
1183 * @arg @ref LL_DMA_CHANNEL_6
1184 * @arg @ref LL_DMA_CHANNEL_7
1185 * @param Request This parameter can be one of the following values:
1186 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1187 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1188 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1189 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1190 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1191 * @arg @ref LL_DMAMUX_REQ_ADC1
1192 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1193 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1194 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1195 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1196 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1197 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1198 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1199 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1200 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1201 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1202 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1203 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1204 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1205 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1206 * @arg @ref LL_DMAMUX_REQ_QUADSPI
1207 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1208 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1209 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1210 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1211 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1212 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1213 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1214 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1215 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1216 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1217 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1218 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1219 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1220 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1221 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1222 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1223 * @arg @ref LL_DMAMUX_REQ_AES1_IN
1224 * @arg @ref LL_DMAMUX_REQ_AES1_OUT
1225 * @arg @ref LL_DMAMUX_REQ_AES2_IN
1226 * @arg @ref LL_DMAMUX_REQ_AES2_OUT
1227 * @retval None
1228 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1229 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1230 {
1231 MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1232 }
1233
1234 /**
1235 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1236 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1237 #if defined(DMA2)
1238 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1239 #endif
1240 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1241 * @param DMAx DMAx Instance
1242 * @param Channel This parameter can be one of the following values:
1243 * @arg @ref LL_DMA_CHANNEL_1
1244 * @arg @ref LL_DMA_CHANNEL_2
1245 * @arg @ref LL_DMA_CHANNEL_3
1246 * @arg @ref LL_DMA_CHANNEL_4
1247 * @arg @ref LL_DMA_CHANNEL_5
1248 * @arg @ref LL_DMA_CHANNEL_6
1249 * @arg @ref LL_DMA_CHANNEL_7
1250 * @retval Returned value can be one of the following values:
1251 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1252 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1253 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1254 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1255 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1256 * @arg @ref LL_DMAMUX_REQ_ADC1
1257 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1258 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1259 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1260 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1261 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1262 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1263 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1264 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1265 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1266 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1267 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1268 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1269 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1270 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1271 * @arg @ref LL_DMAMUX_REQ_QUADSPI
1272 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1273 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1274 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1275 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1276 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1277 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1278 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1279 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1280 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1281 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1282 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1283 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1284 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1285 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1286 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1287 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1288 * @arg @ref LL_DMAMUX_REQ_AES1_IN
1289 * @arg @ref LL_DMAMUX_REQ_AES1_OUT
1290 * @arg @ref LL_DMAMUX_REQ_AES2_IN
1291 * @arg @ref LL_DMAMUX_REQ_AES2_OUT
1292 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1293 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1294 {
1295 return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1296 }
1297
1298 /**
1299 * @}
1300 */
1301
1302 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1303 * @{
1304 */
1305
1306 /**
1307 * @brief Get Channel 1 global interrupt flag.
1308 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1309 * @param DMAx DMAx Instance
1310 * @retval State of bit (1 or 0).
1311 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1312 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1313 {
1314 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1315 }
1316
1317 /**
1318 * @brief Get Channel 2 global interrupt flag.
1319 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1320 * @param DMAx DMAx Instance
1321 * @retval State of bit (1 or 0).
1322 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1323 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1324 {
1325 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1326 }
1327
1328 /**
1329 * @brief Get Channel 3 global interrupt flag.
1330 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1331 * @param DMAx DMAx Instance
1332 * @retval State of bit (1 or 0).
1333 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1334 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1335 {
1336 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1337 }
1338
1339 /**
1340 * @brief Get Channel 4 global interrupt flag.
1341 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1342 * @param DMAx DMAx Instance
1343 * @retval State of bit (1 or 0).
1344 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1345 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1346 {
1347 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1348 }
1349
1350 /**
1351 * @brief Get Channel 5 global interrupt flag.
1352 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1353 * @param DMAx DMAx Instance
1354 * @retval State of bit (1 or 0).
1355 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1356 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1357 {
1358 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1359 }
1360
1361 /**
1362 * @brief Get Channel 6 global interrupt flag.
1363 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1364 * @param DMAx DMAx Instance
1365 * @retval State of bit (1 or 0).
1366 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1367 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1368 {
1369 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1370 }
1371
1372 /**
1373 * @brief Get Channel 7 global interrupt flag.
1374 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1375 * @param DMAx DMAx Instance
1376 * @retval State of bit (1 or 0).
1377 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1378 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1379 {
1380 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1381 }
1382
1383 /**
1384 * @brief Get Channel 1 transfer complete flag.
1385 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1386 * @param DMAx DMAx Instance
1387 * @retval State of bit (1 or 0).
1388 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1389 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1390 {
1391 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1392 }
1393
1394 /**
1395 * @brief Get Channel 2 transfer complete flag.
1396 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1397 * @param DMAx DMAx Instance
1398 * @retval State of bit (1 or 0).
1399 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1400 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1401 {
1402 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1403 }
1404
1405 /**
1406 * @brief Get Channel 3 transfer complete flag.
1407 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1408 * @param DMAx DMAx Instance
1409 * @retval State of bit (1 or 0).
1410 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1411 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1412 {
1413 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1414 }
1415
1416 /**
1417 * @brief Get Channel 4 transfer complete flag.
1418 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1419 * @param DMAx DMAx Instance
1420 * @retval State of bit (1 or 0).
1421 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1422 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1423 {
1424 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1425 }
1426
1427 /**
1428 * @brief Get Channel 5 transfer complete flag.
1429 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1430 * @param DMAx DMAx Instance
1431 * @retval State of bit (1 or 0).
1432 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1433 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1434 {
1435 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1436 }
1437
1438 /**
1439 * @brief Get Channel 6 transfer complete flag.
1440 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1441 * @param DMAx DMAx Instance
1442 * @retval State of bit (1 or 0).
1443 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1444 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1445 {
1446 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1447 }
1448
1449 /**
1450 * @brief Get Channel 7 transfer complete flag.
1451 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1452 * @param DMAx DMAx Instance
1453 * @retval State of bit (1 or 0).
1454 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1455 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1456 {
1457 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1458 }
1459
1460 /**
1461 * @brief Get Channel 1 half transfer flag.
1462 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1463 * @param DMAx DMAx Instance
1464 * @retval State of bit (1 or 0).
1465 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1466 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1467 {
1468 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1469 }
1470
1471 /**
1472 * @brief Get Channel 2 half transfer flag.
1473 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1474 * @param DMAx DMAx Instance
1475 * @retval State of bit (1 or 0).
1476 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1477 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1478 {
1479 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1480 }
1481
1482 /**
1483 * @brief Get Channel 3 half transfer flag.
1484 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1485 * @param DMAx DMAx Instance
1486 * @retval State of bit (1 or 0).
1487 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1488 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1489 {
1490 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1491 }
1492
1493 /**
1494 * @brief Get Channel 4 half transfer flag.
1495 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1496 * @param DMAx DMAx Instance
1497 * @retval State of bit (1 or 0).
1498 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1499 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1500 {
1501 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1502 }
1503
1504 /**
1505 * @brief Get Channel 5 half transfer flag.
1506 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1507 * @param DMAx DMAx Instance
1508 * @retval State of bit (1 or 0).
1509 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1510 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1511 {
1512 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1513 }
1514
1515 /**
1516 * @brief Get Channel 6 half transfer flag.
1517 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1518 * @param DMAx DMAx Instance
1519 * @retval State of bit (1 or 0).
1520 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1521 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1522 {
1523 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1524 }
1525
1526 /**
1527 * @brief Get Channel 7 half transfer flag.
1528 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1529 * @param DMAx DMAx Instance
1530 * @retval State of bit (1 or 0).
1531 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1532 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1533 {
1534 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1535 }
1536
1537 /**
1538 * @brief Get Channel 1 transfer error flag.
1539 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1540 * @param DMAx DMAx Instance
1541 * @retval State of bit (1 or 0).
1542 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1543 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1544 {
1545 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1546 }
1547
1548 /**
1549 * @brief Get Channel 2 transfer error flag.
1550 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1551 * @param DMAx DMAx Instance
1552 * @retval State of bit (1 or 0).
1553 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1554 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1555 {
1556 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1557 }
1558
1559 /**
1560 * @brief Get Channel 3 transfer error flag.
1561 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1562 * @param DMAx DMAx Instance
1563 * @retval State of bit (1 or 0).
1564 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1565 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1566 {
1567 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1568 }
1569
1570 /**
1571 * @brief Get Channel 4 transfer error flag.
1572 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1573 * @param DMAx DMAx Instance
1574 * @retval State of bit (1 or 0).
1575 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1576 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1577 {
1578 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1579 }
1580
1581 /**
1582 * @brief Get Channel 5 transfer error flag.
1583 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1584 * @param DMAx DMAx Instance
1585 * @retval State of bit (1 or 0).
1586 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1587 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1588 {
1589 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1590 }
1591
1592 /**
1593 * @brief Get Channel 6 transfer error flag.
1594 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1595 * @param DMAx DMAx Instance
1596 * @retval State of bit (1 or 0).
1597 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1598 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1599 {
1600 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Get Channel 7 transfer error flag.
1605 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1606 * @param DMAx DMAx Instance
1607 * @retval State of bit (1 or 0).
1608 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1609 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1610 {
1611 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1612 }
1613
1614 /**
1615 * @brief Clear Channel 1 global interrupt flag.
1616 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1617 * @param DMAx DMAx Instance
1618 * @retval None
1619 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1620 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1621 {
1622 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1623 }
1624
1625 /**
1626 * @brief Clear Channel 2 global interrupt flag.
1627 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1628 * @param DMAx DMAx Instance
1629 * @retval None
1630 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1631 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1632 {
1633 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1634 }
1635
1636 /**
1637 * @brief Clear Channel 3 global interrupt flag.
1638 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1639 * @param DMAx DMAx Instance
1640 * @retval None
1641 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1642 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1643 {
1644 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1645 }
1646
1647 /**
1648 * @brief Clear Channel 4 global interrupt flag.
1649 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1650 * @param DMAx DMAx Instance
1651 * @retval None
1652 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1653 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1654 {
1655 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1656 }
1657
1658 /**
1659 * @brief Clear Channel 5 global interrupt flag.
1660 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1661 * @param DMAx DMAx Instance
1662 * @retval None
1663 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1664 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1665 {
1666 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1667 }
1668
1669 /**
1670 * @brief Clear Channel 6 global interrupt flag.
1671 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1672 * @param DMAx DMAx Instance
1673 * @retval None
1674 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1675 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1676 {
1677 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1678 }
1679
1680 /**
1681 * @brief Clear Channel 7 global interrupt flag.
1682 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1683 * @param DMAx DMAx Instance
1684 * @retval None
1685 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1686 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1687 {
1688 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1689 }
1690
1691 /**
1692 * @brief Clear Channel 1 transfer complete flag.
1693 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1694 * @param DMAx DMAx Instance
1695 * @retval None
1696 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1697 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1698 {
1699 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1700 }
1701
1702 /**
1703 * @brief Clear Channel 2 transfer complete flag.
1704 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1705 * @param DMAx DMAx Instance
1706 * @retval None
1707 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1708 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1709 {
1710 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1711 }
1712
1713 /**
1714 * @brief Clear Channel 3 transfer complete flag.
1715 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1716 * @param DMAx DMAx Instance
1717 * @retval None
1718 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1719 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1720 {
1721 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1722 }
1723
1724 /**
1725 * @brief Clear Channel 4 transfer complete flag.
1726 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1727 * @param DMAx DMAx Instance
1728 * @retval None
1729 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1730 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1731 {
1732 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1733 }
1734
1735 /**
1736 * @brief Clear Channel 5 transfer complete flag.
1737 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1738 * @param DMAx DMAx Instance
1739 * @retval None
1740 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1741 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1742 {
1743 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1744 }
1745
1746 /**
1747 * @brief Clear Channel 6 transfer complete flag.
1748 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1749 * @param DMAx DMAx Instance
1750 * @retval None
1751 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1752 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1753 {
1754 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1755 }
1756
1757 /**
1758 * @brief Clear Channel 7 transfer complete flag.
1759 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1760 * @param DMAx DMAx Instance
1761 * @retval None
1762 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1763 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1764 {
1765 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1766 }
1767
1768 /**
1769 * @brief Clear Channel 1 half transfer flag.
1770 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1771 * @param DMAx DMAx Instance
1772 * @retval None
1773 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1774 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1775 {
1776 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1777 }
1778
1779 /**
1780 * @brief Clear Channel 2 half transfer flag.
1781 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1782 * @param DMAx DMAx Instance
1783 * @retval None
1784 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1785 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1786 {
1787 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1788 }
1789
1790 /**
1791 * @brief Clear Channel 3 half transfer flag.
1792 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1793 * @param DMAx DMAx Instance
1794 * @retval None
1795 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1796 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1797 {
1798 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1799 }
1800
1801 /**
1802 * @brief Clear Channel 4 half transfer flag.
1803 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1804 * @param DMAx DMAx Instance
1805 * @retval None
1806 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1807 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1808 {
1809 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1810 }
1811
1812 /**
1813 * @brief Clear Channel 5 half transfer flag.
1814 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1815 * @param DMAx DMAx Instance
1816 * @retval None
1817 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1818 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1819 {
1820 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1821 }
1822
1823 /**
1824 * @brief Clear Channel 6 half transfer flag.
1825 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1826 * @param DMAx DMAx Instance
1827 * @retval None
1828 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1829 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1830 {
1831 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1832 }
1833
1834 /**
1835 * @brief Clear Channel 7 half transfer flag.
1836 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1837 * @param DMAx DMAx Instance
1838 * @retval None
1839 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1840 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1841 {
1842 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1843 }
1844
1845 /**
1846 * @brief Clear Channel 1 transfer error flag.
1847 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1848 * @param DMAx DMAx Instance
1849 * @retval None
1850 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1851 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1852 {
1853 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1854 }
1855
1856 /**
1857 * @brief Clear Channel 2 transfer error flag.
1858 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1859 * @param DMAx DMAx Instance
1860 * @retval None
1861 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1862 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1863 {
1864 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1865 }
1866
1867 /**
1868 * @brief Clear Channel 3 transfer error flag.
1869 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1870 * @param DMAx DMAx Instance
1871 * @retval None
1872 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1873 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1874 {
1875 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1876 }
1877
1878 /**
1879 * @brief Clear Channel 4 transfer error flag.
1880 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1881 * @param DMAx DMAx Instance
1882 * @retval None
1883 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1884 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1885 {
1886 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1887 }
1888
1889 /**
1890 * @brief Clear Channel 5 transfer error flag.
1891 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1892 * @param DMAx DMAx Instance
1893 * @retval None
1894 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1895 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1896 {
1897 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1898 }
1899
1900 /**
1901 * @brief Clear Channel 6 transfer error flag.
1902 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1903 * @param DMAx DMAx Instance
1904 * @retval None
1905 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1906 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1907 {
1908 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1909 }
1910
1911 /**
1912 * @brief Clear Channel 7 transfer error flag.
1913 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1914 * @param DMAx DMAx Instance
1915 * @retval None
1916 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1917 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1918 {
1919 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1920 }
1921
1922 /**
1923 * @}
1924 */
1925
1926 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1927 * @{
1928 */
1929 /**
1930 * @brief Enable Transfer complete interrupt.
1931 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1932 * @param DMAx DMAx Instance
1933 * @param Channel This parameter can be one of the following values:
1934 * @arg @ref LL_DMA_CHANNEL_1
1935 * @arg @ref LL_DMA_CHANNEL_2
1936 * @arg @ref LL_DMA_CHANNEL_3
1937 * @arg @ref LL_DMA_CHANNEL_4
1938 * @arg @ref LL_DMA_CHANNEL_5
1939 * @arg @ref LL_DMA_CHANNEL_6
1940 * @arg @ref LL_DMA_CHANNEL_7
1941 * @retval None
1942 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1943 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1944 {
1945 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
1946 }
1947
1948 /**
1949 * @brief Enable Half transfer interrupt.
1950 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1951 * @param DMAx DMAx Instance
1952 * @param Channel This parameter can be one of the following values:
1953 * @arg @ref LL_DMA_CHANNEL_1
1954 * @arg @ref LL_DMA_CHANNEL_2
1955 * @arg @ref LL_DMA_CHANNEL_3
1956 * @arg @ref LL_DMA_CHANNEL_4
1957 * @arg @ref LL_DMA_CHANNEL_5
1958 * @arg @ref LL_DMA_CHANNEL_6
1959 * @arg @ref LL_DMA_CHANNEL_7
1960 * @retval None
1961 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1962 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1963 {
1964 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
1965 }
1966
1967 /**
1968 * @brief Enable Transfer error interrupt.
1969 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1970 * @param DMAx DMAx Instance
1971 * @param Channel This parameter can be one of the following values:
1972 * @arg @ref LL_DMA_CHANNEL_1
1973 * @arg @ref LL_DMA_CHANNEL_2
1974 * @arg @ref LL_DMA_CHANNEL_3
1975 * @arg @ref LL_DMA_CHANNEL_4
1976 * @arg @ref LL_DMA_CHANNEL_5
1977 * @arg @ref LL_DMA_CHANNEL_6
1978 * @arg @ref LL_DMA_CHANNEL_7
1979 * @retval None
1980 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1981 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1982 {
1983 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
1984 }
1985
1986 /**
1987 * @brief Disable Transfer complete interrupt.
1988 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1989 * @param DMAx DMAx Instance
1990 * @param Channel This parameter can be one of the following values:
1991 * @arg @ref LL_DMA_CHANNEL_1
1992 * @arg @ref LL_DMA_CHANNEL_2
1993 * @arg @ref LL_DMA_CHANNEL_3
1994 * @arg @ref LL_DMA_CHANNEL_4
1995 * @arg @ref LL_DMA_CHANNEL_5
1996 * @arg @ref LL_DMA_CHANNEL_6
1997 * @arg @ref LL_DMA_CHANNEL_7
1998 * @retval None
1999 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2000 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2001 {
2002 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
2003 }
2004
2005 /**
2006 * @brief Disable Half transfer interrupt.
2007 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2008 * @param DMAx DMAx Instance
2009 * @param Channel This parameter can be one of the following values:
2010 * @arg @ref LL_DMA_CHANNEL_1
2011 * @arg @ref LL_DMA_CHANNEL_2
2012 * @arg @ref LL_DMA_CHANNEL_3
2013 * @arg @ref LL_DMA_CHANNEL_4
2014 * @arg @ref LL_DMA_CHANNEL_5
2015 * @arg @ref LL_DMA_CHANNEL_6
2016 * @arg @ref LL_DMA_CHANNEL_7
2017 * @retval None
2018 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2019 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2020 {
2021 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
2022 }
2023
2024 /**
2025 * @brief Disable Transfer error interrupt.
2026 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2027 * @param DMAx DMAx Instance
2028 * @param Channel This parameter can be one of the following values:
2029 * @arg @ref LL_DMA_CHANNEL_1
2030 * @arg @ref LL_DMA_CHANNEL_2
2031 * @arg @ref LL_DMA_CHANNEL_3
2032 * @arg @ref LL_DMA_CHANNEL_4
2033 * @arg @ref LL_DMA_CHANNEL_5
2034 * @arg @ref LL_DMA_CHANNEL_6
2035 * @arg @ref LL_DMA_CHANNEL_7
2036 * @retval None
2037 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2038 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2039 {
2040 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
2041 }
2042
2043 /**
2044 * @brief Check if Transfer complete Interrupt is enabled.
2045 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2046 * @param DMAx DMAx Instance
2047 * @param Channel This parameter can be one of the following values:
2048 * @arg @ref LL_DMA_CHANNEL_1
2049 * @arg @ref LL_DMA_CHANNEL_2
2050 * @arg @ref LL_DMA_CHANNEL_3
2051 * @arg @ref LL_DMA_CHANNEL_4
2052 * @arg @ref LL_DMA_CHANNEL_5
2053 * @arg @ref LL_DMA_CHANNEL_6
2054 * @arg @ref LL_DMA_CHANNEL_7
2055 * @retval State of bit (1 or 0).
2056 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2057 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2058 {
2059 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2060 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2061 }
2062
2063 /**
2064 * @brief Check if Half transfer Interrupt is enabled.
2065 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2066 * @param DMAx DMAx Instance
2067 * @param Channel This parameter can be one of the following values:
2068 * @arg @ref LL_DMA_CHANNEL_1
2069 * @arg @ref LL_DMA_CHANNEL_2
2070 * @arg @ref LL_DMA_CHANNEL_3
2071 * @arg @ref LL_DMA_CHANNEL_4
2072 * @arg @ref LL_DMA_CHANNEL_5
2073 * @arg @ref LL_DMA_CHANNEL_6
2074 * @arg @ref LL_DMA_CHANNEL_7
2075 * @retval State of bit (1 or 0).
2076 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2077 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2078 {
2079 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2080 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2081 }
2082
2083 /**
2084 * @brief Check if Transfer error Interrupt is enabled.
2085 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2086 * @param DMAx DMAx Instance
2087 * @param Channel This parameter can be one of the following values:
2088 * @arg @ref LL_DMA_CHANNEL_1
2089 * @arg @ref LL_DMA_CHANNEL_2
2090 * @arg @ref LL_DMA_CHANNEL_3
2091 * @arg @ref LL_DMA_CHANNEL_4
2092 * @arg @ref LL_DMA_CHANNEL_5
2093 * @arg @ref LL_DMA_CHANNEL_6
2094 * @arg @ref LL_DMA_CHANNEL_7
2095 * @retval State of bit (1 or 0).
2096 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2097 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2098 {
2099 return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
2100 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2101 }
2102
2103 /**
2104 * @}
2105 */
2106
2107 #if defined(USE_FULL_LL_DRIVER)
2108 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2109 * @{
2110 */
2111
2112 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2113 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2114 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2115
2116 /**
2117 * @}
2118 */
2119 #endif /* USE_FULL_LL_DRIVER */
2120
2121 /**
2122 * @}
2123 */
2124
2125 /**
2126 * @}
2127 */
2128
2129 #endif /* DMA1 || DMA2 */
2130
2131 /**
2132 * @}
2133 */
2134
2135 #ifdef __cplusplus
2136 }
2137 #endif
2138
2139 #endif /* STM32WBxx_LL_DMA_H */
2140
2141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2142