1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32WBxx_LL_BUS_H
39 #define STM32WBxx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32wbxx.h"
47
48 /** @addtogroup STM32WBxx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
69 * @{
70 */
71
72 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
73 * @{
74 */
75 #define LL_AHB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
76
77 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
78 #if defined(DMA2)
79 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
80 #endif
81 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
82 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
83 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
84 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
85 /**
86 * @}
87 */
88
89 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
90 * @{
91 */
92 #define LL_AHB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
93
94 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
95 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
96 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
97 #if defined(GPIOD)
98 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
99 #endif
100 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
101 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
102 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
103 #if defined(AES1)
104 #define LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN
105 #endif
106 /**
107 * @}
108 */
109
110 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
111 * @{
112 */
113 #define LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
114 #if defined(QUADSPI)
115 #define LL_AHB3_GRP1_PERIPH_QUADSPI RCC_AHB3ENR_QUADSPIEN
116 #endif
117 #define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN
118 #define LL_AHB3_GRP1_PERIPH_AES2 RCC_AHB3ENR_AES2EN
119 #define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN
120 #define LL_AHB3_GRP1_PERIPH_HSEM RCC_AHB3ENR_HSEMEN
121 #define LL_AHB3_GRP1_PERIPH_IPCC RCC_AHB3ENR_IPCCEN
122 #define LL_AHB3_GRP1_PERIPH_SRAM2 RCC_AHB3SMENR_SRAM2SMEN
123 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3ENR_FLASHEN
124 /**
125 * @}
126 */
127
128 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
129 * @{
130 */
131 #define LL_APB1_GRP1_PERIPH_ALL (0xFFFFFFFFU)
132 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
133 #if defined(LCD)
134 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
135 #endif
136 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
137 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
138 #if defined(SPI2)
139 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
140 #endif
141 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
142 #if defined(I2C3)
143 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
144 #endif
145 #if defined(CRS)
146 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
147 #endif
148 #if defined(USB)
149 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
150 #endif
151 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
152 /**
153 * @}
154 */
155
156
157 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
158 * @{
159 */
160 #define LL_APB1_GRP2_PERIPH_ALL (0xFFFFFFFFU)
161
162 #if defined(LPUART1)
163 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
164 #endif
165 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
166 /**
167 * @}
168 */
169
170 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
171 * @{
172 */
173 #define LL_APB2_GRP1_PERIPH_ALL (0xFFFFFFFFU)
174
175 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
176 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
177 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
178 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
179 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
180 #if defined(SAI1)
181 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
182 #endif
183 /**
184 * @}
185 */
186
187 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
188 * @{
189 */
190 #define LL_APB3_GRP1_PERIPH_ALL (0xFFFFFFFFU)
191 #define LL_APB3_GRP1_PERIPH_RF RCC_APB3RSTR_RFRST
192 /**
193 * @}
194 */
195
196
197 /** @defgroup BUS_LL_EC_C2_AHB1_GRP1_PERIPH C2 AHB1 GRP1 PERIPH
198 * @{
199 */
200 #define LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN
201 #if defined(DMA2)
202 #define LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN
203 #endif
204 #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN
205 #define LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN
206 #define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN
207 #define LL_C2_AHB1_GRP1_PERIPH_TSC RCC_C2AHB1ENR_TSCEN
208 /**
209 * @}
210 */
211
212
213 /** @defgroup BUS_LL_EC_C2_AHB2_GRP1_PERIPH C2 AHB2 GRP1 PERIPH
214 * @{
215 */
216 #define LL_C2_AHB2_GRP1_PERIPH_GPIOA RCC_C2AHB2ENR_GPIOAEN
217 #define LL_C2_AHB2_GRP1_PERIPH_GPIOB RCC_C2AHB2ENR_GPIOBEN
218 #define LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN
219 #if defined(GPIOD)
220 #define LL_C2_AHB2_GRP1_PERIPH_GPIOD RCC_C2AHB2ENR_GPIODEN
221 #endif
222 #define LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN
223 #define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN
224 #define LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN
225 #if defined(AES1)
226 #define LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN
227 #endif
228 /**
229 * @}
230 */
231
232
233 /** @defgroup BUS_LL_EC_C2_AHB3_GRP1_PERIPH C2 AHB3 GRP1 PERIPH
234 * @{
235 */
236 #define LL_C2_AHB3_GRP1_PERIPH_PKA RCC_C2AHB3ENR_PKAEN
237 #define LL_C2_AHB3_GRP1_PERIPH_AES2 RCC_C2AHB3ENR_AES2EN
238 #define LL_C2_AHB3_GRP1_PERIPH_RNG RCC_C2AHB3ENR_RNGEN
239 #define LL_C2_AHB3_GRP1_PERIPH_HSEM RCC_C2AHB3ENR_HSEMEN
240 #define LL_C2_AHB3_GRP1_PERIPH_IPCC RCC_C2AHB3ENR_IPCCEN
241 #define LL_C2_AHB3_GRP1_PERIPH_FLASH RCC_C2AHB3ENR_FLASHEN
242 #define LL_C2_AHB3_GRP1_PERIPH_SRAM2 RCC_C2AHB3SMENR_SRAM2SMEN
243 /**
244 * @}
245 */
246
247
248 /** @defgroup BUS_LL_EC_C2_APB1_GRP1_PERIPH C2 APB1 GRP1 PERIPH
249 * @{
250 */
251 #define LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN
252 #if defined(LCD)
253 #define LL_C2_APB1_GRP1_PERIPH_LCD RCC_C2APB1ENR1_LCDEN
254 #endif
255 #define LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN
256 #if defined(SPI2)
257 #define LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN
258 #endif
259 #define LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN
260 #if defined(I2C3)
261 #define LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN
262 #define LL_C2_APB1_GRP1_PERIPH_CRS RCC_C2APB1ENR1_CRSEN
263 #define LL_C2_APB1_GRP1_PERIPH_USB RCC_C2APB1ENR1_USBEN
264 #endif
265 #define LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN
266 /**
267 * @}
268 */
269
270
271 /** @defgroup BUS_LL_EC_C2_APB1_GRP2_PERIPH C2 APB1 GRP2 PERIPH
272 * @{
273 */
274 #if defined(LPUART1)
275 #define LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN
276 #endif
277 #define LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN
278 /**
279 * @}
280 */
281
282
283 /** @defgroup BUS_LL_EC_C2_APB2_GRP1_PERIPH C2 APB2 GRP1 PERIPH
284 * @{
285 */
286 #define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN
287 #define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN
288 #define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN
289 #define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN
290 #define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN
291 #if defined(SAI1)
292 #define LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN
293 #endif
294 /**
295 * @}
296 */
297
298
299 /** @defgroup BUS_LL_EC_C2_APB3_GRP1_PERIPH C2 APB3 GRP1 PERIPH
300 * @{
301 */
302 #define LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN
303 #define LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN
304 /**
305 * @}
306 */
307
308
309 /**
310 * @}
311 */
312
313 /* Exported macro ------------------------------------------------------------*/
314
315 /* Exported functions --------------------------------------------------------*/
316
317 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
318 * @{
319 */
320
321 /** @defgroup BUS_LL_EF_AHB1 AHB1
322 * @{
323 */
324
325 /**
326 * @brief Enable AHB1 peripherals clock.
327 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
328 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
329 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
330 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
331 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
332 * @param Periphs This parameter can be a combination of the following values:
333 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
334 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
335 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
336 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
337 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
338 * @retval None
339 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)340 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
341 {
342 __IO uint32_t tmpreg;
343 SET_BIT(RCC->AHB1ENR, Periphs);
344 /* Delay after an RCC peripheral clock enabling */
345 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
346 (void)tmpreg;
347 }
348
349 /**
350 * @brief Check if AHB1 peripheral clock is enabled or not
351 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
352 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
353 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
354 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
355 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
356 * @param Periphs This parameter can be a combination of the following values:
357 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
358 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
359 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
360 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
361 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
362 * @retval uint32_t
363 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)364 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
365 {
366 return ((READ_BIT(RCC->AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
367 }
368
369 /**
370 * @brief Disable AHB1 peripherals clock.
371 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
372 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
373 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
374 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
375 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
376 * @param Periphs This parameter can be a combination of the following values:
377 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
378 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
379 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
380 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
381 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
382 * @retval None
383 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)384 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
385 {
386 CLEAR_BIT(RCC->AHB1ENR, Periphs);
387 }
388
389 /**
390 * @brief Force AHB1 peripherals reset.
391 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
392 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
393 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
394 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
395 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
396 * @param Periphs This parameter can be a combination of the following values:
397 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
398 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
399 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
400 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
401 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
402 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
403 * @retval None
404 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)405 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
406 {
407 SET_BIT(RCC->AHB1RSTR, Periphs);
408 }
409
410 /**
411 * @brief Release AHB1 peripherals reset.
412 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
413 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
414 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
415 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
416 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
417 * @param Periphs This parameter can be a combination of the following values:
418 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
419 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
420 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
421 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
422 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
423 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
424 * @retval None
425 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)426 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
427 {
428 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
429 }
430
431 /**
432 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
433 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockSleep\n
434 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockSleep\n
435 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockSleep\n
436 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockSleep\n
437 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n
438 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep
439 * @param Periphs This parameter can be a combination of the following values:
440 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
441 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
442 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
443 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
444 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
445 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
446 * @retval None
447 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)448 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
449 {
450 __IO uint32_t tmpreg;
451 SET_BIT(RCC->AHB1SMENR, Periphs);
452 /* Delay after an RCC peripheral clock enabling */
453 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
454 (void)tmpreg;
455 }
456
457 /**
458 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
459 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockSleep\n
460 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockSleep\n
461 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockSleep\n
462 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockSleep\n
463 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n
464 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep
465 * @param Periphs This parameter can be a combination of the following values:
466 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
467 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
468 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
469 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
470 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
471 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
472 * @retval None
473 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)474 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
475 {
476 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
477 }
478
479 /**
480 * @}
481 */
482
483 /** @defgroup BUS_LL_EF_AHB2 AHB2
484 * @{
485 */
486
487 /**
488 * @brief Enable AHB2 peripherals clock.
489 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
490 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
491 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
492 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
493 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
494 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
495 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
496 * AHB2ENR AES1EN LL_AHB2_GRP1_EnableClock
497 * @param Periphs This parameter can be a combination of the following values:
498 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
499 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
500 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
501 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
502 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
503 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
504 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
505 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
506 * @retval None
507 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)508 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
509 {
510 __IO uint32_t tmpreg;
511 SET_BIT(RCC->AHB2ENR, Periphs);
512 /* Delay after an RCC peripheral clock enabling */
513 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
514 (void)tmpreg;
515 }
516
517 /**
518 * @brief Check if AHB2 peripheral clock is enabled or not
519 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
520 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
521 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
522 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
523 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
524 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
525 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
526 * AHB2ENR AES1EN LL_AHB2_GRP1_IsEnabledClock
527 * @param Periphs This parameter can be a combination of the following values:
528 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
529 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
530 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
531 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
532 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
533 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
534 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
535 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
536 * @retval uint32_t
537 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)538 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
539 {
540 return ((READ_BIT(RCC->AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Disable AHB2 peripherals clock.
545 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
546 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
547 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
548 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
549 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
550 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
551 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
552 * AHB2ENR AES1EN LL_AHB2_GRP1_DisableClock
553 * @param Periphs This parameter can be a combination of the following values:
554 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
555 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
556 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
557 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
558 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
559 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
560 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
561 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
562 * @retval None
563 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)564 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
565 {
566 CLEAR_BIT(RCC->AHB2ENR, Periphs);
567 }
568
569 /**
570 * @brief Force AHB2 peripherals reset.
571 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
572 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
573 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
574 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
575 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
576 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
577 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
578 * AHB2RSTR AES1RST LL_AHB2_GRP1_ForceReset
579 * @param Periphs This parameter can be a combination of the following values:
580 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
581 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
582 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
583 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
584 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
585 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
586 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
587 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
588 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
589 * @retval None
590 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)591 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
592 {
593 SET_BIT(RCC->AHB2RSTR, Periphs);
594 }
595
596 /**
597 * @brief Release AHB2 peripherals reset.
598 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
599 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
600 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
601 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
602 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
603 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
604 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
605 * AHB2RSTR AES1RST LL_AHB2_GRP1_ReleaseReset
606 * @param Periphs This parameter can be a combination of the following values:
607 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
608 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
609 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
610 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
611 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
612 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
613 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
614 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
615 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
616 * @retval None
617 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)618 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
619 {
620 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
621 }
622
623 /**
624 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
625 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockSleep\n
626 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockSleep\n
627 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockSleep\n
628 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockSleep\n
629 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockSleep\n
630 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockSleep\n
631 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockSleep\n
632 * AHB2SMENR AES1SMEN LL_AHB2_GRP1_EnableClockSleep
633 * @param Periphs This parameter can be a combination of the following values:
634 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
635 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
636 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
637 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
638 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
639 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
640 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
641 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
642 * @retval None
643 */
LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)644 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
645 {
646 __IO uint32_t tmpreg;
647 SET_BIT(RCC->AHB2SMENR, Periphs);
648 /* Delay after an RCC peripheral clock enabling */
649 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
650 (void)tmpreg;
651 }
652
653 /**
654 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
655 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockSleep\n
656 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockSleep\n
657 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockSleep\n
658 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockSleep\n
659 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockSleep\n
660 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockSleep\n
661 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockSleep\n
662 * AHB2SMENR AES1SMEN LL_AHB2_GRP1_DisableClockSleep
663 * @param Periphs This parameter can be a combination of the following values:
664 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
665 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
666 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
667 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
668 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
669 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
670 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
671 * @arg @ref LL_AHB2_GRP1_PERIPH_AES1
672 * @retval None
673 */
LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)674 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
675 {
676 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
677 }
678
679 /**
680 * @}
681 */
682
683 /** @defgroup BUS_LL_EF_AHB3 AHB3
684 * @{
685 */
686
687 /**
688 * @brief Enable AHB3 peripherals clock.
689 * @rmtoll AHB3ENR QUADSPIEN LL_AHB3_GRP1_EnableClock\n
690 * AHB3ENR PKAEN LL_AHB3_GRP1_EnableClock\n
691 * AHB3ENR AES2EN LL_AHB3_GRP1_EnableClock\n
692 * AHB3ENR RNGEN LL_AHB3_GRP1_EnableClock\n
693 * AHB3ENR HSEMEN LL_AHB3_GRP1_EnableClock\n
694 * AHB3ENR IPCCEN LL_AHB3_GRP1_EnableClock\n
695 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock
696 * @param Periphs This parameter can be a combination of the following values:
697 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
698 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
699 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
700 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
701 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
702 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
703 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
704 * @retval None
705 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)706 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
707 {
708 __IO uint32_t tmpreg;
709 SET_BIT(RCC->AHB3ENR, Periphs);
710 /* Delay after an RCC peripheral clock enabling */
711 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
712 (void)tmpreg;
713 }
714
715 /**
716 * @brief Check if AHB3 peripheral clock is enabled or not
717 * @rmtoll AHB3ENR QUADSPIEN LL_AHB3_GRP1_IsEnabledClock\n
718 * AHB3ENR PKAEN LL_AHB3_GRP1_IsEnabledClock\n
719 * AHB3ENR AES2EN LL_AHB3_GRP1_IsEnabledClock\n
720 * AHB3ENR RNGEN LL_AHB3_GRP1_IsEnabledClock\n
721 * AHB3ENR HSEMEN LL_AHB3_GRP1_IsEnabledClock\n
722 * AHB3ENR IPCCEN LL_AHB3_GRP1_IsEnabledClock\n
723 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock
724 * @param Periphs This parameter can be a combination of the following values:
725 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
726 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
727 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
728 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
729 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
730 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
731 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
732 * @retval uint32_t
733 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)734 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
735 {
736 return ((READ_BIT(RCC->AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
737 }
738
739 /**
740 * @brief Disable AHB3 peripherals clock.
741 * @rmtoll AHB3ENR QUADSPIEN LL_AHB3_GRP1_DisableClock\n
742 * AHB3ENR PKAEN LL_AHB3_GRP1_DisableClock\n
743 * AHB3ENR AES2EN LL_AHB3_GRP1_DisableClock\n
744 * AHB3ENR RNGEN LL_AHB3_GRP1_DisableClock\n
745 * AHB3ENR HSEMEN LL_AHB3_GRP1_DisableClock\n
746 * AHB3ENR IPCCEN LL_AHB3_GRP1_DisableClock\n
747 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock
748 * @param Periphs This parameter can be a combination of the following values:
749 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
750 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
751 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
752 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
753 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
754 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
755 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
756 * @retval None
757 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)758 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
759 {
760 CLEAR_BIT(RCC->AHB3ENR, Periphs);
761 }
762
763 /**
764 * @brief Force AHB3 peripherals reset.
765 * @rmtoll AHB3RSTR QUADSPIRST LL_AHB3_GRP1_ForceReset\n
766 * AHB3RSTR PKARST LL_AHB3_GRP1_ForceReset\n
767 * AHB3RSTR AES2RST LL_AHB3_GRP1_ForceReset\n
768 * AHB3RSTR RNGRST LL_AHB3_GRP1_ForceReset\n
769 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ForceReset\n
770 * AHB3RSTR IPCCRST LL_AHB3_GRP1_ForceReset\n
771 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ForceReset
772 * @param Periphs This parameter can be a combination of the following values:
773 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
774 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
775 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
776 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
777 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
778 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
779 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
780 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
781 * @retval None
782 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)783 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
784 {
785 SET_BIT(RCC->AHB3RSTR, Periphs);
786 }
787
788 /**
789 * @brief Release AHB3 peripherals reset.
790 * @rmtoll AHB3RSTR QUADSPIRST LL_AHB3_GRP1_ReleaseReset\n
791 * AHB3RSTR PKARST LL_AHB3_GRP1_ReleaseReset\n
792 * AHB3RSTR AES2RST LL_AHB3_GRP1_ReleaseReset\n
793 * AHB3RSTR RNGRST LL_AHB3_GRP1_ReleaseReset\n
794 * AHB3RSTR HSEMRST LL_AHB3_GRP1_ReleaseReset\n
795 * AHB3RSTR IPCCRST LL_AHB3_GRP1_ReleaseReset\n
796 * AHB3RSTR FLASHRST LL_AHB3_GRP1_ReleaseReset
797 * @param Periphs This parameter can be a combination of the following values:
798 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
799 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
800 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
801 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
802 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
803 * @arg @ref LL_AHB3_GRP1_PERIPH_HSEM
804 * @arg @ref LL_AHB3_GRP1_PERIPH_IPCC
805 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
806 * @retval None
807 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)808 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
809 {
810 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
811 }
812
813 /**
814 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
815 * @rmtoll AHB3SMENR QUADSPISMEN LL_AHB3_GRP1_EnableClockSleep\n
816 * AHB3SMENR PKASMEN LL_AHB3_GRP1_EnableClockSleep\n
817 * AHB3SMENR AES2SMEN LL_AHB3_GRP1_EnableClockSleep\n
818 * AHB3SMENR RNGSMEN LL_AHB3_GRP1_EnableClockSleep\n
819 * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_EnableClockSleep\n
820 * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_EnableClockSleep
821 * @param Periphs This parameter can be a combination of the following values:
822 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
823 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
824 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
825 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
826 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
827 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
828 * @retval None
829 */
LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)830 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
831 {
832 __IO uint32_t tmpreg;
833 SET_BIT(RCC->AHB3SMENR, Periphs);
834 /* Delay after an RCC peripheral clock enabling */
835 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
836 (void)tmpreg;
837 }
838
839 /**
840 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
841 * @rmtoll AHB3SMENR QUADSPISMEN LL_AHB3_GRP1_DisableClockSleep\n
842 * AHB3SMENR PKASMEN LL_AHB3_GRP1_DisableClockSleep\n
843 * AHB3SMENR AES2SMEN LL_AHB3_GRP1_DisableClockSleep\n
844 * AHB3SMENR RNGSMEN LL_AHB3_GRP1_DisableClockSleep\n
845 * AHB3SMENR SRAM2SMEN LL_AHB3_GRP1_DisableClockSleep\n
846 * AHB3SMENR FLASHSMEN LL_AHB3_GRP1_DisableClockSleep
847 * @param Periphs This parameter can be a combination of the following values:
848 * @arg @ref LL_AHB3_GRP1_PERIPH_QUADSPI
849 * @arg @ref LL_AHB3_GRP1_PERIPH_PKA
850 * @arg @ref LL_AHB3_GRP1_PERIPH_AES2
851 * @arg @ref LL_AHB3_GRP1_PERIPH_RNG
852 * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM2
853 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
854 * @retval None
855 */
LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)856 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
857 {
858 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
859 }
860
861 /**
862 * @}
863 */
864
865 /** @defgroup BUS_LL_EF_APB1 APB1
866 * @{
867 */
868
869 /**
870 * @brief Enable APB1 peripherals clock.
871 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
872 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
873 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
874 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
875 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
876 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
877 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
878 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
879 * APB1ENR1 USBEN LL_APB1_GRP1_EnableClock\n
880 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
881 * @param Periphs This parameter can be a combination of the following values:
882 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
883 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
884 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
885 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
886 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
887 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
888 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
889 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
890 * @arg @ref LL_APB1_GRP1_PERIPH_USB
891 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
892 * @retval None
893 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)894 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
895 {
896 __IO uint32_t tmpreg;
897 SET_BIT(RCC->APB1ENR1, Periphs);
898 /* Delay after an RCC peripheral clock enabling */
899 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
900 (void)tmpreg;
901 }
902
903 /**
904 * @brief Enable APB1 peripherals clock.
905 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
906 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
907 * @param Periphs This parameter can be a combination of the following values:
908 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
909 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
910 * @retval None
911 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)912 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
913 {
914 __IO uint32_t tmpreg;
915 SET_BIT(RCC->APB1ENR2, Periphs);
916 /* Delay after an RCC peripheral clock enabling */
917 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
918 (void)tmpreg;
919 }
920
921 /**
922 * @brief Check if APB1 peripheral clock is enabled or not
923 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
924 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
925 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
926 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
927 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
928 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
929 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
930 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
931 * APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
932 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
933 * @param Periphs This parameter can be a combination of the following values:
934 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
935 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
936 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
937 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
938 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
939 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
940 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
941 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
942 * @arg @ref LL_APB1_GRP1_PERIPH_USB
943 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
944 * @retval uint32_t
945 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)946 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
947 {
948 return ((READ_BIT(RCC->APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
949 }
950
951 /**
952 * @brief Check if APB1 peripheral clock is enabled or not
953 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
954 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
955 * @param Periphs This parameter can be a combination of the following values:
956 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
957 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
958 * @retval uint32_t
959 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)960 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
961 {
962 return ((READ_BIT(RCC->APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
963 }
964
965 /**
966 * @brief Disable APB1 peripherals clock.
967 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
968 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
969 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
970 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
971 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
972 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
973 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
974 * APB1ENR1 USBEN LL_APB1_GRP1_DisableClock\n
975 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
976 * @param Periphs This parameter can be a combination of the following values:
977 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
978 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
979 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
980 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
981 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
982 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
983 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
984 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
985 * @arg @ref LL_APB1_GRP1_PERIPH_USB
986 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
987 * @retval None
988 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)989 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
990 {
991 CLEAR_BIT(RCC->APB1ENR1, Periphs);
992 }
993
994 /**
995 * @brief Disable APB1 peripherals clock.
996 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
997 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
998 * @param Periphs This parameter can be a combination of the following values:
999 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1000 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1001 * @retval None
1002 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1003 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1004 {
1005 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1006 }
1007
1008 /**
1009 * @brief Force APB1 peripherals reset.
1010 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1011 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
1012 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1013 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1014 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1015 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1016 * APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset\n
1017 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1018 * @param Periphs This parameter can be a combination of the following values:
1019 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1020 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1021 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
1022 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1023 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1024 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1025 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1026 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1027 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1028 * @retval None
1029 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1030 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1031 {
1032 SET_BIT(RCC->APB1RSTR1, Periphs);
1033 }
1034
1035 /**
1036 * @brief Force APB1 peripherals reset.
1037 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1038 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
1039 * @param Periphs This parameter can be a combination of the following values:
1040 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1041 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1042 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1043 * @retval None
1044 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1045 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1046 {
1047 SET_BIT(RCC->APB1RSTR2, Periphs);
1048 }
1049
1050 /**
1051 * @brief Release APB1 peripherals reset.
1052 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1053 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
1054 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1055 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1056 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1057 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1058 * APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
1059 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1060 * @param Periphs This parameter can be a combination of the following values:
1061 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1062 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1063 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
1064 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1065 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1066 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1067 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1068 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1069 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1070 * @retval None
1071 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1072 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1073 {
1074 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1075 }
1076
1077 /**
1078 * @brief Release APB1 peripherals reset.
1079 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1080 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1081 * @param Periphs This parameter can be a combination of the following values:
1082 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1083 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1084 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1085 * @retval None
1086 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1087 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1088 {
1089 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1090 }
1091
1092 /**
1093 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1094 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n
1095 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockSleep\n
1096 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockSleep\n
1097 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n
1098 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n
1099 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n
1100 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n
1101 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockSleep\n
1102 * APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockSleep\n
1103 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep
1104 * @param Periphs This parameter can be a combination of the following values:
1105 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1106 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
1107 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1108 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1109 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1110 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1111 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1112 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1113 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1114 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1115 * @retval None
1116 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1117 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1118 {
1119 __IO uint32_t tmpreg;
1120 SET_BIT(RCC->APB1SMENR1, Periphs);
1121 /* Delay after an RCC peripheral clock enabling */
1122 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1123 (void)tmpreg;
1124 }
1125
1126 /**
1127 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
1128 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockSleep\n
1129 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockSleep
1130 * @param Periphs This parameter can be a combination of the following values:
1131 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1132 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1133 * @retval None
1134 */
LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)1135 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
1136 {
1137 __IO uint32_t tmpreg;
1138 SET_BIT(RCC->APB1SMENR2, Periphs);
1139 /* Delay after an RCC peripheral clock enabling */
1140 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1141 (void)tmpreg;
1142 }
1143
1144 /**
1145 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1146 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n
1147 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockSleep\n
1148 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockSleep\n
1149 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n
1150 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n
1151 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n
1152 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n
1153 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockSleep\n
1154 * APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockSleep\n
1155 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep
1156 * @param Periphs This parameter can be a combination of the following values:
1157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1158 * @arg @ref LL_APB1_GRP1_PERIPH_LCD
1159 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1160 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1161 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1162 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1163 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1164 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1165 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1166 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1167 * @retval None
1168 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)1169 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
1170 {
1171 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1172 }
1173
1174 /**
1175 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
1176 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockSleep\n
1177 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockSleep
1178 * @param Periphs This parameter can be a combination of the following values:
1179 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1180 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1181 * @retval None
1182 */
LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)1183 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
1184 {
1185 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1186 }
1187
1188 /**
1189 * @}
1190 */
1191
1192 /** @defgroup BUS_LL_EF_APB2 APB2
1193 * @{
1194 */
1195
1196 /**
1197 * @brief Enable APB2 peripherals clock.
1198 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1199 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1200 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1201 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1202 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1203 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock
1204 * @param Periphs This parameter can be a combination of the following values:
1205 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1206 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1207 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1208 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1209 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1210 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1211 * @retval None
1212 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1213 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1214 {
1215 __IO uint32_t tmpreg;
1216 SET_BIT(RCC->APB2ENR, Periphs);
1217 /* Delay after an RCC peripheral clock enabling */
1218 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1219 (void)tmpreg;
1220 }
1221
1222 /**
1223 * @brief Check if APB2 peripheral clock is enabled or not
1224 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1225 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1226 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1227 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1228 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1229 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock
1230 * @param Periphs This parameter can be a combination of the following values:
1231 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1232 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1233 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1234 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1235 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1236 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1237 * @retval uint32_t
1238 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1239 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1240 {
1241 return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1242 }
1243
1244 /**
1245 * @brief Disable APB2 peripherals clock.
1246 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1247 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1248 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1249 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1250 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1251 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock
1252 * @param Periphs This parameter can be a combination of the following values:
1253 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1254 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1255 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1256 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1257 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1258 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1259 * @retval None
1260 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1261 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1262 {
1263 CLEAR_BIT(RCC->APB2ENR, Periphs);
1264 }
1265
1266 /**
1267 * @brief Force APB2 peripherals reset.
1268 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1269 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1270 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1271 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1272 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1273 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset
1274 * @param Periphs This parameter can be a combination of the following values:
1275 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1276 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1277 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1278 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1279 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1280 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1281 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1282 * @retval None
1283 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1284 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1285 {
1286 SET_BIT(RCC->APB2RSTR, Periphs);
1287 }
1288
1289 /**
1290 * @brief Release APB2 peripherals reset.
1291 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1292 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1293 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1294 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1295 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1296 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset
1297 * @param Periphs This parameter can be a combination of the following values:
1298 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1299 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1300 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1301 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1302 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1303 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1304 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1305 * @retval None
1306 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1307 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1308 {
1309 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1310 }
1311
1312 /**
1313 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
1314 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockSleep\n
1315 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n
1316 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n
1317 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockSleep\n
1318 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockSleep\n
1319 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockSleep
1320 * @param Periphs This parameter can be a combination of the following values:
1321 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1322 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1323 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1324 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1325 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1326 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1327 * @retval None
1328 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)1329 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
1330 {
1331 __IO uint32_t tmpreg;
1332 SET_BIT(RCC->APB2SMENR, Periphs);
1333 /* Delay after an RCC peripheral clock enabling */
1334 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1335 (void)tmpreg;
1336 }
1337
1338 /**
1339 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
1340 * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockSleep\n
1341 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n
1342 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n
1343 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockSleep\n
1344 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockSleep\n
1345 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockSleep
1346 * @param Periphs This parameter can be a combination of the following values:
1347 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1348 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1349 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1350 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1351 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1352 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1353 * @retval None
1354 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)1355 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
1356 {
1357 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1358 }
1359
1360 /**
1361 * @}
1362 */
1363
1364 /** @defgroup BUS_LL_EF_APB3 APB3
1365 * @{
1366 */
1367
1368 /**
1369 * @brief Force APB3 peripherals reset.
1370 * @rmtoll APB3RSTR RFRST LL_APB3_GRP1_ForceReset
1371 * @param Periphs This parameter can be a combination of the following values:
1372 * @arg @ref LL_APB3_GRP1_PERIPH_RF
1373 * @retval None
1374 */
LL_APB3_GRP1_ForceReset(uint32_t Periphs)1375 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
1376 {
1377 SET_BIT(RCC->APB3RSTR, Periphs);
1378 }
1379
1380 /**
1381 * @brief Release APB3 peripherals reset.
1382 * @rmtoll APB3RSTR RFRST LL_APB3_GRP1_ReleaseReset
1383 * @param Periphs This parameter can be a combination of the following values:
1384 * @arg @ref LL_APB3_GRP1_PERIPH_RF
1385 * @retval None
1386 */
LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)1387 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
1388 {
1389 CLEAR_BIT(RCC->APB3RSTR, Periphs);
1390 }
1391
1392 /**
1393 * @}
1394 */
1395
1396 /** @defgroup BUS_LL_EF_C2_AHB1 C2 AHB1
1397 * @{
1398 */
1399 /**
1400 * @brief Enable C2AHB1 peripherals clock.
1401 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n
1402 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n
1403 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_EnableClock\n
1404 * C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_EnableClock\n
1405 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_EnableClock\n
1406 * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_EnableClock
1407 * @param Periphs This parameter can be a combination of the following values:
1408 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1409 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1410 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1411 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1412 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1413 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1414 * @retval None
1415 */
1416
LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)1417 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
1418 {
1419 __IO uint32_t tmpreg;
1420 SET_BIT(RCC->C2AHB1ENR, Periphs);
1421 /* Delay after an RCC peripheral clock enabling */
1422 tmpreg = READ_BIT(RCC->C2AHB1ENR, Periphs);
1423 (void)tmpreg;
1424 }
1425
1426 /**
1427 * @brief Check if C2AHB1 peripheral clock is enabled or not
1428 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1429 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1430 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1431 * C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_IsEnabledClock\n
1432 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_IsEnabledClock\n
1433 * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_IsEnabledClock
1434 * @param Periphs This parameter can be a combination of the following values:
1435 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1436 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1437 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1438 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1439 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1440 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1441 * @retval uint32_t
1442 */
1443
LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)1444 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
1445 {
1446 return ((READ_BIT(RCC->C2AHB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1447 }
1448
1449 /**
1450 * @brief Disable C2AHB1 peripherals clock.
1451 * @rmtoll C2AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n
1452 * C2AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n
1453 * C2AHB1ENR DMAMUX1EN LL_C2_AHB1_GRP1_DisableClock\n
1454 * C2AHB1ENR SRAM1EN LL_C2_AHB1_GRP1_DisableClock\n
1455 * C2AHB1ENR CRCEN LL_C2_AHB1_GRP1_DisableClock\n
1456 * C2AHB1ENR TSCEN LL_C2_AHB1_GRP1_DisableClock
1457 * @param Periphs This parameter can be a combination of the following values:
1458 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1459 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1460 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1461 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1462 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1463 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1464 * @retval None
1465 */
1466
LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)1467 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
1468 {
1469 CLEAR_BIT(RCC->C2AHB1ENR, Periphs);
1470 }
1471
1472 /**
1473 * @brief Enable C2AHB1 peripherals clock during Low Power (Sleep) mode.
1474 * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1475 * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1476 * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1477 * C2AHB1ENR SRAM1SMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1478 * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_EnableClockSleep\n
1479 * C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_EnableClockSleep
1480 * @param Periphs This parameter can be a combination of the following values:
1481 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1482 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1483 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1484 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1485 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1486 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1487 * @retval None
1488 */
1489
LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)1490 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
1491 {
1492 __IO uint32_t tmpreg;
1493 SET_BIT(RCC->C2AHB1SMENR, Periphs);
1494 /* Delay after an RCC peripheral clock enabling */
1495 tmpreg = READ_BIT(RCC->C2AHB1SMENR, Periphs);
1496 (void)tmpreg;
1497 }
1498
1499 /**
1500 * @brief Disable C2AHB1 peripherals clock during Low Power (Sleep) mode.
1501 * @rmtoll C2AHB1SMENR DMA1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1502 * C2AHB1SMENR DMA2SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1503 * C2AHB1SMENR DMAMUX1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1504 * C2AHB1ENR SRAM1SMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1505 * C2AHB1SMENR CRCSMEN LL_C2_AHB1_GRP1_DisableClockSleep\n
1506 * C2AHB1SMENR TSCSMEN LL_C2_AHB1_GRP1_DisableClockSleep
1507 * @param Periphs This parameter can be a combination of the following values:
1508 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA1
1509 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMA2
1510 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_DMAMUX1
1511 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_SRAM1
1512 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_CRC
1513 * @arg @ref LL_C2_AHB1_GRP1_PERIPH_TSC
1514 * @retval None
1515 */
1516
LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)1517 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
1518 {
1519 CLEAR_BIT(RCC->C2AHB1SMENR, Periphs);
1520 }
1521
1522 /**
1523 * @}
1524 */
1525
1526 /** @defgroup BUS_LL_EF_C2_AHB2 C2 AHB2
1527 * @{
1528 */
1529
1530 /**
1531 * @brief Enable C2AHB2 peripherals clock.
1532 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_EnableClock\n
1533 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_EnableClock\n
1534 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_EnableClock\n
1535 * C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_EnableClock\n
1536 * C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_EnableClock\n
1537 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_EnableClock\n
1538 * C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_EnableClock\n
1539 * C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_EnableClock
1540 * @param Periphs This parameter can be a combination of the following values:
1541 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1542 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1543 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1544 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
1545 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1546 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1547 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
1548 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
1549 * @retval None
1550 */
LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)1551 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
1552 {
1553 __IO uint32_t tmpreg;
1554 SET_BIT(RCC->C2AHB2ENR, Periphs);
1555 /* Delay after an RCC peripheral clock enabling */
1556 tmpreg = READ_BIT(RCC->C2AHB2ENR, Periphs);
1557 (void)tmpreg;
1558 }
1559
1560 /**
1561 * @brief Check if C2AHB2 peripheral clock is enabled or not
1562 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1563 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1564 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1565 * C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1566 * C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1567 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1568 * C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_IsEnabledClock\n
1569 * C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_IsEnabledClock
1570 * @param Periphs This parameter can be a combination of the following values:
1571 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1572 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1573 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1574 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
1575 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1576 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1577 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
1578 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
1579 * @retval uint32_t
1580 */
LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)1581 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
1582 {
1583 return ((READ_BIT(RCC->C2AHB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1584 }
1585
1586 /**
1587 * @brief Disable C2AHB2 peripherals clock.
1588 * @rmtoll C2AHB2ENR GPIOAEN LL_C2_AHB2_GRP1_DisableClock\n
1589 * C2AHB2ENR GPIOBEN LL_C2_AHB2_GRP1_DisableClock\n
1590 * C2AHB2ENR GPIOCEN LL_C2_AHB2_GRP1_DisableClock\n
1591 * C2AHB2ENR GPIODEN LL_C2_AHB2_GRP1_DisableClock\n
1592 * C2AHB2ENR GPIOEEN LL_C2_AHB2_GRP1_DisableClock\n
1593 * C2AHB2ENR GPIOHEN LL_C2_AHB2_GRP1_DisableClock\n
1594 * C2AHB2ENR ADCEN LL_C2_AHB2_GRP1_DisableClock\n
1595 * C2AHB2ENR AES1EN LL_C2_AHB2_GRP1_DisableClock
1596 * @param Periphs This parameter can be a combination of the following values:
1597 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1598 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1599 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1600 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
1601 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1602 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1603 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
1604 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
1605 * @retval None
1606 */
LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)1607 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
1608 {
1609 CLEAR_BIT(RCC->C2AHB2ENR, Periphs);
1610 }
1611
1612 /**
1613 * @brief Enable C2AHB2 peripherals clock during Low Power (Sleep) mode.
1614 * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1615 * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1616 * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1617 * C2AHB2SMENR GPIODSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1618 * C2AHB2SMENR GPIOESMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1619 * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1620 * C2AHB2SMENR ADCSMEN LL_C2_AHB2_GRP1_EnableClockSleep\n
1621 * C2AHB2SMENR AES1SMEN LL_C2_AHB2_GRP1_EnableClockSleep
1622 * @param Periphs This parameter can be a combination of the following values:
1623 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1624 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1625 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1626 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
1627 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1628 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1629 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
1630 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
1631 * @retval None
1632 */
LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)1633 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
1634 {
1635 __IO uint32_t tmpreg;
1636 SET_BIT(RCC->C2AHB2SMENR, Periphs);
1637 /* Delay after an RCC peripheral clock enabling */
1638 tmpreg = READ_BIT(RCC->C2AHB2SMENR, Periphs);
1639 (void)tmpreg;
1640 }
1641
1642 /**
1643 * @brief Disable C2AHB2 peripherals clock during Low Power (Sleep) mode.
1644 * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1645 * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1646 * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1647 * C2AHB2SMENR GPIODSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1648 * C2AHB2SMENR GPIOESMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1649 * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1650 * C2AHB2SMENR ADCSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n
1651 * C2AHB2SMENR AES1SMEN LL_C2_AHB2_GRP1_DisableClockSleep
1652 * @param Periphs This parameter can be a combination of the following values:
1653 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA
1654 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOB
1655 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOC
1656 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOD
1657 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOE
1658 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOH
1659 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_ADC
1660 * @arg @ref LL_C2_AHB2_GRP1_PERIPH_AES1
1661 * @retval None
1662 */
LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)1663 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
1664 {
1665 CLEAR_BIT(RCC->C2AHB2SMENR, Periphs);
1666 }
1667
1668 /**
1669 * @}
1670 */
1671
1672 /** @defgroup BUS_LL_EF_C2_AHB3 C2 AHB3
1673 * @{
1674 */
1675
1676 /**
1677 * @brief Enable C2AHB3 peripherals clock.
1678 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_EnableClock\n
1679 * C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_EnableClock\n
1680 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_EnableClock\n
1681 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_EnableClock\n
1682 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_EnableClock\n
1683 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock
1684 * @param Periphs This parameter can be a combination of the following values:
1685 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1686 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1687 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1688 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1689 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1690 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1691 * @retval None
1692 */
LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)1693 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
1694 {
1695 __IO uint32_t tmpreg;
1696 SET_BIT(RCC->C2AHB3ENR, Periphs);
1697 /* Delay after an RCC peripheral clock enabling */
1698 tmpreg = READ_BIT(RCC->C2AHB3ENR, Periphs);
1699 (void)tmpreg;
1700 }
1701
1702 /**
1703 * @brief Check if C2AHB3 peripheral clock is enabled or not
1704 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1705 * C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_IsEnabledClock\n
1706 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1707 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1708 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_IsEnabledClock\n
1709 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock
1710 * @param Periphs This parameter can be a combination of the following values:
1711 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1712 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1713 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1714 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1715 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1716 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1717 * @retval uint32_t
1718 */
LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)1719 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1720 {
1721 return ((READ_BIT(RCC->C2AHB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
1722 }
1723
1724 /**
1725 * @brief Disable C2AHB3 peripherals clock.
1726 * @rmtoll C2AHB3ENR PKAEN LL_C2_AHB3_GRP1_DisableClock\n
1727 * C2AHB3ENR AES2EN LL_C2_AHB3_GRP1_DisableClock\n
1728 * C2AHB3ENR RNGEN LL_C2_AHB3_GRP1_DisableClock\n
1729 * C2AHB3ENR HSEMEN LL_C2_AHB3_GRP1_DisableClock\n
1730 * C2AHB3ENR IPCCEN LL_C2_AHB3_GRP1_DisableClock\n
1731 * C2AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock
1732 * @param Periphs This parameter can be a combination of the following values:
1733 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1734 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1735 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1736 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_HSEM
1737 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_IPCC
1738 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1739 * @retval None
1740 */
LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)1741 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
1742 {
1743 CLEAR_BIT(RCC->C2AHB3ENR, Periphs);
1744 }
1745
1746 /**
1747 * @brief Enable C2AHB3 peripherals clock during Low Power (Sleep) mode.
1748 * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1749 * C2AHB3SMENR AES2SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1750 * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1751 * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_EnableClockSleep\n
1752 * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_EnableClockSleep
1753 * @param Periphs This parameter can be a combination of the following values:
1754 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1755 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1756 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1757 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
1758 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1759 * @retval None
1760 */
LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)1761 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
1762 {
1763 __IO uint32_t tmpreg;
1764 SET_BIT(RCC->C2AHB3SMENR, Periphs);
1765 /* Delay after an RCC peripheral clock enabling */
1766 tmpreg = READ_BIT(RCC->C2AHB3SMENR, Periphs);
1767 (void)tmpreg;
1768 }
1769
1770 /**
1771 * @brief Disable C2AHB3 peripherals clock during Low Power (Sleep) mode.
1772 * @rmtoll C2AHB3SMENR PKASMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1773 * C2AHB3SMENR AES2SMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1774 * C2AHB3SMENR RNGSMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1775 * C2AHB3SMENR SRAM2SMEN LL_C2_AHB3_GRP1_DisableClockSleep\n
1776 * C2AHB3SMENR FLASHSMEN LL_C2_AHB3_GRP1_DisableClockSleep
1777 * @param Periphs This parameter can be a combination of the following values:
1778 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_PKA
1779 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_AES2
1780 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_RNG
1781 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_SRAM2
1782 * @arg @ref LL_C2_AHB3_GRP1_PERIPH_FLASH
1783 * @retval None
1784 */
LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)1785 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
1786 {
1787 CLEAR_BIT(RCC->C2AHB3SMENR, Periphs);
1788 }
1789
1790 /**
1791 * @}
1792 */
1793
1794 /** @defgroup BUS_LL_EF_C2_APB1 C2 APB1
1795 * @{
1796 */
1797
1798 /**
1799 * @brief Enable C2APB1 peripherals clock.
1800 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_EnableClock\n
1801 * C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_EnableClock\n
1802 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_EnableClock\n
1803 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_EnableClock\n
1804 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_EnableClock\n
1805 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_EnableClock\n
1806 * C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_EnableClock\n
1807 * C2APB1ENR1 USBEN LL_C2_APB1_GRP1_EnableClock\n
1808 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_EnableClock
1809 * @param Periphs This parameter can be a combination of the following values:
1810 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1811 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
1812 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1813 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
1814 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
1815 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
1816 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
1817 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
1818 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
1819 * @retval None
1820 */
LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)1821 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
1822 {
1823 __IO uint32_t tmpreg;
1824 SET_BIT(RCC->C2APB1ENR1, Periphs);
1825 /* Delay after an RCC peripheral clock enabling */
1826 tmpreg = READ_BIT(RCC->C2APB1ENR1, Periphs);
1827 (void)tmpreg;
1828 }
1829
1830 /**
1831 * @brief Enable C2APB1 peripherals clock.
1832 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_EnableClock\n
1833 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_EnableClock
1834 * @param Periphs This parameter can be a combination of the following values:
1835 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
1836 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
1837 * @retval None
1838 */
LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)1839 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
1840 {
1841 __IO uint32_t tmpreg;
1842 SET_BIT(RCC->C2APB1ENR2, Periphs);
1843 /* Delay after an RCC peripheral clock enabling */
1844 tmpreg = READ_BIT(RCC->C2APB1ENR2, Periphs);
1845 (void)tmpreg;
1846 }
1847
1848 /**
1849 * @brief Check if C2APB1 peripheral clock is enabled or not
1850 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n
1851 * C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_IsEnabledClock\n
1852 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_IsEnabledClock\n
1853 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n
1854 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n
1855 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n
1856 * C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_IsEnabledClock\n
1857 * C2APB1ENR1 USBEN LL_C2_APB1_GRP1_IsEnabledClock\n
1858 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock
1859 * @param Periphs This parameter can be a combination of the following values:
1860 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1861 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
1862 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1863 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
1864 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
1865 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
1866 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
1867 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
1868 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
1869 * @retval uint32_t
1870 */
LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1871 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1872 {
1873 return ((READ_BIT(RCC->C2APB1ENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
1874 }
1875
1876 /**
1877 * @brief Check if C2APB1 peripheral clock is enabled or not
1878 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_IsEnabledClock\n
1879 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_IsEnabledClock
1880 * @param Periphs This parameter can be a combination of the following values:
1881 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
1882 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
1883 * @retval uint32_t
1884 */
LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1885 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1886 {
1887 return ((READ_BIT(RCC->C2APB1ENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
1888 }
1889
1890 /**
1891 * @brief Disable C2APB1 peripherals clock.
1892 * @rmtoll C2APB1ENR1 TIM2EN LL_C2_APB1_GRP1_DisableClock\n
1893 * C2APB1ENR1 LCDEN LL_C2_APB1_GRP1_DisableClock\n
1894 * C2APB1ENR1 RTCAPBEN LL_C2_APB1_GRP1_DisableClock\n
1895 * C2APB1ENR1 SPI2EN LL_C2_APB1_GRP1_DisableClock\n
1896 * C2APB1ENR1 I2C1EN LL_C2_APB1_GRP1_DisableClock\n
1897 * C2APB1ENR1 I2C3EN LL_C2_APB1_GRP1_DisableClock\n
1898 * C2APB1ENR1 CRSEN LL_C2_APB1_GRP1_DisableClock\n
1899 * C2APB1ENR1 USBEN LL_C2_APB1_GRP1_DisableClock\n
1900 * C2APB1ENR1 LPTIM1EN LL_C2_APB1_GRP1_DisableClock
1901 * @param Periphs This parameter can be a combination of the following values:
1902 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1903 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
1904 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1905 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
1906 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
1907 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
1908 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
1909 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
1910 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
1911 * @retval None
1912 */
LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)1913 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
1914 {
1915 CLEAR_BIT(RCC->C2APB1ENR1, Periphs);
1916 }
1917
1918 /**
1919 * @brief Disable C2APB1 peripherals clock.
1920 * @rmtoll C2APB1ENR2 LPUART1EN LL_C2_APB1_GRP2_DisableClock\n
1921 * C2APB1ENR2 LPTIM2EN LL_C2_APB1_GRP2_DisableClock
1922 * @param Periphs This parameter can be a combination of the following values:
1923 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
1924 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
1925 * @retval None
1926 */
LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)1927 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
1928 {
1929 CLEAR_BIT(RCC->C2APB1ENR2, Periphs);
1930 }
1931
1932 /**
1933 * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
1934 * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1935 * C2APB1SMENR1 LCDSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1936 * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1937 * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1938 * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1939 * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1940 * C2APB1SMENR1 CRSSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1941 * C2APB1SMENR1 USBSMEN LL_C2_APB1_GRP1_EnableClockSleep\n
1942 * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_EnableClockSleep
1943 * @param Periphs This parameter can be a combination of the following values:
1944 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1945 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
1946 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1947 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
1948 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
1949 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
1950 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
1951 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
1952 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
1953 * @retval None
1954 */
LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)1955 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
1956 {
1957 __IO uint32_t tmpreg;
1958 SET_BIT(RCC->C2APB1SMENR1, Periphs);
1959 /* Delay after an RCC peripheral clock enabling */
1960 tmpreg = READ_BIT(RCC->C2APB1SMENR1, Periphs);
1961 (void)tmpreg;
1962 }
1963
1964 /**
1965 * @brief Enable C2APB1 peripherals clock during Low Power (Sleep) mode.
1966 * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_EnableClockSleep\n
1967 * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_EnableClockSleep
1968 * @param Periphs This parameter can be a combination of the following values:
1969 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
1970 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
1971 * @retval None
1972 */
LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)1973 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
1974 {
1975 __IO uint32_t tmpreg;
1976 SET_BIT(RCC->C2APB1SMENR2, Periphs);
1977 /* Delay after an RCC peripheral clock enabling */
1978 tmpreg = READ_BIT(RCC->C2APB1SMENR2, Periphs);
1979 (void)tmpreg;
1980 }
1981
1982 /**
1983 * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
1984 * @rmtoll C2APB1SMENR1 TIM2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1985 * C2APB1SMENR1 LCDSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1986 * C2APB1SMENR1 RTCAPBSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1987 * C2APB1SMENR1 SPI2SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1988 * C2APB1SMENR1 I2C1SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1989 * C2APB1SMENR1 I2C3SMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1990 * C2APB1SMENR1 CRSSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1991 * C2APB1SMENR1 USBSMEN LL_C2_APB1_GRP1_DisableClockSleep\n
1992 * C2APB1SMENR1 LPTIM1SMEN LL_C2_APB1_GRP1_DisableClockSleep
1993 * @param Periphs This parameter can be a combination of the following values:
1994 * @arg @ref LL_C2_APB1_GRP1_PERIPH_TIM2
1995 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LCD
1996 * @arg @ref LL_C2_APB1_GRP1_PERIPH_RTCAPB
1997 * @arg @ref LL_C2_APB1_GRP1_PERIPH_SPI2
1998 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C1
1999 * @arg @ref LL_C2_APB1_GRP1_PERIPH_I2C3
2000 * @arg @ref LL_C2_APB1_GRP1_PERIPH_CRS
2001 * @arg @ref LL_C2_APB1_GRP1_PERIPH_USB
2002 * @arg @ref LL_C2_APB1_GRP1_PERIPH_LPTIM1
2003 * @retval None
2004 */
LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)2005 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
2006 {
2007 CLEAR_BIT(RCC->C2APB1SMENR1, Periphs);
2008 }
2009
2010 /**
2011 * @brief Disable C2APB1 peripherals clock during Low Power (Sleep) mode.
2012 * @rmtoll C2APB1SMENR2 LPUART1SMEN LL_C2_APB1_GRP2_DisableClockSleep\n
2013 * C2APB1SMENR2 LPTIM2SMEN LL_C2_APB1_GRP2_DisableClockSleep
2014 * @param Periphs This parameter can be a combination of the following values:
2015 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPUART1
2016 * @arg @ref LL_C2_APB1_GRP2_PERIPH_LPTIM2
2017 * @retval None
2018 */
LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)2019 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
2020 {
2021 CLEAR_BIT(RCC->C2APB1SMENR2, Periphs);
2022 }
2023
2024 /**
2025 * @}
2026 */
2027
2028 /** @defgroup BUS_LL_EF_C2_APB2 C2 APB2
2029 * @{
2030 */
2031
2032 /**
2033 * @brief Enable C2APB2 peripherals clock.
2034 * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n
2035 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n
2036 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n
2037 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n
2038 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n
2039 * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock
2040 * @param Periphs This parameter can be a combination of the following values:
2041 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2042 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2043 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2044 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2045 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2046 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
2047 * @retval None
2048 */
LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)2049 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
2050 {
2051 __IO uint32_t tmpreg;
2052 SET_BIT(RCC->C2APB2ENR, Periphs);
2053 /* Delay after an RCC peripheral clock enabling */
2054 tmpreg = READ_BIT(RCC->C2APB2ENR, Periphs);
2055 (void)tmpreg;
2056 }
2057
2058 /**
2059 * @brief Check if C2APB2 peripheral clock is enabled or not
2060 * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2061 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2062 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n
2063 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n
2064 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n
2065 * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock
2066 * @param Periphs This parameter can be a combination of the following values:
2067 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2068 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2069 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2070 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2071 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2072 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
2073 * @retval uint32_t
2074 */
LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)2075 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
2076 {
2077 return ((READ_BIT(RCC->C2APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2078 }
2079
2080 /**
2081 * @brief Disable C2APB2 peripherals clock.
2082 * @rmtoll C2APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n
2083 * C2APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n
2084 * C2APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n
2085 * C2APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n
2086 * C2APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n
2087 * C2APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock
2088 * @param Periphs This parameter can be a combination of the following values:
2089 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2090 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2091 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2092 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2093 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2094 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
2095 * @retval None
2096 */
LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)2097 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
2098 {
2099 CLEAR_BIT(RCC->C2APB2ENR, Periphs);
2100 }
2101
2102 /**
2103 * @brief Enable C2APB2 peripherals clock during Low Power (Sleep) mode.
2104 * @rmtoll C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2105 * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2106 * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2107 * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2108 * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_EnableClockSleep\n
2109 * C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_EnableClockSleep
2110 * @param Periphs This parameter can be a combination of the following values:
2111 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2112 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2113 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2114 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2115 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2116 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
2117 * @retval None
2118 */
LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)2119 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
2120 {
2121 __IO uint32_t tmpreg;
2122 SET_BIT(RCC->C2APB2SMENR, Periphs);
2123 /* Delay after an RCC peripheral clock enabling */
2124 tmpreg = READ_BIT(RCC->C2APB2SMENR, Periphs);
2125 (void)tmpreg;
2126 }
2127
2128 /**
2129 * @brief Disable C2APB2 peripherals clock during Low Power (Sleep) mode.
2130 * @rmtoll C2APB2SMENR TIM1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2131 * C2APB2SMENR SPI1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2132 * C2APB2SMENR USART1SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2133 * C2APB2SMENR TIM16SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2134 * C2APB2SMENR TIM17SMEN LL_C2_APB2_GRP1_DisableClockSleep\n
2135 * C2APB2SMENR SAI1SMEN LL_C2_APB2_GRP1_DisableClockSleep
2136 * @param Periphs This parameter can be a combination of the following values:
2137 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM1
2138 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SPI1
2139 * @arg @ref LL_C2_APB2_GRP1_PERIPH_USART1
2140 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM16
2141 * @arg @ref LL_C2_APB2_GRP1_PERIPH_TIM17
2142 * @arg @ref LL_C2_APB2_GRP1_PERIPH_SAI1
2143 * @retval None
2144 */
LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)2145 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
2146 {
2147 CLEAR_BIT(RCC->C2APB2SMENR, Periphs);
2148 }
2149
2150 /**
2151 * @}
2152 */
2153
2154 /** @defgroup BUS_LL_EF_C2_APB3 C2 APB3
2155 * @{
2156 */
2157
2158 /**
2159 * @brief Enable C2APB3 peripherals clock.
2160 * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_EnableClock\n
2161 * C2APB3ENR 802EN LL_C2_APB3_GRP1_EnableClock
2162 * @param Periphs This parameter can be a combination of the following values:
2163 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2164 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
2165 * @retval None
2166 */
LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)2167 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
2168 {
2169 __IO uint32_t tmpreg;
2170 SET_BIT(RCC->C2APB3ENR, Periphs);
2171 /* Delay after an RCC peripheral clock enabling */
2172 tmpreg = READ_BIT(RCC->C2APB3ENR, Periphs);
2173 (void)tmpreg;
2174 }
2175
2176 /**
2177 * @brief Check if C2APB3 peripheral clock is enabled or not
2178 * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_IsEnabledClock\n
2179 * C2APB3ENR 802EN LL_C2_APB3_GRP1_IsEnabledClock
2180 * @param Periphs This parameter can be a combination of the following values:
2181 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2182 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
2183 * @retval uint32_t
2184 */
LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)2185 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
2186 {
2187 return ((READ_BIT(RCC->C2APB3ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
2188 }
2189
2190 /**
2191 * @brief Disable C2APB3 peripherals clock.
2192 * @rmtoll C2APB3ENR BLEEN LL_C2_APB3_GRP1_DisableClock\n
2193 * C2APB3ENR 802EN LL_C2_APB3_GRP1_DisableClock
2194 * @param Periphs This parameter can be a combination of the following values:
2195 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2196 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
2197 * @retval None
2198 */
LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)2199 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
2200 {
2201 CLEAR_BIT(RCC->C2APB3ENR, Periphs);
2202 }
2203
2204 /**
2205 * @brief Enable C2APB3 peripherals clock during Low Power (Sleep) mode.
2206 * @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_EnableClockSleep\n
2207 * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_EnableClockSleep
2208 * @param Periphs This parameter can be a combination of the following values:
2209 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2210 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
2211 * @retval None
2212 */
LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)2213 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
2214 {
2215 __IO uint32_t tmpreg;
2216 SET_BIT(RCC->C2APB3SMENR, Periphs);
2217 /* Delay after an RCC peripheral clock enabling */
2218 tmpreg = READ_BIT(RCC->C2APB3SMENR, Periphs);
2219 (void)tmpreg;
2220 }
2221
2222 /**
2223 * @brief Disable C2APB3 peripherals clock during Low Power (Sleep) mode.
2224 * @rmtoll C2APB3SMENR BLESMEN LL_C2_APB3_GRP1_DisableClockSleep\n
2225 * C2APB3SMENR 802SMEN LL_C2_APB3_GRP1_DisableClockSleep
2226 * @param Periphs This parameter can be a combination of the following values:
2227 * @arg @ref LL_C2_APB3_GRP1_PERIPH_BLE
2228 * @arg @ref LL_C2_APB3_GRP1_PERIPH_802
2229 * @retval None
2230 */
LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)2231 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
2232 {
2233 CLEAR_BIT(RCC->C2APB3SMENR, Periphs);
2234 }
2235
2236 /**
2237 * @}
2238 */
2239
2240 /**
2241 * @}
2242 */
2243
2244 /**
2245 * @}
2246 */
2247
2248 #endif /* defined(RCC) */
2249
2250 /**
2251 * @}
2252 */
2253
2254 #ifdef __cplusplus
2255 }
2256 #endif
2257
2258 #endif /* STM32WBxx_LL_BUS_H */
2259
2260 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2261