1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_TIM_H 22 #define STM32WBxx_HAL_TIM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 31 /** @addtogroup STM32WBxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TIM_Exported_Types TIM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TIM Time base Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 51 52 uint32_t CounterMode; /*!< Specifies the counter mode. 53 This parameter can be a value of @ref TIM_Counter_Mode */ 54 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active 56 Auto-Reload Register at the next update event. 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 58 59 uint32_t ClockDivision; /*!< Specifies the clock division. 60 This parameter can be a value of @ref TIM_ClockDivision */ 61 62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 63 reaches zero, an update event is generated and counting restarts 64 from the RCR value (N). 65 This means in PWM mode that (N+1) corresponds to: 66 - the number of PWM periods in edge-aligned mode 67 - the number of half PWM period in center-aligned mode 68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 70 71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 72 This parameter can be a value of @ref TIM_AutoReloadPreload */ 73 } TIM_Base_InitTypeDef; 74 75 /** 76 * @brief TIM Output Compare Configuration Structure definition 77 */ 78 typedef struct 79 { 80 uint32_t OCMode; /*!< Specifies the TIM mode. 81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 82 83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 85 86 uint32_t OCPolarity; /*!< Specifies the output polarity. 87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 88 89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 91 @note This parameter is valid only for timer instances supporting break feature. */ 92 93 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 94 This parameter can be a value of @ref TIM_Output_Fast_State 95 @note This parameter is valid only in PWM1 and PWM2 mode. */ 96 97 98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 100 @note This parameter is valid only for timer instances supporting break feature. */ 101 102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 104 @note This parameter is valid only for timer instances supporting break feature. */ 105 } TIM_OC_InitTypeDef; 106 107 /** 108 * @brief TIM One Pulse Mode Configuration Structure definition 109 */ 110 typedef struct 111 { 112 uint32_t OCMode; /*!< Specifies the TIM mode. 113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 114 115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 117 118 uint32_t OCPolarity; /*!< Specifies the output polarity. 119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 120 121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 123 @note This parameter is valid only for timer instances supporting break feature. */ 124 125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 127 @note This parameter is valid only for timer instances supporting break feature. */ 128 129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 131 @note This parameter is valid only for timer instances supporting break feature. */ 132 133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 135 136 uint32_t ICSelection; /*!< Specifies the input. 137 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 138 139 uint32_t ICFilter; /*!< Specifies the input capture filter. 140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 141 } TIM_OnePulse_InitTypeDef; 142 143 /** 144 * @brief TIM Input Capture Configuration Structure definition 145 */ 146 typedef struct 147 { 148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 150 151 uint32_t ICSelection; /*!< Specifies the input. 152 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 153 154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 156 157 uint32_t ICFilter; /*!< Specifies the input capture filter. 158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 159 } TIM_IC_InitTypeDef; 160 161 /** 162 * @brief TIM Encoder Configuration Structure definition 163 */ 164 typedef struct 165 { 166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 167 This parameter can be a value of @ref TIM_Encoder_Mode */ 168 169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 170 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 171 172 uint32_t IC1Selection; /*!< Specifies the input. 173 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 174 175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 177 178 uint32_t IC1Filter; /*!< Specifies the input capture filter. 179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 180 181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 182 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 183 184 uint32_t IC2Selection; /*!< Specifies the input. 185 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 186 187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 189 190 uint32_t IC2Filter; /*!< Specifies the input capture filter. 191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 192 } TIM_Encoder_InitTypeDef; 193 194 /** 195 * @brief Clock Configuration Handle Structure definition 196 */ 197 typedef struct 198 { 199 uint32_t ClockSource; /*!< TIM clock sources 200 This parameter can be a value of @ref TIM_Clock_Source */ 201 uint32_t ClockPolarity; /*!< TIM clock polarity 202 This parameter can be a value of @ref TIM_Clock_Polarity */ 203 uint32_t ClockPrescaler; /*!< TIM clock prescaler 204 This parameter can be a value of @ref TIM_Clock_Prescaler */ 205 uint32_t ClockFilter; /*!< TIM clock filter 206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 207 } TIM_ClockConfigTypeDef; 208 209 /** 210 * @brief TIM Clear Input Configuration Handle Structure definition 211 */ 212 typedef struct 213 { 214 uint32_t ClearInputState; /*!< TIM clear Input state 215 This parameter can be ENABLE or DISABLE */ 216 uint32_t ClearInputSource; /*!< TIM clear Input sources 217 This parameter can be a value of @ref TIM_ClearInput_Source */ 218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 219 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ 222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 224 } TIM_ClearInputConfigTypeDef; 225 226 /** 227 * @brief TIM Master configuration Structure definition 228 * @note Advanced timers provide TRGO2 internal line which is redirected 229 * to the ADC 230 */ 231 typedef struct 232 { 233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 234 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 235 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 236 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 237 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 238 This parameter can be a value of @ref TIM_Master_Slave_Mode 239 @note When the Master/slave mode is enabled, the effect of 240 an event on the trigger input (TRGI) is delayed to allow a 241 perfect synchronization between the current timer and its 242 slaves (through TRGO). It is not mandatory in case of timer 243 synchronization mode. */ 244 } TIM_MasterConfigTypeDef; 245 246 /** 247 * @brief TIM Slave configuration Structure definition 248 */ 249 typedef struct 250 { 251 uint32_t SlaveMode; /*!< Slave mode selection 252 This parameter can be a value of @ref TIM_Slave_Mode */ 253 uint32_t InputTrigger; /*!< Input Trigger source 254 This parameter can be a value of @ref TIM_Trigger_Selection */ 255 uint32_t TriggerPolarity; /*!< Input Trigger polarity 256 This parameter can be a value of @ref TIM_Trigger_Polarity */ 257 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 258 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 259 uint32_t TriggerFilter; /*!< Input trigger filter 260 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 261 262 } TIM_SlaveConfigTypeDef; 263 264 /** 265 * @brief TIM Break input(s) and Dead time configuration Structure definition 266 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 267 * filter and polarity. 268 */ 269 typedef struct 270 { 271 uint32_t OffStateRunMode; /*!< TIM off state in run mode 272 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 273 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 274 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 275 uint32_t LockLevel; /*!< TIM Lock level 276 This parameter can be a value of @ref TIM_Lock_level */ 277 uint32_t DeadTime; /*!< TIM dead Time 278 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 279 uint32_t BreakState; /*!< TIM Break State 280 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 281 uint32_t BreakPolarity; /*!< TIM Break input polarity 282 This parameter can be a value of @ref TIM_Break_Polarity */ 283 uint32_t BreakFilter; /*!< Specifies the break input filter. 284 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 285 uint32_t Break2State; /*!< TIM Break2 State 286 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 287 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 288 This parameter can be a value of @ref TIM_Break2_Polarity */ 289 uint32_t Break2Filter; /*!< TIM break2 input filter. 290 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 291 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 292 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 293 } TIM_BreakDeadTimeConfigTypeDef; 294 295 /** 296 * @brief HAL State structures definition 297 */ 298 typedef enum 299 { 300 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 301 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 302 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 303 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 304 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 305 } HAL_TIM_StateTypeDef; 306 307 /** 308 * @brief HAL Active channel structures definition 309 */ 310 typedef enum 311 { 312 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 313 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 314 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 315 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 316 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 317 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 318 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 319 } HAL_TIM_ActiveChannel; 320 321 /** 322 * @brief TIM Time Base Handle Structure definition 323 */ 324 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 325 typedef struct __TIM_HandleTypeDef 326 #else 327 typedef struct 328 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 329 { 330 TIM_TypeDef *Instance; /*!< Register base address */ 331 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 332 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 333 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 334 This array is accessed by a @ref DMA_Handle_index */ 335 HAL_LockTypeDef Lock; /*!< Locking object */ 336 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 337 338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 339 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 340 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 341 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 342 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 343 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 344 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 345 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 346 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 347 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 348 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 349 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 350 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 351 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 352 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 353 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 354 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 355 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 356 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 357 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 358 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 359 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 360 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 361 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 362 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 363 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 364 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 365 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 366 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 367 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 368 } TIM_HandleTypeDef; 369 370 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 371 /** 372 * @brief HAL TIM Callback ID enumeration definition 373 */ 374 typedef enum 375 { 376 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 377 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 378 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 379 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 380 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 381 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 382 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 383 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 384 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 385 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 386 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 387 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 388 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 389 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 390 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 391 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 392 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 393 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 394 395 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 396 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 397 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 398 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 399 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 400 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 401 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 402 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 403 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 404 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 405 } HAL_TIM_CallbackIDTypeDef; 406 407 /** 408 * @brief HAL TIM Callback pointer definition 409 */ 410 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 411 412 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 413 414 /** 415 * @} 416 */ 417 /* End of exported types -----------------------------------------------------*/ 418 419 /* Exported constants --------------------------------------------------------*/ 420 /** @defgroup TIM_Exported_Constants TIM Exported Constants 421 * @{ 422 */ 423 424 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 425 * @{ 426 */ 427 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 428 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 429 #define TIM_CLEARINPUTSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< OCREF_CLR_INT is connected to COMP1 output */ 430 #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< OCREF_CLR_INT is connected to COMP2 output */ 431 /** 432 * @} 433 */ 434 435 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 436 * @{ 437 */ 438 #define TIM_DMABASE_CR1 0x00000000U 439 #define TIM_DMABASE_CR2 0x00000001U 440 #define TIM_DMABASE_SMCR 0x00000002U 441 #define TIM_DMABASE_DIER 0x00000003U 442 #define TIM_DMABASE_SR 0x00000004U 443 #define TIM_DMABASE_EGR 0x00000005U 444 #define TIM_DMABASE_CCMR1 0x00000006U 445 #define TIM_DMABASE_CCMR2 0x00000007U 446 #define TIM_DMABASE_CCER 0x00000008U 447 #define TIM_DMABASE_CNT 0x00000009U 448 #define TIM_DMABASE_PSC 0x0000000AU 449 #define TIM_DMABASE_ARR 0x0000000BU 450 #define TIM_DMABASE_RCR 0x0000000CU 451 #define TIM_DMABASE_CCR1 0x0000000DU 452 #define TIM_DMABASE_CCR2 0x0000000EU 453 #define TIM_DMABASE_CCR3 0x0000000FU 454 #define TIM_DMABASE_CCR4 0x00000010U 455 #define TIM_DMABASE_BDTR 0x00000011U 456 #define TIM_DMABASE_DCR 0x00000012U 457 #define TIM_DMABASE_DMAR 0x00000013U 458 #define TIM_DMABASE_OR 0x00000014U 459 #define TIM_DMABASE_CCMR3 0x00000015U 460 #define TIM_DMABASE_CCR5 0x00000016U 461 #define TIM_DMABASE_CCR6 0x00000017U 462 #define TIM_DMABASE_AF1 0x00000018U 463 #define TIM_DMABASE_AF2 0x00000019U 464 /** 465 * @} 466 */ 467 468 /** @defgroup TIM_Event_Source TIM Event Source 469 * @{ 470 */ 471 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 472 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 473 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 474 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 475 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 476 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 477 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 478 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 479 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 480 /** 481 * @} 482 */ 483 484 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 485 * @{ 486 */ 487 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 488 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 489 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 490 /** 491 * @} 492 */ 493 494 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 495 * @{ 496 */ 497 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 498 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 499 /** 500 * @} 501 */ 502 503 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 504 * @{ 505 */ 506 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 507 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 508 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 509 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 510 /** 511 * @} 512 */ 513 514 /** @defgroup TIM_Counter_Mode TIM Counter Mode 515 * @{ 516 */ 517 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 518 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 519 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 520 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 521 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 522 /** 523 * @} 524 */ 525 526 /** @defgroup TIM_ClockDivision TIM Clock Division 527 * @{ 528 */ 529 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 530 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 531 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 537 * @{ 538 */ 539 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 540 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 546 * @{ 547 */ 548 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 549 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 550 551 /** 552 * @} 553 */ 554 555 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 556 * @{ 557 */ 558 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 559 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 560 /** 561 * @} 562 */ 563 564 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 565 * @{ 566 */ 567 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 568 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 569 /** 570 * @} 571 */ 572 573 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 574 * @{ 575 */ 576 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 577 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 578 /** 579 * @} 580 */ 581 582 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 583 * @{ 584 */ 585 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 586 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 592 * @{ 593 */ 594 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 595 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 596 /** 597 * @} 598 */ 599 600 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 601 * @{ 602 */ 603 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 604 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 605 /** 606 * @} 607 */ 608 609 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 610 * @{ 611 */ 612 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 613 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 614 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 615 /** 616 * @} 617 */ 618 619 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 620 * @{ 621 */ 622 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 623 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 629 * @{ 630 */ 631 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 632 connected to IC1, IC2, IC3 or IC4, respectively */ 633 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 634 connected to IC2, IC1, IC4 or IC3, respectively */ 635 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 641 * @{ 642 */ 643 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 644 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 645 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 646 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 652 * @{ 653 */ 654 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 655 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 661 * @{ 662 */ 663 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 664 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 665 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 666 /** 667 * @} 668 */ 669 670 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 671 * @{ 672 */ 673 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 674 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 675 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 676 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 677 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 678 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 679 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 680 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 681 /** 682 * @} 683 */ 684 685 /** @defgroup TIM_Commutation_Source TIM Commutation Source 686 * @{ 687 */ 688 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 689 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 690 /** 691 * @} 692 */ 693 694 /** @defgroup TIM_DMA_sources TIM DMA Sources 695 * @{ 696 */ 697 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 698 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 699 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 700 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 701 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 702 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 703 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 704 /** 705 * @} 706 */ 707 708 /** @defgroup TIM_Flag_definition TIM Flag Definition 709 * @{ 710 */ 711 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 712 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 713 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 714 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 715 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 716 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 717 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 718 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 719 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 720 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 721 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 722 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 723 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 724 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 725 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 726 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 727 /** 728 * @} 729 */ 730 731 /** @defgroup TIM_Channel TIM Channel 732 * @{ 733 */ 734 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 735 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 736 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 737 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 738 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 739 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 740 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 741 /** 742 * @} 743 */ 744 745 /** @defgroup TIM_Clock_Source TIM Clock Source 746 * @{ 747 */ 748 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 749 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 750 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 751 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 752 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 753 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 754 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 755 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 756 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 757 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 758 /** 759 * @} 760 */ 761 762 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 763 * @{ 764 */ 765 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 766 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 767 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 768 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 769 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 770 /** 771 * @} 772 */ 773 774 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 775 * @{ 776 */ 777 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 778 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 779 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 780 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 781 /** 782 * @} 783 */ 784 785 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 786 * @{ 787 */ 788 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 789 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 790 /** 791 * @} 792 */ 793 794 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 795 * @{ 796 */ 797 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 798 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 799 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 800 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 801 /** 802 * @} 803 */ 804 805 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 806 * @{ 807 */ 808 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 809 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 810 /** 811 * @} 812 */ 813 814 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 815 * @{ 816 */ 817 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 818 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 819 /** 820 * @} 821 */ 822 /** @defgroup TIM_Lock_level TIM Lock level 823 * @{ 824 */ 825 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 826 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 827 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 828 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 829 /** 830 * @} 831 */ 832 833 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 834 * @{ 835 */ 836 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 837 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 838 /** 839 * @} 840 */ 841 842 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 843 * @{ 844 */ 845 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 846 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 847 /** 848 * @} 849 */ 850 851 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 852 * @{ 853 */ 854 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 855 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 856 /** 857 * @} 858 */ 859 860 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 861 * @{ 862 */ 863 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 864 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 865 /** 866 * @} 867 */ 868 869 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 870 * @{ 871 */ 872 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 873 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 874 (if none of the break inputs BRK and BRK2 is active) */ 875 /** 876 * @} 877 */ 878 879 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 880 * @{ 881 */ 882 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 883 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 884 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 885 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 886 /** 887 * @} 888 */ 889 890 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 891 * @{ 892 */ 893 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 894 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 895 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 896 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 897 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 898 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 899 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 900 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 901 /** 902 * @} 903 */ 904 905 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 906 * @{ 907 */ 908 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 909 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 910 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 911 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 912 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 913 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 914 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 915 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 916 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 917 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 918 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 919 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 920 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 921 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 922 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 923 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 924 /** 925 * @} 926 */ 927 928 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 929 * @{ 930 */ 931 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 932 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 933 /** 934 * @} 935 */ 936 937 /** @defgroup TIM_Slave_Mode TIM Slave mode 938 * @{ 939 */ 940 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 941 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 942 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 943 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 944 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 945 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 946 /** 947 * @} 948 */ 949 950 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 951 * @{ 952 */ 953 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 954 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 955 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 956 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 957 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 958 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 959 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 960 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 961 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 962 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 963 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 964 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 965 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 966 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 967 /** 968 * @} 969 */ 970 971 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 972 * @{ 973 */ 974 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 975 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 976 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 977 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 978 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 979 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 980 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 981 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 982 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 983 /** 984 * @} 985 */ 986 987 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 988 * @{ 989 */ 990 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 991 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 992 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 993 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 994 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 995 /** 996 * @} 997 */ 998 999 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1000 * @{ 1001 */ 1002 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1003 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1004 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1005 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1006 /** 1007 * @} 1008 */ 1009 1010 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1011 * @{ 1012 */ 1013 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1014 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1015 /** 1016 * @} 1017 */ 1018 1019 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1020 * @{ 1021 */ 1022 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1023 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1024 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1025 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1026 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1027 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1028 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1029 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1030 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1031 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1032 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1033 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1034 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1035 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1036 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1037 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1038 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1039 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1040 /** 1041 * @} 1042 */ 1043 1044 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1045 * @{ 1046 */ 1047 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1048 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1049 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1050 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1051 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1052 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1053 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1054 /** 1055 * @} 1056 */ 1057 1058 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1059 * @{ 1060 */ 1061 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1062 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1063 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1064 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1065 /** 1066 * @} 1067 */ 1068 1069 /** @defgroup TIM_Break_System TIM Break System 1070 * @{ 1071 */ 1072 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ 1073 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1074 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ 1075 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 1076 /** 1077 * @} 1078 */ 1079 1080 /** 1081 * @} 1082 */ 1083 /* End of exported constants -------------------------------------------------*/ 1084 1085 /* Exported macros -----------------------------------------------------------*/ 1086 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1087 * @{ 1088 */ 1089 1090 /** @brief Reset TIM handle state. 1091 * @param __HANDLE__ TIM handle. 1092 * @retval None 1093 */ 1094 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1095 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1096 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1097 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1098 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1099 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1100 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1101 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1102 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1103 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1104 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1105 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1106 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1107 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1108 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1109 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1110 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1111 } while(0) 1112 #else 1113 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 1114 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1115 1116 /** 1117 * @brief Enable the TIM peripheral. 1118 * @param __HANDLE__ TIM handle 1119 * @retval None 1120 */ 1121 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1122 1123 /** 1124 * @brief Enable the TIM main Output. 1125 * @param __HANDLE__ TIM handle 1126 * @retval None 1127 */ 1128 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1129 1130 /** 1131 * @brief Disable the TIM peripheral. 1132 * @param __HANDLE__ TIM handle 1133 * @retval None 1134 */ 1135 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1136 do { \ 1137 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1138 { \ 1139 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1140 { \ 1141 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1142 } \ 1143 } \ 1144 } while(0) 1145 1146 /** 1147 * @brief Disable the TIM main Output. 1148 * @param __HANDLE__ TIM handle 1149 * @retval None 1150 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1151 */ 1152 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1153 do { \ 1154 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1155 { \ 1156 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1157 { \ 1158 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1159 } \ 1160 } \ 1161 } while(0) 1162 1163 /** 1164 * @brief Disable the TIM main Output. 1165 * @param __HANDLE__ TIM handle 1166 * @retval None 1167 * @note The Main Output Enable of a timer instance is disabled unconditionally 1168 */ 1169 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1170 1171 /** @brief Enable the specified TIM interrupt. 1172 * @param __HANDLE__ specifies the TIM Handle. 1173 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1174 * This parameter can be one of the following values: 1175 * @arg TIM_IT_UPDATE: Update interrupt 1176 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1177 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1178 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1179 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1180 * @arg TIM_IT_COM: Commutation interrupt 1181 * @arg TIM_IT_TRIGGER: Trigger interrupt 1182 * @arg TIM_IT_BREAK: Break interrupt 1183 * @retval None 1184 */ 1185 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1186 1187 /** @brief Disable the specified TIM interrupt. 1188 * @param __HANDLE__ specifies the TIM Handle. 1189 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1190 * This parameter can be one of the following values: 1191 * @arg TIM_IT_UPDATE: Update interrupt 1192 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1193 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1194 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1195 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1196 * @arg TIM_IT_COM: Commutation interrupt 1197 * @arg TIM_IT_TRIGGER: Trigger interrupt 1198 * @arg TIM_IT_BREAK: Break interrupt 1199 * @retval None 1200 */ 1201 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1202 1203 /** @brief Enable the specified DMA request. 1204 * @param __HANDLE__ specifies the TIM Handle. 1205 * @param __DMA__ specifies the TIM DMA request to enable. 1206 * This parameter can be one of the following values: 1207 * @arg TIM_DMA_UPDATE: Update DMA request 1208 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1209 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1210 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1211 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1212 * @arg TIM_DMA_COM: Commutation DMA request 1213 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1214 * @retval None 1215 */ 1216 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1217 1218 /** @brief Disable the specified DMA request. 1219 * @param __HANDLE__ specifies the TIM Handle. 1220 * @param __DMA__ specifies the TIM DMA request to disable. 1221 * This parameter can be one of the following values: 1222 * @arg TIM_DMA_UPDATE: Update DMA request 1223 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1224 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1225 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1226 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1227 * @arg TIM_DMA_COM: Commutation DMA request 1228 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1229 * @retval None 1230 */ 1231 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1232 1233 /** @brief Check whether the specified TIM interrupt flag is set or not. 1234 * @param __HANDLE__ specifies the TIM Handle. 1235 * @param __FLAG__ specifies the TIM interrupt flag to check. 1236 * This parameter can be one of the following values: 1237 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1238 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1239 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1240 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1241 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1242 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1243 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1244 * @arg TIM_FLAG_COM: Commutation interrupt flag 1245 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1246 * @arg TIM_FLAG_BREAK: Break interrupt flag 1247 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1248 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1249 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1250 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1251 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1252 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1253 * @retval The new state of __FLAG__ (TRUE or FALSE). 1254 */ 1255 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1256 1257 /** @brief Clear the specified TIM interrupt flag. 1258 * @param __HANDLE__ specifies the TIM Handle. 1259 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1260 * This parameter can be one of the following values: 1261 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1262 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1263 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1264 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1265 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1266 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1267 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1268 * @arg TIM_FLAG_COM: Commutation interrupt flag 1269 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1270 * @arg TIM_FLAG_BREAK: Break interrupt flag 1271 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1272 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1273 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1274 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1275 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1276 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1277 * @retval The new state of __FLAG__ (TRUE or FALSE). 1278 */ 1279 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1280 1281 /** 1282 * @brief Check whether the specified TIM interrupt source is enabled or not. 1283 * @param __HANDLE__ TIM handle 1284 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1285 * This parameter can be one of the following values: 1286 * @arg TIM_IT_UPDATE: Update interrupt 1287 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1288 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1289 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1290 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1291 * @arg TIM_IT_COM: Commutation interrupt 1292 * @arg TIM_IT_TRIGGER: Trigger interrupt 1293 * @arg TIM_IT_BREAK: Break interrupt 1294 * @retval The state of TIM_IT (SET or RESET). 1295 */ 1296 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1297 == (__INTERRUPT__)) ? SET : RESET) 1298 1299 /** @brief Clear the TIM interrupt pending bits. 1300 * @param __HANDLE__ TIM handle 1301 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1302 * This parameter can be one of the following values: 1303 * @arg TIM_IT_UPDATE: Update interrupt 1304 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1305 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1306 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1307 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1308 * @arg TIM_IT_COM: Commutation interrupt 1309 * @arg TIM_IT_TRIGGER: Trigger interrupt 1310 * @arg TIM_IT_BREAK: Break interrupt 1311 * @retval None 1312 */ 1313 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1314 1315 /** 1316 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1317 * @param __HANDLE__ TIM handle. 1318 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1319 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1320 mode. 1321 */ 1322 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1323 1324 /** 1325 * @brief Set the TIM Prescaler on runtime. 1326 * @param __HANDLE__ TIM handle. 1327 * @param __PRESC__ specifies the Prescaler new value. 1328 * @retval None 1329 */ 1330 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1331 1332 /** 1333 * @brief Set the TIM Counter Register value on runtime. 1334 * @param __HANDLE__ TIM handle. 1335 * @param __COUNTER__ specifies the Counter register new value. 1336 * @retval None 1337 */ 1338 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1339 1340 /** 1341 * @brief Get the TIM Counter Register value on runtime. 1342 * @param __HANDLE__ TIM handle. 1343 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1344 */ 1345 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1346 1347 /** 1348 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1349 * @param __HANDLE__ TIM handle. 1350 * @param __AUTORELOAD__ specifies the Counter register new value. 1351 * @retval None 1352 */ 1353 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1354 do{ \ 1355 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1356 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1357 } while(0) 1358 1359 /** 1360 * @brief Get the TIM Autoreload Register value on runtime. 1361 * @param __HANDLE__ TIM handle. 1362 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1363 */ 1364 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1365 1366 /** 1367 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1368 * @param __HANDLE__ TIM handle. 1369 * @param __CKD__ specifies the clock division value. 1370 * This parameter can be one of the following value: 1371 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1372 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1373 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1374 * @retval None 1375 */ 1376 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1377 do{ \ 1378 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1379 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1380 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1381 } while(0) 1382 1383 /** 1384 * @brief Get the TIM Clock Division value on runtime. 1385 * @param __HANDLE__ TIM handle. 1386 * @retval The clock division can be one of the following values: 1387 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1388 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1389 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1390 */ 1391 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1392 1393 /** 1394 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1395 * @param __HANDLE__ TIM handle. 1396 * @param __CHANNEL__ TIM Channels to be configured. 1397 * This parameter can be one of the following values: 1398 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1399 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1400 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1401 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1402 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1403 * This parameter can be one of the following values: 1404 * @arg TIM_ICPSC_DIV1: no prescaler 1405 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1406 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1407 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1408 * @retval None 1409 */ 1410 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1411 do{ \ 1412 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1413 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1414 } while(0) 1415 1416 /** 1417 * @brief Get the TIM Input Capture prescaler on runtime. 1418 * @param __HANDLE__ TIM handle. 1419 * @param __CHANNEL__ TIM Channels to be configured. 1420 * This parameter can be one of the following values: 1421 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1422 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1423 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1424 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1425 * @retval The input capture prescaler can be one of the following values: 1426 * @arg TIM_ICPSC_DIV1: no prescaler 1427 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1428 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1429 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1430 */ 1431 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1432 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1433 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1434 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1435 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1436 1437 /** 1438 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1439 * @param __HANDLE__ TIM handle. 1440 * @param __CHANNEL__ TIM Channels to be configured. 1441 * This parameter can be one of the following values: 1442 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1443 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1444 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1445 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1446 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1447 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1448 * @param __COMPARE__ specifies the Capture Compare register new value. 1449 * @retval None 1450 */ 1451 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1452 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1453 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1454 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1455 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1456 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1457 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1458 1459 /** 1460 * @brief Get the TIM Capture Compare Register value on runtime. 1461 * @param __HANDLE__ TIM handle. 1462 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1463 * This parameter can be one of the following values: 1464 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1465 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1466 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1467 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1468 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1469 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1470 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1471 */ 1472 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1473 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1474 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1475 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1476 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1477 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1478 ((__HANDLE__)->Instance->CCR6)) 1479 1480 /** 1481 * @brief Set the TIM Output compare preload. 1482 * @param __HANDLE__ TIM handle. 1483 * @param __CHANNEL__ TIM Channels to be configured. 1484 * This parameter can be one of the following values: 1485 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1486 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1487 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1488 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1489 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1490 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1491 * @retval None 1492 */ 1493 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1494 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1495 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1496 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1497 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1498 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1499 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1500 1501 /** 1502 * @brief Reset the TIM Output compare preload. 1503 * @param __HANDLE__ TIM handle. 1504 * @param __CHANNEL__ TIM Channels to be configured. 1505 * This parameter can be one of the following values: 1506 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1507 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1508 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1509 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1510 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1511 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1512 * @retval None 1513 */ 1514 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1515 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1516 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1517 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1518 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1519 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1520 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1521 1522 /** 1523 * @brief Enable fast mode for a given channel. 1524 * @param __HANDLE__ TIM handle. 1525 * @param __CHANNEL__ TIM Channels to be configured. 1526 * This parameter can be one of the following values: 1527 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1528 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1529 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1530 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1531 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1532 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1533 * @note When fast mode is enabled an active edge on the trigger input acts 1534 * like a compare match on CCx output. Delay to sample the trigger 1535 * input and to activate CCx output is reduced to 3 clock cycles. 1536 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1537 * @retval None 1538 */ 1539 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1540 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1541 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1542 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1543 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1544 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1545 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1546 1547 /** 1548 * @brief Disable fast mode for a given channel. 1549 * @param __HANDLE__ TIM handle. 1550 * @param __CHANNEL__ TIM Channels to be configured. 1551 * This parameter can be one of the following values: 1552 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1553 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1554 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1555 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1556 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1557 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1558 * @note When fast mode is disabled CCx output behaves normally depending 1559 * on counter and CCRx values even when the trigger is ON. The minimum 1560 * delay to activate CCx output when an active edge occurs on the 1561 * trigger input is 5 clock cycles. 1562 * @retval None 1563 */ 1564 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1565 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1566 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1567 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1568 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1569 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1570 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1571 1572 /** 1573 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1574 * @param __HANDLE__ TIM handle. 1575 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1576 * overflow/underflow generates an update interrupt or DMA request (if 1577 * enabled) 1578 * @retval None 1579 */ 1580 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1581 1582 /** 1583 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1584 * @param __HANDLE__ TIM handle. 1585 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1586 * following events generate an update interrupt or DMA request (if 1587 * enabled): 1588 * _ Counter overflow underflow 1589 * _ Setting the UG bit 1590 * _ Update generation through the slave mode controller 1591 * @retval None 1592 */ 1593 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1594 1595 /** 1596 * @brief Set the TIM Capture x input polarity on runtime. 1597 * @param __HANDLE__ TIM handle. 1598 * @param __CHANNEL__ TIM Channels to be configured. 1599 * This parameter can be one of the following values: 1600 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1601 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1602 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1603 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1604 * @param __POLARITY__ Polarity for TIx source 1605 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1606 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1607 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1608 * @retval None 1609 */ 1610 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1611 do{ \ 1612 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1613 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1614 }while(0) 1615 1616 /** 1617 * @} 1618 */ 1619 /* End of exported macros ----------------------------------------------------*/ 1620 1621 /* Private constants ---------------------------------------------------------*/ 1622 /** @defgroup TIM_Private_Constants TIM Private Constants 1623 * @{ 1624 */ 1625 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1626 channels have been disabled */ 1627 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1628 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1629 /** 1630 * @} 1631 */ 1632 /* End of private constants --------------------------------------------------*/ 1633 1634 /* Private macros ------------------------------------------------------------*/ 1635 /** @defgroup TIM_Private_Macros TIM Private Macros 1636 * @{ 1637 */ 1638 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1639 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ 1640 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ 1641 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1642 1643 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1644 ((__BASE__) == TIM_DMABASE_CR2) || \ 1645 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1646 ((__BASE__) == TIM_DMABASE_DIER) || \ 1647 ((__BASE__) == TIM_DMABASE_SR) || \ 1648 ((__BASE__) == TIM_DMABASE_EGR) || \ 1649 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1650 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1651 ((__BASE__) == TIM_DMABASE_CCER) || \ 1652 ((__BASE__) == TIM_DMABASE_CNT) || \ 1653 ((__BASE__) == TIM_DMABASE_PSC) || \ 1654 ((__BASE__) == TIM_DMABASE_ARR) || \ 1655 ((__BASE__) == TIM_DMABASE_RCR) || \ 1656 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1657 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1658 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1659 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1660 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1661 ((__BASE__) == TIM_DMABASE_OR) || \ 1662 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1663 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1664 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1665 ((__BASE__) == TIM_DMABASE_AF1) || \ 1666 ((__BASE__) == TIM_DMABASE_AF2)) 1667 1668 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1669 1670 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1671 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1672 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1673 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1674 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1675 1676 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1677 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1678 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1679 1680 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1681 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1682 1683 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1684 ((__STATE__) == TIM_OCFAST_ENABLE)) 1685 1686 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1687 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1688 1689 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1690 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1691 1692 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1693 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1694 1695 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1696 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1697 1698 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1699 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1700 1701 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1702 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1703 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1704 1705 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1706 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1707 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1708 1709 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1710 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1711 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1712 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1713 1714 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1715 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1716 1717 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1718 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1719 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1720 1721 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1722 1723 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1724 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1725 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1726 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1727 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1728 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1729 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1730 1731 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1732 ((__CHANNEL__) == TIM_CHANNEL_2)) 1733 1734 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1735 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1736 ((__CHANNEL__) == TIM_CHANNEL_3)) 1737 1738 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1739 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1740 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1741 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1742 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1743 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1744 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1745 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1746 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1747 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 1748 1749 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1750 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1751 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1752 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1753 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1754 1755 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1756 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1757 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1758 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1759 1760 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1761 1762 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1763 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1764 1765 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1766 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1767 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1768 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1769 1770 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1771 1772 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1773 ((__STATE__) == TIM_OSSR_DISABLE)) 1774 1775 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1776 ((__STATE__) == TIM_OSSI_DISABLE)) 1777 1778 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1779 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1780 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1781 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1782 1783 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1784 1785 1786 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1787 ((__STATE__) == TIM_BREAK_DISABLE)) 1788 1789 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1790 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1791 1792 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1793 ((__STATE__) == TIM_BREAK2_DISABLE)) 1794 1795 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1796 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1797 1798 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1799 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1800 1801 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1802 1803 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1804 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1805 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1806 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1807 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1808 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1809 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1810 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1811 1812 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 1813 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 1814 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 1815 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 1816 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 1817 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 1818 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1819 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1820 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 1821 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 1822 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 1823 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 1824 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 1825 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 1826 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 1827 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 1828 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 1829 1830 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1831 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1832 1833 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1834 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1835 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1836 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1837 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 1838 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1839 1840 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1841 ((__MODE__) == TIM_OCMODE_PWM2) || \ 1842 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 1843 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 1844 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 1845 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 1846 1847 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1848 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1849 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1850 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1851 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1852 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 1853 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 1854 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 1855 1856 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1857 ((__SELECTION__) == TIM_TS_ITR1) || \ 1858 ((__SELECTION__) == TIM_TS_ITR2) || \ 1859 ((__SELECTION__) == TIM_TS_ITR3) || \ 1860 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1861 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1862 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1863 ((__SELECTION__) == TIM_TS_ETRF)) 1864 1865 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1866 ((__SELECTION__) == TIM_TS_ITR1) || \ 1867 ((__SELECTION__) == TIM_TS_ITR2) || \ 1868 ((__SELECTION__) == TIM_TS_ITR3) || \ 1869 ((__SELECTION__) == TIM_TS_NONE)) 1870 1871 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1872 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1873 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1874 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1875 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1876 1877 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1878 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1879 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1880 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1881 1882 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1883 1884 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1885 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1886 1887 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1888 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1889 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1890 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1891 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1892 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1893 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1894 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1895 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1896 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1897 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1898 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1899 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1900 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1901 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1902 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1903 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1904 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1905 1906 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1907 1908 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 1909 1910 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 1911 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 1912 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ 1913 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 1914 1915 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 1916 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1917 1918 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1919 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1920 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1921 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1922 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1923 1924 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1925 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 1926 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 1927 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 1928 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 1929 1930 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1931 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1932 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1933 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1934 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1935 1936 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1937 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1938 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1939 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1940 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1941 1942 /** 1943 * @} 1944 */ 1945 /* End of private macros -----------------------------------------------------*/ 1946 1947 /* Include TIM HAL Extended module */ 1948 #include "stm32wbxx_hal_tim_ex.h" 1949 1950 /* Exported functions --------------------------------------------------------*/ 1951 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1952 * @{ 1953 */ 1954 1955 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 1956 * @brief Time Base functions 1957 * @{ 1958 */ 1959 /* Time Base functions ********************************************************/ 1960 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1961 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1962 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1963 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1964 /* Blocking mode: Polling */ 1965 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1966 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1967 /* Non-Blocking mode: Interrupt */ 1968 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1969 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1970 /* Non-Blocking mode: DMA */ 1971 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1972 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1973 /** 1974 * @} 1975 */ 1976 1977 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 1978 * @brief TIM Output Compare functions 1979 * @{ 1980 */ 1981 /* Timer Output Compare functions *********************************************/ 1982 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1983 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1984 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1985 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1986 /* Blocking mode: Polling */ 1987 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1988 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1989 /* Non-Blocking mode: Interrupt */ 1990 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1991 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1992 /* Non-Blocking mode: DMA */ 1993 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 1994 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 1995 /** 1996 * @} 1997 */ 1998 1999 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2000 * @brief TIM PWM functions 2001 * @{ 2002 */ 2003 /* Timer PWM functions ********************************************************/ 2004 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2005 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2006 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2007 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2008 /* Blocking mode: Polling */ 2009 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2010 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2011 /* Non-Blocking mode: Interrupt */ 2012 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2013 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2014 /* Non-Blocking mode: DMA */ 2015 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2016 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2017 /** 2018 * @} 2019 */ 2020 2021 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2022 * @brief TIM Input Capture functions 2023 * @{ 2024 */ 2025 /* Timer Input Capture functions **********************************************/ 2026 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2027 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2028 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2029 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2030 /* Blocking mode: Polling */ 2031 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2032 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2033 /* Non-Blocking mode: Interrupt */ 2034 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2035 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2036 /* Non-Blocking mode: DMA */ 2037 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2038 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2039 /** 2040 * @} 2041 */ 2042 2043 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2044 * @brief TIM One Pulse functions 2045 * @{ 2046 */ 2047 /* Timer One Pulse functions **************************************************/ 2048 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2049 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2050 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2051 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2052 /* Blocking mode: Polling */ 2053 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2054 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2055 /* Non-Blocking mode: Interrupt */ 2056 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2057 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2058 /** 2059 * @} 2060 */ 2061 2062 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2063 * @brief TIM Encoder functions 2064 * @{ 2065 */ 2066 /* Timer Encoder functions ****************************************************/ 2067 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2068 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2069 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2070 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2071 /* Blocking mode: Polling */ 2072 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2073 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2074 /* Non-Blocking mode: Interrupt */ 2075 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2076 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2077 /* Non-Blocking mode: DMA */ 2078 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2079 uint32_t *pData2, uint16_t Length); 2080 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2081 /** 2082 * @} 2083 */ 2084 2085 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2086 * @brief IRQ handler management 2087 * @{ 2088 */ 2089 /* Interrupt Handler functions ***********************************************/ 2090 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2091 /** 2092 * @} 2093 */ 2094 2095 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2096 * @brief Peripheral Control functions 2097 * @{ 2098 */ 2099 /* Control functions *********************************************************/ 2100 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2101 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2102 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2103 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2104 uint32_t OutputChannel, uint32_t InputChannel); 2105 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2106 uint32_t Channel); 2107 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2108 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2109 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2110 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2111 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2112 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2113 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2114 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2115 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2116 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2117 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2118 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2119 /** 2120 * @} 2121 */ 2122 2123 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2124 * @brief TIM Callbacks functions 2125 * @{ 2126 */ 2127 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2128 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2129 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2130 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2131 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2132 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2133 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2134 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2135 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2136 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2137 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2138 2139 /* Callbacks Register/UnRegister functions ***********************************/ 2140 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2141 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2142 pTIM_CallbackTypeDef pCallback); 2143 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2144 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2145 2146 /** 2147 * @} 2148 */ 2149 2150 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2151 * @brief Peripheral State functions 2152 * @{ 2153 */ 2154 /* Peripheral State functions ************************************************/ 2155 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2156 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2157 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2158 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2159 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2160 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2161 /** 2162 * @} 2163 */ 2164 2165 /** 2166 * @} 2167 */ 2168 /* End of exported functions -------------------------------------------------*/ 2169 2170 /* Private functions----------------------------------------------------------*/ 2171 /** @defgroup TIM_Private_Functions TIM Private Functions 2172 * @{ 2173 */ 2174 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2175 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2176 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2177 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2178 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2179 2180 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 2181 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2182 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2183 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2184 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2185 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2186 2187 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2188 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2189 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2190 2191 /** 2192 * @} 2193 */ 2194 /* End of private functions --------------------------------------------------*/ 2195 2196 /** 2197 * @} 2198 */ 2199 2200 /** 2201 * @} 2202 */ 2203 2204 #ifdef __cplusplus 2205 } 2206 #endif 2207 2208 #endif /* STM32WBxx_HAL_TIM_H */ 2209 2210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2211