1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_RCC_EX_H 22 #define STM32WBxx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 #include "stm32wbxx_ll_crs.h" 31 #include "stm32wbxx_ll_exti.h" 32 #include "stm32wbxx_ll_pwr.h" 33 34 /** @addtogroup STM32WBxx_HAL_Driver 35 * @{ 36 */ 37 38 /** @addtogroup RCCEx 39 * @{ 40 */ 41 /* Private constants ---------------------------------------------------------*/ 42 /** @addtogroup RCC_Private_Constants 43 * @{ 44 */ 45 /* CRS IT Error Mask */ 46 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) 47 48 /* CRS Flag Error Mask */ 49 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) 50 51 /* RNG closk selection CLK48 clock mask */ 52 #define CLK48_MASK 0x10000000U 53 /** 54 * @} 55 */ 56 57 58 /* Private macros ------------------------------------------------------------*/ 59 /** @addtogroup RCCEx_Private_Macros 60 * @{ 61 */ 62 #define IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) || ((__LSCOX__) == RCC_LSCO2) || ((__LSCOX__) == RCC_LSCO3) ) 63 64 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 65 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 66 67 #if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT) 68 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 69 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 70 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 71 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 72 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 73 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 74 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 75 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 76 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 77 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 78 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 79 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 80 (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ 81 (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)) 82 #else 83 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 84 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 85 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 86 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 87 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 88 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 89 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 90 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 91 (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)) 92 #endif 93 94 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 95 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 96 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 97 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 98 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 99 100 #if defined(LPUART1) 101 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 102 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 103 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 104 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 105 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 106 #endif 107 108 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 109 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 110 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 111 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 112 113 #if defined(I2C3) 114 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 115 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 116 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 117 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 118 #endif 119 120 #if defined(SAI1) 121 #define IS_RCC_SAI1CLK(__SOURCE__) \ 122 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 123 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 124 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ 125 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 126 #endif 127 128 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 129 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 130 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 131 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 132 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 133 134 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 135 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 136 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 137 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 138 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 139 140 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 141 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 142 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 143 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \ 144 ((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ 145 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ 146 ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) 147 148 #if defined(SAI1) 149 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 150 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 151 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 152 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 153 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 154 #else 155 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 156 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 157 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 158 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 159 #endif 160 161 #if defined(SAI1) 162 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 163 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 164 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ 165 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 166 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 167 #else 168 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 169 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 170 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ 171 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 172 #endif 173 174 #define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \ 175 (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \ 176 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \ 177 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \ 178 ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024)) 179 180 #if defined(RCC_SMPS_SUPPORT) 181 #define IS_RCC_SMPSCLKDIV(__DIV__) \ 182 (((__DIV__) == RCC_SMPSCLKDIV_RANGE0) || \ 183 ((__DIV__) == RCC_SMPSCLKDIV_RANGE1) || \ 184 ((__DIV__) == RCC_SMPSCLKDIV_RANGE2) || \ 185 ((__DIV__) == RCC_SMPSCLKDIV_RANGE3)) 186 187 #define IS_RCC_SMPSCLKSOURCE(__SOURCE__) \ 188 (((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI) || \ 189 ((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI) || \ 190 ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) 191 #endif 192 193 #if defined(SAI1) 194 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 195 196 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 197 198 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 199 200 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 201 #endif 202 203 #define IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2) 204 205 #if defined(CRS) 206 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 207 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 208 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 209 210 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 211 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 212 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 213 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 214 215 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 216 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 217 218 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 219 220 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 221 222 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 223 224 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 225 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 226 #endif 227 /** 228 * @} 229 */ 230 231 /* Exported types ------------------------------------------------------------*/ 232 233 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 234 * @{ 235 */ 236 237 #if defined(SAI1) 238 /** 239 * @brief PLLSAI1 Clock structure definition 240 */ 241 typedef struct 242 { 243 244 uint32_t PLLN; /*!< PLLN: specifies the multiplication factor for PLLSAI1 VCO output clock. 245 This parameter must be a number between Min_Data=6 and Max_Data=127. */ 246 247 uint32_t PLLP; /*!< PLLP: specifies the division factor for SAI clock. 248 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 249 250 uint32_t PLLQ; /*!< PLLQ: specifies the division factor for USB/RNG clock. 251 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 252 253 uint32_t PLLR; /*!< PLLR: specifies the division factor for ADC clock. 254 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 255 256 uint32_t PLLSAI1ClockOut; /*!< PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled. 257 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 258 } RCC_PLLSAI1InitTypeDef; 259 #endif 260 261 /** 262 * @brief RCC extended clocks structure definition 263 */ 264 typedef struct 265 { 266 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 267 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 268 269 #if defined(SAI1) 270 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 271 This parameter will be used only when PLLSAI1 is selected as Clock 272 Source for SAI, USB/RNG or ADC */ 273 #endif 274 275 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 276 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 277 278 #if defined(LPUART1) 279 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 280 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 281 #endif 282 283 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 284 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 285 286 #if defined(I2C3) 287 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 288 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 289 #endif 290 291 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 292 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 293 294 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 295 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 296 297 #if defined(SAI1) 298 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 299 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 300 #endif 301 302 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). 303 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 304 305 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). 306 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 307 308 309 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 310 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 311 312 uint32_t RTCClockSelection; /*!< Specifies RTC clock source (also used for LCD). 313 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 314 315 uint32_t RFWakeUpClockSelection; /*!< Specifies RF Wake-up clock source. 316 This parameter can be a value of @ref RCCEx_RFWKP_Clock_Source */ 317 318 #if defined(RCC_SMPS_SUPPORT) 319 uint32_t SmpsClockSelection; /*!< Specifies SMPS clock source. 320 This parameter can be a value of @ref RCCEx_SMPS_Clock_Source */ 321 322 uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor. 323 This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ 324 #endif 325 } RCC_PeriphCLKInitTypeDef; 326 327 328 #if defined(CRS) 329 /** 330 * @brief RCC_CRS Init structure definition 331 */ 332 typedef struct 333 { 334 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 335 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 336 337 uint32_t Source; /*!< Specifies the SYNC signal source. 338 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 339 340 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 341 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 342 343 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 344 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 345 This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 346 347 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 348 This parameter must be a number between Min_Data=0 and Max_Data=0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 349 350 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 351 This parameter must be a number between Min_Data=0 and Max_Data=0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 352 353 } RCC_CRSInitTypeDef; 354 355 /** 356 * @brief RCC_CRS Synchronization structure definition 357 */ 358 typedef struct 359 { 360 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 361 This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF */ 362 363 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 364 This parameter must be a number between Min_Data=0 and Max_Data=0x3F */ 365 366 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 367 value latched in the time of the last SYNC event. 368 This parameter must be a number between Min_Data=0 and Max_Data=0xFFFF */ 369 370 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 371 frequency error counter latched in the time of the last SYNC event. 372 It shows whether the actual frequency is below or above the target. 373 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 374 375 } RCC_CRSSynchroInfoTypeDef; 376 #endif 377 378 /** 379 * @} 380 */ 381 382 /* Exported constants --------------------------------------------------------*/ 383 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 384 * @{ 385 */ 386 387 /** @defgroup RCC_LSCO_Index LSCO Index 388 * @{ 389 */ 390 #define RCC_LSCO1 0x00000000U /*!< LSCO1 index */ 391 #define RCC_LSCO2 0x00000001U /*!< LSCO2 index */ 392 #define RCC_LSCO3 0x00000002U /*!< LSCO3 index */ 393 /** 394 * @} 395 */ 396 397 398 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 399 * @{ 400 */ 401 #define RCC_LSCOSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI /*!< LSI selection for low speed clock output */ 402 #define RCC_LSCOSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE /*!< LSE selection for low speed clock output */ 403 /** 404 * @} 405 */ 406 407 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 408 * @{ 409 */ 410 #define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */ 411 #if defined(LPUART1) 412 #define RCC_PERIPHCLK_LPUART1 0x00000002U /*!< LPUART1 Peripheral Clock Selection */ 413 #endif 414 #define RCC_PERIPHCLK_I2C1 0x00000004U /*!< I2C1 Peripheral Clock Selection */ 415 #if defined(I2C3) 416 #define RCC_PERIPHCLK_I2C3 0x00000008U /*!< I2C3 Peripheral Clock Selection */ 417 #endif 418 #define RCC_PERIPHCLK_LPTIM1 0x00000010U /*!< LPTIM1 Peripheral Clock Selection */ 419 #define RCC_PERIPHCLK_LPTIM2 0x00000020U /*!< LPTIM2 Peripheral Clock Selection */ 420 #if defined(SAI1) 421 #define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */ 422 #endif 423 #define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */ 424 #define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */ 425 #define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */ 426 #define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */ 427 #define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */ 428 #define RCC_PERIPHCLK_RFWAKEUP 0x00001000U /*!< RF Wakeup Peripheral Clock Selection */ 429 #if defined(RCC_SMPS_SUPPORT) 430 #define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */ 431 #endif 432 /** 433 * @} 434 */ 435 436 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 437 * @{ 438 */ 439 #define RCC_USART1CLKSOURCE_PCLK2 LL_RCC_USART1_CLKSOURCE_PCLK2 /*!< APB2 clock selected as USART 1 clock*/ 440 #define RCC_USART1CLKSOURCE_SYSCLK LL_RCC_USART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as USART 1 clock*/ 441 #define RCC_USART1CLKSOURCE_HSI LL_RCC_USART1_CLKSOURCE_HSI /*!< HSI clock selected as USART 1 clock*/ 442 #define RCC_USART1CLKSOURCE_LSE LL_RCC_USART1_CLKSOURCE_LSE /*!< LSE clock selected as USART 1 clock*/ 443 /** 444 * @} 445 */ 446 447 #if defined(LPUART1) 448 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 449 * @{ 450 */ 451 #define RCC_LPUART1CLKSOURCE_PCLK1 LL_RCC_LPUART1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPUART 1 clock*/ 452 #define RCC_LPUART1CLKSOURCE_SYSCLK LL_RCC_LPUART1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as LPUART 1 clock*/ 453 #define RCC_LPUART1CLKSOURCE_HSI LL_RCC_LPUART1_CLKSOURCE_HSI /*!< HSI clock selected as LPUART 1 clock*/ 454 #define RCC_LPUART1CLKSOURCE_LSE LL_RCC_LPUART1_CLKSOURCE_LSE /*!< LSE clock selected as LPUART 1 clock*/ 455 /** 456 * @} 457 */ 458 #endif 459 460 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 461 * @{ 462 */ 463 #define RCC_I2C1CLKSOURCE_PCLK1 LL_RCC_I2C1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C1 clock */ 464 #define RCC_I2C1CLKSOURCE_SYSCLK LL_RCC_I2C1_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C1 clock */ 465 #define RCC_I2C1CLKSOURCE_HSI LL_RCC_I2C1_CLKSOURCE_HSI /*!< HSI clock selected as I2C1 clock */ 466 /** 467 * @} 468 */ 469 470 #if defined(I2C3) 471 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 472 * @{ 473 */ 474 #define RCC_I2C3CLKSOURCE_PCLK1 LL_RCC_I2C3_CLKSOURCE_PCLK1 /*!< APB1 clock selected as I2C3 clock */ 475 #define RCC_I2C3CLKSOURCE_SYSCLK LL_RCC_I2C3_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as I2C3 clock */ 476 #define RCC_I2C3CLKSOURCE_HSI LL_RCC_I2C3_CLKSOURCE_HSI /*!< HSI clock selected as I2C3 clock */ 477 /** 478 * @} 479 */ 480 #endif 481 482 #if defined(SAI1) 483 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 484 * @{ 485 */ 486 #define RCC_SAI1CLKSOURCE_PLLSAI1 LL_RCC_SAI1_CLKSOURCE_PLLSAI1 /*!< PLLSAI "P" clock selected as SAI1 clock */ 487 #define RCC_SAI1CLKSOURCE_PLL LL_RCC_SAI1_CLKSOURCE_PLL /*!< PLL "P" clock selected as SAI1 clock */ 488 #define RCC_SAI1CLKSOURCE_HSI LL_RCC_SAI1_CLKSOURCE_HSI /*!< HSI clock selected as SAI1 clock */ 489 #define RCC_SAI1CLKSOURCE_PIN LL_RCC_SAI1_CLKSOURCE_PIN /*!< External PIN clock selected as SAI1 clock */ 490 /** 491 * @} 492 */ 493 #endif 494 495 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 496 * @{ 497 */ 498 #define RCC_LPTIM1CLKSOURCE_PCLK1 LL_RCC_LPTIM1_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM1 clock */ 499 #define RCC_LPTIM1CLKSOURCE_LSI LL_RCC_LPTIM1_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM1 clock */ 500 #define RCC_LPTIM1CLKSOURCE_HSI LL_RCC_LPTIM1_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM1 clock */ 501 #define RCC_LPTIM1CLKSOURCE_LSE LL_RCC_LPTIM1_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM1 clock */ 502 /** 503 * @} 504 */ 505 506 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 507 * @{ 508 */ 509 #define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM2 clock */ 510 #define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM2 clock */ 511 #define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM2 clock */ 512 #define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM2 clock */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 518 * @{ 519 */ 520 #define RCC_RNGCLKSOURCE_HSI48 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48) /*!< HSI48 clock divided by 3 selected as RNG clock */ 521 #define RCC_RNGCLKSOURCE_PLL (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL) /*!< PLL "Q" clock divided by 3 selected as RNG clock */ 522 #define RCC_RNGCLKSOURCE_MSI (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI) /*!< MSI clock divided by 3 selected as RNG clock */ 523 #define RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48 /*!< CLK48 divided by 3 selected as RNG Clock */ 524 #define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI clock selected as RNG clock */ 525 #define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE clock selected as RNG clock */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 531 * @{ 532 */ 533 #define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */ 534 #define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */ 535 #define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */ 536 #define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */ 537 /** 538 * @} 539 */ 540 541 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 542 * @{ 543 */ 544 545 #define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ 546 #if defined(SAI1) 547 #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ 548 #endif 549 #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ 550 #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ 551 552 /** 553 * @} 554 */ 555 556 /** @defgroup RCCEx_HCLK5_Clock_Source HCLK RF Clock Source 557 * @{ 558 */ 559 560 #define RCC_HCLK5SOURCE_HSI 0x00000001U /*!< HSI clock not divided selected as Radio Domain clock */ 561 #define RCC_HCLK5SOURCE_HSE 0x00000002U /*!< HSE clock divided by 2 selected as Radio Domain clock */ 562 563 /** 564 * @} 565 */ 566 567 /** @defgroup RCCEx_RFWKP_Clock_Source RF WKP Clock Source 568 * @{ 569 */ 570 571 #define RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE /*!< None clock selected as RF system wakeup clock */ 572 #define RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE /*!< LSE clock selected as RF system wakeup clock */ 573 #define RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI /*!< LSI clock selected as RF system wakeup clock */ 574 #define RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 /*!< HSE clock divided by 1024 selected as RF system wakeup clock */ 575 576 /** 577 * @} 578 */ 579 580 581 #if defined(RCC_SMPS_SUPPORT) 582 /** @defgroup RCCEx_SMPS_Clock_Source SMPS Clock Source 583 * @{ 584 */ 585 #define RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI /*!< HSI selection as smps clock */ 586 #define RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI /*!< MSI selection as smps clock */ 587 #define RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE /*!< HSE selection as smps clock */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 593 * @{ 594 */ 595 #define RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI /*!< HSI selection as smps clock */ 596 #define RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI /*!< MSI selection as smps clock */ 597 #define RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE /*!< HSE selection as smps clock */ 598 /** 599 * @} 600 */ 601 602 /** @defgroup RCCEx_SMPS_Clock_Divider SMPS Clock Division Factor 603 * @{ 604 */ 605 #define RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0 /*!< PLLM division factor = 0 */ 606 #define RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1 /*!< PLLM division factor = 1 */ 607 #define RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2 /*!< PLLM division factor = 2 */ 608 #define RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3 /*!< PLLM division factor = 3 */ 609 /** 610 * @} 611 */ 612 #endif 613 614 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 615 * @{ 616 */ 617 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ 618 619 /** 620 * @} 621 */ 622 623 624 #if defined(CRS) 625 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 626 * @{ 627 */ 628 #define RCC_CRS_NONE 0x00000000U /*!< CRS status none */ 629 #define RCC_CRS_TIMEOUT 0x00000001U /*!< CRS status timeout */ 630 #define RCC_CRS_SYNCOK 0x00000002U /*!< CRS status synchronization success */ 631 #define RCC_CRS_SYNCWARN 0x00000004U /*!< CRS status synchronization warning */ 632 #define RCC_CRS_SYNCERR 0x00000008U /*!< CRS status synchronization error */ 633 #define RCC_CRS_SYNCMISS 0x00000010U /*!< CRS status synchronization missed */ 634 #define RCC_CRS_TRIMOVF 0x00000020U /*!< CRS status trimming overflow or underflow */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 640 * @{ 641 */ 642 #define RCC_CRS_SYNC_SOURCE_GPIO LL_CRS_SYNC_SOURCE_GPIO /*!< Synchro Signal source GPIO */ 643 #define RCC_CRS_SYNC_SOURCE_LSE LL_CRS_SYNC_SOURCE_LSE /*!< Synchro Signal source LSE */ 644 #define RCC_CRS_SYNC_SOURCE_USB LL_CRS_SYNC_SOURCE_USB /*!< Synchro Signal source USB SOF (default)*/ 645 /** 646 * @} 647 */ 648 649 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 650 * @{ 651 */ 652 #define RCC_CRS_SYNC_DIV1 LL_CRS_SYNC_DIV_1 /*!< Synchro Signal not divided (default) */ 653 #define RCC_CRS_SYNC_DIV2 LL_CRS_SYNC_DIV_2 /*!< Synchro Signal divided by 2 */ 654 #define RCC_CRS_SYNC_DIV4 LL_CRS_SYNC_DIV_4 /*!< Synchro Signal divided by 4 */ 655 #define RCC_CRS_SYNC_DIV8 LL_CRS_SYNC_DIV_8 /*!< Synchro Signal divided by 8 */ 656 #define RCC_CRS_SYNC_DIV16 LL_CRS_SYNC_DIV_16 /*!< Synchro Signal divided by 16 */ 657 #define RCC_CRS_SYNC_DIV32 LL_CRS_SYNC_DIV_32 /*!< Synchro Signal divided by 32 */ 658 #define RCC_CRS_SYNC_DIV64 LL_CRS_SYNC_DIV_64 /*!< Synchro Signal divided by 64 */ 659 #define RCC_CRS_SYNC_DIV128 LL_CRS_SYNC_DIV_128 /*!< Synchro Signal divided by 128 */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 665 * @{ 666 */ 667 #define RCC_CRS_SYNC_POLARITY_RISING LL_CRS_SYNC_POLARITY_RISING /*!< Synchro Active on rising edge (default) */ 668 #define RCC_CRS_SYNC_POLARITY_FALLING LL_CRS_SYNC_POLARITY_FALLING /*!< Synchro Active on falling edge */ 669 /** 670 * @} 671 */ 672 673 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 674 * @{ 675 */ 676 #define RCC_CRS_RELOADVALUE_DEFAULT LL_CRS_RELOADVALUE_DEFAULT /*!< The reset value of the RELOAD field corresponds 677 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 678 /** 679 * @} 680 */ 681 682 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 683 * @{ 684 */ 685 #define RCC_CRS_ERRORLIMIT_DEFAULT LL_CRS_ERRORLIMIT_DEFAULT /*!< Default Frequency error limit */ 686 /** 687 * @} 688 */ 689 690 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 691 * @{ 692 */ 693 #define RCC_CRS_HSI48CALIBRATION_DEFAULT LL_CRS_HSI48CALIBRATION_DEFAULT /*!< The default value is 32, which corresponds to the middle of the trimming interval. 694 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 695 corresponds to a higher output frequency */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 701 * @{ 702 */ 703 #define RCC_CRS_FREQERRORDIR_UP LL_CRS_FREQ_ERROR_DIR_UP /*!< Upcounting direction, the actual frequency is above the target */ 704 #define RCC_CRS_FREQERRORDIR_DOWN LL_CRS_FREQ_ERROR_DIR_DOWN /*!< Downcounting direction, the actual frequency is below the target */ 705 /** 706 * @} 707 */ 708 709 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 710 * @{ 711 */ 712 #define RCC_CRS_IT_SYNCOK LL_CRS_CR_SYNCOKIE /*!< SYNC event OK */ 713 #define RCC_CRS_IT_SYNCWARN LL_CRS_CR_SYNCWARNIE /*!< SYNC warning */ 714 #define RCC_CRS_IT_ERR LL_CRS_CR_ERRIE /*!< Error */ 715 #define RCC_CRS_IT_ESYNC LL_CRS_CR_ESYNCIE /*!< Expected SYNC */ 716 #define RCC_CRS_IT_SYNCERR LL_CRS_CR_ERRIE /*!< SYNC error */ 717 #define RCC_CRS_IT_SYNCMISS LL_CRS_CR_ERRIE /*!< SYNC missed */ 718 #define RCC_CRS_IT_TRIMOVF LL_CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 719 720 /** 721 * @} 722 */ 723 724 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 725 * @{ 726 */ 727 #define RCC_CRS_FLAG_SYNCOK LL_CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 728 #define RCC_CRS_FLAG_SYNCWARN LL_CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 729 #define RCC_CRS_FLAG_ERR LL_CRS_ISR_ERRF /*!< Error flag */ 730 #define RCC_CRS_FLAG_ESYNC LL_CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 731 #define RCC_CRS_FLAG_SYNCERR LL_CRS_ISR_SYNCERR /*!< SYNC error */ 732 #define RCC_CRS_FLAG_SYNCMISS LL_CRS_ISR_SYNCMISS /*!< SYNC missed*/ 733 #define RCC_CRS_FLAG_TRIMOVF LL_CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 734 735 /** 736 * @} 737 */ 738 #endif 739 740 /** 741 * @} 742 */ 743 744 /* Exported macros -----------------------------------------------------------*/ 745 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 746 * @{ 747 */ 748 749 /*================================================================================================================*/ 750 751 #if defined(SAI1) 752 /** 753 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 754 * 755 * @note This function must be used only when the PLLSAI1 is disabled. 756 * @note PLLSAI1 clock source is common with the main PLL (configured through 757 * @ref __HAL_RCC_PLL_CONFIG() macro) 758 * 759 * @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. 760 * This parameter must be a number between 6 and 127. 761 * @note You have to set the PLLN parameter correctly to ensure that the VCO 762 * output frequency is between 96 and 344 MHz. 763 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN 764 * 765 * @param __PLLP__ specifies the division factor for SAI clock. 766 * This parameter must be a number in the range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32). 767 * SAI clock frequency = f(PLLSAI1) / PLLP 768 * 769 * @param __PLLQ__ specifies the division factor for USB/RNG clock. 770 * This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8). 771 * USB/RNG clock frequency = f(PLLSAI1) / PLLQ 772 * 773 * @param __PLLR__ specifies the division factor for SAR ADC clock. 774 * This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8). 775 * ADC clock frequency = f(PLLSAI1) / PLLR 776 * 777 * @retval None 778 */ 779 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLN__, __PLLP__, __PLLQ__, __PLLR__) \ 780 MODIFY_REG(RCC->PLLSAI1CFGR, \ 781 (RCC_PLLSAI1CFGR_PLLN | RCC_PLLSAI1CFGR_PLLP | RCC_PLLSAI1CFGR_PLLQ | RCC_PLLSAI1CFGR_PLLR), \ 782 (((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | (__PLLP__) | (__PLLQ__) | (__PLLR__))) 783 784 /** 785 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 786 * 787 * @note This function must be used only when the PLLSAI1 is disabled. 788 * @note PLLSAI1 clock source is common with the main PLL (configured through 789 * @ref __HAL_RCC_PLL_CONFIG() macro) 790 * 791 * @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. 792 * This parameter must be a number between Min_Data=6 and Max_Data=127. 793 * @note You have to set the PLLN parameter correctly to ensure that the VCO 794 * output frequency is between 96 and 344 MHz. 795 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN 796 * 797 * @retval None 798 */ 799 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLN__) \ 800 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLN, (__PLLN__) << RCC_PLLSAI1CFGR_PLLN_Pos) 801 802 803 /** @brief Macro to configure the PLLSAI1 clock division factor P. 804 * 805 * @note This function must be used only when the PLLSAI1 is disabled. 806 * @note PLLSAI1 clock source is common with the main PLL (configured through 807 * @ref __HAL_RCC_PLL_CONFIG() macro) 808 * 809 * @param __PLLP__ specifies the division factor for SAI clock. 810 * This parameter must be a number in range (RCC_PLLP_DIV2 to RCC_PLLP_DIV32). 811 * Use to set SAI clock frequency = f(PLLSAI1) / PLLP 812 * 813 * @retval None 814 */ 815 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLP__) \ 816 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLP, (__PLLP__)) 817 818 819 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 820 * 821 * @note This function must be used only when the PLLSAI1 is disabled. 822 * @note PLLSAI1 clock source is common with the main PLL (configured through 823 * @ref __HAL_RCC_PLL_CONFIG() macro) 824 * 825 * @param __PLLQ__ specifies the division factor for USB clock. 826 * This parameter must be in the range (RCC_PLLQ_DIV2 to RCC_PLLQ_DIV8). 827 * Use to set USB clock frequency = f(PLLSAI1) / PLLQ 828 * 829 * @retval None 830 */ 831 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLQ__) \ 832 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLQ, (__PLLQ__)) 833 834 /** @brief Macro to configure the PLLSAI1 clock division factor R. 835 * 836 * @note This function must be used only when the PLLSAI1 is disabled. 837 * @note PLLSAI1 clock source is common with the main PLL (configured through 838 * @ref __HAL_RCC_PLL_CONFIG() macro) 839 * 840 * @param __PLLR__ specifies the division factor for ADC clock. 841 * This parameter must be in the range (RCC_PLLR_DIV2 to RCC_PLLR_DIV8). 842 * Use to set ADC clock frequency = f(PLLSAI1) / PLLR 843 * 844 * @retval None 845 */ 846 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLR__) \ 847 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR, (__PLLR__)) 848 849 /** 850 * @brief Macros to enable the PLLSAI1. 851 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 852 * @retval None 853 */ 854 #define __HAL_RCC_PLLSAI1_ENABLE() LL_RCC_PLLSAI1_Enable() 855 856 /** 857 * @brief Macros to disable the PLLSAI1. 858 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 859 * @retval None 860 */ 861 #define __HAL_RCC_PLLSAI1_DISABLE() LL_RCC_PLLSAI1_Disable() 862 863 /** 864 * @brief Macros to enable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK). 865 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 866 * This is mainly used to save Power. 867 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 868 * This parameter can be one or a combination of the following values: 869 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 870 * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral 871 * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) 872 * 873 * @retval None 874 */ 875 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 876 877 /** 878 * @brief Macros to disable each clock output (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK). 879 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 880 * This is mainly used to save Power. 881 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 882 * This parameter can be one or a combination of the following values: 883 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 884 * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral 885 * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) 886 * 887 * @retval None 888 */ 889 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 890 891 /** 892 * @brief Macro to get clock output enable status (RCC_PLLSAI1_SAI1CLK, RCC_PLLSAI1_USBCLK and RCC_PLLSAI1_ADCCLK). 893 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 894 * This parameter can be one or a combination of the following values: 895 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 896 * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral 897 * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) 898 * @retval SET / RESET 899 */ 900 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 901 902 903 /** 904 * @brief Macro to configure the SAI1 clock source. 905 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 906 * from the PLLSAI1, system PLL, HSI or external clock (through a dedicated pin). 907 * This parameter can be one of the following values: 908 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock 909 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock 910 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI clock 911 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 912 * 913 * @retval None 914 */ 915 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) LL_RCC_SetSAIClockSource(__SAI1_CLKSOURCE__) 916 917 918 /** @brief Macro to get the SAI1 clock source. 919 * @retval The clock source can be one of the following values: 920 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock 921 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock 922 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI clock 923 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 924 * 925 * @retval None 926 */ 927 #define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE) 928 #endif 929 930 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 931 * 932 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 933 * This parameter can be one of the following values: 934 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 935 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 936 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 937 * @retval None 938 */ 939 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__) 940 941 /** @brief Macro to get the I2C1 clock source. 942 * @retval The clock source can be one of the following values: 943 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 944 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 945 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 946 */ 947 #define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE) 948 949 #if defined(I2C3) 950 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 951 * 952 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 953 * This parameter can be one of the following values: 954 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 955 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 956 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 957 * @retval None 958 */ 959 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__) 960 961 /** @brief Macro to get the I2C3 clock source. 962 * @retval The clock source can be one of the following values: 963 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 964 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 965 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 966 */ 967 #define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) 968 #endif 969 970 /** @brief Macro to configure the USART1 clock (USART1CLK). 971 * 972 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 973 * This parameter can be one of the following values: 974 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 975 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 976 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 977 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 978 * @retval None 979 */ 980 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__) 981 982 /** @brief Macro to get the USART1 clock source. 983 * @retval The clock source can be one of the following values: 984 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 985 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 986 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 987 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 988 */ 989 #define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE) 990 991 #if defined(LPUART1) 992 /** @brief Macro to configure the LPUART clock (LPUARTCLK). 993 * 994 * @param __LPUART_CLKSOURCE__ specifies the LPUART clock source. 995 * This parameter can be one of the following values: 996 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 997 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 998 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 999 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1000 * @retval None 1001 */ 1002 #define __HAL_RCC_LPUART1_CONFIG(__LPUART_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART_CLKSOURCE__) 1003 1004 /** @brief Macro to get the LPUART clock source. 1005 * @retval The clock source can be one of the following values: 1006 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 1007 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 1008 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 1009 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 1010 */ 1011 #define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) 1012 #endif 1013 1014 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 1015 * 1016 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 1017 * This parameter can be one of the following values: 1018 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock 1019 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1020 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 1021 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1022 * @retval None 1023 */ 1024 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__) 1025 1026 /** @brief Macro to get the LPTIM1 clock source. 1027 * @retval The clock source can be one of the following values: 1028 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK selected as LPTIM1 clock 1029 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 1030 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPTIM1 clock 1031 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 1032 */ 1033 #define __HAL_RCC_GET_LPTIM1_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE) 1034 1035 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 1036 * 1037 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 1038 * This parameter can be one of the following values: 1039 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock 1040 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1041 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock 1042 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1043 * @retval None 1044 */ 1045 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__) 1046 1047 /** @brief Macro to get the LPTIM2 clock source. 1048 * @retval The clock source can be one of the following values: 1049 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK selected as LPTIM2 clock 1050 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 1051 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock 1052 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 1053 */ 1054 #define __HAL_RCC_GET_LPTIM2_SOURCE() LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE) 1055 1056 1057 /** @brief Macro to configure the RNG clock. 1058 * 1059 * @note USB and RNG peripherals share the same 48MHz clock source. 1060 * 1061 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 1062 * This parameter can be one of the following values: 1063 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock 1064 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock 1065 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock 1066 * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock (default HSI48) 1067 * @arg @ref RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock 1068 * @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock 1069 * @retval None 1070 */ 1071 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 1072 do { \ 1073 if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \ 1074 || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE) \ 1075 || ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48)) \ 1076 { \ 1077 LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__)); \ 1078 } \ 1079 else \ 1080 { \ 1081 uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK); \ 1082 LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \ 1083 LL_RCC_SetCLK48ClockSource(tmp); \ 1084 } \ 1085 } while(0U) 1086 1087 /** @brief Macro to get the direct RNG clock. 1088 * @note @ref HAL_RCCEx_GetRngCLKSource can also be called to get direct 1089 * of indirect (48 MHz clock source) RNG clock source. 1090 * @retval The RNG clock source can be one of the following values: 1091 * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock 1092 * @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock 1093 * @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock 1094 */ 1095 #define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE) 1096 1097 /** @brief Macro to configure the USB clock (USBCLK). 1098 * 1099 * @note USB and RNG peripherals share the same 48MHz clock source. 1100 * 1101 * @param __USB_CLKSOURCE__ specifies the USB clock source. 1102 * This parameter can be one of the following values: 1103 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1104 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1105 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1106 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1107 * @retval None 1108 */ 1109 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) LL_RCC_SetUSBClockSource(__USB_CLKSOURCE__) 1110 1111 /** @brief Macro to get the USB clock source. 1112 * @retval The clock source can be one of the following values: 1113 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 1114 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 1115 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 1116 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 1117 */ 1118 #define __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE) 1119 1120 /** @brief Macro to configure the ADC interface clock. 1121 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 1122 * This parameter can be one of the following values: 1123 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1124 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1125 * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock 1126 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1127 * @retval None 1128 */ 1129 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__) 1130 1131 /** @brief Macro to get the ADC clock source. 1132 * @retval The clock source can be one of the following values: 1133 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 1134 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 1135 * @arg @ref RCC_ADCCLKSOURCE_PLL PLL Clock selected as ADC clock 1136 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 1137 */ 1138 #define __HAL_RCC_GET_ADC_SOURCE() LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE) 1139 1140 /** @brief Macro to configure the RFWKP interface clock. 1141 * @param __RFWKP_CLKSOURCE__ specifies the RFWKP digital interface clock source. 1142 * This parameter can be one of the following values: 1143 * @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock 1144 * @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock 1145 * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock 1146 * @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock 1147 * @retval None 1148 */ 1149 #define __HAL_RCC_RFWAKEUP_CONFIG(__RFWKP_CLKSOURCE__) LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__) 1150 1151 /** @brief Macro to get the RFWKP clock source. 1152 * This parameter can be one of the following values: 1153 * @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock 1154 * @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock 1155 * @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock 1156 * @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock 1157 */ 1158 #define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource() 1159 1160 #if defined(RCC_SMPS_SUPPORT) 1161 /** @brief Macro to configure the SMPS clock division factor. 1162 * 1163 * @param __SMPSCLKDIV__ specifies the division factor for SMPS clock. 1164 * This parameter can be one of the following values: 1165 * @arg @ref RCC_SMPSCLKDIV_RANGE0 1st divider factor value 1166 * @arg @ref RCC_SMPSCLKDIV_RANGE1 2nd divider factor value 1167 * @arg @ref RCC_SMPSCLKDIV_RANGE2 3th divider factor value 1168 * @arg @ref RCC_SMPSCLKDIV_RANGE3 4th divider factor value 1169 * 1170 * @note divider value predefined by HW depending of SMPS clock source 1171 * 1172 * @retval None 1173 */ 1174 #define __HAL_RCC_SMPS_DIV_CONFIG(__SMPSCLKDIV__) LL_RCC_SetSMPSPrescaler(__SMPSCLKDIV__) 1175 1176 /** @brief Macro to get the SMPS clock division factor. 1177 * 1178 * This parameter can be one of the following values: 1179 * @arg @ref RCC_SMPSCLKDIV_RANGE0 1st divider factor value 1180 * @arg @ref RCC_SMPSCLKDIV_RANGE1 2nd divider factor value 1181 * @arg @ref RCC_SMPSCLKDIV_RANGE2 3th divider factor value 1182 * @arg @ref RCC_SMPSCLKDIV_RANGE3 4th divider factor value 1183 * 1184 */ 1185 #define __HAL_RCC_GET_SMPS_DIV() LL_RCC_GetSMPSPrescaler() 1186 1187 /** @brief Macro to configure the SMPS interface clock. 1188 * @param __SMPS_CLKSOURCE__ specifies the SMPS digital interface clock source. 1189 * This parameter can be one of the following values: 1190 * @arg @ref RCC_SMPSCLKSOURCE_HSI HSI clock selected as SMPS clock 1191 * @arg @ref RCC_SMPSCLKSOURCE_MSI MSI Clock selected as SMPS clock 1192 * @arg @ref RCC_SMPSCLKSOURCE_HSE HSE Clock selected as SMPS clock 1193 * @retval None 1194 */ 1195 1196 #define __HAL_RCC_SMPS_CONFIG(__SMPS_CLKSOURCE__) LL_RCC_SetSMPSClockSource(__SMPS_CLKSOURCE__) 1197 1198 /** @brief Macro to get the SMPS clock source. 1199 * This parameter can be one of the following values: 1200 * @arg @ref RCC_SMPSCLKSOURCE_HSI HSI clock selected as SMPS clock 1201 * @arg @ref RCC_SMPSCLKSOURCE_MSI MSI Clock selected as SMPS clock 1202 * @arg @ref RCC_SMPSCLKSOURCE_HSE HSE Clock selected as SMPS clock 1203 */ 1204 #define __HAL_RCC_GET_SMPS_SOURCE() LL_RCC_GetSMPSClockSelection() 1205 1206 /** @brief Macro to get the SMPS clock source. 1207 * This parameter can be one of the following values: 1208 * @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSI HSI clock selected as SMPS clock 1209 * @arg @ref RCC_SMPSCLKSOURCE_STATUS_MSI MSI Clock selected as SMPS clock 1210 * @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSE HSE Clock selected as SMPS clock 1211 */ 1212 #define __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource() 1213 #endif 1214 1215 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 1216 * @brief macros to manage the specified RCC Flags and interrupts. 1217 * @{ 1218 */ 1219 1220 #if defined(SAI1) 1221 /** @brief Enable PLLSAI1RDY interrupt. 1222 * @retval None 1223 */ 1224 #define __HAL_RCC_PLLSAI1_ENABLE_IT() LL_RCC_EnableIT_PLLSAI1RDY() 1225 1226 /** @brief Disable PLLSAI1RDY interrupt. 1227 * @retval None 1228 */ 1229 #define __HAL_RCC_PLLSAI1_DISABLE_IT() LL_RCC_DisableIT_PLLSAI1RDY() 1230 1231 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 1232 * @retval None 1233 */ 1234 #define __HAL_RCC_PLLSAI1_CLEAR_IT() LL_RCC_ClearFlag_PLLSAI1RDY() 1235 1236 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 1237 * @retval TRUE or FALSE. 1238 */ 1239 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() LL_RCC_IsActiveFlag_PLLSAI1RDY() 1240 1241 /** @brief Check whether the PLLSAI1RDY flag is set or not. 1242 * @retval TRUE or FALSE. 1243 */ 1244 #define __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady() 1245 #endif 1246 1247 /** 1248 * @brief Enable the RCC LSE CSS Extended Interrupt C1 Line. 1249 * @retval None 1250 */ 1251 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS) 1252 1253 /** 1254 * @brief Enable the RCC LSE CSS Extended Interrupt C2 Line. 1255 * @retval None 1256 */ 1257 #define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS) 1258 1259 /** 1260 * @brief Disable the RCC LSE CSS Extended Interrupt C1 Line. 1261 * @retval None 1262 */ 1263 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS) 1264 1265 /** 1266 * @brief Disable the RCC LSE CSS Extended Interrupt C2 Line. 1267 * @retval None 1268 */ 1269 #define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS) 1270 1271 /** 1272 * @brief Enable the RCC LSE CSS Event C1 Line. 1273 * @retval None. 1274 */ 1275 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1276 1277 /** 1278 * @brief Enable the RCC LSE CSS Event C2 Line. 1279 * @retval None. 1280 */ 1281 #define __HAL_C2_RCC_LSECSS_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1282 1283 /** 1284 * @brief Disable the RCC LSE CSS Event C1 Line. 1285 * @retval None. 1286 */ 1287 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1288 1289 /** 1290 * @brief Disable the RCC LSE CSS Event C2 Line. 1291 * @retval None. 1292 */ 1293 #define __HAL_C2_RCC_LSECSS_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS) 1294 1295 /** 1296 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 1297 * @retval None. 1298 */ 1299 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1300 1301 /** 1302 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1303 * @retval None. 1304 */ 1305 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1306 1307 /** 1308 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 1309 * @retval None. 1310 */ 1311 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1312 1313 /** 1314 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1315 * @retval None. 1316 */ 1317 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(RCC_EXTI_LINE_LSECSS) 1318 1319 /** 1320 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1321 * @retval None. 1322 */ 1323 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1324 do { \ 1325 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1326 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1327 } while(0) 1328 1329 /** 1330 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1331 * @retval None. 1332 */ 1333 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1334 do { \ 1335 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1336 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1337 } while(0) 1338 1339 /** 1340 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1341 * @retval EXTI RCC LSE CSS Line Status. 1342 */ 1343 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(RCC_EXTI_LINE_LSECSS) 1344 1345 /** 1346 * @brief Clear the RCC LSE CSS EXTI flag. 1347 * @retval None. 1348 */ 1349 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(RCC_EXTI_LINE_LSECSS) 1350 1351 /** 1352 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 1353 * @retval None. 1354 */ 1355 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS) 1356 1357 #if defined(CRS) 1358 /** 1359 * @brief Enable the specified CRS interrupts. 1360 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1361 * This parameter can be any combination of the following values: 1362 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1363 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1364 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1365 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1366 * @retval None 1367 */ 1368 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1369 1370 /** 1371 * @brief Disable the specified CRS interrupts. 1372 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1373 * This parameter can be any combination of the following values: 1374 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1375 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1376 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1377 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1378 * @retval None 1379 */ 1380 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1381 1382 /** @brief Check whether the CRS interrupt has occurred or not. 1383 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1384 * This parameter can be one of the following values: 1385 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1386 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1387 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1388 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1389 * @retval The new state of __INTERRUPT__ (SET or RESET). 1390 */ 1391 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) 1392 1393 /** @brief Clear the CRS interrupt pending bits 1394 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1395 * This parameter can be any combination of the following values: 1396 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1397 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1398 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1399 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1400 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1401 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1402 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1403 */ 1404 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1405 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ 1406 { \ 1407 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1408 } \ 1409 else \ 1410 { \ 1411 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1412 } \ 1413 } while(0) 1414 1415 /** 1416 * @brief Check whether the specified CRS flag is set or not. 1417 * @param __FLAG__ specifies the flag to check. 1418 * This parameter can be one of the following values: 1419 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1420 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1421 * @arg @ref RCC_CRS_FLAG_ERR Error 1422 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1423 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1424 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1425 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1426 * @retval The new state of _FLAG_ (TRUE or FALSE). 1427 */ 1428 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1429 1430 /** 1431 * @brief Clear the CRS specified FLAG. 1432 * @param __FLAG__ specifies the flag to clear. 1433 * This parameter can be one of the following values: 1434 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1435 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1436 * @arg @ref RCC_CRS_FLAG_ERR Error 1437 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1438 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1439 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1440 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1441 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1442 * @retval None 1443 */ 1444 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1445 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1446 { \ 1447 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1448 } \ 1449 else \ 1450 { \ 1451 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1452 } \ 1453 } while(0) 1454 #endif 1455 /** 1456 * @} 1457 */ 1458 1459 1460 #if defined(CRS) 1461 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1462 * @{ 1463 */ 1464 /** 1465 * @brief Enable the oscillator clock for frequency error counter. 1466 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1467 * @retval None 1468 */ 1469 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() LL_CRS_EnableFreqErrorCounter() 1470 1471 /** 1472 * @brief Disable the oscillator clock for frequency error counter. 1473 * @retval None 1474 */ 1475 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() LL_CRS_DisableFreqErrorCounter() 1476 1477 /** 1478 * @brief Enable the automatic hardware adjustement of TRIM bits. 1479 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1480 * @retval None 1481 */ 1482 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() LL_CRS_EnableAutoTrimming() 1483 1484 /** 1485 * @brief Enable or disable the automatic hardware adjustement of TRIM bits. 1486 * @retval None 1487 */ 1488 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() LL_CRS_DisableAutoTrimming() 1489 1490 /** 1491 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1492 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1493 * of the synchronization source after prescaling. It is then decreased by one in order to 1494 * reach the expected synchronization on the zero value. The formula is the following: 1495 * RELOAD = (fTARGET / fSYNC) -1 1496 * @param __FTARGET__ Target frequency (value in Hz) 1497 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1498 * @retval None 1499 */ 1500 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) __LL_CRS_CALC_CALCULATE_RELOADVALUE((__FTARGET__),(__FSYNC__)) 1501 1502 /** 1503 * @} 1504 */ 1505 #endif 1506 1507 /** 1508 * @} 1509 */ 1510 1511 /* Exported functions --------------------------------------------------------*/ 1512 /** @addtogroup RCCEx_Exported_Functions 1513 * @{ 1514 */ 1515 1516 /** @addtogroup RCCEx_Exported_Functions_Group1 1517 * @{ 1518 */ 1519 1520 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1521 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1522 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1523 uint32_t HAL_RCCEx_GetRngCLKSource(void); 1524 1525 /** 1526 * @} 1527 */ 1528 1529 /** @addtogroup RCCEx_Exported_Functions_Group2 1530 * @{ 1531 */ 1532 1533 #if defined(SAI1) 1534 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 1535 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 1536 #endif 1537 1538 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 1539 1540 void HAL_RCCEx_EnableLSECSS(void); 1541 void HAL_RCCEx_DisableLSECSS(void); 1542 void HAL_RCCEx_EnableLSECSS_IT(void); 1543 void HAL_RCCEx_LSECSS_IRQHandler(void); 1544 void HAL_RCCEx_LSECSS_Callback(void); 1545 1546 void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource); 1547 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1548 void HAL_RCCEx_DisableLSCO(void); 1549 1550 void HAL_RCCEx_EnableMSIPLLMode(void); 1551 void HAL_RCCEx_DisableMSIPLLMode(void); 1552 1553 HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType); 1554 1555 /** 1556 * @} 1557 */ 1558 1559 1560 #if defined(CRS) 1561 1562 /** @addtogroup RCCEx_Exported_Functions_Group3 1563 * @{ 1564 */ 1565 1566 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1567 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1568 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1569 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1570 void HAL_RCCEx_CRS_IRQHandler(void); 1571 void HAL_RCCEx_CRS_SyncOkCallback(void); 1572 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1573 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1574 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1575 1576 /** 1577 * @} 1578 */ 1579 1580 #endif 1581 /** 1582 * @} 1583 */ 1584 1585 /** 1586 * @} 1587 */ 1588 1589 /** 1590 * @} 1591 */ 1592 1593 #ifdef __cplusplus 1594 } 1595 #endif 1596 1597 #endif /* STM32WBxx_HAL_RCC_EX_H */ 1598 1599 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1600