1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_RCC_H 22 #define STM32WBxx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 #include "stm32wbxx_ll_rcc.h" 31 #include "stm32wbxx_ll_bus.h" 32 33 34 /** @addtogroup STM32WBxx_HAL_Driver 35 * @{ 36 */ 37 38 /** @addtogroup RCC 39 * @{ 40 */ 41 42 /* Private constants ---------------------------------------------------------*/ 43 /** @addtogroup RCC_Private_Constants 44 * @{ 45 */ 46 /* Defines used for Flags */ 47 #define CR_REG_INDEX 1U 48 #define BDCR_REG_INDEX 2U 49 #define CSR_REG_INDEX 3U 50 #define CRRCR_REG_INDEX 4U 51 52 #define RCC_FLAG_MASK 0x1FU 53 /** 54 * @} 55 */ 56 57 /* Private macros ------------------------------------------------------------*/ 58 /** @addtogroup RCC_Private_Macros 59 * @{ 60 */ 61 62 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 63 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 64 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 65 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 66 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 67 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \ 68 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \ 69 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 70 71 72 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 73 ((__HSE__) == RCC_HSE_BYPASS)) 74 75 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 76 ((__LSE__) == RCC_LSE_BYPASS)) 77 78 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 79 80 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) 81 82 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 83 84 #define IS_RCC_LSI2_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)15U) 85 86 87 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 88 89 90 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) 91 92 93 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 94 95 96 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 97 ((__PLL__) == RCC_PLL_ON)) 98 99 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 100 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 101 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 102 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 103 104 #define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || \ 105 ((__VALUE__) == RCC_PLLM_DIV2) || \ 106 ((__VALUE__) == RCC_PLLM_DIV3) || \ 107 ((__VALUE__) == RCC_PLLM_DIV4) || \ 108 ((__VALUE__) == RCC_PLLM_DIV5) || \ 109 ((__VALUE__) == RCC_PLLM_DIV6) || \ 110 ((__VALUE__) == RCC_PLLM_DIV7) || \ 111 ((__VALUE__) == RCC_PLLM_DIV8)) 112 113 #define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 114 115 #define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) 116 117 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) 118 119 #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) 120 121 #if defined(SAI1) 122 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_ADCCLK) == RCC_PLLSAI1_ADCCLK) || \ 123 (((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 124 (((__VALUE__) & RCC_PLLSAI1_USBCLK) == RCC_PLLSAI1_USBCLK)) && \ 125 (((__VALUE__) & ~(RCC_PLLSAI1_ADCCLK|RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_USBCLK)) == 0U)) 126 #endif 127 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 128 ((__RANGE__) == RCC_MSIRANGE_1) || \ 129 ((__RANGE__) == RCC_MSIRANGE_2) || \ 130 ((__RANGE__) == RCC_MSIRANGE_3) || \ 131 ((__RANGE__) == RCC_MSIRANGE_4) || \ 132 ((__RANGE__) == RCC_MSIRANGE_5) || \ 133 ((__RANGE__) == RCC_MSIRANGE_6) || \ 134 ((__RANGE__) == RCC_MSIRANGE_7) || \ 135 ((__RANGE__) == RCC_MSIRANGE_8) || \ 136 ((__RANGE__) == RCC_MSIRANGE_9) || \ 137 ((__RANGE__) == RCC_MSIRANGE_10) || \ 138 ((__RANGE__) == RCC_MSIRANGE_11)) 139 140 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \ 141 RCC_CLOCKTYPE_HCLK | \ 142 RCC_CLOCKTYPE_PCLK1 | \ 143 RCC_CLOCKTYPE_PCLK2 | \ 144 RCC_CLOCKTYPE_HCLK2 | \ 145 RCC_CLOCKTYPE_HCLK4))) 146 147 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 148 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 149 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 150 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 151 152 #define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || ((__HCLK__) == RCC_SYSCLK_DIV3) || \ 153 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV5) || ((__HCLK__) == RCC_SYSCLK_DIV6) || \ 154 ((__HCLK__) == RCC_SYSCLK_DIV8) || ((__HCLK__) == RCC_SYSCLK_DIV10) || ((__HCLK__) == RCC_SYSCLK_DIV16) || \ 155 ((__HCLK__) == RCC_SYSCLK_DIV32) || ((__HCLK__) == RCC_SYSCLK_DIV64) || ((__HCLK__) == RCC_SYSCLK_DIV128) || \ 156 ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512)) 157 158 #define IS_RCC_PCLKx(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 159 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 160 ((__PCLK__) == RCC_HCLK_DIV16)) 161 162 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 163 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 164 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 165 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 166 167 #define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) || ((__MCOX__) == RCC_MCO3) ) 168 169 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 170 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 171 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 172 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 173 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 174 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 175 ((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \ 176 ((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \ 177 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 178 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 179 180 #define IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) 181 #define IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__)) 182 183 184 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 185 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 186 ((__DIV__) == RCC_MCODIV_16)) 187 188 189 190 191 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 192 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 193 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 194 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 195 196 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 197 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 198 /** 199 * @} 200 */ 201 202 /* Exported types ------------------------------------------------------------*/ 203 /** @defgroup RCC_Exported_Types RCC Exported Types 204 * @{ 205 */ 206 207 208 /** 209 * @brief RCC PLL configuration structure definition 210 */ 211 typedef struct 212 { 213 uint32_t PLLState; /*!< The new state of the PLL. 214 This parameter must be a value of @ref RCC_PLL_Config */ 215 216 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 217 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 218 219 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 220 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 221 222 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 223 This parameter must be a number between Min_Data = 6 and Max_Data = 127 */ 224 225 uint32_t PLLP; /*!< PLLP: Division factor for SAI & ADC clock. 226 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 227 228 uint32_t PLLQ; /*!< PLLQ: Division factor for RNG and USB clocks. 229 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 230 231 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 232 User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. 233 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 234 235 } RCC_PLLInitTypeDef; 236 237 /** 238 * @brief RCC Internal/External Oscillator (HSE, HSI, HSI48, MSI, LSE and LSI) configuration structure definition 239 */ 240 typedef struct 241 { 242 uint32_t OscillatorType; /*!< The oscillators to be configured. 243 This parameter can be a combination of @ref RCC_Oscillator_Type */ 244 245 uint32_t HSEState; /*!< The new state of the HSE. 246 This parameter can be a value of @ref RCC_HSE_Config */ 247 248 uint32_t LSEState; /*!< The new state of the LSE. 249 This parameter can be a value of @ref RCC_LSE_Config */ 250 251 uint32_t HSIState; /*!< The new state of the HSI. 252 This parameter can be a value of @ref RCC_HSI_Config */ 253 254 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_HSICALIBRATION_DEFAULT).*/ 255 256 uint32_t LSIState; /*!< The new state of the LSI. 257 This parameter can be a value of @ref RCC_LSI_Config */ 258 259 uint32_t LSI2CalibrationValue; /*!< The LSI2 calibration trimming value . 260 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xF */ 261 262 uint32_t MSIState; /*!< The new state of the MSI. 263 This parameter can be a value of @ref RCC_MSI_Config */ 264 265 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is @ref RCC_MSICALIBRATION_DEFAULT). 266 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 267 268 uint32_t MSIClockRange; /*!< The MSI frequency range. 269 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 270 271 uint32_t HSI48State; /*!< The new state of the HSI48 . 272 This parameter can be a value of @ref RCC_HSI48_Config */ 273 274 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 275 276 } RCC_OscInitTypeDef; 277 278 /** 279 * @brief RCC System, AHB and APB buses clock configuration structure definition 280 */ 281 typedef struct 282 { 283 uint32_t ClockType; /*!< The clock to be configured. 284 This parameter can be a combination of @ref RCC_System_Clock_Type */ 285 286 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 287 This parameter can be a value of @ref RCC_System_Clock_Source */ 288 289 uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK). 290 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 291 292 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 293 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 294 295 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 296 This parameter can be a value of @ref RCC_APBx_Clock_Source */ 297 298 uint32_t AHBCLK2Divider; /*!< The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK). 299 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 300 301 uint32_t AHBCLK4Divider; /*!< The AHB shared clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK). 302 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 303 304 } RCC_ClkInitTypeDef; 305 306 /** 307 * @} 308 */ 309 310 /* Exported constants --------------------------------------------------------*/ 311 /** @defgroup RCC_Exported_Constants RCC Exported Constants 312 * @{ 313 */ 314 315 /** @defgroup RCC_Timeout_Value Timeout Values 316 * @{ 317 */ 318 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 319 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ 320 /** 321 * @} 322 */ 323 324 /** @defgroup RCC_Oscillator_Type Oscillator Type 325 * @{ 326 */ 327 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 328 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 329 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 330 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 331 #define RCC_OSCILLATORTYPE_LSI1 0x00000008U /*!< LSI1 to configure */ 332 #define RCC_OSCILLATORTYPE_LSI2 0x00000010U /*!< LSI2 to configure */ 333 #define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */ 334 #define RCC_OSCILLATORTYPE_HSI48 0x00000040U /*!< HSI48 to configure */ 335 /** 336 * @} 337 */ 338 339 /** @defgroup RCC_HSE_Config HSE Config 340 * @{ 341 */ 342 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 343 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 344 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup RCC_LSE_Config LSE Config 350 * @{ 351 */ 352 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 353 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 354 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 355 /** 356 * @} 357 */ 358 359 /** @defgroup RCC_HSI_Config HSI Config 360 * @{ 361 */ 362 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 363 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 364 365 #define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ 366 /** 367 * @} 368 */ 369 370 /** @defgroup RCC_LSI_Config LSI Config 371 * @{ 372 */ 373 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 374 #define RCC_LSI_ON (RCC_CSR_LSI1ON | RCC_CSR_LSI2ON) /*!< LSI1 or LSI2 clock activation */ 375 /** 376 * @} 377 */ 378 379 /** @defgroup RCC_MSI_Config MSI Config 380 * @{ 381 */ 382 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 383 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 384 385 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 386 /** 387 * @} 388 */ 389 390 391 /** @defgroup RCC_HSI48_Config HSI48 Config 392 * @{ 393 */ 394 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 395 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 396 /** 397 * @} 398 */ 399 400 401 /** @defgroup RCC_PLL_Config PLL Config 402 * @{ 403 */ 404 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 405 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 406 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 407 /** 408 * @} 409 */ 410 411 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 412 * @{ 413 */ 414 #define RCC_PLLM_DIV1 LL_RCC_PLLM_DIV_1 /*!< PLLM division factor = 1 */ 415 #define RCC_PLLM_DIV2 LL_RCC_PLLM_DIV_2 /*!< PLLM division factor = 2 */ 416 #define RCC_PLLM_DIV3 LL_RCC_PLLM_DIV_3 /*!< PLLM division factor = 3 */ 417 #define RCC_PLLM_DIV4 LL_RCC_PLLM_DIV_4 /*!< PLLM division factor = 4 */ 418 #define RCC_PLLM_DIV5 LL_RCC_PLLM_DIV_5 /*!< PLLM division factor = 5 */ 419 #define RCC_PLLM_DIV6 LL_RCC_PLLM_DIV_6 /*!< PLLM division factor = 6 */ 420 #define RCC_PLLM_DIV7 LL_RCC_PLLM_DIV_7 /*!< PLLM division factor = 7 */ 421 #define RCC_PLLM_DIV8 LL_RCC_PLLM_DIV_8 /*!< PLLM division factor = 8 */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 427 * @{ 428 */ 429 #define RCC_PLLP_DIV2 LL_RCC_PLLP_DIV_2 /*!< PLLP division factor = 2 */ 430 #define RCC_PLLP_DIV3 LL_RCC_PLLP_DIV_3 /*!< PLLP division factor = 3 */ 431 #define RCC_PLLP_DIV4 LL_RCC_PLLP_DIV_4 /*!< PLLP division factor = 4 */ 432 #define RCC_PLLP_DIV5 LL_RCC_PLLP_DIV_5 /*!< PLLP division factor = 5 */ 433 #define RCC_PLLP_DIV6 LL_RCC_PLLP_DIV_6 /*!< PLLP division factor = 6 */ 434 #define RCC_PLLP_DIV7 LL_RCC_PLLP_DIV_7 /*!< PLLP division factor = 7 */ 435 #define RCC_PLLP_DIV8 LL_RCC_PLLP_DIV_8 /*!< PLLP division factor = 8 */ 436 #define RCC_PLLP_DIV9 LL_RCC_PLLP_DIV_9 /*!< PLLP division factor = 9 */ 437 #define RCC_PLLP_DIV10 LL_RCC_PLLP_DIV_10 /*!< PLLP division factor = 10 */ 438 #define RCC_PLLP_DIV11 LL_RCC_PLLP_DIV_11 /*!< PLLP division factor = 11 */ 439 #define RCC_PLLP_DIV12 LL_RCC_PLLP_DIV_12 /*!< PLLP division factor = 12 */ 440 #define RCC_PLLP_DIV13 LL_RCC_PLLP_DIV_13 /*!< PLLP division factor = 13 */ 441 #define RCC_PLLP_DIV14 LL_RCC_PLLP_DIV_14 /*!< PLLP division factor = 14 */ 442 #define RCC_PLLP_DIV15 LL_RCC_PLLP_DIV_15 /*!< PLLP division factor = 15 */ 443 #define RCC_PLLP_DIV16 LL_RCC_PLLP_DIV_16 /*!< PLLP division factor = 16 */ 444 #define RCC_PLLP_DIV17 LL_RCC_PLLP_DIV_17 /*!< PLLP division factor = 17 */ 445 #define RCC_PLLP_DIV18 LL_RCC_PLLP_DIV_18 /*!< PLLP division factor = 18 */ 446 #define RCC_PLLP_DIV19 LL_RCC_PLLP_DIV_19 /*!< PLLP division factor = 19 */ 447 #define RCC_PLLP_DIV20 LL_RCC_PLLP_DIV_20 /*!< PLLP division factor = 20 */ 448 #define RCC_PLLP_DIV21 LL_RCC_PLLP_DIV_21 /*!< PLLP division factor = 21 */ 449 #define RCC_PLLP_DIV22 LL_RCC_PLLP_DIV_22 /*!< PLLP division factor = 22 */ 450 #define RCC_PLLP_DIV23 LL_RCC_PLLP_DIV_23 /*!< PLLP division factor = 23 */ 451 #define RCC_PLLP_DIV24 LL_RCC_PLLP_DIV_24 /*!< PLLP division factor = 24 */ 452 #define RCC_PLLP_DIV25 LL_RCC_PLLP_DIV_25 /*!< PLLP division factor = 25 */ 453 #define RCC_PLLP_DIV26 LL_RCC_PLLP_DIV_26 /*!< PLLP division factor = 26 */ 454 #define RCC_PLLP_DIV27 LL_RCC_PLLP_DIV_27 /*!< PLLP division factor = 27 */ 455 #define RCC_PLLP_DIV28 LL_RCC_PLLP_DIV_28 /*!< PLLP division factor = 28 */ 456 #define RCC_PLLP_DIV29 LL_RCC_PLLP_DIV_29 /*!< PLLP division factor = 29 */ 457 #define RCC_PLLP_DIV30 LL_RCC_PLLP_DIV_30 /*!< PLLP division factor = 30 */ 458 #define RCC_PLLP_DIV31 LL_RCC_PLLP_DIV_31 /*!< PLLP division factor = 31 */ 459 #define RCC_PLLP_DIV32 LL_RCC_PLLP_DIV_32 /*!< PLLP division factor = 32 */ 460 /** 461 * @} 462 */ 463 464 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 465 * @{ 466 */ 467 #define RCC_PLLQ_DIV2 LL_RCC_PLLQ_DIV_2 /*!< PLLQ division factor = 2 */ 468 #define RCC_PLLQ_DIV3 LL_RCC_PLLQ_DIV_3 /*!< PLLQ division factor = 3 */ 469 #define RCC_PLLQ_DIV4 LL_RCC_PLLQ_DIV_4 /*!< PLLQ division factor = 4 */ 470 #define RCC_PLLQ_DIV5 LL_RCC_PLLQ_DIV_5 /*!< PLLQ division factor = 5 */ 471 #define RCC_PLLQ_DIV6 LL_RCC_PLLQ_DIV_6 /*!< PLLQ division factor = 6 */ 472 #define RCC_PLLQ_DIV7 LL_RCC_PLLQ_DIV_7 /*!< PLLQ division factor = 7 */ 473 #define RCC_PLLQ_DIV8 LL_RCC_PLLQ_DIV_8 /*!< PLLQ division factor = 8 */ 474 /** 475 * @} 476 */ 477 478 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 479 * @{ 480 */ 481 #define RCC_PLLR_DIV2 LL_RCC_PLLR_DIV_2 /*!< PLLR division factor = 2 */ 482 #define RCC_PLLR_DIV3 LL_RCC_PLLR_DIV_3 /*!< PLLR division factor = 3 */ 483 #define RCC_PLLR_DIV4 LL_RCC_PLLR_DIV_4 /*!< PLLR division factor = 4 */ 484 #define RCC_PLLR_DIV5 LL_RCC_PLLR_DIV_5 /*!< PLLR division factor = 5 */ 485 #define RCC_PLLR_DIV6 LL_RCC_PLLR_DIV_6 /*!< PLLR division factor = 6 */ 486 #define RCC_PLLR_DIV7 LL_RCC_PLLR_DIV_7 /*!< PLLR division factor = 7 */ 487 #define RCC_PLLR_DIV8 LL_RCC_PLLR_DIV_8 /*!< PLLR division factor = 8 */ 488 /** 489 * @} 490 */ 491 492 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 493 * @{ 494 */ 495 #define RCC_PLLSOURCE_NONE LL_RCC_PLLSOURCE_NONE /*!< No clock selected as PLL entry clock source */ 496 #define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI /*!< MSI clock selected as PLL entry clock source */ 497 #define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI /*!< HSI clock selected as PLL entry clock source */ 498 #define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE /*!< HSE clock selected as PLL entry clock source */ 499 /** 500 * @} 501 */ 502 503 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 504 * @{ 505 */ 506 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 507 #define RCC_PLL_USBCLK RCC_PLLCFGR_PLLQEN /*!< PLLUSBCLK selection from main PLL */ 508 #define RCC_PLL_RNGCLK RCC_PLLCFGR_PLLQEN /*!< PLLRNGCLK selection from main PLL */ 509 #if defined(SAI1) 510 #define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */ 511 #endif 512 #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ 513 /** 514 * @} 515 */ 516 517 #if defined(SAI1) 518 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 519 * @{ 520 */ 521 #define RCC_PLLSAI1_ADCCLK RCC_PLLSAI1CFGR_PLLREN /*!< PLLADCCLK selection from PLLSAI1 */ 522 #define RCC_PLLSAI1_USBCLK RCC_PLLSAI1CFGR_PLLQEN /*!< USBCLK selection from PLLSAI1 */ 523 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLPEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 524 /** 525 * @} 526 */ 527 #endif 528 529 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 530 * @{ 531 */ 532 #define RCC_MSIRANGE_0 LL_RCC_MSIRANGE_0 /*!< MSI = 100 KHz */ 533 #define RCC_MSIRANGE_1 LL_RCC_MSIRANGE_1 /*!< MSI = 200 KHz */ 534 #define RCC_MSIRANGE_2 LL_RCC_MSIRANGE_2 /*!< MSI = 400 KHz */ 535 #define RCC_MSIRANGE_3 LL_RCC_MSIRANGE_3 /*!< MSI = 800 KHz */ 536 #define RCC_MSIRANGE_4 LL_RCC_MSIRANGE_4 /*!< MSI = 1 MHz */ 537 #define RCC_MSIRANGE_5 LL_RCC_MSIRANGE_5 /*!< MSI = 2 MHz */ 538 #define RCC_MSIRANGE_6 LL_RCC_MSIRANGE_6 /*!< MSI = 4 MHz */ 539 #define RCC_MSIRANGE_7 LL_RCC_MSIRANGE_7 /*!< MSI = 8 MHz */ 540 #define RCC_MSIRANGE_8 LL_RCC_MSIRANGE_8 /*!< MSI = 16 MHz */ 541 #define RCC_MSIRANGE_9 LL_RCC_MSIRANGE_9 /*!< MSI = 24 MHz */ 542 #define RCC_MSIRANGE_10 LL_RCC_MSIRANGE_10 /*!< MSI = 32 MHz */ 543 #define RCC_MSIRANGE_11 LL_RCC_MSIRANGE_11 /*!< MSI = 48 MHz */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup RCC_System_Clock_Type System Clock Type 549 * @{ 550 */ 551 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 552 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 553 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 554 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 555 #define RCC_CLOCKTYPE_HCLK2 0x00000020U /*!< HCLK2 to configure */ 556 #define RCC_CLOCKTYPE_HCLK4 0x00000040U /*!< HCLK4 to configure */ 557 /** 558 * @} 559 */ 560 561 /** @defgroup RCC_System_Clock_Source System Clock Source 562 * @{ 563 */ 564 #define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI /*!< MSI selection as system clock */ 565 #define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI /*!< HSI selection as system clock */ 566 #define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE /*!< HSE selection as system clock */ 567 #define RCC_SYSCLKSOURCE_PLLCLK LL_RCC_SYS_CLKSOURCE_PLL /*!< PLL selection as system clock */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 573 * @{ 574 */ 575 #define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI /*!< MSI used as system clock */ 576 #define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI /*!< HSI used as system clock */ 577 #define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE /*!< HSE used as system clock */ 578 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL /*!< PLL used as system clock */ 579 /** 580 * @} 581 */ 582 583 /** @defgroup RCC_AHBx_Clock_Source AHB Clock Source 584 * @{ 585 */ 586 #define RCC_SYSCLK_DIV1 LL_RCC_SYSCLK_DIV_1 /*!< SYSCLK not divided */ 587 #define RCC_SYSCLK_DIV2 LL_RCC_SYSCLK_DIV_2 /*!< SYSCLK divided by 2 */ 588 #define RCC_SYSCLK_DIV3 LL_RCC_SYSCLK_DIV_3 /*!< SYSCLK divided by 3 */ 589 #define RCC_SYSCLK_DIV4 LL_RCC_SYSCLK_DIV_4 /*!< SYSCLK divided by 4 */ 590 #define RCC_SYSCLK_DIV5 LL_RCC_SYSCLK_DIV_5 /*!< SYSCLK divided by 5 */ 591 #define RCC_SYSCLK_DIV6 LL_RCC_SYSCLK_DIV_6 /*!< SYSCLK divided by 6 */ 592 #define RCC_SYSCLK_DIV8 LL_RCC_SYSCLK_DIV_8 /*!< SYSCLK divided by 8 */ 593 #define RCC_SYSCLK_DIV10 LL_RCC_SYSCLK_DIV_10 /*!< SYSCLK divided by 10 */ 594 #define RCC_SYSCLK_DIV16 LL_RCC_SYSCLK_DIV_16 /*!< SYSCLK divided by 16 */ 595 #define RCC_SYSCLK_DIV32 LL_RCC_SYSCLK_DIV_32 /*!< SYSCLK divided by 32 */ 596 #define RCC_SYSCLK_DIV64 LL_RCC_SYSCLK_DIV_64 /*!< SYSCLK divided by 64 */ 597 #define RCC_SYSCLK_DIV128 LL_RCC_SYSCLK_DIV_128 /*!< SYSCLK divided by 128 */ 598 #define RCC_SYSCLK_DIV256 LL_RCC_SYSCLK_DIV_256 /*!< SYSCLK divided by 256 */ 599 #define RCC_SYSCLK_DIV512 LL_RCC_SYSCLK_DIV_512 /*!< SYSCLK divided by 512 */ 600 /** 601 * @} 602 */ 603 604 /** @defgroup RCC_APBx_Clock_Source APB1 Clock Source 605 * @{ 606 */ 607 #define RCC_HCLK_DIV1 LL_RCC_APB1_DIV_1 /*!< HCLK not divided */ 608 #define RCC_HCLK_DIV2 LL_RCC_APB1_DIV_2 /*!< HCLK divided by 2 */ 609 #define RCC_HCLK_DIV4 LL_RCC_APB1_DIV_4 /*!< HCLK divided by 4 */ 610 #define RCC_HCLK_DIV8 LL_RCC_APB1_DIV_8 /*!< HCLK divided by 8 */ 611 #define RCC_HCLK_DIV16 LL_RCC_APB1_DIV_16 /*!< HCLK divided by 16 */ 612 /** 613 * @} 614 */ 615 616 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 617 * @{ 618 */ 619 #define RCC_RTCCLKSOURCE_NONE LL_RCC_RTC_CLKSOURCE_NONE /*!< No clock used as RTC clock */ 620 #define RCC_RTCCLKSOURCE_LSE LL_RCC_RTC_CLKSOURCE_LSE /*!< LSE oscillator clock used as RTC clock */ 621 #define RCC_RTCCLKSOURCE_LSI LL_RCC_RTC_CLKSOURCE_LSI /*!< LSI oscillator clock used as RTC clock */ 622 #define RCC_RTCCLKSOURCE_HSE_DIV32 LL_RCC_RTC_CLKSOURCE_HSE_DIV32 /*!< HSE oscillator clock divided by 32 used as RTC clock */ 623 /** 624 * @} 625 */ 626 627 /** @defgroup RCC_MCO_Index MCO Index 628 * @{ 629 */ 630 #define RCC_MCO1 0x00000000U /*!< MCO1 index */ 631 #define RCC_MCO2 0x00000001U /*!< MCO2 index */ 632 #define RCC_MCO3 0x00000002U /*!< MCO3 index */ 633 634 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ 635 /** 636 * @} 637 */ 638 639 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 640 * @{ 641 */ 642 #define RCC_MCO1SOURCE_NOCLOCK LL_RCC_MCO1SOURCE_NOCLOCK /*!< MCO1 output disabled, no clock on MCO1 */ 643 #define RCC_MCO1SOURCE_SYSCLK LL_RCC_MCO1SOURCE_SYSCLK /*!< SYSCLK selection as MCO1 source */ 644 #define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI selection as MCO1 source */ 645 #define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI selection as MCO1 source */ 646 #define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE after stabilization selection as MCO1 source */ 647 #define RCC_MCO1SOURCE_PLLCLK LL_RCC_MCO1SOURCE_PLLCLK /*!< PLLCLK selection as MCO1 source */ 648 #define RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1 /*!< LSI1 selection as MCO1 source */ 649 #define RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2 /*!< LSI2 selection as MCO1 source */ 650 #define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selection as MCO1 source */ 651 #define RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48 /*!< HSI48 selection as MCO1 source */ 652 #define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB /*!< HSE before stabilization selection as MCO1 source */ 653 654 /** 655 * @} 656 */ 657 658 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 659 * @{ 660 */ 661 #define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO not divided */ 662 #define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ 663 #define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ 664 #define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ 665 #define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16 /*!< MCO divided by 16 */ 666 /** 667 * @} 668 */ 669 670 /** @defgroup RCC_HSEAMPTHRESHOLD HSE bias current factor 671 * @{ 672 */ 673 #define RCC_HSEAMPTHRESHOLD_1_2 LL_RCC_HSEAMPTHRESHOLD_1_2 /*!< HSE bias current factor 1/2 */ 674 #define RCC_HSEAMPTHRESHOLD_3_4 LL_RCC_HSEAMPTHRESHOLD_3_4 /*!< HSE bias current factor 3/4 */ 675 676 /** 677 * @} 678 */ 679 680 /** @defgroup RCC_HSE_CURRENTMAX HSE current max limit 681 * @{ 682 */ 683 #define RCC_HSE_CURRENTMAX_0 LL_RCC_HSE_CURRENTMAX_0 /*!< HSE current max limit 0.18 mA/V */ 684 #define RCC_HSE_CURRENTMAX_1 LL_RCC_HSE_CURRENTMAX_1 /*!< HSE current max limit 0.57 mA/V */ 685 #define RCC_HSE_CURRENTMAX_2 LL_RCC_HSE_CURRENTMAX_2 /*!< HSE current max limit 0.78 mA/V */ 686 #define RCC_HSE_CURRENTMAX_3 LL_RCC_HSE_CURRENTMAX_3 /*!< HSE current max limit 1.13 mA/V */ 687 #define RCC_HSE_CURRENTMAX_4 LL_RCC_HSE_CURRENTMAX_4 /*!< HSE current max limit 0.61 mA/V */ 688 #define RCC_HSE_CURRENTMAX_5 LL_RCC_HSE_CURRENTMAX_5 /*!< HSE current max limit 1.65 mA/V */ 689 #define RCC_HSE_CURRENTMAX_6 LL_RCC_HSE_CURRENTMAX_6 /*!< HSE current max limit 2.12 mA/V */ 690 #define RCC_HSE_CURRENTMAX_7 LL_RCC_HSE_CURRENTMAX_7 /*!< HSE current max limit 2.84 mA/V */ 691 692 /** 693 * @} 694 */ 695 696 /** @defgroup RCC_Interrupt Interrupts 697 * @{ 698 */ 699 #define RCC_IT_LSI1RDY LL_RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ 700 #define RCC_IT_LSI2RDY LL_RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ 701 #define RCC_IT_LSERDY LL_RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 702 #define RCC_IT_MSIRDY LL_RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 703 #define RCC_IT_HSIRDY LL_RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 704 #define RCC_IT_HSERDY LL_RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 705 #define RCC_IT_PLLRDY LL_RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 706 #if defined(SAI1) 707 #define RCC_IT_PLLSAI1RDY LL_RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 708 #endif 709 #define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 710 #define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 711 #define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 712 /** 713 * @} 714 */ 715 716 717 /** @defgroup RCC_Flag Flags 718 * Elements values convention: XXXYYYYYb 719 * - YYYYY : Flag position in the register 720 * - XXX : Register index 721 * - 001: CR register 722 * - 010: BDCR register 723 * - 011: CSR register 724 * - 100: CRRCR register 725 * @{ 726 */ 727 /* Flags in the CR register */ 728 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 729 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 730 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 731 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 732 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 733 734 /* Flags in the BDCR register */ 735 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 736 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 737 738 /* Flags in the CSR register */ 739 #define RCC_FLAG_LSI1RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI1RDY_Pos) /*!< LSI1 Ready flag */ 740 #define RCC_FLAG_LSI2RDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSI2RDY_Pos) /*!< LSI2 Ready flag */ 741 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 742 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< Pin reset flag (NRST pin) */ 743 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 744 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 745 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Watchdog reset flag */ 746 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 747 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 748 749 /* Flags in the CRRCR register */ 750 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 751 752 /** 753 * @} 754 */ 755 756 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration 757 * @{ 758 */ 759 #define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW /*!< LSE low drive capability */ 760 #define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW /*!< LSE medium low drive capability */ 761 #define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH /*!< LSE medium high drive capability */ 762 #define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH /*!< LSE high drive capability */ 763 /** 764 * @} 765 */ 766 767 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 768 * @{ 769 */ 770 #define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_STOP_WAKEUPCLOCK_MSI /*!< MSI selection after wake-up from STOP */ 771 #define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_STOP_WAKEUPCLOCK_HSI /*!< HSI selection after wake-up from STOP */ 772 /** 773 * @} 774 */ 775 776 /** 777 * @} 778 */ 779 780 /* Exported macros -----------------------------------------------------------*/ 781 782 /** @defgroup RCC_Exported_Macros RCC Exported Macros 783 * @{ 784 */ 785 786 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 787 * @brief Enable or disable the AHB1 peripheral clock. 788 * @note After reset, the peripheral clock (used for registers read/write access) 789 * is disabled and the application software has to enable this clock before 790 * using it. 791 * @{ 792 */ 793 794 #define __HAL_RCC_DMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) 795 #if defined(DMA2) 796 #define __HAL_RCC_DMA2_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2) 797 #endif 798 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 799 #define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC) 800 #define __HAL_RCC_TSC_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC) 801 802 #define __HAL_RCC_DMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1) 803 #if defined(DMA2) 804 #define __HAL_RCC_DMA2_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2) 805 #endif 806 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 807 #define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC) 808 #define __HAL_RCC_TSC_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_TSC) 809 810 /** 811 * @} 812 */ 813 814 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 815 * @brief Enable or disable the AHB2 peripheral clock. 816 * @note After reset, the peripheral clock (used for registers read/write access) 817 * is disabled and the application software has to enable this clock before 818 * using it. 819 * @{ 820 */ 821 822 #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 823 #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 824 #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 825 826 #if defined(GPIOD) 827 #define __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD) 828 #endif 829 #define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE) 830 #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 831 832 #define __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC) 833 #if defined(AES1) 834 #define __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1) 835 #endif 836 #define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA) 837 #define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB) 838 #define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC) 839 #if defined(GPIOD) 840 #define __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD) 841 #endif 842 #define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE) 843 #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH) 844 845 #define __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC) 846 847 #if defined(AES1) 848 #define __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1) 849 #endif 850 851 /** 852 * @} 853 */ 854 855 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 856 * @brief Enable or disable the AHB3 peripheral clock. 857 * @note After reset, the peripheral clock (used for registers read/write access) 858 * is disabled and the application software has to enable this clock before 859 * using it. 860 * @{ 861 */ 862 863 #if defined(QUADSPI) 864 #define __HAL_RCC_QUADSPI_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 865 #endif 866 #define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) 867 #define __HAL_RCC_AES2_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2) 868 #define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) 869 #define __HAL_RCC_HSEM_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM) 870 #define __HAL_RCC_IPCC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC) 871 #define __HAL_RCC_FLASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH) 872 873 #if defined(QUADSPI) 874 #define __HAL_RCC_QUADSPI_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 875 #endif 876 #define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) 877 #define __HAL_RCC_AES2_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES2) 878 #define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) 879 #define __HAL_RCC_HSEM_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM) 880 #define __HAL_RCC_IPCC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC) 881 #define __HAL_RCC_FLASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH) 882 883 /** 884 * @} 885 */ 886 887 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 888 * @brief Enable or disable the APB1 peripheral clock. 889 * @note After reset, the peripheral clock (used for registers read/write access) 890 * is disabled and the application software has to enable this clock before 891 * using it. 892 * @{ 893 */ 894 895 #define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 896 #define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) 897 #define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) 898 #if defined(LCD) 899 #define __HAL_RCC_LCD_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD) 900 #endif 901 #if defined(SPI2) 902 #define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) 903 #endif 904 #define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) 905 #if defined(I2C3) 906 #define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) 907 #endif 908 #if defined(CRS) 909 #define __HAL_RCC_CRS_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS) 910 #endif 911 #if defined(USB) 912 #define __HAL_RCC_USB_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB) 913 #endif 914 #define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 915 #define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 916 #if defined(LPUART1) 917 #define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1) 918 #endif 919 920 #define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB) 921 #define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) 922 #if defined(LCD) 923 #define __HAL_RCC_LCD_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LCD) 924 #endif 925 #if defined(SPI2) 926 #define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) 927 #endif 928 #define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) 929 #if defined(I2C3) 930 #define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) 931 #endif 932 #if defined(CRS) 933 #define __HAL_RCC_CRS_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_CRS) 934 #endif 935 #if defined(USB) 936 #define __HAL_RCC_USB_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USB) 937 #endif 938 #define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 939 940 #define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2) 941 #if defined(LPUART1) 942 #define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1) 943 #endif 944 945 /** 946 * @} 947 */ 948 949 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 950 * @brief Enable or disable the APB2 peripheral clock. 951 * @note After reset, the peripheral clock (used for registers read/write access) 952 * is disabled and the application software has to enable this clock before 953 * using it. 954 * @{ 955 */ 956 957 #define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) 958 #define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) 959 #define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) 960 #define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) 961 #define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) 962 #if defined(SAI1) 963 #define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1) 964 #endif 965 966 #define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) 967 #define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) 968 #define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) 969 #define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) 970 #define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) 971 #if defined(SAI1) 972 #define __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1) 973 #endif 974 975 /** 976 * @} 977 */ 978 979 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 980 * @brief Check whether the AHB1 peripheral clock is enabled or not. 981 * @note After reset, the peripheral clock (used for registers read/write access) 982 * is disabled and the application software has to enable this clock before 983 * using it. 984 * @{ 985 */ 986 987 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1) 988 #if defined(DMA2) 989 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2) 990 #endif 991 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1) 992 #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC) 993 #define __HAL_RCC_TSC_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC) 994 995 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)) 996 #if defined(DMA2) 997 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)) 998 #endif 999 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)) 1000 #define __HAL_RCC_CRC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)) 1001 #define __HAL_RCC_TSC_IS_CLK_DISABLED() !(LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_TSC)) 1002 1003 /** 1004 * @} 1005 */ 1006 1007 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1008 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1009 * @note After reset, the peripheral clock (used for registers read/write access) 1010 * is disabled and the application software has to enable this clock before 1011 * using it. 1012 * @{ 1013 */ 1014 1015 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA) 1016 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB) 1017 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC) 1018 #if defined(GPIOD) 1019 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD) 1020 #endif 1021 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE) 1022 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH) 1023 #define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC) 1024 #if defined(AES1) 1025 #define __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1) 1026 #endif 1027 1028 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)) 1029 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)) 1030 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)) 1031 #if defined(GPIOD) 1032 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD)) 1033 #endif 1034 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)) 1035 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)) 1036 #define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)) 1037 #if defined(AES1) 1038 #define __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)) 1039 #endif 1040 1041 /** 1042 * @} 1043 */ 1044 1045 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1046 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1047 * @note After reset, the peripheral clock (used for registers read/write access) 1048 * is disabled and the application software has to enable this clock before 1049 * using it. 1050 * @{ 1051 */ 1052 1053 #if defined(QUADSPI) 1054 #define __HAL_RCC_QUADSPI_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI) 1055 #endif 1056 #define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) 1057 #define __HAL_RCC_AES2_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2) 1058 #define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) 1059 #define __HAL_RCC_HSEM_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM) 1060 #define __HAL_RCC_IPCC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC) 1061 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH) 1062 1063 #if defined(QUADSPI) 1064 #define __HAL_RCC_QUADSPI_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_QUADSPI)) 1065 #endif 1066 #define __HAL_RCC_PKA_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)) 1067 #define __HAL_RCC_AES2_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES2)) 1068 #define __HAL_RCC_RNG_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)) 1069 #define __HAL_RCC_HSEM_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)) 1070 #define __HAL_RCC_IPCC_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)) 1071 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() !(LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)) 1072 1073 /** 1074 * @} 1075 */ 1076 1077 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1078 * @brief Check whether the APB1 peripheral clock is enabled or not. 1079 * @note After reset, the peripheral clock (used for registers read/write access) 1080 * is disabled and the application software has to enable this clock before 1081 * using it. 1082 * @{ 1083 */ 1084 1085 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB) 1086 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) 1087 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) 1088 #if defined(LCD) 1089 #define __HAL_RCC_LCD_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD) 1090 #endif 1091 #if defined(SPI2) 1092 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) 1093 #endif 1094 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) 1095 #if defined(I2C3) 1096 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) 1097 #endif 1098 #if defined(CRS) 1099 #define __HAL_RCC_CRS_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS) 1100 #endif 1101 #if defined(USB) 1102 #define __HAL_RCC_USB_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB) 1103 #endif 1104 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1105 1106 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2) 1107 #if defined(LPUART1) 1108 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1) 1109 #endif 1110 1111 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)) 1112 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)) 1113 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)) 1114 #if defined(LCD) 1115 #define __HAL_RCC_LCD_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LCD)) 1116 #endif 1117 #if defined(SPI2) 1118 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)) 1119 #endif 1120 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)) 1121 #if defined(I2C3) 1122 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)) 1123 #endif 1124 #if defined(CRS) 1125 #define __HAL_RCC_CRS_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_CRS)) 1126 #endif 1127 #if defined(USB) 1128 #define __HAL_RCC_USB_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USB)) 1129 #endif 1130 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() !(LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)) 1131 1132 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)) 1133 #if defined(LPUART1) 1134 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() !(LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)) 1135 #endif 1136 1137 /** 1138 * @} 1139 */ 1140 1141 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1142 * @brief Check whether the APB2 peripheral clock is enabled or not. 1143 * @note After reset, the peripheral clock (used for registers read/write access) 1144 * is disabled and the application software has to enable this clock before 1145 * using it. 1146 * @{ 1147 */ 1148 1149 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) 1150 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) 1151 #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) 1152 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) 1153 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) 1154 #if defined(SAI1) 1155 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1) 1156 #endif 1157 1158 1159 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)) 1160 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)) 1161 #define __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)) 1162 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)) 1163 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)) 1164 #if defined(SAI1) 1165 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1)) 1166 #endif 1167 1168 /** 1169 * @} 1170 */ 1171 1172 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 1173 * @brief Enable or disable the AHB1 peripheral clock. 1174 * @note After reset, the peripheral clock (used for registers read/write access) 1175 * is disabled and the application software has to enable this clock before 1176 * using it. 1177 * @{ 1178 */ 1179 1180 #define __HAL_RCC_C2DMA1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1181 #if defined(DMA2) 1182 #define __HAL_RCC_C2DMA2_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1183 #endif 1184 #define __HAL_RCC_C2DMAMUX1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1185 #define __HAL_RCC_C2SRAM1_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1186 #define __HAL_RCC_C2CRC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1187 #define __HAL_RCC_C2TSC_CLK_ENABLE() LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1188 1189 #define __HAL_RCC_C2DMA1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1190 #if defined(DMA2) 1191 #define __HAL_RCC_C2DMA2_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1192 #endif 1193 #define __HAL_RCC_C2DMAMUX1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1194 #define __HAL_RCC_C2SRAM1_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1195 #define __HAL_RCC_C2CRC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1196 #define __HAL_RCC_C2TSC_CLK_DISABLE() LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1197 1198 /** 1199 * @} 1200 */ 1201 1202 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 1203 * @brief Enable or disable the AHB2 peripheral clock. 1204 * @note After reset, the peripheral clock (used for registers read/write access) 1205 * is disabled and the application software has to enable this clock before 1206 * using it. 1207 * @{ 1208 */ 1209 1210 #define __HAL_RCC_C2GPIOA_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1211 #define __HAL_RCC_C2GPIOB_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1212 #define __HAL_RCC_C2GPIOC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1213 #if defined(GPIOD) 1214 #define __HAL_RCC_C2GPIOD_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1215 #endif 1216 #define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1217 #define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1218 #define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1219 #if defined(GPIOD) 1220 #define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1221 #endif 1222 1223 #define __HAL_RCC_C2GPIOA_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1224 #define __HAL_RCC_C2GPIOB_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1225 #define __HAL_RCC_C2GPIOC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1226 #if defined(GPIOD) 1227 #define __HAL_RCC_C2GPIOD_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1228 #endif 1229 #define __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1230 #define __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1231 #define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1232 #if defined(AES1) 1233 #define __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1234 #endif 1235 1236 /** 1237 * @} 1238 */ 1239 1240 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 1241 * @brief Enable or disable the AHB3 peripheral clock. 1242 * @note After reset, the peripheral clock (used for registers read/write access) 1243 * is disabled and the application software has to enable this clock before 1244 * using it. 1245 * @{ 1246 */ 1247 1248 #define __HAL_RCC_C2PKA_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1249 #define __HAL_RCC_C2AES2_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1250 #define __HAL_RCC_C2RNG_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1251 #define __HAL_RCC_C2HSEM_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1252 #define __HAL_RCC_C2IPCC_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1253 #define __HAL_RCC_C2FLASH_CLK_ENABLE() LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1254 1255 #define __HAL_RCC_C2PKA_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1256 #define __HAL_RCC_C2AES2_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1257 #define __HAL_RCC_C2RNG_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1258 #define __HAL_RCC_C2HSEM_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1259 #define __HAL_RCC_C2IPCC_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1260 #define __HAL_RCC_C2FLASH_CLK_DISABLE() LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1261 1262 /** 1263 * @} 1264 */ 1265 1266 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1267 * @brief Enable or disable the APB1 peripheral clock. 1268 * @note After reset, the peripheral clock (used for registers read/write access) 1269 * is disabled and the application software has to enable this clock before 1270 * using it. 1271 * @{ 1272 */ 1273 1274 #define __HAL_RCC_C2RTCAPB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1275 #define __HAL_RCC_C2TIM2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1276 #if defined(LCD) 1277 #define __HAL_RCC_C2LCD_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1278 #endif 1279 #if defined(SPI2) 1280 #define __HAL_RCC_C2SPI2_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1281 #endif 1282 #define __HAL_RCC_C2I2C1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1283 #if defined(I2C3) 1284 #define __HAL_RCC_C2I2C3_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1285 #endif 1286 #if defined(CRS) 1287 #define __HAL_RCC_C2CRS_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1288 #endif 1289 #if defined(USB) 1290 #define __HAL_RCC_C2USB_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USB) 1291 #endif 1292 #define __HAL_RCC_C2LPTIM1_CLK_ENABLE() LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1293 1294 #define __HAL_RCC_C2LPTIM2_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1295 #if defined(LPUART1) 1296 #define __HAL_RCC_C2LPUART1_CLK_ENABLE() LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1297 #endif 1298 1299 #define __HAL_RCC_C2RTCAPB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1300 #define __HAL_RCC_C2TIM2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1301 #if defined(LCD) 1302 #define __HAL_RCC_C2LCD_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1303 #endif 1304 #if defined(SPI2) 1305 #define __HAL_RCC_C2SPI2_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1306 #endif 1307 #define __HAL_RCC_C2I2C1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1308 #if defined(I2C3) 1309 #define __HAL_RCC_C2I2C3_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1310 #endif 1311 #if defined(CRS) 1312 #define __HAL_RCC_C2CRS_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1313 #endif 1314 #if defined(USB) 1315 #define __HAL_RCC_C2USB_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USB) 1316 #endif 1317 #define __HAL_RCC_C2LPTIM1_CLK_DISABLE() LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1318 1319 #define __HAL_RCC_C2LPTIM2_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1320 #if defined(LPUART1) 1321 #define __HAL_RCC_C2LPUART1_CLK_DISABLE() LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1322 #endif 1323 1324 /** 1325 * @} 1326 */ 1327 1328 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1329 * @brief Enable or disable the APB2 peripheral clock. 1330 * @note After reset, the peripheral clock (used for registers read/write access) 1331 * is disabled and the application software has to enable this clock before 1332 * using it. 1333 * @{ 1334 */ 1335 1336 #define __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1337 #define __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1338 #define __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1339 #define __HAL_RCC_C2TIM16_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1340 #define __HAL_RCC_C2TIM17_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1341 #if defined(SAI1) 1342 #define __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1343 #endif 1344 1345 #define __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1346 #define __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1347 #define __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1348 #define __HAL_RCC_C2TIM16_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1349 #define __HAL_RCC_C2TIM17_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1350 #if defined(SAI1) 1351 #define __HAL_RCC_C2SAI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1352 #endif 1353 1354 /** 1355 * @} 1356 */ 1357 1358 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1359 * @brief Enable or disable the APB3 peripheral clock. 1360 * @note After reset, the peripheral clock (used for registers read/write access) 1361 * is disabled and the application software has to enable this clock before 1362 * using it. 1363 * @{ 1364 */ 1365 1366 #define __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1367 #define __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802) 1368 1369 #define __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1370 #define __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802) 1371 1372 1373 /** 1374 * @} 1375 */ 1376 1377 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1378 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1379 * @note After reset, the peripheral clock (used for registers read/write access) 1380 * is disabled and the application software has to enable this clock before 1381 * using it. 1382 * @{ 1383 */ 1384 1385 #define __HAL_RCC_C2DMA1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1386 #if defined(DMA2) 1387 #define __HAL_RCC_C2DMA2_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1388 #endif 1389 #define __HAL_RCC_C2DMAMUX1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1390 #define __HAL_RCC_C2SRAM1_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1391 #define __HAL_RCC_C2CRC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC) 1392 #define __HAL_RCC_C2TSC_IS_CLK_ENABLED() LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC) 1393 1394 #define __HAL_RCC_C2DMA1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)) 1395 #if defined(DMA2) 1396 #define __HAL_RCC_C2DMA2_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)) 1397 #endif 1398 #define __HAL_RCC_C2DMAMUX1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)) 1399 #define __HAL_RCC_C2SRAM1_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_SRAM1)) 1400 #define __HAL_RCC_C2CRC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)) 1401 #define __HAL_RCC_C2TSC_IS_CLK_DISABLED() !(LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_TSC)) 1402 1403 /** 1404 * @} 1405 */ 1406 1407 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1408 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1409 * @note After reset, the peripheral clock (used for registers read/write access) 1410 * is disabled and the application software has to enable this clock before 1411 * using it. 1412 * @{ 1413 */ 1414 1415 #define __HAL_RCC_C2GPIOA_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1416 #define __HAL_RCC_C2GPIOB_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1417 #define __HAL_RCC_C2GPIOC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1418 #if defined(GPIOD) 1419 #define __HAL_RCC_C2GPIOD_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1420 #endif 1421 #define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1422 #define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1423 #define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC) 1424 #if defined(AES1) 1425 #define __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1) 1426 #endif 1427 1428 #define __HAL_RCC_C2GPIOA_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)) 1429 #define __HAL_RCC_C2GPIOB_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)) 1430 #define __HAL_RCC_C2GPIOC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)) 1431 #if defined(GPIOD) 1432 #define __HAL_RCC_C2GPIOD_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOD)) 1433 #endif 1434 #define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)) 1435 #define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)) 1436 #define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)) 1437 #if defined(AES1) 1438 #define __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)) 1439 #endif 1440 1441 /** 1442 * @} 1443 */ 1444 1445 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1446 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1447 * @note After reset, the peripheral clock (used for registers read/write access) 1448 * is disabled and the application software has to enable this clock before 1449 * using it. 1450 * @{ 1451 */ 1452 1453 #define __HAL_RCC_C2PKA_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA) 1454 #define __HAL_RCC_C2AES2_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2) 1455 #define __HAL_RCC_C2RNG_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG) 1456 #define __HAL_RCC_C2HSEM_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM) 1457 #define __HAL_RCC_C2IPCC_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC) 1458 #define __HAL_RCC_C2FLASH_IS_CLK_ENABLED() LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1459 1460 #define __HAL_RCC_C2PKA_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)) 1461 #define __HAL_RCC_C2AES2_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES2)) 1462 #define __HAL_RCC_C2RNG_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)) 1463 #define __HAL_RCC_C2HSEM_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)) 1464 #define __HAL_RCC_C2IPCC_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)) 1465 #define __HAL_RCC_C2FLASH_IS_CLK_DISABLED() !(LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)) 1466 1467 /** 1468 * @} 1469 */ 1470 1471 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1472 * @brief Check whether the APB1 peripheral clock is enabled or not. 1473 * @note After reset, the peripheral clock (used for registers read/write access) 1474 * is disabled and the application software has to enable this clock before 1475 * using it. 1476 * @{ 1477 */ 1478 1479 #define __HAL_RCC_C2RTCAPB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 1480 #define __HAL_RCC_C2TIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2) 1481 #if defined(LCD) 1482 #define __HAL_RCC_C2LCD_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD) 1483 #endif 1484 #if defined(SPI2) 1485 #define __HAL_RCC_C2SPI2_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2) 1486 #endif 1487 #define __HAL_RCC_C2I2C1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1) 1488 #if defined(I2C3) 1489 #define __HAL_RCC_C2I2C3_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3) 1490 #endif 1491 #if defined(CRS) 1492 #define __HAL_RCC_C2CRS_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS) 1493 #endif 1494 #if defined(USB) 1495 #define __HAL_RCC_C2USB_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB) 1496 #endif 1497 #define __HAL_RCC_C2LPTIM1_IS_CLK_ENABLED() LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 1498 1499 #define __HAL_RCC_C2LPTIM2_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 1500 #if defined(LPUART1) 1501 #define __HAL_RCC_C2LPUART1_IS_CLK_ENABLED() LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1) 1502 #endif 1503 1504 #define __HAL_RCC_C2RTCAPB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)) 1505 #define __HAL_RCC_C2TIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)) 1506 #if defined(LCD) 1507 #define __HAL_RCC_C2LCD_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LCD)) 1508 #endif 1509 #if defined(SPI2) 1510 #define __HAL_RCC_C2SPI2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)) 1511 #endif 1512 #define __HAL_RCC_C2I2C1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)) 1513 #if defined(I2C3) 1514 #define __HAL_RCC_C2I2C3_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)) 1515 #endif 1516 #if defined(CRS) 1517 #define __HAL_RCC_C2CRS_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_CRS)) 1518 #endif 1519 #if defined(USB) 1520 #define __HAL_RCC_C2USB_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USB)) 1521 #endif 1522 #define __HAL_RCC_C2LPTIM1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) 1523 1524 #define __HAL_RCC_C2LPTIM2_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)) 1525 #if defined(LPUART1) 1526 #define __HAL_RCC_C2LPUART1_IS_CLK_DISABLED() !(LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)) 1527 #endif 1528 1529 /** 1530 * @} 1531 */ 1532 1533 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1534 * @brief Check whether the APB2 peripheral clock is enabled or not. 1535 * @note After reset, the peripheral clock (used for registers read/write access) 1536 * is disabled and the application software has to enable this clock before 1537 * using it. 1538 * @{ 1539 */ 1540 1541 #define __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1) 1542 #define __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1) 1543 #define __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1) 1544 #define __HAL_RCC_C2TIM16_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16) 1545 #define __HAL_RCC_C2TIM17_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17) 1546 #if defined(SAI1) 1547 #define __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1) 1548 #endif 1549 1550 #define __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)) 1551 #define __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)) 1552 #define __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)) 1553 #define __HAL_RCC_C2TIM16_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)) 1554 #define __HAL_RCC_C2TIM17_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)) 1555 #if defined(SAI1) 1556 #define __HAL_RCC_C2SAI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)) 1557 #endif 1558 1559 /** 1560 * @} 1561 */ 1562 1563 1564 /** @defgroup RCC_APB3_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 1565 * @brief Check whether the APB3 peripheral clock is enabled or not. 1566 * @note After reset, the peripheral clock (used for registers read/write access) 1567 * is disabled and the application software has to enable this clock before 1568 * using it. 1569 * @{ 1570 */ 1571 1572 #define __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE) 1573 #define __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802) 1574 1575 #define __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)) 1576 #define __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)) 1577 1578 /** 1579 * @} 1580 */ 1581 1582 1583 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1584 * @brief Force or release AHB1 peripheral reset. 1585 * @{ 1586 */ 1587 #define __HAL_RCC_AHB1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL) 1588 #define __HAL_RCC_DMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1) 1589 #if defined(DMA2) 1590 #define __HAL_RCC_DMA2_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2) 1591 #endif 1592 #define __HAL_RCC_DMAMUX1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1593 #define __HAL_RCC_CRC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC) 1594 #define __HAL_RCC_TSC_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_TSC) 1595 1596 1597 #define __HAL_RCC_AHB1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL) 1598 #define __HAL_RCC_DMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1) 1599 #if defined(DMA2) 1600 #define __HAL_RCC_DMA2_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2) 1601 #endif 1602 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1603 #define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC) 1604 #define __HAL_RCC_TSC_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_TSC) 1605 1606 1607 /** 1608 * @} 1609 */ 1610 1611 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1612 * @brief Force or release AHB2 peripheral reset. 1613 * @{ 1614 */ 1615 #define __HAL_RCC_AHB2_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) 1616 #define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1617 #define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1618 #define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1619 #if defined(GPIOD) 1620 #define __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD) 1621 #endif 1622 #define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE) 1623 #define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1624 #define __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC) 1625 #if defined(AES1) 1626 #define __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1) 1627 #endif 1628 1629 #define __HAL_RCC_AHB2_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) 1630 #define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA) 1631 #define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB) 1632 #define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC) 1633 #if defined(GPIOD) 1634 #define __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD) 1635 #endif 1636 #define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE) 1637 #define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH) 1638 #define __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC) 1639 #if defined(AES1) 1640 #define __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1) 1641 #endif 1642 1643 /** 1644 * @} 1645 */ 1646 1647 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1648 * @brief Force or release AHB3 peripheral reset. 1649 * @{ 1650 */ 1651 #define __HAL_RCC_AHB3_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL) 1652 #if defined(QUADSPI) 1653 #define __HAL_RCC_QUADSPI_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_QUADSPI) 1654 #endif 1655 #define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) 1656 #define __HAL_RCC_AES2_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES2) 1657 #define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) 1658 #define __HAL_RCC_HSEM_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM) 1659 #define __HAL_RCC_IPCC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC) 1660 #define __HAL_RCC_FLASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH) 1661 1662 #define __HAL_RCC_AHB3_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL) 1663 #if defined(QUADSPI) 1664 #define __HAL_RCC_QUADSPI_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_QUADSPI) 1665 #endif 1666 #define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) 1667 #define __HAL_RCC_AES2_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES2) 1668 #define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) 1669 #define __HAL_RCC_HSEM_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM) 1670 #define __HAL_RCC_IPCC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC) 1671 #define __HAL_RCC_FLASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH) 1672 /** 1673 * @} 1674 */ 1675 1676 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1677 * @brief Force or release APB1 peripheral reset. 1678 * @{ 1679 */ 1680 1681 #define __HAL_RCC_APB1L_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL) 1682 #define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) 1683 #if defined(LCD) 1684 #define __HAL_RCC_LCD_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LCD) 1685 #endif 1686 #if defined(SPI2) 1687 #define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) 1688 #endif 1689 #define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) 1690 #if defined(I2C3) 1691 #define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) 1692 #endif 1693 #if defined(CRS) 1694 #define __HAL_RCC_CRS_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS) 1695 #endif 1696 #if defined(USB) 1697 #define __HAL_RCC_USB_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USB) 1698 #endif 1699 #define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1700 1701 #define __HAL_RCC_APB1H_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL) 1702 #if defined(LPUART1) 1703 #define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1) 1704 #endif 1705 #define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1706 1707 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 1708 __HAL_RCC_APB1L_FORCE_RESET();\ 1709 __HAL_RCC_APB1H_FORCE_RESET();\ 1710 } while(0U) 1711 1712 #define __HAL_RCC_APB1L_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL) 1713 #define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) 1714 #if defined(LCD) 1715 #define __HAL_RCC_LCD_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LCD) 1716 #endif 1717 #if defined(SPI2) 1718 #define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) 1719 #endif 1720 #define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) 1721 #if defined(I2C3) 1722 #define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) 1723 #endif 1724 #if defined(CRS) 1725 #define __HAL_RCC_CRS_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS) 1726 #endif 1727 #if defined(USB) 1728 #define __HAL_RCC_USB_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USB) 1729 #endif 1730 #define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) 1731 1732 #define __HAL_RCC_APB1H_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL) 1733 #if defined(LPUART1) 1734 #define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1) 1735 #endif 1736 #define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2) 1737 1738 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 1739 __HAL_RCC_APB1L_RELEASE_RESET();\ 1740 __HAL_RCC_APB1H_RELEASE_RESET();\ 1741 } while(0U) 1742 /** 1743 * @} 1744 */ 1745 1746 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1747 * @brief Force or release APB2 peripheral reset. 1748 * @{ 1749 */ 1750 #define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL) 1751 #define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) 1752 #define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) 1753 #define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) 1754 #define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) 1755 #define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) 1756 #if defined(SAI1) 1757 #define __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1) 1758 #endif 1759 1760 #define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) 1761 #define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) 1762 #define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) 1763 #define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) 1764 #define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) 1765 #define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) 1766 #if defined(SAI1) 1767 #define __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1) 1768 #endif 1769 /** 1770 * @} 1771 */ 1772 1773 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 1774 * @brief Force or release APB3 peripheral reset. 1775 * @{ 1776 */ 1777 #define __HAL_RCC_APB3_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL) 1778 #define __HAL_RCC_RF_FORCE_RESET() LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_RF) 1779 1780 #define __HAL_RCC_APB3_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL) 1781 #define __HAL_RCC_RF_RELEASE_RESET() LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_RF) 1782 1783 /** 1784 * @} 1785 */ 1786 1787 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 1788 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1789 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1790 * power consumption. 1791 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1792 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1793 * @{ 1794 */ 1795 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1796 #if defined(DMA2) 1797 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1798 #endif 1799 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1800 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) 1801 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1802 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) 1803 1804 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1) 1805 #if defined(DMA2) 1806 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2) 1807 #endif 1808 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1) 1809 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_SRAM1) 1810 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC) 1811 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_TSC) 1812 1813 #define __HAL_RCC_C2DMA1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1814 #if defined(DMA2) 1815 #define __HAL_RCC_C2DMA2_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1816 #endif 1817 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1818 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1819 #define __HAL_RCC_C2CRC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1820 #define __HAL_RCC_C2TSC_CLK_SLEEP_ENABLE() LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) 1821 1822 #define __HAL_RCC_C2DMA1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1) 1823 #if defined(DMA2) 1824 #define __HAL_RCC_C2DMA2_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2) 1825 #endif 1826 #define __HAL_RCC_C2DMAMUX1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1) 1827 #define __HAL_RCC_C2SRAM1_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_SRAM1) 1828 1829 #define __HAL_RCC_C2CRC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC) 1830 #define __HAL_RCC_C2TSC_CLK_SLEEP_DISABLE() LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_TSC) 1831 1832 /** 1833 * @} 1834 */ 1835 1836 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 1837 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 1838 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1839 * power consumption. 1840 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1841 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1842 * @{ 1843 */ 1844 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 1845 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 1846 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 1847 #if defined(GPIOD) 1848 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) 1849 #endif 1850 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) 1851 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 1852 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) 1853 #if defined(AES1) 1854 #define __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) 1855 #endif 1856 1857 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA) 1858 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB) 1859 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC) 1860 #if defined(GPIOD) 1861 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOD) 1862 #endif 1863 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE) 1864 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH) 1865 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC) 1866 #if defined(AES1) 1867 #define __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1) 1868 #endif 1869 1870 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1871 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1872 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1873 #if defined(GPIOD) 1874 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1875 #endif 1876 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1877 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1878 #define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) 1879 #if defined(AES1) 1880 #define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) 1881 #endif 1882 1883 #define __HAL_RCC_C2GPIOA_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA) 1884 #define __HAL_RCC_C2GPIOB_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB) 1885 #define __HAL_RCC_C2GPIOC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC) 1886 #if defined(GPIOD) 1887 #define __HAL_RCC_C2GPIOD_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOD) 1888 #endif 1889 #define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE) 1890 #define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH) 1891 #define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC) 1892 #if defined(AES1) 1893 #define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1) 1894 #endif 1895 1896 /** 1897 * @} 1898 */ 1899 1900 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 1901 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 1902 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1903 * power consumption. 1904 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1905 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1906 * @{ 1907 */ 1908 #if defined(QUADSPI) 1909 #define __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) 1910 #endif 1911 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 1912 #define __HAL_RCC_AES2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) 1913 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 1914 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 1915 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 1916 1917 #if defined(QUADSPI) 1918 #define __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_QUADSPI) 1919 #endif 1920 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA) 1921 #define __HAL_RCC_AES2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES2) 1922 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG) 1923 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2) 1924 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH) 1925 1926 #define __HAL_RCC_C2PKA_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 1927 #define __HAL_RCC_C2AES2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2) 1928 #define __HAL_RCC_C2RNG_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 1929 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 1930 #define __HAL_RCC_C2FLASH_CLK_SLEEP_ENABLE() LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1931 1932 #define __HAL_RCC_C2PKA_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA) 1933 #define __HAL_RCC_C2AES2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES2) 1934 #define __HAL_RCC_C2RNG_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG) 1935 #define __HAL_RCC_C2SRAM2_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2) 1936 #define __HAL_RCC_C2FLASH_CLK_SLEEP_DISABLE() LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH) 1937 1938 /** 1939 * @} 1940 */ 1941 1942 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 1943 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1944 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1945 * power consumption. 1946 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1947 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1948 * @{ 1949 */ 1950 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 1951 #if defined(LCD) 1952 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LCD) 1953 #endif 1954 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 1955 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 1956 #if defined(SPI2) 1957 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 1958 #endif 1959 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 1960 #if defined(I2C3) 1961 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 1962 #endif 1963 #if defined(CRS) 1964 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_CRS) 1965 #endif 1966 #if defined(USB) 1967 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USB) 1968 #endif 1969 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 1970 #if defined(LPUART1) 1971 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 1972 #endif 1973 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 1974 1975 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2) 1976 #if defined(LCD) 1977 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LCD) 1978 #endif 1979 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB) 1980 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG) 1981 #if defined(SPI2) 1982 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2) 1983 #endif 1984 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1) 1985 #if defined(I2C3) 1986 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3) 1987 #endif 1988 #if defined(CRS) 1989 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_CRS) 1990 #endif 1991 #if defined(USB) 1992 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USB) 1993 #endif 1994 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1) 1995 #if defined(LPUART1) 1996 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1) 1997 #endif 1998 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2) 1999 2000 #define __HAL_RCC_C2TIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 2001 #if defined(LCD) 2002 #define __HAL_RCC_C2LCD_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) 2003 #endif 2004 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 2005 #if defined(SPI2) 2006 #define __HAL_RCC_C2SPI2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 2007 #endif 2008 #define __HAL_RCC_C2I2C1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 2009 #if defined(I2C3) 2010 #define __HAL_RCC_C2I2C3_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 2011 #endif 2012 #if defined(CRS) 2013 #define __HAL_RCC_C2CRS_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) 2014 #endif 2015 #if defined(USB) 2016 #define __HAL_RCC_C2USB_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) 2017 #endif 2018 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 2019 #if defined(LPUART1) 2020 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 2021 #endif 2022 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_ENABLE() LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 2023 2024 #define __HAL_RCC_C2TIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2) 2025 #if defined(LCD) 2026 #define __HAL_RCC_C2LCD_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LCD) 2027 #endif 2028 #define __HAL_RCC_C2RTCAPB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB) 2029 #if defined(SPI2) 2030 #define __HAL_RCC_C2SPI2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2) 2031 #endif 2032 #define __HAL_RCC_C2I2C1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1) 2033 #if defined(I2C3) 2034 #define __HAL_RCC_C2I2C3_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3) 2035 #endif 2036 #if defined(CRS) 2037 #define __HAL_RCC_C2CRS_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_CRS) 2038 #endif 2039 #if defined(USB) 2040 #define __HAL_RCC_C2USB_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USB) 2041 #endif 2042 #define __HAL_RCC_C2LPTIM1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1) 2043 #if defined(LPUART1) 2044 #define __HAL_RCC_C2LPUART1_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1) 2045 #endif 2046 #define __HAL_RCC_C2LPTIM2_CLK_SLEEP_DISABLE() LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2) 2047 2048 /** 2049 * @} 2050 */ 2051 2052 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2053 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2054 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2055 * power consumption. 2056 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2057 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2058 * @{ 2059 */ 2060 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 2061 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 2062 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 2063 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 2064 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 2065 #if defined(SAI1) 2066 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) 2067 #endif 2068 2069 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1) 2070 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1) 2071 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1) 2072 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16) 2073 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17) 2074 #if defined(SAI1) 2075 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1) 2076 #endif 2077 2078 #define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 2079 #define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 2080 #define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 2081 #define __HAL_RCC_C2TIM16_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 2082 #define __HAL_RCC_C2TIM17_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 2083 #if defined(SAI1) 2084 #define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) 2085 #endif 2086 2087 #define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1) 2088 #define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1) 2089 #define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1) 2090 #define __HAL_RCC_C2TIM16_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16) 2091 #define __HAL_RCC_C2TIM17_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17) 2092 #if defined(SAI1) 2093 #define __HAL_RCC_C2SAI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1) 2094 #endif 2095 /** 2096 * @} 2097 */ 2098 2099 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 2100 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2101 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2102 * power consumption. 2103 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2104 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2105 * @{ 2106 */ 2107 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) 2108 #if defined(DMA2) 2109 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) 2110 #endif 2111 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) 2112 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) 2113 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) 2114 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) 2115 2116 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) 2117 #if defined(DMA2) 2118 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) 2119 #endif 2120 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) 2121 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) 2122 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) 2123 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) 2124 2125 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) != RESET) 2126 #if defined(DMA2) 2127 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) != RESET) 2128 #endif 2129 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) != RESET) 2130 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) != RESET) 2131 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) != RESET) 2132 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) != RESET) 2133 2134 #define __HAL_RCC_C2DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA1SMEN) == RESET) 2135 #if defined(DMA2) 2136 #define __HAL_RCC_C2DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMA2SMEN) == RESET) 2137 #endif 2138 #define __HAL_RCC_C2DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_DMAMUX1SMEN) == RESET) 2139 #define __HAL_RCC_C2SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_SRAM1SMEN) == RESET) 2140 #define __HAL_RCC_C2CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_CRCSMEN) == RESET) 2141 #define __HAL_RCC_C2TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB1SMENR, RCC_C2AHB1SMENR_TSCSMEN) == RESET) 2142 /** 2143 * @} 2144 */ 2145 2146 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 2147 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2148 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2149 * power consumption. 2150 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2151 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2152 * @{ 2153 */ 2154 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) 2155 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) 2156 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) 2157 #if defined(GPIOD) 2158 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) 2159 #endif 2160 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) 2161 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) 2162 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) 2163 #if defined(AES1) 2164 #define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET) 2165 #endif 2166 2167 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) 2168 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) 2169 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) 2170 #if defined(GPIOD) 2171 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) 2172 #endif 2173 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) 2174 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) 2175 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) 2176 #if defined(AES1) 2177 #define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET) 2178 #endif 2179 2180 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) != RESET) 2181 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) != RESET) 2182 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) != RESET) 2183 #if defined(GPIOD) 2184 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) != RESET) 2185 #endif 2186 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET) 2187 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET) 2188 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET) 2189 #if defined(AES1) 2190 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET) 2191 #endif 2192 2193 #define __HAL_RCC_C2GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOASMEN) == RESET) 2194 #define __HAL_RCC_C2GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOBSMEN) == RESET) 2195 #define __HAL_RCC_C2GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOCSMEN) == RESET) 2196 #if defined(GPIOD) 2197 #define __HAL_RCC_C2GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIODSMEN) == RESET) 2198 #endif 2199 #define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET) 2200 #define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET) 2201 #define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET) 2202 #if defined(AES1) 2203 #define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET) 2204 #endif 2205 /** 2206 * @} 2207 */ 2208 2209 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 2210 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2211 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2212 * power consumption. 2213 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2214 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2215 * @{ 2216 */ 2217 #if defined(QUADSPI) 2218 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) != RESET) 2219 #endif 2220 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) != RESET) 2221 #define __HAL_RCC_AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) != RESET) 2222 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) != RESET) 2223 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) != RESET) 2224 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) != RESET) 2225 2226 #if defined(QUADSPI) 2227 #define __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QUADSPISMEN) == RESET) 2228 #endif 2229 #define __HAL_RCC_PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PKASMEN) == RESET) 2230 #define __HAL_RCC_AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_AES2SMEN) == RESET) 2231 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_RNGSMEN) == RESET) 2232 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM2SMEN) == RESET) 2233 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FLASHSMEN) == RESET) 2234 2235 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) != RESET) 2236 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) != RESET) 2237 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) != RESET) 2238 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) != RESET) 2239 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) != RESET) 2240 2241 #define __HAL_RCC_C2PKA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_PKASMEN) == RESET) 2242 #define __HAL_RCC_C2AES2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_AES2SMEN) == RESET) 2243 #define __HAL_RCC_C2RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_RNGSMEN) == RESET) 2244 #define __HAL_RCC_C2SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_SRAM2SMEN) == RESET) 2245 #define __HAL_RCC_C2FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB3SMENR, RCC_C2AHB3SMENR_FLASHSMEN) == RESET) 2246 2247 /** 2248 * @} 2249 */ 2250 2251 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 2252 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2253 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2254 * power consumption. 2255 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2256 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2257 * @{ 2258 */ 2259 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) 2260 #if defined(LCD) 2261 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) 2262 #endif 2263 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) 2264 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) 2265 #if defined(SPI2) 2266 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) 2267 #endif 2268 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) 2269 #if defined(I2C3) 2270 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) 2271 #endif 2272 #if defined(CRS) 2273 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) 2274 #endif 2275 #if defined(USB) 2276 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != RESET) 2277 #endif 2278 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) 2279 #if defined(LPUART1) 2280 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) 2281 #endif 2282 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) 2283 2284 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) 2285 #if defined(LCD) 2286 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) 2287 #endif 2288 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) 2289 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) 2290 #if defined(SPI2) 2291 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) 2292 #endif 2293 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) 2294 #if defined(I2C3) 2295 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) 2296 #endif 2297 #if defined(CRS) 2298 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) 2299 #endif 2300 #if defined(USB) 2301 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == RESET) 2302 #endif 2303 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) 2304 #if defined(LPUART1) 2305 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) 2306 #endif 2307 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) 2308 2309 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) != RESET) 2310 #if defined(LCD) 2311 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) != RESET) 2312 #endif 2313 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) != RESET) 2314 #if defined(SPI2) 2315 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) != RESET) 2316 #endif 2317 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) != RESET) 2318 #if defined(I2C3) 2319 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) != RESET) 2320 #endif 2321 #if defined(CRS) 2322 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) != RESET) 2323 #endif 2324 #if defined(USB) 2325 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) != RESET) 2326 #endif 2327 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) != RESET) 2328 #if defined(LPUART1) 2329 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) != RESET) 2330 #endif 2331 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) != RESET) 2332 2333 #define __HAL_RCC_C2TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_TIM2SMEN) == RESET) 2334 #if defined(LCD) 2335 #define __HAL_RCC_C2LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LCDSMEN) == RESET) 2336 #endif 2337 #define __HAL_RCC_C2RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_RTCAPBSMEN) == RESET) 2338 #if defined(SPI2) 2339 #define __HAL_RCC_C2SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_SPI2SMEN) == RESET) 2340 #endif 2341 #define __HAL_RCC_C2I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C1SMEN) == RESET) 2342 #if defined(I2C3) 2343 #define __HAL_RCC_C2I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_I2C3SMEN) == RESET) 2344 #endif 2345 #if defined(CRS) 2346 #define __HAL_RCC_C2CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_CRSSMEN) == RESET) 2347 #endif 2348 #if defined(USB) 2349 #define __HAL_RCC_C2USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_USBSMEN) == RESET) 2350 #endif 2351 #define __HAL_RCC_C2LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR1, RCC_C2APB1SMENR1_LPTIM1SMEN) == RESET) 2352 #if defined(LPUART1) 2353 #define __HAL_RCC_C2LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPUART1SMEN) == RESET) 2354 #endif 2355 #define __HAL_RCC_C2LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB1SMENR2, RCC_C2APB1SMENR2_LPTIM2SMEN) == RESET) 2356 /** 2357 * @} 2358 */ 2359 2360 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 2361 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2362 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2363 * power consumption. 2364 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2365 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2366 * @{ 2367 */ 2368 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) 2369 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) 2370 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) 2371 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) 2372 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) 2373 #if defined(SAI1) 2374 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) 2375 #endif 2376 2377 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) 2378 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) 2379 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) 2380 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) 2381 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) 2382 #if defined(SAI1) 2383 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) 2384 #endif 2385 2386 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET) 2387 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET) 2388 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET) 2389 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) != RESET) 2390 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) != RESET) 2391 #if defined(SAI1) 2392 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET) 2393 #endif 2394 2395 #define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET) 2396 #define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET) 2397 #define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET) 2398 #define __HAL_RCC_C2TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM16SMEN) == RESET) 2399 #define __HAL_RCC_C2TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM17SMEN) == RESET) 2400 #if defined(SAI1) 2401 #define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) == RESET) 2402 #endif 2403 /** 2404 * @} 2405 */ 2406 2407 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 2408 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. 2409 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2410 * power consumption. 2411 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2412 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2413 * @{ 2414 */ 2415 #define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) 2416 #define __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) 2417 2418 #define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE) 2419 #define __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802) 2420 /** 2421 * @} 2422 */ 2423 2424 /** @defgroup RCC_C2APB3_Clock_Sleep_Enable_Disable_Status APB3 Peripheral Clock Sleep Enabled or Disabled Status 2425 * @brief Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2426 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2427 * power consumption. 2428 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2429 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2430 * @{ 2431 */ 2432 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET) 2433 #define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET) 2434 2435 #define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET) 2436 #define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET) 2437 /** 2438 * @} 2439 */ 2440 2441 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2442 * @{ 2443 */ 2444 2445 /** @brief Macros to force or release the Backup domain reset. 2446 * @note This function resets the RTC peripheral (including the backup registers) 2447 * and the RTC clock source selection in RCC_CSR register. 2448 * @note The BKPSRAM is not affected by this reset. 2449 * @retval None 2450 */ 2451 #define __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset() 2452 #define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset() 2453 2454 /** 2455 * @} 2456 */ 2457 2458 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2459 * @{ 2460 */ 2461 2462 /** @brief Macros to enable or disable the RTC clock. 2463 * @note As the RTC is in the Backup domain and write access is denied to 2464 * this domain after reset, you have to enable write access using 2465 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2466 * (to be done once after reset). 2467 * @note These macros must be used after the RTC clock source was selected. 2468 * @retval None 2469 */ 2470 #define __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC() 2471 #define __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC() 2472 2473 /** 2474 * @} 2475 */ 2476 2477 /** @brief Macros to enable the Internal High Speed oscillator (HSI). 2478 * @note The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes. 2479 * It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1 2480 * or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE 2481 * crystal oscillator and Security System CSS is enabled. 2482 * @note After enabling the HSI, the application software should wait on HSIRDY 2483 * flag to be set indicating that HSI clock is stable and can be used as 2484 * system clock source. 2485 * @retval None 2486 */ 2487 #define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() 2488 2489 /** @brief Macro to disable the Internal High Speed oscillator (HSI). 2490 * @note HSI can not be stopped if it is used as system clock source. In this case, 2491 * you have to select another source of the system clock then stop the HSI. 2492 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2493 * clock cycles. 2494 * @retval None 2495 */ 2496 #define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable() 2497 2498 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 2499 * @note The calibration is used to compensate for the variations in voltage 2500 * and temperature that influence the frequency of the internal HSI RC. 2501 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2502 * (default is RCC_HSICALIBRATION_DEFAULT). 2503 * This parameter must be a number between Min_data=0 and Max_Data=127. 2504 * @retval None 2505 */ 2506 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__) 2507 2508 /** 2509 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 2510 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 2511 * @note The enable of this function has not effect on the HSION bit. 2512 * This parameter can be: ENABLE or DISABLE. 2513 * @retval None 2514 */ 2515 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() LL_RCC_HSI_EnableAutoFromStop() 2516 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() LL_RCC_HSI_DisableAutoFromStop() 2517 2518 /** 2519 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2520 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2521 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2522 * speed because of the HSI startup time. 2523 * @note The enable of this function has not effect on the HSION bit. 2524 * @retval None 2525 */ 2526 #define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() 2527 #define __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode() 2528 2529 /** 2530 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 2531 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 2532 * It is used (enabled by hardware) as system clock source after 2533 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2534 * of failure of the HSE used directly or indirectly as system clock 2535 * (if the Clock Security System CSS is enabled). 2536 * @note MSI can not be stopped if it is used as system clock source. 2537 * In this case, you have to select another source of the system 2538 * clock then stop the MSI. 2539 * @note After enabling the MSI, the application software should wait on 2540 * MSIRDY flag to be set indicating that MSI clock is stable and can 2541 * be used as system clock source. 2542 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 2543 * clock cycles. 2544 * @retval None 2545 */ 2546 #define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() 2547 #define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() 2548 2549 /** @brief Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value. 2550 * @note The calibration is used to compensate for the variations in voltage 2551 * and temperature that influence the frequency of the internal MSI RC. 2552 * Refer to the Application Note AN3300 for more details on how to 2553 * calibrate the MSI. 2554 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 2555 * (default is @ref RCC_MSICALIBRATION_DEFAULT). 2556 * This parameter must be a number between 0 and 255. 2557 * @retval None 2558 */ 2559 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__) 2560 2561 /** 2562 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 2563 * @note After restart from Reset , the MSI clock is around 4 MHz. 2564 * After stop the startup clock can be MSI (at any of its possible 2565 * frequencies, the one that was used before entering stop mode) or HSI. 2566 * After Standby its frequency can be selected between 4 possible values 2567 * (1, 2, 4 or 8 MHz). 2568 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 2569 * (MSIRDY=1). 2570 * @note The MSI clock range after reset can be modified on the fly. 2571 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 2572 * This parameter must be one of the following values: 2573 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 2574 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 2575 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 2576 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 2577 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2578 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz 2579 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset) 2580 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2581 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2582 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2583 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2584 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2585 * @retval None 2586 */ 2587 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) LL_RCC_MSI_SetRange(__MSIRANGEVALUE__) 2588 2589 2590 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 2591 * @retval MSI clock range. 2592 * This parameter must be one of the following values: 2593 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 2594 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 2595 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 2596 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 2597 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2598 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2599 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2600 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2601 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2602 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2603 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2604 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2605 */ 2606 #define __HAL_RCC_GET_MSI_RANGE() LL_RCC_MSI_GetRange() 2607 2608 2609 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI1). 2610 * @note After enabling the LSI1, the application software should wait on 2611 * LSI1RDY flag to be set indicating that LSI1 clock is stable and can 2612 * be used to clock the IWDG and/or the RTC. 2613 * @retval None 2614 */ 2615 #define __HAL_RCC_LSI1_ENABLE() LL_RCC_LSI1_Enable() 2616 #define __HAL_RCC_LSI1_DISABLE() LL_RCC_LSI1_Disable() 2617 2618 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI2). 2619 * @note After enabling the LSI2, the application software should wait on 2620 * LSI2RDY flag to be set indicating that LSI2 clock is stable and can 2621 * be used to clock the IWDG and/or the RTC. 2622 * @retval None 2623 */ 2624 #define __HAL_RCC_LSI2_ENABLE() LL_RCC_LSI2_Enable() 2625 #define __HAL_RCC_LSI2_DISABLE() LL_RCC_LSI2_Disable() 2626 2627 /** @brief Macro to adjust the Internal Low Speed oscillator (LSI2) calibration value. 2628 * @note The calibration is used to compensate for the variations in voltage 2629 * and temperature that influence the frequency of the internal HSI RC. 2630 * @param __LSI2TRIMMINGVALUE__ specifies the calibration trimming value 2631 * This parameter must be a number between Min_data=0 and Max_Data=15. 2632 * @retval None 2633 */ 2634 #define __HAL_RCC_LSI2_CALIBRATIONVALUE_ADJUST(__LSI2TRIMMINGVALUE__) LL_RCC_LSI2_SetTrimming(__LSI2TRIMMINGVALUE__) 2635 2636 /** 2637 * @brief Macro to configure the External High Speed oscillator (HSE). 2638 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 2639 * supported by this macro. User should request a transition to HSE Off 2640 * first and then HSE On or HSE Bypass. 2641 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 2642 * software should wait on HSERDY flag to be set indicating that HSE clock 2643 * is stable and can be used to clock the PLL and/or system clock. 2644 * @note HSE state can not be changed if it is used directly or through the 2645 * PLL as system clock. In this case, you have to select another source 2646 * of the system clock then change the HSE state (ex. disable it). 2647 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2648 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2649 * was previously enabled you have to enable it again after calling this 2650 * function. 2651 * @param __STATE__ specifies the new state of the HSE. 2652 * This parameter can be one of the following values: 2653 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2654 * 6 HSE oscillator clock cycles. 2655 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2656 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 2657 * @retval None 2658 */ 2659 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 2660 do { \ 2661 if((__STATE__) == RCC_HSE_ON) \ 2662 { \ 2663 LL_RCC_HSE_Enable(); \ 2664 } \ 2665 else if((__STATE__) == RCC_HSE_BYPASS) \ 2666 { \ 2667 LL_RCC_HSE_EnableBypass(); \ 2668 LL_RCC_HSE_Enable(); \ 2669 } \ 2670 else \ 2671 { \ 2672 LL_RCC_HSE_Disable(); \ 2673 LL_RCC_HSE_DisableBypass(); \ 2674 } \ 2675 } while(0U) 2676 2677 /** @brief Macros to enable or disable the HSE Prescaler 2678 * @note HSE div2 could be used as Sysclk or PLL entry in Range2 2679 * @retval None 2680 */ 2681 #define __HAL_RCC_HSE_DIV2_ENABLE() LL_RCC_HSE_EnableDiv2() 2682 #define __HAL_RCC_HSE_DIV2_DISABLE() LL_RCC_HSE_DisableDiv2() 2683 2684 /** 2685 * @brief Macro to configure the External Low Speed oscillator (LSE). 2686 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2687 * supported by this macro. User should request a transition to LSE Off 2688 * first and then LSE On or LSE Bypass. 2689 * @note As the LSE is in the Backup domain and write access is denied to 2690 * this domain after reset, you have to enable write access using 2691 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2692 * (to be done once after reset). 2693 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2694 * software should wait on LSERDY flag to be set indicating that LSE clock 2695 * is stable and can be used to clock the RTC. 2696 * @param __STATE__ specifies the new state of the LSE. 2697 * This parameter can be one of the following values: 2698 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2699 * 6 LSE oscillator clock cycles. 2700 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2701 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2702 * @retval None 2703 */ 2704 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 2705 do { \ 2706 if((__STATE__) == RCC_LSE_ON) \ 2707 { \ 2708 LL_RCC_LSE_Enable(); \ 2709 } \ 2710 else if((__STATE__) == RCC_LSE_BYPASS) \ 2711 { \ 2712 LL_RCC_LSE_EnableBypass(); \ 2713 LL_RCC_LSE_Enable(); \ 2714 } \ 2715 else \ 2716 { \ 2717 LL_RCC_LSE_Disable(); \ 2718 LL_RCC_LSE_DisableBypass(); \ 2719 } \ 2720 } while(0U) 2721 2722 2723 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 2724 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 2725 * @note After enabling the HSI48, the application software should wait on HSI48RDY 2726 * flag to be set indicating that HSI48 clock is stable. 2727 * This parameter can be: ENABLE or DISABLE. 2728 * @retval None 2729 */ 2730 #define __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable() 2731 #define __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable() 2732 2733 /** @brief Macros to configure HSE sense amplifier threshold. 2734 * @note to configure HSE sense amplifier, first disable HSE 2735 * using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2736 * 2737 * @param __HSE_AMPTHRES__ specifies the HSE sense amplifier threshold. 2738 * This parameter can be one of the following values: 2739 * @arg @ref RCC_HSEAMPTHRESHOLD_1_2 HSE bias current factor 1/2. 2740 * @arg @ref RCC_HSEAMPTHRESHOLD_3_4 HSE bias current factor 3/4. 2741 * @retval None 2742 */ 2743 #define __HAL_RCC_HSE_AMPCONFIG(__HSE_AMPTHRES__) LL_RCC_HSE_SetSenseAmplifier(__HSE_AMPTHRES__) 2744 2745 /** @brief Macros to configure HSE current control. 2746 * @note to configure HSE current control, first disable HSE 2747 * using @ref __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2748 * 2749 * @param __HSE_CURRENTMAX__ specifies the HSE current max limit. 2750 * This parameter can be one of the following values: 2751 * @arg @ref RCC_HSE_CURRENTMAX_0 HSE current max limit 0.18 mA/V. 2752 * @arg @ref RCC_HSE_CURRENTMAX_1 HSE current max limit 0.57 mA/V. 2753 * @arg @ref RCC_HSE_CURRENTMAX_2 HSE current max limit 0.78 mA/V. 2754 * @arg @ref RCC_HSE_CURRENTMAX_3 HSE current max limit 1.13 mA/V. 2755 * @arg @ref RCC_HSE_CURRENTMAX_4 HSE current max limit 0.61 mA/V. 2756 * @arg @ref RCC_HSE_CURRENTMAX_5 HSE current max limit 1.65 mA/V. 2757 * @arg @ref RCC_HSE_CURRENTMAX_6 HSE current max limit 2.12 mA/V. 2758 * @arg @ref RCC_HSE_CURRENTMAX_7 HSE current max limit 2.84 mA/V. 2759 * @retval None 2760 */ 2761 #define __HAL_RCC_HSE_CURRENTCONFIG(__HSE_CURRENTMAX__) LL_RCC_HSE_SetCurrentControl(__HSE_CURRENTMAX__) 2762 2763 /** @brief Macros to configure HSE capacitor tuning. 2764 * @note to configure HSE current control, first disable HSE 2765 * using __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF) macro. 2766 * 2767 * @param __HSE_LOAD_CAPACITANCE__ specifies the HSE capacitor value. 2768 * This Value Between Min_Data = 0 and Max_Data = 63 2769 * @retval None 2770 */ 2771 #define __HAL_RCC_HSE_CAPACITORTUNING(__HSE_LOAD_CAPACITANCE__) LL_RCC_HSE_SetCapacitorTuning(__HSE_LOAD_CAPACITANCE__) 2772 2773 2774 /** @brief Macros to configure the RTC clock (RTCCLK). 2775 * @note As the RTC clock configuration bits are in the Backup domain and write 2776 * access is denied to this domain after reset, you have to enable write 2777 * access using the Power Backup Access macro before to configure 2778 * the RTC clock source (to be done once after reset). 2779 * @note Once the RTC clock is configured it cannot be changed unless the 2780 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2781 * a Power On Reset (POR). 2782 * 2783 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2784 * This parameter can be one of the following values:* 2785 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 2786 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2787 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2788 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2789 * 2790 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2791 * work in STOP and STANDBY modes, and can be used as wakeup source. 2792 * However, when the HSE clock is used as RTC clock source, the RTC 2793 * cannot be used in STOP and STANDBY modes. 2794 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2795 * RTC clock source). 2796 * @retval None 2797 */ 2798 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__) 2799 2800 2801 /** @brief Macro to get the RTC clock source. 2802 * @retval The returned value can be one of the following: 2803 * @arg @ref RCC_RTCCLKSOURCE_NONE none clock selected as RTC clock. 2804 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2805 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2806 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2807 */ 2808 #define __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource() 2809 2810 /** @brief Macros to enable or disable the main PLL. 2811 * @note After enabling the main PLL, the application software should wait on 2812 * PLLRDY flag to be set indicating that PLL clock is stable and can 2813 * be used as system clock source. 2814 * @note The main PLL can not be disabled if it is used as system clock source 2815 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 2816 * @retval None 2817 */ 2818 #define __HAL_RCC_PLL_ENABLE() LL_RCC_PLL_Enable() 2819 #define __HAL_RCC_PLL_DISABLE() LL_RCC_PLL_Disable() 2820 2821 /** @brief Macro to configure the PLL clock source. 2822 * @note This function must be used only when the main PLL is disabled. 2823 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2824 * This parameter can be one of the following values: 2825 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2826 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 2827 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2828 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2829 * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). 2830 * @retval None 2831 * 2832 */ 2833 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 2834 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 2835 2836 /** @brief Macro to configure the PLL multiplication factor. 2837 * @note This function must be used only when the main PLL is disabled. 2838 * @param __PLLM__ specifies the division factor for PLL VCO input clock 2839 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 2840 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2841 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 2842 * of 16 MHz to limit PLL jitter. 2843 * @retval None 2844 * 2845 */ 2846 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 2847 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 2848 2849 /** 2850 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 2851 * @note This function must be used only when the main PLL is disabled. 2852 * 2853 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2854 * This parameter can be one of the following values: 2855 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2856 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 2857 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2858 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2859 * @note This clock source is common for the main PLL and audio PLL (PLL and PLLSAI1). 2860 * 2861 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 2862 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 2863 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2864 * frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency 2865 * of 16 MHz to limit PLL jitter. 2866 * 2867 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 2868 * This parameter must be a number between 6 and 127. 2869 * @note You have to set the PLLN parameter correctly to ensure that the VCO 2870 * output frequency is between 96 and 344 MHz. 2871 * 2872 * @param __PLLP__ specifies the division factor for ADC and SAI1 clock. 2873 * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. 2874 * 2875 * @param __PLLQ__ specifies the division factor for USB and RNG clocks. 2876 * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider 2877 * @note If the USB FS is used in your application, you have to set the 2878 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 2879 * the RNG need a frequency lower than or equal to 48 MHz to work 2880 * correctly. 2881 * 2882 * @param __PLLR__ specifies the division factor for the main system clock. 2883 * This parameter must be a value of @ref RCC_PLLR_Clock_Divider 2884 * @note You have to set the PLLR parameter correctly to not exceed 48 MHZ. 2885 * @retval None 2886 */ 2887 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 2888 MODIFY_REG( RCC->PLLCFGR, \ 2889 (RCC_PLLCFGR_PLLSRC | \ 2890 RCC_PLLCFGR_PLLM | \ 2891 RCC_PLLCFGR_PLLN | \ 2892 RCC_PLLCFGR_PLLP | \ 2893 RCC_PLLCFGR_PLLQ | \ 2894 RCC_PLLCFGR_PLLR), \ 2895 ((uint32_t) (__PLLSOURCE__) | \ 2896 (uint32_t) (__PLLM__) | \ 2897 (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 2898 (uint32_t) (__PLLP__) | \ 2899 (uint32_t) (__PLLQ__) | \ 2900 (uint32_t) (__PLLR__))) 2901 2902 /** @brief Macro to get the oscillator used as PLL clock source. 2903 * @retval The oscillator used as PLL clock source. The returned value can be one 2904 * of the following: 2905 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 2906 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 2907 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 2908 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 2909 */ 2910 #define __HAL_RCC_GET_PLL_OSCSOURCE() LL_RCC_PLL_GetMainSource() 2911 2912 /** 2913 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK) 2914 * @note Enabling/disabling clock outputs RCC_PLL_SAI1CLK and RCC_PLL_USBCLK can be done at anytime 2915 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 2916 * be stopped if used as System Clock. 2917 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 2918 * This parameter can be one or a combination of the following values: 2919 * @arg @ref RCC_PLL_SAI1CLK This clock is used to generate the clock for SAI 2920 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate the clock for ADC 2921 * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) 2922 * @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG 2923 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) 2924 * @retval None 2925 */ 2926 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2927 2928 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2929 2930 /** 2931 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_USBCLK, RCC_PLL_SAI1CLK) 2932 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 2933 * This parameter can be one of the following values: 2934 * @arg @ref RCC_PLL_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface 2935 * @arg @ref RCC_PLL_ADCCLK same 2936 * @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz) 2937 * @arg @ref RCC_PLL_RNGCLK same 2938 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz) 2939 * @retval SET / RESET 2940 */ 2941 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 2942 2943 /** 2944 * @brief Macro to configure the system clock source. 2945 * @param __SYSCLKSOURCE__ specifies the system clock source. 2946 * This parameter can be one of the following values: 2947 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 2948 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 2949 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 2950 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 2951 * @retval None 2952 */ 2953 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource(__SYSCLKSOURCE__) 2954 2955 /** @brief Macro to get the clock source used as system clock. 2956 * @retval The clock source used as system clock. The returned value can be one 2957 * of the following: 2958 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock. 2959 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 2960 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 2961 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. 2962 */ 2963 #define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource() 2964 2965 /** 2966 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 2967 * @note As the LSE is in the Backup domain and write access is denied to 2968 * this domain after reset, you have to enable write access using 2969 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2970 * (to be done once after reset). 2971 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 2972 * This parameter can be one of the following values: 2973 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 2974 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 2975 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 2976 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 2977 * @retval None 2978 */ 2979 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__) 2980 2981 /** 2982 * @brief Macro to configure the wake up from stop clock. 2983 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 2984 * This parameter can be one of the following values: 2985 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 2986 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 2987 * @retval None 2988 */ 2989 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__) 2990 2991 2992 /** @brief Macro to configure the MCO clock. 2993 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 2994 * This parameter can be one of the following values: 2995 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 2996 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 2997 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 2998 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 2999 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 3000 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 3001 * @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source 3002 * @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source 3003 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3004 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source 3005 3006 * @param __MCODIV__ specifies the MCO clock prescaler. 3007 * This parameter can be one of the following values: 3008 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3009 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3010 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3011 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3012 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3013 */ 3014 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__)) 3015 3016 3017 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3018 * @brief macros to manage the specified RCC Flags and interrupts. 3019 * @{ 3020 */ 3021 3022 /** @brief Enable RCC interrupt. 3023 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 3024 * This parameter can be any combination of the following values: 3025 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt enable 3026 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 3027 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 3028 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 3029 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 3030 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 3031 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable 3032 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 3033 * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable 3034 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable 3035 * @retval None 3036 */ 3037 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3038 3039 /** @brief Disable RCC interrupt. 3040 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 3041 * This parameter can be any combination of the following values: 3042 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt enable 3043 * @arg @ref RCC_IT_LSERDY LSE ready interrupt enable 3044 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt enable 3045 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt enable 3046 * @arg @ref RCC_IT_HSERDY HSE ready interrupt enable 3047 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable 3048 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable 3049 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable 3050 * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable 3051 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable 3052 * @retval None 3053 */ 3054 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3055 3056 /** @brief Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0] 3057 * bits to clear the selected interrupt pending bits. 3058 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3059 * This parameter can be any combination of the following values: 3060 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt clear 3061 * @arg @ref RCC_IT_LSERDY LSE ready interrupt clear 3062 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt clear 3063 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt clear 3064 * @arg @ref RCC_IT_HSERDY HSE ready interrupt clear 3065 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt clear 3066 * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt clear 3067 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear 3068 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear 3069 * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt clear 3070 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt clear 3071 */ 3072 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 3073 3074 /** @brief Check whether the RCC interrupt has occurred or not. 3075 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 3076 * This parameter can be one of the following values: 3077 * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt flag 3078 * @arg @ref RCC_IT_LSERDY LSE ready interrupt flag 3079 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt flag 3080 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt flag 3081 * @arg @ref RCC_IT_HSERDY HSE ready interrupt flag 3082 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt flag 3083 * @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt flag 3084 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag 3085 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag 3086 * @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt flag 3087 * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt flag 3088 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 3089 */ 3090 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 3091 3092 /** @brief Set RMVF bit to clear the reset flags. 3093 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3094 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3095 * @retval None 3096 */ 3097 #define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags() 3098 3099 /** @brief Check whether the selected RCC flag is set or not. 3100 * @param __FLAG__ specifies the flag to check. 3101 * This parameter can be one of the following values: 3102 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 3103 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3104 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3105 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 3106 * @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready 3107 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 3108 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3109 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3110 * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready 3111 * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready 3112 * @arg @ref RCC_FLAG_BORRST BOR reset 3113 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3114 * @arg @ref RCC_FLAG_PINRST Pin reset 3115 * @arg @ref RCC_FLAG_SFTRST Software reset 3116 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3117 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3118 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3119 * @retval The new state of __FLAG__ (TRUE or FALSE). 3120 */ 3121 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 3122 ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ 3123 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 3124 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ 3125 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ 3126 ? 1U : 0U) 3127 3128 /** 3129 * @} 3130 */ 3131 3132 /** 3133 * @} 3134 */ 3135 3136 /* Include RCC HAL Extended module */ 3137 #include "stm32wbxx_hal_rcc_ex.h" 3138 3139 /* Exported functions --------------------------------------------------------*/ 3140 /** @addtogroup RCC_Exported_Functions 3141 * @{ 3142 */ 3143 3144 3145 /** @addtogroup RCC_Exported_Functions_Group1 3146 * @{ 3147 */ 3148 3149 /* Initialization and de-initialization functions ******************************/ 3150 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3151 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3152 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 3153 3154 /** 3155 * @} 3156 */ 3157 3158 /** @addtogroup RCC_Exported_Functions_Group2 3159 * @{ 3160 */ 3161 3162 /* Peripheral Control functions ************************************************/ 3163 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3164 void HAL_RCC_EnableCSS(void); 3165 uint32_t HAL_RCC_GetSysClockFreq(void); 3166 3167 uint32_t HAL_RCC_GetHCLKFreq(void); 3168 uint32_t HAL_RCC_GetHCLK2Freq(void); 3169 uint32_t HAL_RCC_GetHCLK4Freq(void); 3170 3171 uint32_t HAL_RCC_GetPCLK1Freq(void); 3172 uint32_t HAL_RCC_GetPCLK2Freq(void); 3173 3174 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3175 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3176 /* LSE & HSE CSS NMI IRQ handler */ 3177 void HAL_RCC_NMI_IRQHandler(void); 3178 /* User Callbacks in non blocking mode (IT mode) */ 3179 void HAL_RCC_CSSCallback(void); 3180 3181 /** 3182 * @} 3183 */ 3184 3185 /** 3186 * @} 3187 */ 3188 3189 /** 3190 * @} 3191 */ 3192 3193 /** 3194 * @} 3195 */ 3196 3197 #ifdef __cplusplus 3198 } 3199 #endif 3200 3201 #endif /* STM32WBxx_HAL_RCC_H */ 3202 3203 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3204 3205