1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_PWR_EX_H 22 #define STM32WBxx_HAL_PWR_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 31 /** @addtogroup STM32WBxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup PWREx PWREx 36 * @brief PWR Extended HAL module driver 37 * @{ 38 */ 39 40 41 /* Exported types ------------------------------------------------------------*/ 42 43 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 44 * @{ 45 */ 46 47 /** 48 * @brief PWR PVM configuration structure definition 49 */ 50 typedef struct 51 { 52 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 53 This parameter can be a value of @ref PWREx_PVM_Type. 54 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 55 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 56 */ 57 58 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 59 This parameter can be a value of @ref PWREx_PVM_Mode. */ 60 uint32_t WakeupTarget; /*!< Specifies the Wakeup Target 61 This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */ 62 }PWR_PVMTypeDef; 63 64 #if defined(PWR_CR5_SMPSEN) 65 /** 66 * @brief PWR SMPS step down configuration structure definition 67 */ 68 typedef struct 69 { 70 uint32_t StartupCurrent; /*!< SMPS step down converter supply startup current selection. 71 This parameter can be a value of @ref PWREx_SMPS_STARTUP_CURRENT. */ 72 73 uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level. 74 This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */ 75 }PWR_SMPSTypeDef; 76 #endif 77 78 /** 79 * @} 80 */ 81 82 /* Exported constants --------------------------------------------------------*/ 83 84 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 85 * @{ 86 */ 87 88 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 89 * @{ 90 */ 91 #define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polarity */ 92 /** 93 * @} 94 */ 95 96 97 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 98 * @{ 99 */ 100 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 101 #if defined(PWR_CR3_EWUP2) 102 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 103 #endif 104 #if defined(PWR_CR3_EWUP3) 105 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 106 #endif 107 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 108 #if defined(PWR_CR3_EWUP5) 109 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 110 #endif 111 112 #define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 113 #if defined(PWR_CR3_EWUP2) 114 #define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 115 #endif 116 #if defined(PWR_CR3_EWUP3) 117 #define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 118 #endif 119 #define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 120 #if defined(PWR_CR3_EWUP5) 121 #define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 122 #endif 123 /** 124 * @} 125 */ 126 127 /* Literals kept for legacy purpose */ 128 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 129 #if defined(PWR_CR3_EWUP2) 130 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 131 #endif 132 #if defined(PWR_CR3_EWUP3) 133 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 134 #endif 135 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 136 #if defined(PWR_CR3_EWUP5) 137 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 138 #endif 139 140 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration 141 * @{ 142 */ 143 #define PWR_PIN_POLARITY_HIGH 0x00000000U 144 #define PWR_PIN_POLARITY_LOW 0x00000001U 145 /** 146 * @} 147 */ 148 149 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 150 * @{ 151 */ 152 #if defined(PWR_CR2_PVME1) 153 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 154 #endif 155 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 156 /** 157 * @} 158 */ 159 160 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 161 * @{ 162 */ 163 #define PWR_PVM_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ 164 165 #define PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */ 166 #define PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */ 167 #define PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 168 169 #define PWR_PVM_MODE_EVENT_RISING (PVM_MODE_EVT | PVM_RISING_EDGE) /*!< Event Mode with Rising edge trigger detection */ 170 #define PWR_PVM_MODE_EVENT_FALLING (PVM_MODE_EVT | PVM_FALLING_EDGE) /*!< Event Mode with Falling edge trigger detection */ 171 #define PWR_PVM_MODE_EVENT_RISING_FALLING (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE) /*!< Event Mode with Rising/Falling edge trigger detection */ 172 /** 173 * @} 174 */ 175 176 /** @defgroup PWREx_Flash_PowerDown Flash Power Down modes 177 * @{ 178 */ 179 #define PWR_FLASHPD_LPRUN PWR_CR1_FPDR /*!< Enable Flash power down in low power run mode */ 180 #define PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS /*!< Enable Flash power down in low power sleep mode */ 181 /** 182 * @} 183 */ 184 185 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 186 * @{ 187 */ 188 #if defined(PWR_CR1_VOS) 189 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ 190 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */ 191 #else 192 #define PWR_REGULATOR_VOLTAGE_SCALE1 (0x00000200UL) /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ 193 #endif 194 /** 195 * @} 196 */ 197 198 199 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 200 * @{ 201 */ 202 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ 203 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 209 * @{ 210 */ 211 #define PWR_BATTERY_CHARGING_DISABLE (0x00000000U) 212 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 213 /** 214 * @} 215 */ 216 217 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 218 * @{ 219 */ 220 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ 221 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ 222 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ 223 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ 224 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ 225 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ 226 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ 227 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ 228 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ 229 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ 230 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ 231 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ 232 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ 233 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 14 */ 234 #define PWR_GPIO_BIT_14 PWR_PDCRC_PC14 /*!< GPIO port I/O pin 14 */ 235 #define PWR_GPIO_BIT_15 PWR_PUCRC_PC15 /*!< GPIO port I/O pin 15 */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup PWREx_GPIO GPIO port 241 * @{ 242 */ 243 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 244 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 245 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 246 #if defined(GPIOD) 247 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 248 #endif 249 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 250 #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ 251 /** 252 * @} 253 */ 254 255 #if defined(PWR_CR5_SMPSEN) 256 /** @defgroup PWREx_BOR_CONFIGURATION BOR configuration 257 * @{ 258 */ 259 #define PWR_BOR_SYSTEM_RESET (LL_PWR_BOR_SYSTEM_RESET) /*!< BOR will generate a system reset */ 260 #define PWR_BOR_SMPS_FORCE_BYPASS (LL_PWR_BOR_SMPS_FORCE_BYPASS) /*!< BOR will for SMPS step down converter in bypass mode */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup PWREx_SMPS_OPERATING_MODES SMPS step down converter operating modes 266 * @{ 267 */ 268 /* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF */ 269 /* but they are also used as register CR5 bits SMPSEN and SMPSBEN, */ 270 /* as used by all SMPS operating mode functions targetting different */ 271 /* registers: */ 272 /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */ 273 /* and "LL_PWR_SMPS_GetEffectiveMode()". */ 274 #define PWR_SMPS_BYPASS (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode */ 275 #define PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup PWREx_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection 281 * @{ 282 */ 283 #define PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U) /*!< SMPS step down converter supply startup current 80mA */ 284 #define PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */ 285 #define PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 120mA */ 286 #define PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */ 287 #define PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 ) /*!< SMPS step down converter supply startup current 160mA */ 288 #define PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */ 289 #define PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 200mA */ 290 #define PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */ 291 /** 292 * @} 293 */ 294 295 /** @defgroup PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level 296 * @{ 297 */ 298 /* Note: SMPS voltage is trimmed during device production to control 299 the actual voltage level variation from device to device. */ 300 #define PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U) /*!< SMPS step down converter supply output voltage 1.20V */ 301 #define PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */ 302 #define PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.30V */ 303 #define PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */ 304 #define PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.40V */ 305 #define PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */ 306 #define PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.50V */ 307 #define PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */ 308 #define PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 ) /*!< SMPS step down converter supply output voltage 1.60V */ 309 #define PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */ 310 #define PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.70V */ 311 #define PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */ 312 #define PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.80V */ 313 #define PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */ 314 #define PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.90V */ 315 /** 316 * @} 317 */ 318 #endif 319 320 /** @defgroup PWREx_Flag PWR Status Flags 321 * Elements values convention: 0000 0000 0XXY YYYYb 322 * - Y YYYY : Flag position in the XX register (5 bits) 323 * - XX : Status register (2 bits) 324 * - 01: SR1 register 325 * - 10: SR2 register 326 * - 11: C2_SCR register 327 * The only exception is PWR_FLAG_WUF, encompassing all 328 * wake-up flags and set to PWR_SR1_WUF. 329 * @{ 330 */ 331 /*--------------------------------SR1-------------------------------*/ 332 #define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */ 333 #if defined(PWR_CR3_EWUP2) 334 #define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */ 335 #endif 336 #if defined(PWR_CR3_EWUP3) 337 #define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */ 338 #endif 339 #define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */ 340 #if defined(PWR_CR3_EWUP5) 341 #define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */ 342 #endif 343 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 344 345 #if defined(PWR_CR5_SMPSEN) 346 #define PWR_FLAG_FRCBYPI (0x0027U) /*!< SMPS Forced in Bypass Interrupt Flag */ 347 #endif 348 #define PWR_FLAG_BHWF (0x0029U) /*!< BLE_Host WakeUp Flag */ 349 #define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */ 350 #define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */ 351 #define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */ 352 #define PWR_FLAG_HOLDC2I (0x002EU) /*!< CPU2 on-Hold Interrupt Flag */ 353 #define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */ 354 355 /*--------------------------------SR2-------------------------------*/ 356 #if defined(PWR_CR5_SMPSEN) 357 #define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */ 358 #define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */ 359 #endif 360 361 #define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */ 362 #define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */ 363 364 #if defined(PWR_CR1_VOS) 365 #define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */ 366 #endif 367 #define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */ 368 369 #define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */ 370 #define PWR_FLAG_PVMO3 (0x004EU) /*!< Power Voltage Monitoring 3 output flag */ 371 372 /*------------------------------EXTSCR---------------------------*/ 373 #define PWR_FLAG_SB (0x0068U) /*!< System Standby flag for CPU1 */ 374 #define PWR_FLAG_STOP (0x0069U) /*!< System Stop flag for CPU1 */ 375 376 #define PWR_FLAG_C2SB (0x006AU) /*!< System Standby flag for CPU2 */ 377 #define PWR_FLAG_C2STOP (0x006BU) /*!< System Stop flag for CPU2 */ 378 379 #define PWR_FLAG_CRITICAL_RF_PHASE (0x006DU) /*!< Critical radio system phase flag */ 380 #define PWR_FLAG_C1DEEPSLEEP (0x006EU) /*!< CPU1 DeepSleep Flag */ 381 #define PWR_FLAG_C2DEEPSLEEP (0x006FU) /*!< CPU2 DeepSleep Flag */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup PWREx_WakeUpTarget_Definition PWR Wakeup Target Definition 387 * @{ 388 */ 389 #define PWR_WAKEUPTARGET_CPU1 (0x00000001U) 390 #define PWR_WAKEUPTARGET_CPU2 (0x00000002U) 391 #define PWR_WAKEUPTARGET_ALL_CPU (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2) 392 #define PWR_WAKEUPTARGET_RF (0x00000004U) 393 /** 394 * @} 395 */ 396 397 /** @defgroup PWREx_Core_Select PWREx Core definition 398 * @{ 399 */ 400 #define PWR_CORE_CPU1 (0x00000000U) 401 #define PWR_CORE_CPU2 (0x00000001U) 402 /** 403 * @} 404 */ 405 406 /** 407 * @} 408 */ 409 /* Private define ------------------------------------------------------------*/ 410 /** @defgroup PWR_Private_Defines PWR Private Defines 411 * @{ 412 */ 413 414 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 415 * @{ 416 */ 417 #if defined(PWR_CR2_PVME1) 418 #define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31) /*!< External interrupt line 31 Connected to PVM1 */ 419 #endif 420 #define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33) /*!< External interrupt line 33 Connected to PVM3 */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask 426 * @{ 427 */ 428 /* Note: On STM32WB serie, power PVD event is not available on AIEC lines */ 429 /* (only interruption is available through AIEC line 16). */ 430 #define PVM_MODE_IT (0x00010000U) /*!< Mask for interruption yielded by PVM threshold crossing */ 431 #define PVM_MODE_EVT (0x00020000U) /*!< Mask for event yielded by PVM threshold crossing */ 432 #define PVM_RISING_EDGE (0x00000001U) /*!< Mask for rising edge set as PVM trigger */ 433 #define PVM_FALLING_EDGE (0x00000002U) /*!< Mask for falling edge set as PVM trigger */ 434 #define PVM_RISING_FALLING_EDGE (0x00000003U) /*!< Mask for rising and falling edges set as PVM trigger */ 435 /** 436 * @} 437 */ 438 439 /** 440 * @} 441 */ 442 443 /* Exported macros -----------------------------------------------------------*/ 444 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 445 * @{ 446 */ 447 448 #if defined(PWR_CR2_PVME1) 449 /** 450 * @brief Enable the PVM1 Extended Interrupt C1 Line. 451 * @retval None 452 */ 453 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1) 454 455 /** 456 * @brief Enable the PVM1 Extended Interrupt C2 Line. 457 * @retval None 458 */ 459 #define __HAL_PWR_PVM1_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1) 460 461 /** 462 * @brief Disable the PVM1 Extended Interrupt C1 Line. 463 * @retval None 464 */ 465 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1) 466 467 /** 468 * @brief Disable the PVM1 Extended Interrupt C2 Line. 469 * @retval None 470 */ 471 #define __HAL_PWR_PVM1_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1) 472 473 /** 474 * @brief Enable the PVM1 Event C1 Line. 475 * @retval None 476 */ 477 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1) 478 479 /** 480 * @brief Enable the PVM1 Event C2 Line. 481 * @retval None 482 */ 483 #define __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1) 484 485 /** 486 * @brief Disable the PVM1 Event C1 Line. 487 * @retval None 488 */ 489 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1) 490 491 /** 492 * @brief Disable the PVM1 Event C2 Line. 493 * @retval None 494 */ 495 #define __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1) 496 497 /** 498 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 499 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 500 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 501 * @retval None 502 */ 503 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1) 504 505 /** 506 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 507 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 508 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 509 * @retval None 510 */ 511 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1) 512 513 /** 514 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 515 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 516 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 517 * @retval None 518 */ 519 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1) 520 521 522 /** 523 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 524 * @note PVM1 flag polarity is inverted compared to EXTI line, therefore 525 * EXTI rising and falling logic edges are inverted versus PVM1 voltage edges. 526 * @retval None 527 */ 528 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1) 529 530 /** 531 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 532 * @retval None 533 */ 534 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 535 do { \ 536 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 537 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 538 } while(0) 539 540 /** 541 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 542 * @retval None 543 */ 544 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 545 do { \ 546 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 547 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 548 } while(0) 549 550 /** 551 * @brief Generate a Software interrupt on selected EXTI line. 552 * @retval None 553 */ 554 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1) 555 556 /** 557 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 558 * @retval EXTI PVM1 Line Status. 559 */ 560 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1) 561 562 /** 563 * @brief Clear the PVM1 EXTI flag. 564 * @retval None 565 */ 566 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1) 567 568 #endif 569 570 /** 571 * @brief Enable the PVM3 Extended Interrupt C1 Line. 572 * @retval None 573 */ 574 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) 575 576 /** 577 * @brief Enable the PVM3 Extended Interrupt C2 Line. 578 * @retval None 579 */ 580 #define __HAL_PWR_PVM3_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) 581 582 /** 583 * @brief Disable the PVM3 Extended Interrupt C1 Line. 584 * @retval None 585 */ 586 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) 587 588 /** 589 * @brief Disable the PVM3 Extended Interrupt C2 Line. 590 * @retval None 591 */ 592 #define __HAL_PWR_PVM3_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) 593 594 /** 595 * @brief Enable the PVM3 Event C1 Line. 596 * @retval None 597 */ 598 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) 599 600 /** 601 * @brief Enable the PVM3 Event C2 Line. 602 * @retval None 603 */ 604 #define __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) 605 606 /** 607 * @brief Disable the PVM3 Event C1 Line. 608 * @retval None 609 */ 610 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) 611 612 /** 613 * @brief Disable the PVM3 Event C2 Line. 614 * @retval None 615 */ 616 #define __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) 617 618 /** 619 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 620 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 621 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 622 * @retval None 623 */ 624 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3) 625 626 /** 627 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 628 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 629 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 630 * @retval None 631 */ 632 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3) 633 634 /** 635 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 636 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 637 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 638 * @retval None 639 */ 640 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3) 641 642 643 /** 644 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 645 * @note PVM3 flag polarity is inverted compared to EXTI line, therefore 646 * EXTI rising and falling logic edges are inverted versus PVM3 voltage edges. 647 * @retval None 648 */ 649 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3) 650 651 /** 652 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 653 * @retval None 654 */ 655 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 656 do { \ 657 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 658 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 659 } while(0) 660 661 /** 662 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 663 * @retval None 664 */ 665 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 666 do { \ 667 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 668 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 669 } while(0) 670 671 /** 672 * @brief Generate a Software interrupt on selected EXTI line. 673 * @retval None 674 */ 675 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3) 676 677 /** 678 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 679 * @retval EXTI PVM3 Line Status. 680 */ 681 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3) 682 683 /** 684 * @brief Clear the PVM3 EXTI flag. 685 * @retval None 686 */ 687 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3) 688 689 #if defined(PWR_CR1_VOS) 690 /** 691 * @brief Configure the main internal regulator output voltage. 692 * @param __REGULATOR__ specifies the regulator output voltage to achieve 693 * a tradeoff between performance and power consumption. 694 * This parameter can be one of the following values: 695 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 696 * typical output voltage at 1.2 V, 697 * system frequency up to 64 MHz. 698 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 699 * typical output voltage at 1.0 V, 700 * system frequency up to 16 MHz. 701 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 702 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 703 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 704 * @retval None 705 */ 706 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 707 __IO uint32_t tmpreg; \ 708 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 709 /* Delay after an RCC peripheral clock enabling */ \ 710 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 711 UNUSED(tmpreg); \ 712 } while(0) 713 #endif 714 715 /** 716 * @brief Wakeup BLE controller from its sleep mode 717 * @note This bit is automatically reset when 802.15.4 controller 718 * exit its sleep mode. 719 * @retval None 720 */ 721 #define __HAL_C2_PWR_WAKEUP_BLE() LL_C2_PWR_WakeUp_BLE() 722 723 /** 724 * @brief Wakeup 802.15.4 controller from its sleep mode 725 * @note This bit is automatically reset when 802.15.4 controller 726 * exit its sleep mode. 727 * @retval None 728 */ 729 #define __HAL_C2_PWR_WAKEUP_802_15_4() LL_C2_PWR_WakeUp_802_15_4() 730 731 /** 732 * @} 733 */ 734 735 /* Private macros --------------------------------------------------------*/ 736 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 737 * @{ 738 */ 739 #if defined(PWR_CR3_EWUP2) 740 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 741 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 742 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 743 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 744 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 745 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 746 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 747 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 748 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 749 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 750 #else 751 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 752 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 753 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 754 ((PIN) == PWR_WAKEUP_PIN4_LOW)) 755 #endif 756 757 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \ 758 ((POLARITY) == PWR_PIN_POLARITY_LOW)) 759 760 #if defined(PWR_CR2_PVME1) 761 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 762 ((TYPE) == PWR_PVM_3)) 763 #else 764 #define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_3) 765 #endif 766 767 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 768 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 769 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 770 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 771 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 772 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 773 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 774 775 #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \ 776 (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u)) 777 778 #if defined(PWR_CR1_VOS) 779 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 780 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 781 #endif 782 783 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 784 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 785 786 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 787 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 788 789 790 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 791 792 #if defined(GPIOD) 793 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 794 ((GPIO) == PWR_GPIO_B) ||\ 795 ((GPIO) == PWR_GPIO_C) ||\ 796 ((GPIO) == PWR_GPIO_D) ||\ 797 ((GPIO) == PWR_GPIO_E) ||\ 798 ((GPIO) == PWR_GPIO_H)) 799 #else 800 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 801 ((GPIO) == PWR_GPIO_B) ||\ 802 ((GPIO) == PWR_GPIO_C) ||\ 803 ((GPIO) == PWR_GPIO_E) ||\ 804 ((GPIO) == PWR_GPIO_H)) 805 #endif 806 807 #if defined(PWR_CR5_SMPSEN) 808 #define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\ 809 ((SMPS_MODE) == PWR_SMPS_STEP_DOWN)) 810 811 #define IS_PWR_SMPS_STARTUP_CURRENT(SMPS_STARTUP_CURRENT) (((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_80MA) ||\ 812 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_100MA) ||\ 813 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_120MA) ||\ 814 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_140MA) ||\ 815 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_160MA) ||\ 816 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_180MA) ||\ 817 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_200MA) ||\ 818 ((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_220MA)) 819 820 #define IS_PWR_SMPS_OUTPUT_VOLTAGE(SMPS_OUTPUT_VOLTAGE) (((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V20) ||\ 821 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V25) ||\ 822 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V30) ||\ 823 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V35) ||\ 824 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V40) ||\ 825 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V45) ||\ 826 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V50) ||\ 827 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V55) ||\ 828 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V60) ||\ 829 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V65) ||\ 830 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V70) ||\ 831 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V75) ||\ 832 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\ 833 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\ 834 ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90)) 835 #endif 836 837 #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) 838 839 #define IS_PWR_CORE_HOLD_RELEASE(CPU) ((CPU) == PWR_CORE_CPU2) 840 841 /** 842 * @} 843 */ 844 845 846 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 847 * @{ 848 */ 849 850 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 851 * @{ 852 */ 853 854 /* Peripheral Control functions **********************************************/ 855 uint32_t HAL_PWREx_GetVoltageRange(void); 856 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 857 858 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 859 void HAL_PWREx_DisableBatteryCharging(void); 860 861 void HAL_PWREx_EnableVddUSB(void); 862 void HAL_PWREx_DisableVddUSB(void); 863 864 void HAL_PWREx_EnableInternalWakeUpLine(void); 865 void HAL_PWREx_DisableInternalWakeUpLine(void); 866 867 #if defined(PWR_CR5_SMPSEN) 868 void HAL_PWREx_EnableBORH_SMPSBypassIT(void); 869 void HAL_PWREx_DisableBORH_SMPSBypassIT(void); 870 #endif 871 void HAL_PWREx_EnableRFPhaseIT(void); 872 void HAL_PWREx_DisableRFPhaseIT(void); 873 void HAL_PWREx_EnableBLEActivityIT(void); 874 void HAL_PWREx_DisableBLEActivityIT(void); 875 void HAL_PWREx_Enable802ActivityIT(void); 876 void HAL_PWREx_Disable802ActivityIT(void); 877 void HAL_PWREx_EnableHOLDC2IT(void); 878 void HAL_PWREx_DisableHOLDC2IT(void); 879 880 void HAL_PWREx_HoldCore(uint32_t CPU); 881 void HAL_PWREx_ReleaseCore(uint32_t CPU); 882 883 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 884 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 885 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 886 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 887 void HAL_PWREx_EnablePullUpPullDownConfig(void); 888 void HAL_PWREx_DisablePullUpPullDownConfig(void); 889 890 #if defined(PWR_CR5_SMPSEN) 891 void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration); 892 uint32_t HAL_PWREx_GetBORConfig(void); 893 #endif 894 895 void HAL_PWREx_EnableSRAMRetention(void); 896 void HAL_PWREx_DisableSRAMRetention(void); 897 898 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); 899 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); 900 901 #if defined(PWR_CR2_PVME1) 902 void HAL_PWREx_EnablePVM1(void); 903 void HAL_PWREx_DisablePVM1(void); 904 #endif 905 906 void HAL_PWREx_EnablePVM3(void); 907 void HAL_PWREx_DisablePVM3(void); 908 909 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 910 911 #if defined(PWR_CR5_SMPSEN) 912 HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS); 913 void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); 914 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); 915 #endif 916 917 /* WakeUp pins configuration functions ****************************************/ 918 void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget); 919 uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag); 920 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag); 921 922 /* Low Power modes configuration functions ************************************/ 923 void HAL_PWREx_EnableLowPowerRunMode(void); 924 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 925 926 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 927 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 928 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 929 void HAL_PWREx_EnterSHUTDOWNMode(void); 930 931 void HAL_PWREx_PVD_PVM_IRQHandler(void); 932 933 #if defined(PWR_CR2_PVME1) 934 void HAL_PWREx_PVM1Callback(void); 935 #endif 936 void HAL_PWREx_PVM3Callback(void); 937 938 /** 939 * @} 940 */ 941 942 /** 943 * @} 944 */ 945 946 /** 947 * @} 948 */ 949 950 /** 951 * @} 952 */ 953 954 #ifdef __cplusplus 955 } 956 #endif 957 958 959 #endif /* STM32WBxx_HAL_PWR_EX_H */ 960 961 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 962