1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_DMA_H 22 #define STM32WBxx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 #include "stm32wbxx_ll_dma.h" 31 32 /** @addtogroup STM32WBxx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup DMA 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Request; /*!< Specifies the request selected for the specified channel. 51 This parameter can be a value of @ref DMA_request */ 52 53 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 54 from memory to memory or from peripheral to memory. 55 This parameter can be a value of @ref DMA_Data_transfer_direction */ 56 57 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 59 60 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 61 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 62 63 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 64 This parameter can be a value of @ref DMA_Peripheral_data_size */ 65 66 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 67 This parameter can be a value of @ref DMA_Memory_data_size */ 68 69 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 70 This parameter can be a value of @ref DMA_mode 71 @note The circular buffer mode cannot be used if the memory-to-memory 72 data transfer is configured on the selected Channel */ 73 74 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 75 This parameter can be a value of @ref DMA_Priority_level */ 76 } DMA_InitTypeDef; 77 78 /** 79 * @brief HAL DMA State structures definition 80 */ 81 typedef enum 82 { 83 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 84 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 85 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 86 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 87 } HAL_DMA_StateTypeDef; 88 89 /** 90 * @brief HAL DMA Error Code structure definition 91 */ 92 typedef enum 93 { 94 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 95 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 96 } HAL_DMA_LevelCompleteTypeDef; 97 98 99 /** 100 * @brief HAL DMA Callback ID structure definition 101 */ 102 typedef enum 103 { 104 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 105 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 106 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 107 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 108 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 109 110 } HAL_DMA_CallbackIDTypeDef; 111 112 /** 113 * @brief DMA handle Structure definition 114 */ 115 typedef struct __DMA_HandleTypeDef 116 { 117 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 118 119 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 120 121 HAL_LockTypeDef Lock; /*!< DMA locking object */ 122 123 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 124 125 void *Parent; /*!< Parent object state */ 126 127 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 128 129 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 130 131 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 132 133 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 134 135 __IO uint32_t ErrorCode; /*!< DMA Error code */ 136 137 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 138 139 uint32_t ChannelIndex; /*!< DMA Channel Index */ 140 141 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 142 143 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 144 145 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 146 147 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 148 149 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 150 151 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 152 } DMA_HandleTypeDef; 153 /** 154 * @} 155 */ 156 157 /* Exported constants --------------------------------------------------------*/ 158 159 /** @defgroup DMA_Exported_Constants DMA Exported Constants 160 * @{ 161 */ 162 163 /** @defgroup DMA_Error_Code DMA Error Code 164 * @{ 165 */ 166 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 167 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 168 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 169 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 170 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 171 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 172 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 173 174 /** 175 * @} 176 */ 177 178 /** @defgroup DMA_request DMA request 179 * @{ 180 */ 181 182 #define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ 183 184 #define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ 185 #define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ 186 #define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ 187 #define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ 188 189 #define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */ 190 191 #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ 192 #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ 193 #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ 194 #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ 195 196 #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ 197 #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ 198 #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ 199 #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ 200 201 #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ 202 #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ 203 204 #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */ 205 #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */ 206 207 #if defined (SAI1) 208 #define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */ 209 #define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */ 210 #endif /* SAI1 */ 211 212 #define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */ 213 214 #define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ 215 #define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ 216 #define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ 217 #define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ 218 #define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ 219 #define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG /*!< DMAMUX TIM1 TRIG request */ 220 #define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM /*!< DMAMUX TIM1 COM request */ 221 222 #define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ 223 #define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ 224 #define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ 225 #define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ 226 #define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ 227 228 #define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ 229 #define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ 230 231 #define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ 232 #define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ 233 234 #define DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN /*!< DMAMUX AES1 IN request */ 235 #define DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT /*!< DMAMUX AES1 OUT request */ 236 237 #define DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN /*!< DMAMUX AES2 IN request */ 238 #define DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT /*!< DMAMUX AES2 OUT request */ 239 /** 240 * @} 241 */ 242 243 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 244 * @{ 245 */ 246 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ 247 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ 248 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ 249 /** 250 * @} 251 */ 252 253 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 254 * @{ 255 */ 256 #define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ 257 #define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ 258 /** 259 * @} 260 */ 261 262 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 263 * @{ 264 */ 265 #define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ 266 #define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 272 * @{ 273 */ 274 #define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ 275 #define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ 276 #define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ 277 /** 278 * @} 279 */ 280 281 /** @defgroup DMA_Memory_data_size DMA Memory data size 282 * @{ 283 */ 284 #define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ 285 #define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ 286 #define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ 287 /** 288 * @} 289 */ 290 291 /** @defgroup DMA_mode DMA mode 292 * @{ 293 */ 294 #define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ 295 #define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ 296 /** 297 * @} 298 */ 299 300 /** @defgroup DMA_Priority_level DMA Priority level 301 * @{ 302 */ 303 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ 304 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ 305 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ 306 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ 307 /** 308 * @} 309 */ 310 311 312 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 313 * @{ 314 */ 315 #define DMA_IT_TC LL_DMA_CCR_TCIE /*!< Transfer complete interrupt */ 316 #define DMA_IT_HT LL_DMA_CCR_HTIE /*!< Half Transfer interrupt */ 317 #define DMA_IT_TE LL_DMA_CCR_TEIE /*!< Transfer error interrupt */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup DMA_flag_definitions DMA flag definitions 323 * @{ 324 */ 325 #define DMA_FLAG_GL1 LL_DMA_ISR_GIF1 /*!< Channel 1 global flag */ 326 #define DMA_FLAG_TC1 LL_DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 327 #define DMA_FLAG_HT1 LL_DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 328 #define DMA_FLAG_TE1 LL_DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 329 #define DMA_FLAG_GL2 LL_DMA_ISR_GIF2 /*!< Channel 2 global flag */ 330 #define DMA_FLAG_TC2 LL_DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 331 #define DMA_FLAG_HT2 LL_DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 332 #define DMA_FLAG_TE2 LL_DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 333 #define DMA_FLAG_GL3 LL_DMA_ISR_GIF3 /*!< Channel 3 global flag */ 334 #define DMA_FLAG_TC3 LL_DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 335 #define DMA_FLAG_HT3 LL_DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 336 #define DMA_FLAG_TE3 LL_DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 337 #define DMA_FLAG_GL4 LL_DMA_ISR_GIF4 /*!< Channel 4 global flag */ 338 #define DMA_FLAG_TC4 LL_DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 339 #define DMA_FLAG_HT4 LL_DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 340 #define DMA_FLAG_TE4 LL_DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 341 #define DMA_FLAG_GL5 LL_DMA_ISR_GIF5 /*!< Channel 5 global flag */ 342 #define DMA_FLAG_TC5 LL_DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 343 #define DMA_FLAG_HT5 LL_DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 344 #define DMA_FLAG_TE5 LL_DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 345 #define DMA_FLAG_GL6 LL_DMA_ISR_GIF6 /*!< Channel 6 global flag */ 346 #define DMA_FLAG_TC6 LL_DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 347 #define DMA_FLAG_HT6 LL_DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 348 #define DMA_FLAG_TE6 LL_DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 349 #define DMA_FLAG_GL7 LL_DMA_ISR_GIF7 /*!< Channel 7 global flag */ 350 #define DMA_FLAG_TC7 LL_DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 351 #define DMA_FLAG_HT7 LL_DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 352 #define DMA_FLAG_TE7 LL_DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 353 /** 354 * @} 355 */ 356 357 /** 358 * @} 359 */ 360 361 /* Exported macros -----------------------------------------------------------*/ 362 /** @defgroup DMA_Exported_Macros DMA Exported Macros 363 * @{ 364 */ 365 366 /** @brief Reset DMA handle state. 367 * @param __HANDLE__ DMA handle 368 * @retval None 369 */ 370 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 371 372 /** 373 * @brief Enable the specified DMA Channel. 374 * @param __HANDLE__ DMA handle 375 * @retval None 376 */ 377 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 378 379 /** 380 * @brief Disable the specified DMA Channel. 381 * @param __HANDLE__ DMA handle 382 * @retval None 383 */ 384 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 385 386 387 /* Interrupt & Flag management */ 388 389 /** 390 * @brief Return the current DMA Channel transfer complete flag. 391 * @param __HANDLE__ DMA handle 392 * @retval The specified transfer complete flag index. 393 */ 394 395 #if defined(DMA2) 396 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 397 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 398 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 399 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 400 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 401 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 402 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 403 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 404 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 405 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 406 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 407 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 408 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 409 DMA_FLAG_TC7) 410 #else 411 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 412 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 418 DMA_FLAG_TC7) 419 #endif 420 421 /** 422 * @brief Return the current DMA Channel half transfer complete flag. 423 * @param __HANDLE__ DMA handle 424 * @retval The specified half transfer complete flag index. 425 */ 426 #if defined(DMA2) 427 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 428 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 440 DMA_FLAG_HT7) 441 #else 442 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 449 DMA_FLAG_HT7) 450 #endif 451 452 /** 453 * @brief Return the current DMA Channel transfer error flag. 454 * @param __HANDLE__ DMA handle 455 * @retval The specified transfer error flag index. 456 */ 457 #if defined(DMA2) 458 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 459 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 471 DMA_FLAG_TE7) 472 #else 473 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 474 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 480 DMA_FLAG_TE7) 481 #endif 482 483 /** 484 * @brief Return the current DMA Channel Global interrupt flag. 485 * @param __HANDLE__ DMA handle 486 * @retval The specified transfer error flag index. 487 */ 488 #if defined(DMA2) 489 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 490 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 502 DMA_ISR_GIF7) 503 #else 504 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 505 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 511 DMA_ISR_GIF7) 512 #endif 513 514 /** 515 * @brief Get the DMA Channel pending flags. 516 * @param __HANDLE__ DMA handle 517 * @param __FLAG__ Get the specified flag. 518 * This parameter can be any combination of the following values: 519 * @arg DMA_FLAG_TCx: Transfer complete flag 520 * @arg DMA_FLAG_HTx: Half transfer complete flag 521 * @arg DMA_FLAG_TEx: Transfer error flag 522 * @arg DMA_FLAG_GLx: Global interrupt flag 523 * Where x can be from 1 to 7 to select the DMA Channel x flag. 524 * @retval The state of FLAG (SET or RESET). 525 */ 526 #if defined(DMA2) 527 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 528 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 529 #else 530 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 531 #endif 532 533 /** 534 * @brief Clear the DMA Channel pending flags. 535 * @param __HANDLE__ DMA handle 536 * @param __FLAG__ specifies the flag to clear. 537 * This parameter can be any combination of the following values: 538 * @arg DMA_FLAG_TCx: Transfer complete flag 539 * @arg DMA_FLAG_HTx: Half transfer complete flag 540 * @arg DMA_FLAG_TEx: Transfer error flag 541 * @arg DMA_FLAG_GLx: Global interrupt flag 542 * Where x can be from 1 to 7 to select the DMA Channel x flag. 543 * @retval None 544 */ 545 #if defined(DMA2) 546 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 547 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 548 #else 549 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 550 #endif 551 552 /** 553 * @brief Enable the specified DMA Channel interrupts. 554 * @param __HANDLE__ DMA handle 555 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 556 * This parameter can be any combination of the following values: 557 * @arg DMA_IT_TC: Transfer complete interrupt mask 558 * @arg DMA_IT_HT: Half transfer complete interrupt mask 559 * @arg DMA_IT_TE: Transfer error interrupt mask 560 * @retval None 561 */ 562 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 563 564 /** 565 * @brief Disable the specified DMA Channel interrupts. 566 * @param __HANDLE__ DMA handle 567 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 568 * This parameter can be any combination of the following values: 569 * @arg DMA_IT_TC: Transfer complete interrupt mask 570 * @arg DMA_IT_HT: Half transfer complete interrupt mask 571 * @arg DMA_IT_TE: Transfer error interrupt mask 572 * @retval None 573 */ 574 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 575 576 /** 577 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 578 * @param __HANDLE__ DMA handle 579 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 580 * This parameter can be one of the following values: 581 * @arg DMA_IT_TC: Transfer complete interrupt mask 582 * @arg DMA_IT_HT: Half transfer complete interrupt mask 583 * @arg DMA_IT_TE: Transfer error interrupt mask 584 * @retval The state of DMA_IT (SET or RESET). 585 */ 586 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 587 588 /** 589 * @brief Return the number of remaining data units in the current DMA Channel transfer. 590 * @param __HANDLE__ DMA handle 591 * @retval The number of remaining data units in the current DMA Channel transfer. 592 */ 593 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 594 595 /** 596 * @} 597 */ 598 599 /* Include DMA HAL Extension module */ 600 #include "stm32wbxx_hal_dma_ex.h" 601 602 /* Exported functions --------------------------------------------------------*/ 603 604 /** @addtogroup DMA_Exported_Functions 605 * @{ 606 */ 607 608 /** @addtogroup DMA_Exported_Functions_Group1 609 * @{ 610 */ 611 /* Initialization and de-initialization functions *****************************/ 612 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 613 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 614 /** 615 * @} 616 */ 617 618 /** @addtogroup DMA_Exported_Functions_Group2 619 * @{ 620 */ 621 /* IO operation functions *****************************************************/ 622 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 623 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 624 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 625 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 626 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 627 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 628 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 629 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 630 631 /** 632 * @} 633 */ 634 635 /** @addtogroup DMA_Exported_Functions_Group3 636 * @{ 637 */ 638 /* Peripheral State and Error functions ***************************************/ 639 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 640 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 641 /** 642 * @} 643 */ 644 645 /** 646 * @} 647 */ 648 649 /* Private macros ------------------------------------------------------------*/ 650 /** @defgroup DMA_Private_Macros DMA Private Macros 651 * @{ 652 */ 653 654 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 655 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 656 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 657 658 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 659 660 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 661 ((STATE) == DMA_PINC_DISABLE)) 662 663 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 664 ((STATE) == DMA_MINC_DISABLE)) 665 666 667 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_AES2_OUT) 668 669 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 670 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 671 ((SIZE) == DMA_PDATAALIGN_WORD)) 672 673 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 674 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 675 ((SIZE) == DMA_MDATAALIGN_WORD )) 676 677 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 678 ((MODE) == DMA_CIRCULAR)) 679 680 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 681 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 682 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 683 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 684 685 /** 686 * @} 687 */ 688 689 /* Private functions ---------------------------------------------------------*/ 690 691 /** 692 * @} 693 */ 694 695 /** 696 * @} 697 */ 698 699 #ifdef __cplusplus 700 } 701 #endif 702 703 #endif /* STM32WBxx_HAL_DMA_H */ 704 705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 706