1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_CORTEX_H 22 #define STM32WBxx_HAL_CORTEX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 31 /** @addtogroup STM32WBxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup CORTEX CORTEX 36 * @brief CORTEX HAL module driver 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 42 * @{ 43 */ 44 45 #if (__MPU_PRESENT == 1) 46 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 47 * @brief MPU Region initialization structure 48 * @{ 49 */ 50 typedef struct 51 { 52 uint8_t Enable; /*!< Specifies the status of the region. 53 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 54 uint8_t Number; /*!< Specifies the number of the region to protect. 55 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 56 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. 57 */ 58 uint8_t Size; /*!< Specifies the size of the region to protect. 59 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 60 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 61 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 62 uint8_t TypeExtField; /*!< Specifies the TEX field level. 63 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 64 uint8_t AccessPermission; /*!< Specifies the region access permission type. 65 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 66 uint8_t DisableExec; /*!< Specifies the instruction access status. 67 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 68 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 69 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 70 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 71 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 72 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 73 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 74 }MPU_Region_InitTypeDef; 75 /** 76 * @} 77 */ 78 #endif /* __MPU_PRESENT */ 79 80 /** 81 * @} 82 */ 83 84 /* Exported constants --------------------------------------------------------*/ 85 86 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 87 * @{ 88 */ 89 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 90 * @{ 91 */ 92 #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bit for pre-emption priority, 93 4 bits for subpriority */ 94 #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bit for pre-emption priority, 95 3 bits for subpriority */ 96 #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority, 97 2 bits for subpriority */ 98 #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority, 99 1 bit for subpriority */ 100 #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority, 101 0 bit for subpriority */ 102 /** 103 * @} 104 */ 105 106 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 107 * @{ 108 */ 109 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 110 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 111 112 /** 113 * @} 114 */ 115 116 #if (__MPU_PRESENT == 1) 117 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 118 * @{ 119 */ 120 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 121 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 122 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 123 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 124 /** 125 * @} 126 */ 127 128 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 129 * @{ 130 */ 131 #define MPU_REGION_ENABLE ((uint8_t)0x01) 132 #define MPU_REGION_DISABLE ((uint8_t)0x00) 133 /** 134 * @} 135 */ 136 137 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 138 * @{ 139 */ 140 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 141 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 142 /** 143 * @} 144 */ 145 146 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 147 * @{ 148 */ 149 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 150 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 151 /** 152 * @} 153 */ 154 155 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 156 * @{ 157 */ 158 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 159 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 160 /** 161 * @} 162 */ 163 164 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 165 * @{ 166 */ 167 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 168 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 169 /** 170 * @} 171 */ 172 173 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 174 * @{ 175 */ 176 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 177 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 178 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 179 /** 180 * @} 181 */ 182 183 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 184 * @{ 185 */ 186 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 187 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 188 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 189 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 190 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 191 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 192 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 193 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 194 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 195 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 196 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 197 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 198 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 199 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 200 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 201 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 202 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 203 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 204 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 205 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 206 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 207 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 208 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 209 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 210 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 211 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 212 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 213 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 214 /** 215 * @} 216 */ 217 218 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 219 * @{ 220 */ 221 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 222 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 223 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 224 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 225 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 226 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 227 /** 228 * @} 229 */ 230 231 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 232 * @{ 233 */ 234 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 235 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 236 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 237 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 238 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 239 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 240 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 241 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 242 /** 243 * @} 244 */ 245 #endif /* __MPU_PRESENT */ 246 247 /** 248 * @} 249 */ 250 251 /* Exported macros -----------------------------------------------------------*/ 252 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 253 * @{ 254 */ 255 256 /** 257 * @} 258 */ 259 260 /* Exported functions --------------------------------------------------------*/ 261 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 262 * @{ 263 */ 264 265 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 266 * @brief Initialization and Configuration functions 267 * @{ 268 */ 269 /* Initialization and Configuration functions *****************************/ 270 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 271 void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); 272 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 273 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 274 void HAL_NVIC_SystemReset(void); 275 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 276 /** 277 * @} 278 */ 279 280 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 281 * @brief Cortex control functions 282 * @{ 283 */ 284 /* Peripheral Control functions *************************************************/ 285 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 286 uint32_t HAL_NVIC_GetPriorityGrouping(void); 287 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 288 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 289 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 290 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 291 void HAL_SYSTICK_IRQHandler(void); 292 void HAL_SYSTICK_Callback(void); 293 294 #if (__MPU_PRESENT == 1U) 295 void HAL_MPU_Enable(uint32_t MPU_Control); 296 void HAL_MPU_Disable(void); 297 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 298 #endif /* __MPU_PRESENT */ 299 /** 300 * @} 301 */ 302 303 /** 304 * @} 305 */ 306 307 /* Private types -------------------------------------------------------------*/ 308 /* Private variables ---------------------------------------------------------*/ 309 /* Private constants ---------------------------------------------------------*/ 310 /* Private macros ------------------------------------------------------------*/ 311 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 312 * @{ 313 */ 314 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 315 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 316 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 317 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 318 ((GROUP) == NVIC_PRIORITYGROUP_4)) 319 320 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 321 322 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 323 324 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 325 326 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 327 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 328 329 #if (__MPU_PRESENT == 1) 330 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 331 ((STATE) == MPU_REGION_DISABLE)) 332 333 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 334 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 335 336 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 337 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 338 339 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 340 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 341 342 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 343 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 344 345 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 346 ((TYPE) == MPU_TEX_LEVEL1) || \ 347 ((TYPE) == MPU_TEX_LEVEL2)) 348 349 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 350 ((TYPE) == MPU_REGION_PRIV_RW) || \ 351 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 352 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 353 ((TYPE) == MPU_REGION_PRIV_RO) || \ 354 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 355 356 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 357 ((NUMBER) == MPU_REGION_NUMBER1) || \ 358 ((NUMBER) == MPU_REGION_NUMBER2) || \ 359 ((NUMBER) == MPU_REGION_NUMBER3) || \ 360 ((NUMBER) == MPU_REGION_NUMBER4) || \ 361 ((NUMBER) == MPU_REGION_NUMBER5) || \ 362 ((NUMBER) == MPU_REGION_NUMBER6) || \ 363 ((NUMBER) == MPU_REGION_NUMBER7)) 364 365 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 366 ((SIZE) == MPU_REGION_SIZE_64B) || \ 367 ((SIZE) == MPU_REGION_SIZE_128B) || \ 368 ((SIZE) == MPU_REGION_SIZE_256B) || \ 369 ((SIZE) == MPU_REGION_SIZE_512B) || \ 370 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 371 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 372 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 373 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 374 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 375 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 376 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 377 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 378 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 379 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 380 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 381 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 382 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 383 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 384 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 385 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 386 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 387 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 388 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 389 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 390 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 391 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 392 ((SIZE) == MPU_REGION_SIZE_4GB)) 393 394 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 395 #endif /* __MPU_PRESENT */ 396 397 /** 398 * @} 399 */ 400 401 /* Private functions ---------------------------------------------------------*/ 402 403 /** 404 * @} 405 */ 406 407 /** 408 * @} 409 */ 410 411 #ifdef __cplusplus 412 } 413 #endif 414 415 #endif /* STM32WBxx_HAL_CORTEX_H */ 416 417 418 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 419 420