1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L4xx_LL_TIM_H
22 #define __STM32L4xx_LL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
36
37 /** @defgroup TIM_LL TIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
44 * @{
45 */
46 static const uint8_t OFFSET_TAB_CCMRx[] =
47 {
48 0x00U, /* 0: TIMx_CH1 */
49 0x00U, /* 1: TIMx_CH1N */
50 0x00U, /* 2: TIMx_CH2 */
51 0x00U, /* 3: TIMx_CH2N */
52 0x04U, /* 4: TIMx_CH3 */
53 0x04U, /* 5: TIMx_CH3N */
54 0x04U, /* 6: TIMx_CH4 */
55 0x3CU, /* 7: TIMx_CH5 */
56 0x3CU /* 8: TIMx_CH6 */
57 };
58
59 static const uint8_t SHIFT_TAB_OCxx[] =
60 {
61 0U, /* 0: OC1M, OC1FE, OC1PE */
62 0U, /* 1: - NA */
63 8U, /* 2: OC2M, OC2FE, OC2PE */
64 0U, /* 3: - NA */
65 0U, /* 4: OC3M, OC3FE, OC3PE */
66 0U, /* 5: - NA */
67 8U, /* 6: OC4M, OC4FE, OC4PE */
68 0U, /* 7: OC5M, OC5FE, OC5PE */
69 8U /* 8: OC6M, OC6FE, OC6PE */
70 };
71
72 static const uint8_t SHIFT_TAB_ICxx[] =
73 {
74 0U, /* 0: CC1S, IC1PSC, IC1F */
75 0U, /* 1: - NA */
76 8U, /* 2: CC2S, IC2PSC, IC2F */
77 0U, /* 3: - NA */
78 0U, /* 4: CC3S, IC3PSC, IC3F */
79 0U, /* 5: - NA */
80 8U, /* 6: CC4S, IC4PSC, IC4F */
81 0U, /* 7: - NA */
82 0U /* 8: - NA */
83 };
84
85 static const uint8_t SHIFT_TAB_CCxP[] =
86 {
87 0U, /* 0: CC1P */
88 2U, /* 1: CC1NP */
89 4U, /* 2: CC2P */
90 6U, /* 3: CC2NP */
91 8U, /* 4: CC3P */
92 10U, /* 5: CC3NP */
93 12U, /* 6: CC4P */
94 16U, /* 7: CC5P */
95 20U /* 8: CC6P */
96 };
97
98 static const uint8_t SHIFT_TAB_OISx[] =
99 {
100 0U, /* 0: OIS1 */
101 1U, /* 1: OIS1N */
102 2U, /* 2: OIS2 */
103 3U, /* 3: OIS2N */
104 4U, /* 4: OIS3 */
105 5U, /* 5: OIS3N */
106 6U, /* 6: OIS4 */
107 8U, /* 7: OIS5 */
108 10U /* 8: OIS6 */
109 };
110 /**
111 * @}
112 */
113
114 /* Private constants ---------------------------------------------------------*/
115 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
116 * @{
117 */
118
119 /* Defines used for the bit position in the register and perform offsets */
120 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
121
122 /* Generic bit definitions for TIMx_OR2 register */
123 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */
124 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */
125
126 /* Remap mask definitions */
127 #define TIMx_OR1_RMP_SHIFT 16U
128 #define TIMx_OR1_RMP_MASK 0x0000FFFFU
129 #if defined(ADC3)
130 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
131 #else
132 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
133 #endif /* ADC3 */
134 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
135 #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
136 #if defined(ADC2) && defined(ADC3)
137 #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
138 #else
139 #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
140 #endif /* ADC2 & ADC3 */
141 #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
142 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
143 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
144
145 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
146 #define DT_DELAY_1 ((uint8_t)0x7F)
147 #define DT_DELAY_2 ((uint8_t)0x3F)
148 #define DT_DELAY_3 ((uint8_t)0x1F)
149 #define DT_DELAY_4 ((uint8_t)0x1F)
150
151 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
152 #define DT_RANGE_1 ((uint8_t)0x00)
153 #define DT_RANGE_2 ((uint8_t)0x80)
154 #define DT_RANGE_3 ((uint8_t)0xC0)
155 #define DT_RANGE_4 ((uint8_t)0xE0)
156
157 /** Legacy definitions for compatibility purpose
158 @cond 0
159 */
160 #if defined(DFSDM1_Channel0)
161 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
162 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
163 #endif /* DFSDM1_Channel0 */
164 /**
165 @endcond
166 */
167
168 /**
169 * @}
170 */
171
172 /* Private macros ------------------------------------------------------------*/
173 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
174 * @{
175 */
176 /** @brief Convert channel id into channel index.
177 * @param __CHANNEL__ This parameter can be one of the following values:
178 * @arg @ref LL_TIM_CHANNEL_CH1
179 * @arg @ref LL_TIM_CHANNEL_CH1N
180 * @arg @ref LL_TIM_CHANNEL_CH2
181 * @arg @ref LL_TIM_CHANNEL_CH2N
182 * @arg @ref LL_TIM_CHANNEL_CH3
183 * @arg @ref LL_TIM_CHANNEL_CH3N
184 * @arg @ref LL_TIM_CHANNEL_CH4
185 * @arg @ref LL_TIM_CHANNEL_CH5
186 * @arg @ref LL_TIM_CHANNEL_CH6
187 * @retval none
188 */
189 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
190 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
197 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
198
199 /** @brief Calculate the deadtime sampling period(in ps).
200 * @param __TIMCLK__ timer input clock frequency (in Hz).
201 * @param __CKD__ This parameter can be one of the following values:
202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
203 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
204 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
205 * @retval none
206 */
207 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
208 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
209 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
210 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
211 /**
212 * @}
213 */
214
215
216 /* Exported types ------------------------------------------------------------*/
217 #if defined(USE_FULL_LL_DRIVER)
218 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
219 * @{
220 */
221
222 /**
223 * @brief TIM Time Base configuration structure definition.
224 */
225 typedef struct
226 {
227 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
228 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
229
230 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
231
232 uint32_t CounterMode; /*!< Specifies the counter mode.
233 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
234
235 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
236
237 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
238 Auto-Reload Register at the next update event.
239 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
240 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
241
242 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
243
244 uint32_t ClockDivision; /*!< Specifies the clock division.
245 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
246
247 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
248
249 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
250 reaches zero, an update event is generated and counting restarts
251 from the RCR value (N).
252 This means in PWM mode that (N+1) corresponds to:
253 - the number of PWM periods in edge-aligned mode
254 - the number of half PWM period in center-aligned mode
255 This parameter must be a number between 0x00 and 0xFF.
256
257 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
258 } LL_TIM_InitTypeDef;
259
260 /**
261 * @brief TIM Output Compare configuration structure definition.
262 */
263 typedef struct
264 {
265 uint32_t OCMode; /*!< Specifies the output mode.
266 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
267
268 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
269
270 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
271 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
272
273 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
274
275 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
276 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
277
278 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
279
280 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
281 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
282
283 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
284
285 uint32_t OCPolarity; /*!< Specifies the output polarity.
286 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
287
288 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
289
290 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
291 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
292
293 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
294
295
296 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
297 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
298
299 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
300
301 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
302 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
303
304 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
305 } LL_TIM_OC_InitTypeDef;
306
307 /**
308 * @brief TIM Input Capture configuration structure definition.
309 */
310
311 typedef struct
312 {
313
314 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
315 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
316
317 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
318
319 uint32_t ICActiveInput; /*!< Specifies the input.
320 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
321
322 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
323
324 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
325 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
326
327 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
328
329 uint32_t ICFilter; /*!< Specifies the input capture filter.
330 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
331
332 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
333 } LL_TIM_IC_InitTypeDef;
334
335
336 /**
337 * @brief TIM Encoder interface configuration structure definition.
338 */
339 typedef struct
340 {
341 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
342 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
343
344 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
345
346 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
347 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
348
349 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
350
351 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
352 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
353
354 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
355
356 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
357 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
358
359 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
360
361 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
362 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
363
364 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
365
366 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
367 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
368
369 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
370
371 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
372 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
373
374 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
375
376 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
377 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
378
379 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
380
381 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
382 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
383
384 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
385
386 } LL_TIM_ENCODER_InitTypeDef;
387
388 /**
389 * @brief TIM Hall sensor interface configuration structure definition.
390 */
391 typedef struct
392 {
393
394 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
395 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
396
397 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
398
399 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
400 Prescaler must be set to get a maximum counter period longer than the
401 time interval between 2 consecutive changes on the Hall inputs.
402 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
403
404 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
405
406 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
407 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
408
409 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
410
411 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
412 A positive pulse (TRGO event) is generated with a programmable delay every time
413 a change occurs on the Hall inputs.
414 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
415
416 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
417 } LL_TIM_HALLSENSOR_InitTypeDef;
418
419 /**
420 * @brief BDTR (Break and Dead Time) structure definition
421 */
422 typedef struct
423 {
424 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
425 This parameter can be a value of @ref TIM_LL_EC_OSSR
426
427 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
428
429 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
430
431 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
432 This parameter can be a value of @ref TIM_LL_EC_OSSI
433
434 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
435
436 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
437
438 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
439 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
440
441 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
442 has been written, their content is frozen until the next reset.*/
443
444 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
445 switching-on of the outputs.
446 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
447
448 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
449
450 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
451
452 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
453 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
454
455 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
456
457 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
458
459 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
460 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
461
462 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
463
464 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
465
466 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
467 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
468
469 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
470
471 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
472
473 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
474 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
475
476 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
477
478 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
479
480 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
481 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
482
483 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
484
485 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
486
487 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
488 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
489
490 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
491
492 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
493
494 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
495 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
496
497 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
498
499 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
500 } LL_TIM_BDTR_InitTypeDef;
501
502 /**
503 * @}
504 */
505 #endif /* USE_FULL_LL_DRIVER */
506
507 /* Exported constants --------------------------------------------------------*/
508 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
509 * @{
510 */
511
512 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
513 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
514 * @{
515 */
516 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
517 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
518 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
519 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
520 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
521 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
522 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
523 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
524 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
525 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
526 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
527 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
528 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
529 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
530 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
531 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
532 /**
533 * @}
534 */
535
536 #if defined(USE_FULL_LL_DRIVER)
537 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
538 * @{
539 */
540 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
541 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
542 /**
543 * @}
544 */
545
546 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
547 * @{
548 */
549 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
550 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
551 /**
552 * @}
553 */
554
555 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
556 * @{
557 */
558 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
559 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
560 /**
561 * @}
562 */
563 #endif /* USE_FULL_LL_DRIVER */
564
565 /** @defgroup TIM_LL_EC_IT IT Defines
566 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
567 * @{
568 */
569 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
570 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
571 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
572 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
573 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
574 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
575 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
576 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
577 /**
578 * @}
579 */
580
581 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
582 * @{
583 */
584 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
585 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
586 /**
587 * @}
588 */
589
590 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
591 * @{
592 */
593 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
594 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
595 /**
596 * @}
597 */
598
599 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
600 * @{
601 */
602 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
603 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
604 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
605 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
606 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
612 * @{
613 */
614 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
615 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
616 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
617 /**
618 * @}
619 */
620
621 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
622 * @{
623 */
624 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
625 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
626 /**
627 * @}
628 */
629
630 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
631 * @{
632 */
633 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
634 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
635 /**
636 * @}
637 */
638
639 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
640 * @{
641 */
642 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
643 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
644 /**
645 * @}
646 */
647
648 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
649 * @{
650 */
651 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
652 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
653 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
654 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
655 /**
656 * @}
657 */
658
659 /** @defgroup TIM_LL_EC_CHANNEL Channel
660 * @{
661 */
662 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
663 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
664 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
665 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
666 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
667 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
668 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
669 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
670 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
671 /**
672 * @}
673 */
674
675 #if defined(USE_FULL_LL_DRIVER)
676 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
677 * @{
678 */
679 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
680 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
681 /**
682 * @}
683 */
684 #endif /* USE_FULL_LL_DRIVER */
685
686 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
687 * @{
688 */
689 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
690 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
691 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
692 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
693 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
694 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
695 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
696 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
697 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
698 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
699 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
700 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
701 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
702 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
703 /**
704 * @}
705 */
706
707 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
708 * @{
709 */
710 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
711 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
712 /**
713 * @}
714 */
715
716 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
717 * @{
718 */
719 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
720 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
721 /**
722 * @}
723 */
724
725 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
726 * @{
727 */
728 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
729 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
730 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
731 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
732 /**
733 * @}
734 */
735
736 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
737 * @{
738 */
739 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
740 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
741 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
742 /**
743 * @}
744 */
745
746 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
747 * @{
748 */
749 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
750 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
751 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
752 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
753 /**
754 * @}
755 */
756
757 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
758 * @{
759 */
760 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
761 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
762 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
763 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
764 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
765 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
766 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
767 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
768 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
769 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
770 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
771 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
772 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
773 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
774 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
775 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
776 /**
777 * @}
778 */
779
780 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
781 * @{
782 */
783 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
784 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
785 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
791 * @{
792 */
793 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
794 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
795 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
801 * @{
802 */
803 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
804 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
805 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
806 /**
807 * @}
808 */
809
810 /** @defgroup TIM_LL_EC_TRGO Trigger Output
811 * @{
812 */
813 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
814 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
815 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
816 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
817 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
818 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
819 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
820 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
821 /**
822 * @}
823 */
824
825 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
826 * @{
827 */
828 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
829 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
830 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
831 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
832 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
833 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
834 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
835 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
836 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
837 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
838 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
839 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
840 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
841 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
842 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
843 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
844 /**
845 * @}
846 */
847
848 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
849 * @{
850 */
851 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
852 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
853 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
854 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
855 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
856 /**
857 * @}
858 */
859
860 /** @defgroup TIM_LL_EC_TS Trigger Selection
861 * @{
862 */
863 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
864 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
865 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
866 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
867 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
868 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
869 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
870 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
876 * @{
877 */
878 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
879 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
880 /**
881 * @}
882 */
883
884 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
885 * @{
886 */
887 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
888 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
889 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
890 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
891 /**
892 * @}
893 */
894
895 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
896 * @{
897 */
898 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
899 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
900 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
901 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
902 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
903 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
904 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
905 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
906 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
907 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
908 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
909 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
910 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
911 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
912 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
913 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
914 /**
915 * @}
916 */
917
918 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
919 * @{
920 */
921 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */
922 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< COMP1 output connected to ETR input */
923 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< COMP2 output connected to ETR input */
924 /**
925 * @}
926 */
927
928 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
929 * @{
930 */
931 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
932 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
933 /**
934 * @}
935 */
936
937 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
938 * @{
939 */
940 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
941 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
942 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
943 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
944 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
945 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
946 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
947 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
948 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
949 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
950 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
951 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
952 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
953 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
954 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
955 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
956 /**
957 * @}
958 */
959
960 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
961 * @{
962 */
963 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
964 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
965 /**
966 * @}
967 */
968
969 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
970 * @{
971 */
972 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
973 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
974 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
975 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
976 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
977 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
978 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
979 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
980 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
981 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
982 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
983 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
984 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
985 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
986 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
987 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
988 /**
989 * @}
990 */
991
992 /** @defgroup TIM_LL_EC_OSSI OSSI
993 * @{
994 */
995 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
996 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
997 /**
998 * @}
999 */
1000
1001 /** @defgroup TIM_LL_EC_OSSR OSSR
1002 * @{
1003 */
1004 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1005 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1006 /**
1007 * @}
1008 */
1009
1010 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1011 * @{
1012 */
1013 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1014 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1020 * @{
1021 */
1022 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */
1023 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */
1024 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */
1025 #if defined(DFSDM1_Channel0)
1026 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1027 #endif /* DFSDM1_Channel0 */
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1033 * @{
1034 */
1035 #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */
1036 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1042 * @{
1043 */
1044 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1045 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1046 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1047 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1048 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1049 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1050 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1051 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1052 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1053 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1054 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1055 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1056 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1057 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1058 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1059 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1060 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1061 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1062 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1063 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1064 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1065 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1066 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_OR2 register is the DMA base address for DMA burst */
1067 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */
1068 /**
1069 * @}
1070 */
1071
1072 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1073 * @{
1074 */
1075 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1076 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1077 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1078 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1079 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1080 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1081 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1082 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1083 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1084 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1085 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1086 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1087 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1088 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1089 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1090 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1091 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1092 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1093 /**
1094 * @}
1095 */
1096
1097 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1098 * @{
1099 */
1100 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1101 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1102 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1103 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1104 /**
1105 * @}
1106 */
1107
1108 #if defined(ADC3)
1109 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap
1110 * @{
1111 */
1112 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC3 analog watchdog x*/
1113 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */
1114 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */
1115 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */
1116 /**
1117 * @}
1118 */
1119 #endif /* ADC3 */
1120
1121 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1122 * @{
1123 */
1124 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1125 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1126 /**
1127 * @}
1128 */
1129
1130 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1131 * @{
1132 */
1133 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1134 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1135 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1136 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
1137 /* STM32L496xx || STM32L4A6xx || */
1138 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1139 #if defined (STM32L412xx) || defined (STM32L422xx) ||defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
1140 #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
1141 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
1142 #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
1143 /* STM32L451xx || STM32L452xx || STM32L462xx */
1144 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1145 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1146 /**
1147 * @}
1148 */
1149
1150 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1151 * @{
1152 */
1153 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1154 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1155 #if defined (STM32L412xx) || defined (STM32L422xx)
1156 #else
1157 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1158 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1159 #endif
1160 /**
1161 * @}
1162 */
1163
1164 #if defined(TIM3)
1165 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1166 * @{
1167 */
1168 #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */
1169 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */
1170 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */
1171 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1172 /**
1173 * @}
1174 */
1175 #endif /* TIM3 */
1176
1177 #if defined(TIM8)
1178 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
1179 * @{
1180 */
1181 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
1182 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
1183 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
1184 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
1185 /**
1186 * @}
1187 */
1188
1189 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
1190 * @{
1191 */
1192 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
1193 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
1194 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
1195 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
1201 * @{
1202 */
1203 #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */
1204 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */
1205 /**
1206 * @}
1207 */
1208 #endif /* TIM8 */
1209
1210 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1211 * @{
1212 */
1213 #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */
1214 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */
1215 /**
1216 * @}
1217 */
1218
1219 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
1220 * @{
1221 */
1222 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/
1223 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1224 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/
1225 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1226 /**
1227 * @}
1228 */
1229
1230 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1231 * @{
1232 */
1233 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1234 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1235 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1236 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1237 #if defined TIM16_OR1_TI1_RMP_2
1238 #define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MSI */
1239 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */
1240 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
1241 #endif
1242 /**
1243 * @}
1244 */
1245
1246 #if defined(TIM17)
1247 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1248 * @{
1249 */
1250 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1251 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1252 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1253 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1254 /**
1255 * @}
1256 */
1257 #endif /* TIM17 */
1258
1259 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1260 * @{
1261 */
1262 #define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /*!< OCREF_CLR_INT is not connected */
1263 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1264 /**
1265 * @}
1266 */
1267
1268 /** Legacy definitions for compatibility purpose
1269 @cond 0
1270 */
1271 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1272 /**
1273 @endcond
1274 */
1275 /**
1276 * @}
1277 */
1278
1279 /* Exported macro ------------------------------------------------------------*/
1280 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1281 * @{
1282 */
1283
1284 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1285 * @{
1286 */
1287 /**
1288 * @brief Write a value in TIM register.
1289 * @param __INSTANCE__ TIM Instance
1290 * @param __REG__ Register to be written
1291 * @param __VALUE__ Value to be written in the register
1292 * @retval None
1293 */
1294 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1295
1296 /**
1297 * @brief Read a value in TIM register.
1298 * @param __INSTANCE__ TIM Instance
1299 * @param __REG__ Register to be read
1300 * @retval Register value
1301 */
1302 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1303 /**
1304 * @}
1305 */
1306
1307 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1308 * @{
1309 */
1310
1311 /**
1312 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1313 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1314 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1315 * to TIMx_CNT register bit 31)
1316 * @param __CNT__ Counter value
1317 * @retval UIF status bit
1318 */
1319 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1320 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1321
1322 /**
1323 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1324 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1325 * @param __TIMCLK__ timer input clock frequency (in Hz)
1326 * @param __CKD__ This parameter can be one of the following values:
1327 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1328 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1329 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1330 * @param __DT__ deadtime duration (in ns)
1331 * @retval DTG[0:7]
1332 */
1333 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1334 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1335 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1336 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1337 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1338 0U)
1339
1340 /**
1341 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1342 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1343 * @param __TIMCLK__ timer input clock frequency (in Hz)
1344 * @param __CNTCLK__ counter clock frequency (in Hz)
1345 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1346 */
1347 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1348 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1349
1350 /**
1351 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1352 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1353 * @param __TIMCLK__ timer input clock frequency (in Hz)
1354 * @param __PSC__ prescaler
1355 * @param __FREQ__ output signal frequency (in Hz)
1356 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1357 */
1358 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1359 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1360
1361 /**
1362 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1363 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1364 * @param __TIMCLK__ timer input clock frequency (in Hz)
1365 * @param __PSC__ prescaler
1366 * @param __DELAY__ timer output compare active/inactive delay (in us)
1367 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1368 */
1369 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1370 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1371 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1372
1373 /**
1374 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1375 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1376 * @param __TIMCLK__ timer input clock frequency (in Hz)
1377 * @param __PSC__ prescaler
1378 * @param __DELAY__ timer output compare active/inactive delay (in us)
1379 * @param __PULSE__ pulse duration (in us)
1380 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1381 */
1382 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1383 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1384 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1385
1386 /**
1387 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1388 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1389 * @param __ICPSC__ This parameter can be one of the following values:
1390 * @arg @ref LL_TIM_ICPSC_DIV1
1391 * @arg @ref LL_TIM_ICPSC_DIV2
1392 * @arg @ref LL_TIM_ICPSC_DIV4
1393 * @arg @ref LL_TIM_ICPSC_DIV8
1394 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1395 */
1396 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1397 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1398
1399
1400 /**
1401 * @}
1402 */
1403
1404
1405 /**
1406 * @}
1407 */
1408
1409 /* Exported functions --------------------------------------------------------*/
1410 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1411 * @{
1412 */
1413
1414 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1415 * @{
1416 */
1417 /**
1418 * @brief Enable timer counter.
1419 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1420 * @param TIMx Timer instance
1421 * @retval None
1422 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1423 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1424 {
1425 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1426 }
1427
1428 /**
1429 * @brief Disable timer counter.
1430 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1431 * @param TIMx Timer instance
1432 * @retval None
1433 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1434 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1435 {
1436 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1437 }
1438
1439 /**
1440 * @brief Indicates whether the timer counter is enabled.
1441 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1442 * @param TIMx Timer instance
1443 * @retval State of bit (1 or 0).
1444 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)1445 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1446 {
1447 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1448 }
1449
1450 /**
1451 * @brief Enable update event generation.
1452 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1453 * @param TIMx Timer instance
1454 * @retval None
1455 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1456 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1457 {
1458 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1459 }
1460
1461 /**
1462 * @brief Disable update event generation.
1463 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1464 * @param TIMx Timer instance
1465 * @retval None
1466 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1467 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1468 {
1469 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1470 }
1471
1472 /**
1473 * @brief Indicates whether update event generation is enabled.
1474 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1475 * @param TIMx Timer instance
1476 * @retval Inverted state of bit (0 or 1).
1477 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)1478 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1479 {
1480 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1481 }
1482
1483 /**
1484 * @brief Set update event source
1485 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1486 * generate an update interrupt or DMA request if enabled:
1487 * - Counter overflow/underflow
1488 * - Setting the UG bit
1489 * - Update generation through the slave mode controller
1490 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1491 * overflow/underflow generates an update interrupt or DMA request if enabled.
1492 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1493 * @param TIMx Timer instance
1494 * @param UpdateSource This parameter can be one of the following values:
1495 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1496 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1497 * @retval None
1498 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1499 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1500 {
1501 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1502 }
1503
1504 /**
1505 * @brief Get actual event update source
1506 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1507 * @param TIMx Timer instance
1508 * @retval Returned value can be one of the following values:
1509 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1510 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1511 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)1512 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1513 {
1514 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1515 }
1516
1517 /**
1518 * @brief Set one pulse mode (one shot v.s. repetitive).
1519 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1520 * @param TIMx Timer instance
1521 * @param OnePulseMode This parameter can be one of the following values:
1522 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1523 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1524 * @retval None
1525 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1526 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1527 {
1528 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1529 }
1530
1531 /**
1532 * @brief Get actual one pulse mode.
1533 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1534 * @param TIMx Timer instance
1535 * @retval Returned value can be one of the following values:
1536 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1537 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1538 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1539 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1540 {
1541 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1542 }
1543
1544 /**
1545 * @brief Set the timer counter counting mode.
1546 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1547 * check whether or not the counter mode selection feature is supported
1548 * by a timer instance.
1549 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1550 * requires a timer reset to avoid unexpected direction
1551 * due to DIR bit readonly in center aligned mode.
1552 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1553 * CR1 CMS LL_TIM_SetCounterMode
1554 * @param TIMx Timer instance
1555 * @param CounterMode This parameter can be one of the following values:
1556 * @arg @ref LL_TIM_COUNTERMODE_UP
1557 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1558 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1559 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1560 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1561 * @retval None
1562 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1563 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1564 {
1565 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1566 }
1567
1568 /**
1569 * @brief Get actual counter mode.
1570 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1571 * check whether or not the counter mode selection feature is supported
1572 * by a timer instance.
1573 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1574 * CR1 CMS LL_TIM_GetCounterMode
1575 * @param TIMx Timer instance
1576 * @retval Returned value can be one of the following values:
1577 * @arg @ref LL_TIM_COUNTERMODE_UP
1578 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1579 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1580 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1581 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1582 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1583 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1584 {
1585 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1586 }
1587
1588 /**
1589 * @brief Enable auto-reload (ARR) preload.
1590 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1591 * @param TIMx Timer instance
1592 * @retval None
1593 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1594 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1595 {
1596 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1597 }
1598
1599 /**
1600 * @brief Disable auto-reload (ARR) preload.
1601 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1602 * @param TIMx Timer instance
1603 * @retval None
1604 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1605 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1606 {
1607 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1608 }
1609
1610 /**
1611 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1612 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1613 * @param TIMx Timer instance
1614 * @retval State of bit (1 or 0).
1615 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1616 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1617 {
1618 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1619 }
1620
1621 /**
1622 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1623 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1624 * whether or not the clock division feature is supported by the timer
1625 * instance.
1626 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1627 * @param TIMx Timer instance
1628 * @param ClockDivision This parameter can be one of the following values:
1629 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1630 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1631 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1632 * @retval None
1633 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1634 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1635 {
1636 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1637 }
1638
1639 /**
1640 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1641 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1642 * whether or not the clock division feature is supported by the timer
1643 * instance.
1644 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1645 * @param TIMx Timer instance
1646 * @retval Returned value can be one of the following values:
1647 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1648 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1649 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1650 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1651 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1652 {
1653 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1654 }
1655
1656 /**
1657 * @brief Set the counter value.
1658 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1659 * whether or not a timer instance supports a 32 bits counter.
1660 * @rmtoll CNT CNT LL_TIM_SetCounter
1661 * @param TIMx Timer instance
1662 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1663 * @retval None
1664 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1665 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1666 {
1667 WRITE_REG(TIMx->CNT, Counter);
1668 }
1669
1670 /**
1671 * @brief Get the counter value.
1672 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1673 * whether or not a timer instance supports a 32 bits counter.
1674 * @rmtoll CNT CNT LL_TIM_GetCounter
1675 * @param TIMx Timer instance
1676 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1677 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1678 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1679 {
1680 return (uint32_t)(READ_REG(TIMx->CNT));
1681 }
1682
1683 /**
1684 * @brief Get the current direction of the counter
1685 * @rmtoll CR1 DIR LL_TIM_GetDirection
1686 * @param TIMx Timer instance
1687 * @retval Returned value can be one of the following values:
1688 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1689 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1690 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1691 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1692 {
1693 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1694 }
1695
1696 /**
1697 * @brief Set the prescaler value.
1698 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1699 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1700 * prescaler ratio is taken into account at the next update event.
1701 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1702 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1703 * @param TIMx Timer instance
1704 * @param Prescaler between Min_Data=0 and Max_Data=65535
1705 * @retval None
1706 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1707 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1708 {
1709 WRITE_REG(TIMx->PSC, Prescaler);
1710 }
1711
1712 /**
1713 * @brief Get the prescaler value.
1714 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1715 * @param TIMx Timer instance
1716 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1717 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1718 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1719 {
1720 return (uint32_t)(READ_REG(TIMx->PSC));
1721 }
1722
1723 /**
1724 * @brief Set the auto-reload value.
1725 * @note The counter is blocked while the auto-reload value is null.
1726 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1727 * whether or not a timer instance supports a 32 bits counter.
1728 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1729 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1730 * @param TIMx Timer instance
1731 * @param AutoReload between Min_Data=0 and Max_Data=65535
1732 * @retval None
1733 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1734 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1735 {
1736 WRITE_REG(TIMx->ARR, AutoReload);
1737 }
1738
1739 /**
1740 * @brief Get the auto-reload value.
1741 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1742 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1743 * whether or not a timer instance supports a 32 bits counter.
1744 * @param TIMx Timer instance
1745 * @retval Auto-reload value
1746 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1747 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1748 {
1749 return (uint32_t)(READ_REG(TIMx->ARR));
1750 }
1751
1752 /**
1753 * @brief Set the repetition counter value.
1754 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1755 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1756 * whether or not a timer instance supports a repetition counter.
1757 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1758 * @param TIMx Timer instance
1759 * @param RepetitionCounter between Min_Data=0 and Max_Data=255
1760 * @retval None
1761 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1762 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1763 {
1764 WRITE_REG(TIMx->RCR, RepetitionCounter);
1765 }
1766
1767 /**
1768 * @brief Get the repetition counter value.
1769 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1770 * whether or not a timer instance supports a repetition counter.
1771 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1772 * @param TIMx Timer instance
1773 * @retval Repetition counter value
1774 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)1775 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1776 {
1777 return (uint32_t)(READ_REG(TIMx->RCR));
1778 }
1779
1780 /**
1781 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1782 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1783 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1784 * @param TIMx Timer instance
1785 * @retval None
1786 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1787 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1788 {
1789 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1790 }
1791
1792 /**
1793 * @brief Disable update interrupt flag (UIF) remapping.
1794 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1795 * @param TIMx Timer instance
1796 * @retval None
1797 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1798 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1799 {
1800 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1801 }
1802
1803 /**
1804 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1805 * @param Counter Counter value
1806 * @retval State of bit (1 or 0).
1807 */
LL_TIM_IsActiveUIFCPY(uint32_t Counter)1808 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
1809 {
1810 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1811 }
1812
1813 /**
1814 * @}
1815 */
1816
1817 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1818 * @{
1819 */
1820 /**
1821 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1822 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1823 * they are updated only when a commutation event (COM) occurs.
1824 * @note Only on channels that have a complementary output.
1825 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1826 * whether or not a timer instance is able to generate a commutation event.
1827 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1828 * @param TIMx Timer instance
1829 * @retval None
1830 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1831 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1832 {
1833 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1834 }
1835
1836 /**
1837 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1838 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1839 * whether or not a timer instance is able to generate a commutation event.
1840 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1841 * @param TIMx Timer instance
1842 * @retval None
1843 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1844 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1845 {
1846 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1847 }
1848
1849 /**
1850 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1851 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1852 * whether or not a timer instance is able to generate a commutation event.
1853 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1854 * @param TIMx Timer instance
1855 * @param CCUpdateSource This parameter can be one of the following values:
1856 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1857 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1858 * @retval None
1859 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1860 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1861 {
1862 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1863 }
1864
1865 /**
1866 * @brief Set the trigger of the capture/compare DMA request.
1867 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1868 * @param TIMx Timer instance
1869 * @param DMAReqTrigger This parameter can be one of the following values:
1870 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1871 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1872 * @retval None
1873 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1874 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1875 {
1876 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1877 }
1878
1879 /**
1880 * @brief Get actual trigger of the capture/compare DMA request.
1881 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1882 * @param TIMx Timer instance
1883 * @retval Returned value can be one of the following values:
1884 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1885 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1886 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1887 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1888 {
1889 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1890 }
1891
1892 /**
1893 * @brief Set the lock level to freeze the
1894 * configuration of several capture/compare parameters.
1895 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1896 * the lock mechanism is supported by a timer instance.
1897 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1898 * @param TIMx Timer instance
1899 * @param LockLevel This parameter can be one of the following values:
1900 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1901 * @arg @ref LL_TIM_LOCKLEVEL_1
1902 * @arg @ref LL_TIM_LOCKLEVEL_2
1903 * @arg @ref LL_TIM_LOCKLEVEL_3
1904 * @retval None
1905 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1906 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1907 {
1908 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1909 }
1910
1911 /**
1912 * @brief Enable capture/compare channels.
1913 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1914 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1915 * CCER CC2E LL_TIM_CC_EnableChannel\n
1916 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1917 * CCER CC3E LL_TIM_CC_EnableChannel\n
1918 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1919 * CCER CC4E LL_TIM_CC_EnableChannel\n
1920 * CCER CC5E LL_TIM_CC_EnableChannel\n
1921 * CCER CC6E LL_TIM_CC_EnableChannel
1922 * @param TIMx Timer instance
1923 * @param Channels This parameter can be a combination of the following values:
1924 * @arg @ref LL_TIM_CHANNEL_CH1
1925 * @arg @ref LL_TIM_CHANNEL_CH1N
1926 * @arg @ref LL_TIM_CHANNEL_CH2
1927 * @arg @ref LL_TIM_CHANNEL_CH2N
1928 * @arg @ref LL_TIM_CHANNEL_CH3
1929 * @arg @ref LL_TIM_CHANNEL_CH3N
1930 * @arg @ref LL_TIM_CHANNEL_CH4
1931 * @arg @ref LL_TIM_CHANNEL_CH5
1932 * @arg @ref LL_TIM_CHANNEL_CH6
1933 * @retval None
1934 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1935 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1936 {
1937 SET_BIT(TIMx->CCER, Channels);
1938 }
1939
1940 /**
1941 * @brief Disable capture/compare channels.
1942 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1943 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1944 * CCER CC2E LL_TIM_CC_DisableChannel\n
1945 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1946 * CCER CC3E LL_TIM_CC_DisableChannel\n
1947 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1948 * CCER CC4E LL_TIM_CC_DisableChannel\n
1949 * CCER CC5E LL_TIM_CC_DisableChannel\n
1950 * CCER CC6E LL_TIM_CC_DisableChannel
1951 * @param TIMx Timer instance
1952 * @param Channels This parameter can be a combination of the following values:
1953 * @arg @ref LL_TIM_CHANNEL_CH1
1954 * @arg @ref LL_TIM_CHANNEL_CH1N
1955 * @arg @ref LL_TIM_CHANNEL_CH2
1956 * @arg @ref LL_TIM_CHANNEL_CH2N
1957 * @arg @ref LL_TIM_CHANNEL_CH3
1958 * @arg @ref LL_TIM_CHANNEL_CH3N
1959 * @arg @ref LL_TIM_CHANNEL_CH4
1960 * @arg @ref LL_TIM_CHANNEL_CH5
1961 * @arg @ref LL_TIM_CHANNEL_CH6
1962 * @retval None
1963 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1964 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1965 {
1966 CLEAR_BIT(TIMx->CCER, Channels);
1967 }
1968
1969 /**
1970 * @brief Indicate whether channel(s) is(are) enabled.
1971 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1972 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1973 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1974 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1975 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1976 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1977 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1978 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1979 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1980 * @param TIMx Timer instance
1981 * @param Channels This parameter can be a combination of the following values:
1982 * @arg @ref LL_TIM_CHANNEL_CH1
1983 * @arg @ref LL_TIM_CHANNEL_CH1N
1984 * @arg @ref LL_TIM_CHANNEL_CH2
1985 * @arg @ref LL_TIM_CHANNEL_CH2N
1986 * @arg @ref LL_TIM_CHANNEL_CH3
1987 * @arg @ref LL_TIM_CHANNEL_CH3N
1988 * @arg @ref LL_TIM_CHANNEL_CH4
1989 * @arg @ref LL_TIM_CHANNEL_CH5
1990 * @arg @ref LL_TIM_CHANNEL_CH6
1991 * @retval State of bit (1 or 0).
1992 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1993 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1994 {
1995 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1996 }
1997
1998 /**
1999 * @}
2000 */
2001
2002 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2003 * @{
2004 */
2005 /**
2006 * @brief Configure an output channel.
2007 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2008 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2009 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2010 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2011 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2012 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2013 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2014 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2015 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2016 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2017 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2018 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2019 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2020 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2021 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2022 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2023 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2024 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2025 * @param TIMx Timer instance
2026 * @param Channel This parameter can be one of the following values:
2027 * @arg @ref LL_TIM_CHANNEL_CH1
2028 * @arg @ref LL_TIM_CHANNEL_CH2
2029 * @arg @ref LL_TIM_CHANNEL_CH3
2030 * @arg @ref LL_TIM_CHANNEL_CH4
2031 * @arg @ref LL_TIM_CHANNEL_CH5
2032 * @arg @ref LL_TIM_CHANNEL_CH6
2033 * @param Configuration This parameter must be a combination of all the following values:
2034 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2035 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2036 * @retval None
2037 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2038 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2039 {
2040 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2041 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2042 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2043 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2044 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2045 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2046 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2047 }
2048
2049 /**
2050 * @brief Define the behavior of the output reference signal OCxREF from which
2051 * OCx and OCxN (when relevant) are derived.
2052 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2053 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2054 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2055 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2056 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2057 * CCMR3 OC6M LL_TIM_OC_SetMode
2058 * @param TIMx Timer instance
2059 * @param Channel This parameter can be one of the following values:
2060 * @arg @ref LL_TIM_CHANNEL_CH1
2061 * @arg @ref LL_TIM_CHANNEL_CH2
2062 * @arg @ref LL_TIM_CHANNEL_CH3
2063 * @arg @ref LL_TIM_CHANNEL_CH4
2064 * @arg @ref LL_TIM_CHANNEL_CH5
2065 * @arg @ref LL_TIM_CHANNEL_CH6
2066 * @param Mode This parameter can be one of the following values:
2067 * @arg @ref LL_TIM_OCMODE_FROZEN
2068 * @arg @ref LL_TIM_OCMODE_ACTIVE
2069 * @arg @ref LL_TIM_OCMODE_INACTIVE
2070 * @arg @ref LL_TIM_OCMODE_TOGGLE
2071 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2072 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2073 * @arg @ref LL_TIM_OCMODE_PWM1
2074 * @arg @ref LL_TIM_OCMODE_PWM2
2075 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2076 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2077 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2078 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2079 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2080 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2081 * @retval None
2082 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2083 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2084 {
2085 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2086 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2087 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2088 }
2089
2090 /**
2091 * @brief Get the output compare mode of an output channel.
2092 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2093 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2094 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2095 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2096 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2097 * CCMR3 OC6M LL_TIM_OC_GetMode
2098 * @param TIMx Timer instance
2099 * @param Channel This parameter can be one of the following values:
2100 * @arg @ref LL_TIM_CHANNEL_CH1
2101 * @arg @ref LL_TIM_CHANNEL_CH2
2102 * @arg @ref LL_TIM_CHANNEL_CH3
2103 * @arg @ref LL_TIM_CHANNEL_CH4
2104 * @arg @ref LL_TIM_CHANNEL_CH5
2105 * @arg @ref LL_TIM_CHANNEL_CH6
2106 * @retval Returned value can be one of the following values:
2107 * @arg @ref LL_TIM_OCMODE_FROZEN
2108 * @arg @ref LL_TIM_OCMODE_ACTIVE
2109 * @arg @ref LL_TIM_OCMODE_INACTIVE
2110 * @arg @ref LL_TIM_OCMODE_TOGGLE
2111 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2112 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2113 * @arg @ref LL_TIM_OCMODE_PWM1
2114 * @arg @ref LL_TIM_OCMODE_PWM2
2115 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2116 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2117 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2118 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2119 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2120 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2121 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)2122 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2123 {
2124 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2125 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2126 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2127 }
2128
2129 /**
2130 * @brief Set the polarity of an output channel.
2131 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2132 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2133 * CCER CC2P LL_TIM_OC_SetPolarity\n
2134 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2135 * CCER CC3P LL_TIM_OC_SetPolarity\n
2136 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2137 * CCER CC4P LL_TIM_OC_SetPolarity\n
2138 * CCER CC5P LL_TIM_OC_SetPolarity\n
2139 * CCER CC6P LL_TIM_OC_SetPolarity
2140 * @param TIMx Timer instance
2141 * @param Channel This parameter can be one of the following values:
2142 * @arg @ref LL_TIM_CHANNEL_CH1
2143 * @arg @ref LL_TIM_CHANNEL_CH1N
2144 * @arg @ref LL_TIM_CHANNEL_CH2
2145 * @arg @ref LL_TIM_CHANNEL_CH2N
2146 * @arg @ref LL_TIM_CHANNEL_CH3
2147 * @arg @ref LL_TIM_CHANNEL_CH3N
2148 * @arg @ref LL_TIM_CHANNEL_CH4
2149 * @arg @ref LL_TIM_CHANNEL_CH5
2150 * @arg @ref LL_TIM_CHANNEL_CH6
2151 * @param Polarity This parameter can be one of the following values:
2152 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2153 * @arg @ref LL_TIM_OCPOLARITY_LOW
2154 * @retval None
2155 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2156 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2157 {
2158 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2159 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2160 }
2161
2162 /**
2163 * @brief Get the polarity of an output channel.
2164 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2165 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2166 * CCER CC2P LL_TIM_OC_GetPolarity\n
2167 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2168 * CCER CC3P LL_TIM_OC_GetPolarity\n
2169 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2170 * CCER CC4P LL_TIM_OC_GetPolarity\n
2171 * CCER CC5P LL_TIM_OC_GetPolarity\n
2172 * CCER CC6P LL_TIM_OC_GetPolarity
2173 * @param TIMx Timer instance
2174 * @param Channel This parameter can be one of the following values:
2175 * @arg @ref LL_TIM_CHANNEL_CH1
2176 * @arg @ref LL_TIM_CHANNEL_CH1N
2177 * @arg @ref LL_TIM_CHANNEL_CH2
2178 * @arg @ref LL_TIM_CHANNEL_CH2N
2179 * @arg @ref LL_TIM_CHANNEL_CH3
2180 * @arg @ref LL_TIM_CHANNEL_CH3N
2181 * @arg @ref LL_TIM_CHANNEL_CH4
2182 * @arg @ref LL_TIM_CHANNEL_CH5
2183 * @arg @ref LL_TIM_CHANNEL_CH6
2184 * @retval Returned value can be one of the following values:
2185 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2186 * @arg @ref LL_TIM_OCPOLARITY_LOW
2187 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2188 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2189 {
2190 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2191 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2192 }
2193
2194 /**
2195 * @brief Set the IDLE state of an output channel
2196 * @note This function is significant only for the timer instances
2197 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2198 * can be used to check whether or not a timer instance provides
2199 * a break input.
2200 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2201 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2202 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2203 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2204 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2205 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2206 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2207 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2208 * CR2 OIS6 LL_TIM_OC_SetIdleState
2209 * @param TIMx Timer instance
2210 * @param Channel This parameter can be one of the following values:
2211 * @arg @ref LL_TIM_CHANNEL_CH1
2212 * @arg @ref LL_TIM_CHANNEL_CH1N
2213 * @arg @ref LL_TIM_CHANNEL_CH2
2214 * @arg @ref LL_TIM_CHANNEL_CH2N
2215 * @arg @ref LL_TIM_CHANNEL_CH3
2216 * @arg @ref LL_TIM_CHANNEL_CH3N
2217 * @arg @ref LL_TIM_CHANNEL_CH4
2218 * @arg @ref LL_TIM_CHANNEL_CH5
2219 * @arg @ref LL_TIM_CHANNEL_CH6
2220 * @param IdleState This parameter can be one of the following values:
2221 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2222 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2223 * @retval None
2224 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2225 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2226 {
2227 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2228 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2229 }
2230
2231 /**
2232 * @brief Get the IDLE state of an output channel
2233 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2234 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2235 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2236 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2237 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2238 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2239 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2240 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2241 * CR2 OIS6 LL_TIM_OC_GetIdleState
2242 * @param TIMx Timer instance
2243 * @param Channel This parameter can be one of the following values:
2244 * @arg @ref LL_TIM_CHANNEL_CH1
2245 * @arg @ref LL_TIM_CHANNEL_CH1N
2246 * @arg @ref LL_TIM_CHANNEL_CH2
2247 * @arg @ref LL_TIM_CHANNEL_CH2N
2248 * @arg @ref LL_TIM_CHANNEL_CH3
2249 * @arg @ref LL_TIM_CHANNEL_CH3N
2250 * @arg @ref LL_TIM_CHANNEL_CH4
2251 * @arg @ref LL_TIM_CHANNEL_CH5
2252 * @arg @ref LL_TIM_CHANNEL_CH6
2253 * @retval Returned value can be one of the following values:
2254 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2255 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2256 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)2257 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2258 {
2259 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2260 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2261 }
2262
2263 /**
2264 * @brief Enable fast mode for the output channel.
2265 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2266 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2267 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2268 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2269 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2270 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2271 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2272 * @param TIMx Timer instance
2273 * @param Channel This parameter can be one of the following values:
2274 * @arg @ref LL_TIM_CHANNEL_CH1
2275 * @arg @ref LL_TIM_CHANNEL_CH2
2276 * @arg @ref LL_TIM_CHANNEL_CH3
2277 * @arg @ref LL_TIM_CHANNEL_CH4
2278 * @arg @ref LL_TIM_CHANNEL_CH5
2279 * @arg @ref LL_TIM_CHANNEL_CH6
2280 * @retval None
2281 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2282 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2283 {
2284 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2285 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2286 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2287
2288 }
2289
2290 /**
2291 * @brief Disable fast mode for the output channel.
2292 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2293 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2294 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2295 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2296 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2297 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2298 * @param TIMx Timer instance
2299 * @param Channel This parameter can be one of the following values:
2300 * @arg @ref LL_TIM_CHANNEL_CH1
2301 * @arg @ref LL_TIM_CHANNEL_CH2
2302 * @arg @ref LL_TIM_CHANNEL_CH3
2303 * @arg @ref LL_TIM_CHANNEL_CH4
2304 * @arg @ref LL_TIM_CHANNEL_CH5
2305 * @arg @ref LL_TIM_CHANNEL_CH6
2306 * @retval None
2307 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2308 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2309 {
2310 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2311 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2312 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2313
2314 }
2315
2316 /**
2317 * @brief Indicates whether fast mode is enabled for the output channel.
2318 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2319 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2320 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2321 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2322 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2323 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2324 * @param TIMx Timer instance
2325 * @param Channel This parameter can be one of the following values:
2326 * @arg @ref LL_TIM_CHANNEL_CH1
2327 * @arg @ref LL_TIM_CHANNEL_CH2
2328 * @arg @ref LL_TIM_CHANNEL_CH3
2329 * @arg @ref LL_TIM_CHANNEL_CH4
2330 * @arg @ref LL_TIM_CHANNEL_CH5
2331 * @arg @ref LL_TIM_CHANNEL_CH6
2332 * @retval State of bit (1 or 0).
2333 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2334 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2335 {
2336 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2337 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2338 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2339 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2340 }
2341
2342 /**
2343 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2344 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2345 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2346 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2347 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2348 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2349 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2350 * @param TIMx Timer instance
2351 * @param Channel This parameter can be one of the following values:
2352 * @arg @ref LL_TIM_CHANNEL_CH1
2353 * @arg @ref LL_TIM_CHANNEL_CH2
2354 * @arg @ref LL_TIM_CHANNEL_CH3
2355 * @arg @ref LL_TIM_CHANNEL_CH4
2356 * @arg @ref LL_TIM_CHANNEL_CH5
2357 * @arg @ref LL_TIM_CHANNEL_CH6
2358 * @retval None
2359 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2360 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2361 {
2362 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2363 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2364 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2365 }
2366
2367 /**
2368 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2369 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2370 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2371 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2372 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2373 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2374 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2375 * @param TIMx Timer instance
2376 * @param Channel This parameter can be one of the following values:
2377 * @arg @ref LL_TIM_CHANNEL_CH1
2378 * @arg @ref LL_TIM_CHANNEL_CH2
2379 * @arg @ref LL_TIM_CHANNEL_CH3
2380 * @arg @ref LL_TIM_CHANNEL_CH4
2381 * @arg @ref LL_TIM_CHANNEL_CH5
2382 * @arg @ref LL_TIM_CHANNEL_CH6
2383 * @retval None
2384 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2385 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2386 {
2387 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2388 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2389 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2390 }
2391
2392 /**
2393 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2394 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2395 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2396 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2397 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2398 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2399 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2400 * @param TIMx Timer instance
2401 * @param Channel This parameter can be one of the following values:
2402 * @arg @ref LL_TIM_CHANNEL_CH1
2403 * @arg @ref LL_TIM_CHANNEL_CH2
2404 * @arg @ref LL_TIM_CHANNEL_CH3
2405 * @arg @ref LL_TIM_CHANNEL_CH4
2406 * @arg @ref LL_TIM_CHANNEL_CH5
2407 * @arg @ref LL_TIM_CHANNEL_CH6
2408 * @retval State of bit (1 or 0).
2409 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2410 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2411 {
2412 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2413 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2414 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2415 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2416 }
2417
2418 /**
2419 * @brief Enable clearing the output channel on an external event.
2420 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2421 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2422 * or not a timer instance can clear the OCxREF signal on an external event.
2423 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2424 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2425 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2426 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2427 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2428 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2429 * @param TIMx Timer instance
2430 * @param Channel This parameter can be one of the following values:
2431 * @arg @ref LL_TIM_CHANNEL_CH1
2432 * @arg @ref LL_TIM_CHANNEL_CH2
2433 * @arg @ref LL_TIM_CHANNEL_CH3
2434 * @arg @ref LL_TIM_CHANNEL_CH4
2435 * @arg @ref LL_TIM_CHANNEL_CH5
2436 * @arg @ref LL_TIM_CHANNEL_CH6
2437 * @retval None
2438 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2439 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2440 {
2441 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2442 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2443 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2444 }
2445
2446 /**
2447 * @brief Disable clearing the output channel on an external event.
2448 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2449 * or not a timer instance can clear the OCxREF signal on an external event.
2450 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2451 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2452 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2453 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2454 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2455 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2456 * @param TIMx Timer instance
2457 * @param Channel This parameter can be one of the following values:
2458 * @arg @ref LL_TIM_CHANNEL_CH1
2459 * @arg @ref LL_TIM_CHANNEL_CH2
2460 * @arg @ref LL_TIM_CHANNEL_CH3
2461 * @arg @ref LL_TIM_CHANNEL_CH4
2462 * @arg @ref LL_TIM_CHANNEL_CH5
2463 * @arg @ref LL_TIM_CHANNEL_CH6
2464 * @retval None
2465 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2466 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2467 {
2468 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2469 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2470 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2471 }
2472
2473 /**
2474 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2475 * @note This function enables clearing the output channel on an external event.
2476 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2477 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2478 * or not a timer instance can clear the OCxREF signal on an external event.
2479 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2480 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2481 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2482 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2483 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2484 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2485 * @param TIMx Timer instance
2486 * @param Channel This parameter can be one of the following values:
2487 * @arg @ref LL_TIM_CHANNEL_CH1
2488 * @arg @ref LL_TIM_CHANNEL_CH2
2489 * @arg @ref LL_TIM_CHANNEL_CH3
2490 * @arg @ref LL_TIM_CHANNEL_CH4
2491 * @arg @ref LL_TIM_CHANNEL_CH5
2492 * @arg @ref LL_TIM_CHANNEL_CH6
2493 * @retval State of bit (1 or 0).
2494 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2495 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2496 {
2497 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2498 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2499 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2500 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2501 }
2502
2503 /**
2504 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2505 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2506 * dead-time insertion feature is supported by a timer instance.
2507 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2508 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2509 * @param TIMx Timer instance
2510 * @param DeadTime between Min_Data=0 and Max_Data=255
2511 * @retval None
2512 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2513 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2514 {
2515 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2516 }
2517
2518 /**
2519 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2520 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2521 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2522 * whether or not a timer instance supports a 32 bits counter.
2523 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2524 * output channel 1 is supported by a timer instance.
2525 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2526 * @param TIMx Timer instance
2527 * @param CompareValue between Min_Data=0 and Max_Data=65535
2528 * @retval None
2529 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2530 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2531 {
2532 WRITE_REG(TIMx->CCR1, CompareValue);
2533 }
2534
2535 /**
2536 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2537 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2538 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2539 * whether or not a timer instance supports a 32 bits counter.
2540 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2541 * output channel 2 is supported by a timer instance.
2542 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2543 * @param TIMx Timer instance
2544 * @param CompareValue between Min_Data=0 and Max_Data=65535
2545 * @retval None
2546 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2547 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2548 {
2549 WRITE_REG(TIMx->CCR2, CompareValue);
2550 }
2551
2552 /**
2553 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2554 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2555 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2556 * whether or not a timer instance supports a 32 bits counter.
2557 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2558 * output channel is supported by a timer instance.
2559 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2560 * @param TIMx Timer instance
2561 * @param CompareValue between Min_Data=0 and Max_Data=65535
2562 * @retval None
2563 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2564 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2565 {
2566 WRITE_REG(TIMx->CCR3, CompareValue);
2567 }
2568
2569 /**
2570 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2571 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2572 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2573 * whether or not a timer instance supports a 32 bits counter.
2574 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2575 * output channel 4 is supported by a timer instance.
2576 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2577 * @param TIMx Timer instance
2578 * @param CompareValue between Min_Data=0 and Max_Data=65535
2579 * @retval None
2580 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2581 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2582 {
2583 WRITE_REG(TIMx->CCR4, CompareValue);
2584 }
2585
2586 /**
2587 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2588 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2589 * output channel 5 is supported by a timer instance.
2590 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2591 * @param TIMx Timer instance
2592 * @param CompareValue between Min_Data=0 and Max_Data=65535
2593 * @retval None
2594 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2595 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2596 {
2597 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2598 }
2599
2600 /**
2601 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2602 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2603 * output channel 6 is supported by a timer instance.
2604 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2605 * @param TIMx Timer instance
2606 * @param CompareValue between Min_Data=0 and Max_Data=65535
2607 * @retval None
2608 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2609 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2610 {
2611 WRITE_REG(TIMx->CCR6, CompareValue);
2612 }
2613
2614 /**
2615 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2616 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2617 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2618 * whether or not a timer instance supports a 32 bits counter.
2619 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2620 * output channel 1 is supported by a timer instance.
2621 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2622 * @param TIMx Timer instance
2623 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2624 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)2625 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2626 {
2627 return (uint32_t)(READ_REG(TIMx->CCR1));
2628 }
2629
2630 /**
2631 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2632 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2633 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2634 * whether or not a timer instance supports a 32 bits counter.
2635 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2636 * output channel 2 is supported by a timer instance.
2637 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2638 * @param TIMx Timer instance
2639 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2640 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)2641 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2642 {
2643 return (uint32_t)(READ_REG(TIMx->CCR2));
2644 }
2645
2646 /**
2647 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2648 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2649 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2650 * whether or not a timer instance supports a 32 bits counter.
2651 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2652 * output channel 3 is supported by a timer instance.
2653 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2654 * @param TIMx Timer instance
2655 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2656 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)2657 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2658 {
2659 return (uint32_t)(READ_REG(TIMx->CCR3));
2660 }
2661
2662 /**
2663 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2664 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2665 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2666 * whether or not a timer instance supports a 32 bits counter.
2667 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2668 * output channel 4 is supported by a timer instance.
2669 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2670 * @param TIMx Timer instance
2671 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2672 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)2673 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2674 {
2675 return (uint32_t)(READ_REG(TIMx->CCR4));
2676 }
2677
2678 /**
2679 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2680 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2681 * output channel 5 is supported by a timer instance.
2682 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2683 * @param TIMx Timer instance
2684 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2685 */
LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)2686 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2687 {
2688 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2689 }
2690
2691 /**
2692 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2693 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2694 * output channel 6 is supported by a timer instance.
2695 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2696 * @param TIMx Timer instance
2697 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2698 */
LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)2699 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2700 {
2701 return (uint32_t)(READ_REG(TIMx->CCR6));
2702 }
2703
2704 /**
2705 * @brief Select on which reference signal the OC5REF is combined to.
2706 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2707 * whether or not a timer instance supports the combined 3-phase PWM mode.
2708 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2709 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2710 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2711 * @param TIMx Timer instance
2712 * @param GroupCH5 This parameter can be a combination of the following values:
2713 * @arg @ref LL_TIM_GROUPCH5_NONE
2714 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2715 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2716 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2717 * @retval None
2718 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2719 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2720 {
2721 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2722 }
2723
2724 /**
2725 * @}
2726 */
2727
2728 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2729 * @{
2730 */
2731 /**
2732 * @brief Configure input channel.
2733 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2734 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2735 * CCMR1 IC1F LL_TIM_IC_Config\n
2736 * CCMR1 CC2S LL_TIM_IC_Config\n
2737 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2738 * CCMR1 IC2F LL_TIM_IC_Config\n
2739 * CCMR2 CC3S LL_TIM_IC_Config\n
2740 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2741 * CCMR2 IC3F LL_TIM_IC_Config\n
2742 * CCMR2 CC4S LL_TIM_IC_Config\n
2743 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2744 * CCMR2 IC4F LL_TIM_IC_Config\n
2745 * CCER CC1P LL_TIM_IC_Config\n
2746 * CCER CC1NP LL_TIM_IC_Config\n
2747 * CCER CC2P LL_TIM_IC_Config\n
2748 * CCER CC2NP LL_TIM_IC_Config\n
2749 * CCER CC3P LL_TIM_IC_Config\n
2750 * CCER CC3NP LL_TIM_IC_Config\n
2751 * CCER CC4P LL_TIM_IC_Config\n
2752 * CCER CC4NP LL_TIM_IC_Config
2753 * @param TIMx Timer instance
2754 * @param Channel This parameter can be one of the following values:
2755 * @arg @ref LL_TIM_CHANNEL_CH1
2756 * @arg @ref LL_TIM_CHANNEL_CH2
2757 * @arg @ref LL_TIM_CHANNEL_CH3
2758 * @arg @ref LL_TIM_CHANNEL_CH4
2759 * @param Configuration This parameter must be a combination of all the following values:
2760 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2761 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2762 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2763 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2764 * @retval None
2765 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2766 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2767 {
2768 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2769 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2770 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2771 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2772 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2773 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2774 }
2775
2776 /**
2777 * @brief Set the active input.
2778 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2779 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2780 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2781 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2782 * @param TIMx Timer instance
2783 * @param Channel This parameter can be one of the following values:
2784 * @arg @ref LL_TIM_CHANNEL_CH1
2785 * @arg @ref LL_TIM_CHANNEL_CH2
2786 * @arg @ref LL_TIM_CHANNEL_CH3
2787 * @arg @ref LL_TIM_CHANNEL_CH4
2788 * @param ICActiveInput This parameter can be one of the following values:
2789 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2790 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2791 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2792 * @retval None
2793 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2794 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2795 {
2796 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2797 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2798 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2799 }
2800
2801 /**
2802 * @brief Get the current active input.
2803 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2804 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2805 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2806 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2807 * @param TIMx Timer instance
2808 * @param Channel This parameter can be one of the following values:
2809 * @arg @ref LL_TIM_CHANNEL_CH1
2810 * @arg @ref LL_TIM_CHANNEL_CH2
2811 * @arg @ref LL_TIM_CHANNEL_CH3
2812 * @arg @ref LL_TIM_CHANNEL_CH4
2813 * @retval Returned value can be one of the following values:
2814 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2815 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2816 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2817 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)2818 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2819 {
2820 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2821 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2822 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2823 }
2824
2825 /**
2826 * @brief Set the prescaler of input channel.
2827 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2828 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2829 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2830 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2831 * @param TIMx Timer instance
2832 * @param Channel This parameter can be one of the following values:
2833 * @arg @ref LL_TIM_CHANNEL_CH1
2834 * @arg @ref LL_TIM_CHANNEL_CH2
2835 * @arg @ref LL_TIM_CHANNEL_CH3
2836 * @arg @ref LL_TIM_CHANNEL_CH4
2837 * @param ICPrescaler This parameter can be one of the following values:
2838 * @arg @ref LL_TIM_ICPSC_DIV1
2839 * @arg @ref LL_TIM_ICPSC_DIV2
2840 * @arg @ref LL_TIM_ICPSC_DIV4
2841 * @arg @ref LL_TIM_ICPSC_DIV8
2842 * @retval None
2843 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2844 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2845 {
2846 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2847 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2848 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2849 }
2850
2851 /**
2852 * @brief Get the current prescaler value acting on an input channel.
2853 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2854 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2855 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2856 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2857 * @param TIMx Timer instance
2858 * @param Channel This parameter can be one of the following values:
2859 * @arg @ref LL_TIM_CHANNEL_CH1
2860 * @arg @ref LL_TIM_CHANNEL_CH2
2861 * @arg @ref LL_TIM_CHANNEL_CH3
2862 * @arg @ref LL_TIM_CHANNEL_CH4
2863 * @retval Returned value can be one of the following values:
2864 * @arg @ref LL_TIM_ICPSC_DIV1
2865 * @arg @ref LL_TIM_ICPSC_DIV2
2866 * @arg @ref LL_TIM_ICPSC_DIV4
2867 * @arg @ref LL_TIM_ICPSC_DIV8
2868 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)2869 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2870 {
2871 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2872 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2873 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2874 }
2875
2876 /**
2877 * @brief Set the input filter duration.
2878 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2879 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2880 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2881 * CCMR2 IC4F LL_TIM_IC_SetFilter
2882 * @param TIMx Timer instance
2883 * @param Channel This parameter can be one of the following values:
2884 * @arg @ref LL_TIM_CHANNEL_CH1
2885 * @arg @ref LL_TIM_CHANNEL_CH2
2886 * @arg @ref LL_TIM_CHANNEL_CH3
2887 * @arg @ref LL_TIM_CHANNEL_CH4
2888 * @param ICFilter This parameter can be one of the following values:
2889 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2890 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2891 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2892 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2893 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2894 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2895 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2896 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2897 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2898 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2899 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2900 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2901 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2902 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2903 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2904 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2905 * @retval None
2906 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2907 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2908 {
2909 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2910 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2911 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2912 }
2913
2914 /**
2915 * @brief Get the input filter duration.
2916 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2917 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2918 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2919 * CCMR2 IC4F LL_TIM_IC_GetFilter
2920 * @param TIMx Timer instance
2921 * @param Channel This parameter can be one of the following values:
2922 * @arg @ref LL_TIM_CHANNEL_CH1
2923 * @arg @ref LL_TIM_CHANNEL_CH2
2924 * @arg @ref LL_TIM_CHANNEL_CH3
2925 * @arg @ref LL_TIM_CHANNEL_CH4
2926 * @retval Returned value can be one of the following values:
2927 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2928 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2929 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2930 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2931 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2932 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2933 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2934 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2935 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2936 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2937 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2938 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2939 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2940 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2941 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2942 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2943 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2944 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2945 {
2946 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2947 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2948 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2949 }
2950
2951 /**
2952 * @brief Set the input channel polarity.
2953 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2954 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2955 * CCER CC2P LL_TIM_IC_SetPolarity\n
2956 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2957 * CCER CC3P LL_TIM_IC_SetPolarity\n
2958 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2959 * CCER CC4P LL_TIM_IC_SetPolarity\n
2960 * CCER CC4NP LL_TIM_IC_SetPolarity
2961 * @param TIMx Timer instance
2962 * @param Channel This parameter can be one of the following values:
2963 * @arg @ref LL_TIM_CHANNEL_CH1
2964 * @arg @ref LL_TIM_CHANNEL_CH2
2965 * @arg @ref LL_TIM_CHANNEL_CH3
2966 * @arg @ref LL_TIM_CHANNEL_CH4
2967 * @param ICPolarity This parameter can be one of the following values:
2968 * @arg @ref LL_TIM_IC_POLARITY_RISING
2969 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2970 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2971 * @retval None
2972 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2973 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2974 {
2975 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2976 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2977 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2978 }
2979
2980 /**
2981 * @brief Get the current input channel polarity.
2982 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2983 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2984 * CCER CC2P LL_TIM_IC_GetPolarity\n
2985 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2986 * CCER CC3P LL_TIM_IC_GetPolarity\n
2987 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2988 * CCER CC4P LL_TIM_IC_GetPolarity\n
2989 * CCER CC4NP LL_TIM_IC_GetPolarity
2990 * @param TIMx Timer instance
2991 * @param Channel This parameter can be one of the following values:
2992 * @arg @ref LL_TIM_CHANNEL_CH1
2993 * @arg @ref LL_TIM_CHANNEL_CH2
2994 * @arg @ref LL_TIM_CHANNEL_CH3
2995 * @arg @ref LL_TIM_CHANNEL_CH4
2996 * @retval Returned value can be one of the following values:
2997 * @arg @ref LL_TIM_IC_POLARITY_RISING
2998 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2999 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3000 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)3001 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
3002 {
3003 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3004 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3005 SHIFT_TAB_CCxP[iChannel]);
3006 }
3007
3008 /**
3009 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3010 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3011 * a timer instance provides an XOR input.
3012 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3013 * @param TIMx Timer instance
3014 * @retval None
3015 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3016 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3017 {
3018 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3019 }
3020
3021 /**
3022 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3023 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3024 * a timer instance provides an XOR input.
3025 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3026 * @param TIMx Timer instance
3027 * @retval None
3028 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3029 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3030 {
3031 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3032 }
3033
3034 /**
3035 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3036 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3037 * a timer instance provides an XOR input.
3038 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3039 * @param TIMx Timer instance
3040 * @retval State of bit (1 or 0).
3041 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3042 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3043 {
3044 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3045 }
3046
3047 /**
3048 * @brief Get captured value for input channel 1.
3049 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3050 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3051 * whether or not a timer instance supports a 32 bits counter.
3052 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3053 * input channel 1 is supported by a timer instance.
3054 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3055 * @param TIMx Timer instance
3056 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3057 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)3058 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3059 {
3060 return (uint32_t)(READ_REG(TIMx->CCR1));
3061 }
3062
3063 /**
3064 * @brief Get captured value for input channel 2.
3065 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3066 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3067 * whether or not a timer instance supports a 32 bits counter.
3068 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3069 * input channel 2 is supported by a timer instance.
3070 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3071 * @param TIMx Timer instance
3072 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3073 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)3074 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3075 {
3076 return (uint32_t)(READ_REG(TIMx->CCR2));
3077 }
3078
3079 /**
3080 * @brief Get captured value for input channel 3.
3081 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3082 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3083 * whether or not a timer instance supports a 32 bits counter.
3084 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3085 * input channel 3 is supported by a timer instance.
3086 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3087 * @param TIMx Timer instance
3088 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3089 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)3090 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3091 {
3092 return (uint32_t)(READ_REG(TIMx->CCR3));
3093 }
3094
3095 /**
3096 * @brief Get captured value for input channel 4.
3097 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3098 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3099 * whether or not a timer instance supports a 32 bits counter.
3100 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3101 * input channel 4 is supported by a timer instance.
3102 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3103 * @param TIMx Timer instance
3104 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3105 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)3106 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3107 {
3108 return (uint32_t)(READ_REG(TIMx->CCR4));
3109 }
3110
3111 /**
3112 * @}
3113 */
3114
3115 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3116 * @{
3117 */
3118 /**
3119 * @brief Enable external clock mode 2.
3120 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3121 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3122 * whether or not a timer instance supports external clock mode2.
3123 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3124 * @param TIMx Timer instance
3125 * @retval None
3126 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3127 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3128 {
3129 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3130 }
3131
3132 /**
3133 * @brief Disable external clock mode 2.
3134 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3135 * whether or not a timer instance supports external clock mode2.
3136 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3137 * @param TIMx Timer instance
3138 * @retval None
3139 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3140 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3141 {
3142 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3143 }
3144
3145 /**
3146 * @brief Indicate whether external clock mode 2 is enabled.
3147 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3148 * whether or not a timer instance supports external clock mode2.
3149 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3150 * @param TIMx Timer instance
3151 * @retval State of bit (1 or 0).
3152 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)3153 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3154 {
3155 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3156 }
3157
3158 /**
3159 * @brief Set the clock source of the counter clock.
3160 * @note when selected clock source is external clock mode 1, the timer input
3161 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3162 * function. This timer input must be configured by calling
3163 * the @ref LL_TIM_IC_Config() function.
3164 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3165 * whether or not a timer instance supports external clock mode1.
3166 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3167 * whether or not a timer instance supports external clock mode2.
3168 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3169 * SMCR ECE LL_TIM_SetClockSource
3170 * @param TIMx Timer instance
3171 * @param ClockSource This parameter can be one of the following values:
3172 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3173 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3174 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3175 * @retval None
3176 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3177 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3178 {
3179 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3180 }
3181
3182 /**
3183 * @brief Set the encoder interface mode.
3184 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3185 * whether or not a timer instance supports the encoder mode.
3186 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3187 * @param TIMx Timer instance
3188 * @param EncoderMode This parameter can be one of the following values:
3189 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3190 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3191 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3192 * @retval None
3193 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3194 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3195 {
3196 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3197 }
3198
3199 /**
3200 * @}
3201 */
3202
3203 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3204 * @{
3205 */
3206 /**
3207 * @brief Set the trigger output (TRGO) used for timer synchronization .
3208 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3209 * whether or not a timer instance can operate as a master timer.
3210 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3211 * @param TIMx Timer instance
3212 * @param TimerSynchronization This parameter can be one of the following values:
3213 * @arg @ref LL_TIM_TRGO_RESET
3214 * @arg @ref LL_TIM_TRGO_ENABLE
3215 * @arg @ref LL_TIM_TRGO_UPDATE
3216 * @arg @ref LL_TIM_TRGO_CC1IF
3217 * @arg @ref LL_TIM_TRGO_OC1REF
3218 * @arg @ref LL_TIM_TRGO_OC2REF
3219 * @arg @ref LL_TIM_TRGO_OC3REF
3220 * @arg @ref LL_TIM_TRGO_OC4REF
3221 * @retval None
3222 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3223 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3224 {
3225 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3226 }
3227
3228 /**
3229 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3230 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3231 * whether or not a timer instance can be used for ADC synchronization.
3232 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3233 * @param TIMx Timer Instance
3234 * @param ADCSynchronization This parameter can be one of the following values:
3235 * @arg @ref LL_TIM_TRGO2_RESET
3236 * @arg @ref LL_TIM_TRGO2_ENABLE
3237 * @arg @ref LL_TIM_TRGO2_UPDATE
3238 * @arg @ref LL_TIM_TRGO2_CC1F
3239 * @arg @ref LL_TIM_TRGO2_OC1
3240 * @arg @ref LL_TIM_TRGO2_OC2
3241 * @arg @ref LL_TIM_TRGO2_OC3
3242 * @arg @ref LL_TIM_TRGO2_OC4
3243 * @arg @ref LL_TIM_TRGO2_OC5
3244 * @arg @ref LL_TIM_TRGO2_OC6
3245 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3246 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3247 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3248 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3249 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3250 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3251 * @retval None
3252 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3253 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3254 {
3255 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3256 }
3257
3258 /**
3259 * @brief Set the synchronization mode of a slave timer.
3260 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3261 * a timer instance can operate as a slave timer.
3262 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3263 * @param TIMx Timer instance
3264 * @param SlaveMode This parameter can be one of the following values:
3265 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3266 * @arg @ref LL_TIM_SLAVEMODE_RESET
3267 * @arg @ref LL_TIM_SLAVEMODE_GATED
3268 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3269 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3270 * @retval None
3271 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3272 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3273 {
3274 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3275 }
3276
3277 /**
3278 * @brief Set the selects the trigger input to be used to synchronize the counter.
3279 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3280 * a timer instance can operate as a slave timer.
3281 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3282 * @param TIMx Timer instance
3283 * @param TriggerInput This parameter can be one of the following values:
3284 * @arg @ref LL_TIM_TS_ITR0
3285 * @arg @ref LL_TIM_TS_ITR1
3286 * @arg @ref LL_TIM_TS_ITR2
3287 * @arg @ref LL_TIM_TS_ITR3
3288 * @arg @ref LL_TIM_TS_TI1F_ED
3289 * @arg @ref LL_TIM_TS_TI1FP1
3290 * @arg @ref LL_TIM_TS_TI2FP2
3291 * @arg @ref LL_TIM_TS_ETRF
3292 * @retval None
3293 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3294 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3295 {
3296 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3297 }
3298
3299 /**
3300 * @brief Enable the Master/Slave mode.
3301 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3302 * a timer instance can operate as a slave timer.
3303 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3304 * @param TIMx Timer instance
3305 * @retval None
3306 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3307 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3308 {
3309 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3310 }
3311
3312 /**
3313 * @brief Disable the Master/Slave mode.
3314 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3315 * a timer instance can operate as a slave timer.
3316 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3317 * @param TIMx Timer instance
3318 * @retval None
3319 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3320 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3321 {
3322 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3323 }
3324
3325 /**
3326 * @brief Indicates whether the Master/Slave mode is enabled.
3327 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3328 * a timer instance can operate as a slave timer.
3329 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3330 * @param TIMx Timer instance
3331 * @retval State of bit (1 or 0).
3332 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)3333 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3334 {
3335 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3336 }
3337
3338 /**
3339 * @brief Configure the external trigger (ETR) input.
3340 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3341 * a timer instance provides an external trigger input.
3342 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3343 * SMCR ETPS LL_TIM_ConfigETR\n
3344 * SMCR ETF LL_TIM_ConfigETR
3345 * @param TIMx Timer instance
3346 * @param ETRPolarity This parameter can be one of the following values:
3347 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3348 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3349 * @param ETRPrescaler This parameter can be one of the following values:
3350 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3351 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3352 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3353 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3354 * @param ETRFilter This parameter can be one of the following values:
3355 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3356 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3357 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3358 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3359 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3360 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3361 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3362 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3363 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3364 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3365 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3366 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3367 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3368 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3369 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3370 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3371 * @retval None
3372 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3373 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3374 uint32_t ETRFilter)
3375 {
3376 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3377 }
3378
3379 /**
3380 * @brief Select the external trigger (ETR) input source.
3381 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3382 * not a timer instance supports ETR source selection.
3383 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
3384 * @param TIMx Timer instance
3385 * @param ETRSource This parameter can be one of the following values:
3386 * @arg @ref LL_TIM_ETRSOURCE_LEGACY
3387 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3388 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3389 * @retval None
3390 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3391 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3392 {
3393
3394 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
3395 }
3396
3397 /**
3398 * @}
3399 */
3400
3401 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3402 * @{
3403 */
3404 /**
3405 * @brief Enable the break function.
3406 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3407 * a timer instance provides a break input.
3408 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3409 * @param TIMx Timer instance
3410 * @retval None
3411 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3412 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3413 {
3414 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3415 }
3416
3417 /**
3418 * @brief Disable the break function.
3419 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3420 * @param TIMx Timer instance
3421 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3422 * a timer instance provides a break input.
3423 * @retval None
3424 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3425 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3426 {
3427 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3428 }
3429
3430 /**
3431 * @brief Configure the break input.
3432 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3433 * a timer instance provides a break input.
3434 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3435 * BDTR BKF LL_TIM_ConfigBRK
3436 * @param TIMx Timer instance
3437 * @param BreakPolarity This parameter can be one of the following values:
3438 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3439 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3440 * @param BreakFilter This parameter can be one of the following values:
3441 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3442 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3443 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3444 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3445 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3446 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3447 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3448 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3449 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3450 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3451 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3452 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3453 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3454 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3455 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3456 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3457 * @retval None
3458 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3459 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3460 uint32_t BreakFilter)
3461 {
3462 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3463 }
3464
3465 /**
3466 * @brief Enable the break 2 function.
3467 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3468 * a timer instance provides a second break input.
3469 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3470 * @param TIMx Timer instance
3471 * @retval None
3472 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3473 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3474 {
3475 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3476 }
3477
3478 /**
3479 * @brief Disable the break 2 function.
3480 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3481 * a timer instance provides a second break input.
3482 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3483 * @param TIMx Timer instance
3484 * @retval None
3485 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3486 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3487 {
3488 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3489 }
3490
3491 /**
3492 * @brief Configure the break 2 input.
3493 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3494 * a timer instance provides a second break input.
3495 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3496 * BDTR BK2F LL_TIM_ConfigBRK2
3497 * @param TIMx Timer instance
3498 * @param Break2Polarity This parameter can be one of the following values:
3499 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3500 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3501 * @param Break2Filter This parameter can be one of the following values:
3502 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3503 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3504 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3505 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3506 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3507 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3508 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3509 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3510 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3511 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3512 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3513 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3514 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3515 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3516 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3517 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3518 * @retval None
3519 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3520 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3521 {
3522 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3523 }
3524
3525 /**
3526 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3527 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3528 * a timer instance provides a break input.
3529 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3530 * BDTR OSSR LL_TIM_SetOffStates
3531 * @param TIMx Timer instance
3532 * @param OffStateIdle This parameter can be one of the following values:
3533 * @arg @ref LL_TIM_OSSI_DISABLE
3534 * @arg @ref LL_TIM_OSSI_ENABLE
3535 * @param OffStateRun This parameter can be one of the following values:
3536 * @arg @ref LL_TIM_OSSR_DISABLE
3537 * @arg @ref LL_TIM_OSSR_ENABLE
3538 * @retval None
3539 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3540 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3541 {
3542 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3543 }
3544
3545 /**
3546 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3547 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3548 * a timer instance provides a break input.
3549 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3550 * @param TIMx Timer instance
3551 * @retval None
3552 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3553 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3554 {
3555 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3556 }
3557
3558 /**
3559 * @brief Disable automatic output (MOE can be set only by software).
3560 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3561 * a timer instance provides a break input.
3562 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3563 * @param TIMx Timer instance
3564 * @retval None
3565 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3566 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3567 {
3568 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3569 }
3570
3571 /**
3572 * @brief Indicate whether automatic output is enabled.
3573 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3574 * a timer instance provides a break input.
3575 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3576 * @param TIMx Timer instance
3577 * @retval State of bit (1 or 0).
3578 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)3579 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3580 {
3581 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3582 }
3583
3584 /**
3585 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3586 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3587 * software and is reset in case of break or break2 event
3588 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3589 * a timer instance provides a break input.
3590 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3591 * @param TIMx Timer instance
3592 * @retval None
3593 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3594 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3595 {
3596 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3597 }
3598
3599 /**
3600 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3601 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3602 * software and is reset in case of break or break2 event.
3603 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3604 * a timer instance provides a break input.
3605 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3606 * @param TIMx Timer instance
3607 * @retval None
3608 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3609 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3610 {
3611 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3612 }
3613
3614 /**
3615 * @brief Indicates whether outputs are enabled.
3616 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3617 * a timer instance provides a break input.
3618 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3619 * @param TIMx Timer instance
3620 * @retval State of bit (1 or 0).
3621 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)3622 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3623 {
3624 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3625 }
3626
3627 /**
3628 * @brief Enable the signals connected to the designated timer break input.
3629 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3630 * or not a timer instance allows for break input selection.
3631 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
3632 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
3633 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
3634 * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3635 * OR3 BK2INE LL_TIM_EnableBreakInputSource\n
3636 * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3637 * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3638 * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3639 * @param TIMx Timer instance
3640 * @param BreakInput This parameter can be one of the following values:
3641 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3642 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3643 * @param Source This parameter can be one of the following values:
3644 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3645 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3646 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3647 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3648 * @retval None
3649 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3650 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3651 {
3652 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3653 SET_BIT(*pReg, Source);
3654 }
3655
3656 /**
3657 * @brief Disable the signals connected to the designated timer break input.
3658 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3659 * or not a timer instance allows for break input selection.
3660 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
3661 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
3662 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
3663 * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3664 * OR3 BK2INE LL_TIM_DisableBreakInputSource\n
3665 * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3666 * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3667 * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3668 * @param TIMx Timer instance
3669 * @param BreakInput This parameter can be one of the following values:
3670 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3671 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3672 * @param Source This parameter can be one of the following values:
3673 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3674 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3675 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3676 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3677 * @retval None
3678 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3679 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3680 {
3681 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3682 CLEAR_BIT(*pReg, Source);
3683 }
3684
3685 /**
3686 * @brief Set the polarity of the break signal for the timer break input.
3687 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3688 * or not a timer instance allows for break input selection.
3689 * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3690 * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3691 * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3692 * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3693 * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3694 * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3695 * @param TIMx Timer instance
3696 * @param BreakInput This parameter can be one of the following values:
3697 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3698 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3699 * @param Source This parameter can be one of the following values:
3700 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3701 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3702 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3703 * @param Polarity This parameter can be one of the following values:
3704 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3705 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3706 * @retval None
3707 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3708 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3709 uint32_t Polarity)
3710 {
3711 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3712 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3713 }
3714 /**
3715 * @}
3716 */
3717
3718 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3719 * @{
3720 */
3721 /**
3722 * @brief Configures the timer DMA burst feature.
3723 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3724 * not a timer instance supports the DMA burst mode.
3725 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3726 * DCR DBA LL_TIM_ConfigDMABurst
3727 * @param TIMx Timer instance
3728 * @param DMABurstBaseAddress This parameter can be one of the following values:
3729 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3730 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3731 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3732 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3733 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3734 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3735 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3736 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3737 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3738 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3739 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3740 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3741 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3742 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3743 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3744 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3745 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3746 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3747 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3748 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3749 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3750 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3751 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
3752 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
3753 * @param DMABurstLength This parameter can be one of the following values:
3754 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3755 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3756 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3757 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3758 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3759 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3760 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3761 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3762 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3763 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3764 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3765 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3766 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3767 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3768 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3769 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3770 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3771 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3772 * @retval None
3773 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3774 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3775 {
3776 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3777 }
3778
3779 /**
3780 * @}
3781 */
3782
3783 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3784 * @{
3785 */
3786 /**
3787 * @brief Remap TIM inputs (input channel, internal/external triggers).
3788 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3789 * a some timer inputs can be remapped.
3790 @if STM32L486xx
3791 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3792 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3793 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3794 * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
3795 * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3796 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
3797 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3798 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3799 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
3800 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
3801 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3802 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3803 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3804 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap
3805 @endif
3806 @if STM32L443xx
3807 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3808 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3809 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3810 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3811 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3812 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
3813 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3814 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3815 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3816 @endif
3817 * @param TIMx Timer instance
3818 * @param Remap Remap param depends on the TIMx. Description available only
3819 * in CHM version of the User Manual (not in .pdf).
3820 * Otherwise see Reference Manual description of OR registers.
3821 *
3822 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3823 *
3824 @if STM32L486xx
3825 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3826 *
3827 * . . ADC1_RMP can be one of the following values
3828 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3829 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3830 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
3831 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
3832 *
3833 * . . ADC3_RMP can be one of the following values
3834 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
3835 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
3836 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
3837 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
3838 *
3839 * . . TI1_RMP can be one of the following values
3840 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3841 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3842 *
3843 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3844 *
3845 * ITR1_RMP can be one of the following values
3846 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3847 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3848 *
3849 * . . ETR1_RMP can be one of the following values
3850 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3851 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3852 *
3853 * . . TI4_RMP can be one of the following values
3854 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3855 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
3856 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
3857 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
3858 *
3859 * TIM3: one of the following values
3860 *
3861 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3862 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
3863 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
3864 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
3865 *
3866 * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3867 *
3868 * . . ADC1_RMP can be one of the following values
3869 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
3870 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
3871 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
3872 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
3873 *
3874 * . . ADC3_RMP can be one of the following values
3875 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
3876 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
3877 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
3878 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
3879 *
3880 * . . TI1_RMP can be one of the following values
3881 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
3882 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
3883 *
3884 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
3885 *
3886 * . . TI1_RMP can be one of the following values
3887 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3888 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
3889 *
3890 * . . ENCODER_MODE can be one of the following values
3891 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
3892 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
3893 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
3894 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
3895 *
3896 * TIM16: one of the following values
3897 *
3898 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3899 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3900 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3901 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3902 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
3903 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
3904 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
3905 *
3906 * TIM17: one of the following values
3907 *
3908 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3909 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3910 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3911 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3912 @endif
3913 @if STM32L443xx
3914 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3915 *
3916 * . . ADC1_RMP can be one of the following values
3917 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3918 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3919 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
3920 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
3921 *
3922 * . . TI1_RMP can be one of the following values
3923 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3924 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3925 *
3926 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3927 *
3928 * ITR1_RMP can be one of the following values
3929 * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
3930 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
3931 *
3932 * . . ETR1_RMP can be one of the following values
3933 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3934 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3935 *
3936 * . . TI4_RMP can be one of the following values
3937 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3938 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
3939 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
3940 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
3941 *
3942 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
3943 *
3944 * . . TI1_RMP can be one of the following values
3945 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3946 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
3947 *
3948 * . . ENCODER_MODE can be one of the following values
3949 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
3950 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
3951 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
3952 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
3953 *
3954 * TIM16: one of the following values
3955 *
3956 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3957 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3958 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3959 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3960 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
3961 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
3962 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
3963 @endif
3964 * @retval None
3965 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3966 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3967 {
3968 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
3969 }
3970
3971 /**
3972 * @}
3973 */
3974
3975 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3976 * @{
3977 */
3978 /**
3979 * @brief Set the OCREF clear input source
3980 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3981 * @note This function can only be used in Output compare and PWM modes.
3982 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3983 * @param TIMx Timer instance
3984 * @param OCRefClearInputSource This parameter can be one of the following values:
3985 * @arg @ref LL_TIM_OCREF_CLR_INT_NC
3986 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3987 * @retval None
3988 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3989 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3990 {
3991 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
3992 }
3993 /**
3994 * @}
3995 */
3996
3997 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3998 * @{
3999 */
4000 /**
4001 * @brief Clear the update interrupt flag (UIF).
4002 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4003 * @param TIMx Timer instance
4004 * @retval None
4005 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4006 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4007 {
4008 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4009 }
4010
4011 /**
4012 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4013 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4014 * @param TIMx Timer instance
4015 * @retval State of bit (1 or 0).
4016 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)4017 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
4018 {
4019 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4020 }
4021
4022 /**
4023 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4024 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4025 * @param TIMx Timer instance
4026 * @retval None
4027 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4028 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4029 {
4030 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4031 }
4032
4033 /**
4034 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4035 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4036 * @param TIMx Timer instance
4037 * @retval State of bit (1 or 0).
4038 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)4039 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
4040 {
4041 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4042 }
4043
4044 /**
4045 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4046 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4047 * @param TIMx Timer instance
4048 * @retval None
4049 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4050 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4051 {
4052 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4053 }
4054
4055 /**
4056 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4057 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4058 * @param TIMx Timer instance
4059 * @retval State of bit (1 or 0).
4060 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)4061 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
4062 {
4063 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4064 }
4065
4066 /**
4067 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4068 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4069 * @param TIMx Timer instance
4070 * @retval None
4071 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4072 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4073 {
4074 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4075 }
4076
4077 /**
4078 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4079 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4080 * @param TIMx Timer instance
4081 * @retval State of bit (1 or 0).
4082 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)4083 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
4084 {
4085 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4086 }
4087
4088 /**
4089 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4090 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4091 * @param TIMx Timer instance
4092 * @retval None
4093 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4094 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4095 {
4096 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4097 }
4098
4099 /**
4100 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4101 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4102 * @param TIMx Timer instance
4103 * @retval State of bit (1 or 0).
4104 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)4105 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
4106 {
4107 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4108 }
4109
4110 /**
4111 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4112 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4113 * @param TIMx Timer instance
4114 * @retval None
4115 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4116 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4117 {
4118 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4119 }
4120
4121 /**
4122 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4123 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4124 * @param TIMx Timer instance
4125 * @retval State of bit (1 or 0).
4126 */
LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)4127 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
4128 {
4129 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4130 }
4131
4132 /**
4133 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4134 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4135 * @param TIMx Timer instance
4136 * @retval None
4137 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4138 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4139 {
4140 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4141 }
4142
4143 /**
4144 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4145 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4146 * @param TIMx Timer instance
4147 * @retval State of bit (1 or 0).
4148 */
LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)4149 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
4150 {
4151 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4152 }
4153
4154 /**
4155 * @brief Clear the commutation interrupt flag (COMIF).
4156 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4157 * @param TIMx Timer instance
4158 * @retval None
4159 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4160 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4161 {
4162 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4163 }
4164
4165 /**
4166 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4167 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4168 * @param TIMx Timer instance
4169 * @retval State of bit (1 or 0).
4170 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)4171 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
4172 {
4173 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4174 }
4175
4176 /**
4177 * @brief Clear the trigger interrupt flag (TIF).
4178 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4179 * @param TIMx Timer instance
4180 * @retval None
4181 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4182 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4183 {
4184 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4185 }
4186
4187 /**
4188 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4189 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4190 * @param TIMx Timer instance
4191 * @retval State of bit (1 or 0).
4192 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)4193 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
4194 {
4195 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4196 }
4197
4198 /**
4199 * @brief Clear the break interrupt flag (BIF).
4200 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4201 * @param TIMx Timer instance
4202 * @retval None
4203 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4204 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4205 {
4206 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4207 }
4208
4209 /**
4210 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4211 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4212 * @param TIMx Timer instance
4213 * @retval State of bit (1 or 0).
4214 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)4215 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
4216 {
4217 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4218 }
4219
4220 /**
4221 * @brief Clear the break 2 interrupt flag (B2IF).
4222 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4223 * @param TIMx Timer instance
4224 * @retval None
4225 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4226 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4227 {
4228 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4229 }
4230
4231 /**
4232 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4233 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4234 * @param TIMx Timer instance
4235 * @retval State of bit (1 or 0).
4236 */
LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)4237 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
4238 {
4239 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4240 }
4241
4242 /**
4243 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4244 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4245 * @param TIMx Timer instance
4246 * @retval None
4247 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4248 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4249 {
4250 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4251 }
4252
4253 /**
4254 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
4255 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4256 * @param TIMx Timer instance
4257 * @retval State of bit (1 or 0).
4258 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)4259 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
4260 {
4261 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4262 }
4263
4264 /**
4265 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4266 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4267 * @param TIMx Timer instance
4268 * @retval None
4269 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4270 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4271 {
4272 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4273 }
4274
4275 /**
4276 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
4277 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4278 * @param TIMx Timer instance
4279 * @retval State of bit (1 or 0).
4280 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)4281 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
4282 {
4283 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4284 }
4285
4286 /**
4287 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4288 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4289 * @param TIMx Timer instance
4290 * @retval None
4291 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4292 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4293 {
4294 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4295 }
4296
4297 /**
4298 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
4299 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4300 * @param TIMx Timer instance
4301 * @retval State of bit (1 or 0).
4302 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)4303 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
4304 {
4305 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4306 }
4307
4308 /**
4309 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4310 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4311 * @param TIMx Timer instance
4312 * @retval None
4313 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4314 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4315 {
4316 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4317 }
4318
4319 /**
4320 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
4321 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4322 * @param TIMx Timer instance
4323 * @retval State of bit (1 or 0).
4324 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)4325 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
4326 {
4327 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4328 }
4329
4330 /**
4331 * @brief Clear the system break interrupt flag (SBIF).
4332 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4333 * @param TIMx Timer instance
4334 * @retval None
4335 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4336 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4337 {
4338 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4339 }
4340
4341 /**
4342 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4343 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4344 * @param TIMx Timer instance
4345 * @retval State of bit (1 or 0).
4346 */
LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)4347 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
4348 {
4349 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4350 }
4351
4352 /**
4353 * @}
4354 */
4355
4356 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4357 * @{
4358 */
4359 /**
4360 * @brief Enable update interrupt (UIE).
4361 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4362 * @param TIMx Timer instance
4363 * @retval None
4364 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4365 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4366 {
4367 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4368 }
4369
4370 /**
4371 * @brief Disable update interrupt (UIE).
4372 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4373 * @param TIMx Timer instance
4374 * @retval None
4375 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4376 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4377 {
4378 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4379 }
4380
4381 /**
4382 * @brief Indicates whether the update interrupt (UIE) is enabled.
4383 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4384 * @param TIMx Timer instance
4385 * @retval State of bit (1 or 0).
4386 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)4387 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4388 {
4389 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4390 }
4391
4392 /**
4393 * @brief Enable capture/compare 1 interrupt (CC1IE).
4394 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4395 * @param TIMx Timer instance
4396 * @retval None
4397 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4398 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4399 {
4400 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4401 }
4402
4403 /**
4404 * @brief Disable capture/compare 1 interrupt (CC1IE).
4405 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4406 * @param TIMx Timer instance
4407 * @retval None
4408 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4409 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4410 {
4411 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4412 }
4413
4414 /**
4415 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4416 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4417 * @param TIMx Timer instance
4418 * @retval State of bit (1 or 0).
4419 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)4420 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4421 {
4422 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4423 }
4424
4425 /**
4426 * @brief Enable capture/compare 2 interrupt (CC2IE).
4427 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4428 * @param TIMx Timer instance
4429 * @retval None
4430 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4431 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4432 {
4433 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4434 }
4435
4436 /**
4437 * @brief Disable capture/compare 2 interrupt (CC2IE).
4438 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4439 * @param TIMx Timer instance
4440 * @retval None
4441 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4442 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4443 {
4444 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4445 }
4446
4447 /**
4448 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4449 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4450 * @param TIMx Timer instance
4451 * @retval State of bit (1 or 0).
4452 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)4453 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4454 {
4455 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4456 }
4457
4458 /**
4459 * @brief Enable capture/compare 3 interrupt (CC3IE).
4460 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4461 * @param TIMx Timer instance
4462 * @retval None
4463 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4464 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4465 {
4466 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4467 }
4468
4469 /**
4470 * @brief Disable capture/compare 3 interrupt (CC3IE).
4471 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4472 * @param TIMx Timer instance
4473 * @retval None
4474 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4475 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4476 {
4477 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4478 }
4479
4480 /**
4481 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4482 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4483 * @param TIMx Timer instance
4484 * @retval State of bit (1 or 0).
4485 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)4486 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4487 {
4488 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4489 }
4490
4491 /**
4492 * @brief Enable capture/compare 4 interrupt (CC4IE).
4493 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4494 * @param TIMx Timer instance
4495 * @retval None
4496 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4497 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4498 {
4499 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4500 }
4501
4502 /**
4503 * @brief Disable capture/compare 4 interrupt (CC4IE).
4504 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4505 * @param TIMx Timer instance
4506 * @retval None
4507 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4508 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4509 {
4510 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4511 }
4512
4513 /**
4514 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4515 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4516 * @param TIMx Timer instance
4517 * @retval State of bit (1 or 0).
4518 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)4519 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4520 {
4521 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4522 }
4523
4524 /**
4525 * @brief Enable commutation interrupt (COMIE).
4526 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4527 * @param TIMx Timer instance
4528 * @retval None
4529 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4530 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4531 {
4532 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4533 }
4534
4535 /**
4536 * @brief Disable commutation interrupt (COMIE).
4537 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4538 * @param TIMx Timer instance
4539 * @retval None
4540 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4541 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4542 {
4543 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4544 }
4545
4546 /**
4547 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4548 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4549 * @param TIMx Timer instance
4550 * @retval State of bit (1 or 0).
4551 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)4552 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4553 {
4554 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4555 }
4556
4557 /**
4558 * @brief Enable trigger interrupt (TIE).
4559 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4560 * @param TIMx Timer instance
4561 * @retval None
4562 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4563 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4564 {
4565 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4566 }
4567
4568 /**
4569 * @brief Disable trigger interrupt (TIE).
4570 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4571 * @param TIMx Timer instance
4572 * @retval None
4573 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4574 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4575 {
4576 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4577 }
4578
4579 /**
4580 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4581 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4582 * @param TIMx Timer instance
4583 * @retval State of bit (1 or 0).
4584 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)4585 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4586 {
4587 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4588 }
4589
4590 /**
4591 * @brief Enable break interrupt (BIE).
4592 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4593 * @param TIMx Timer instance
4594 * @retval None
4595 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4596 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4597 {
4598 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4599 }
4600
4601 /**
4602 * @brief Disable break interrupt (BIE).
4603 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4604 * @param TIMx Timer instance
4605 * @retval None
4606 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4607 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4608 {
4609 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4610 }
4611
4612 /**
4613 * @brief Indicates whether the break interrupt (BIE) is enabled.
4614 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4615 * @param TIMx Timer instance
4616 * @retval State of bit (1 or 0).
4617 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)4618 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4619 {
4620 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4621 }
4622
4623 /**
4624 * @}
4625 */
4626
4627 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4628 * @{
4629 */
4630 /**
4631 * @brief Enable update DMA request (UDE).
4632 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4633 * @param TIMx Timer instance
4634 * @retval None
4635 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4636 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4637 {
4638 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4639 }
4640
4641 /**
4642 * @brief Disable update DMA request (UDE).
4643 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4644 * @param TIMx Timer instance
4645 * @retval None
4646 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4647 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4648 {
4649 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4650 }
4651
4652 /**
4653 * @brief Indicates whether the update DMA request (UDE) is enabled.
4654 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4655 * @param TIMx Timer instance
4656 * @retval State of bit (1 or 0).
4657 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)4658 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4659 {
4660 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4661 }
4662
4663 /**
4664 * @brief Enable capture/compare 1 DMA request (CC1DE).
4665 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4666 * @param TIMx Timer instance
4667 * @retval None
4668 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4669 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4670 {
4671 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4672 }
4673
4674 /**
4675 * @brief Disable capture/compare 1 DMA request (CC1DE).
4676 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4677 * @param TIMx Timer instance
4678 * @retval None
4679 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4680 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4681 {
4682 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4683 }
4684
4685 /**
4686 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4687 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4688 * @param TIMx Timer instance
4689 * @retval State of bit (1 or 0).
4690 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)4691 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4692 {
4693 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4694 }
4695
4696 /**
4697 * @brief Enable capture/compare 2 DMA request (CC2DE).
4698 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4699 * @param TIMx Timer instance
4700 * @retval None
4701 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4702 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4703 {
4704 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4705 }
4706
4707 /**
4708 * @brief Disable capture/compare 2 DMA request (CC2DE).
4709 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4710 * @param TIMx Timer instance
4711 * @retval None
4712 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4713 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4714 {
4715 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4716 }
4717
4718 /**
4719 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4720 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4721 * @param TIMx Timer instance
4722 * @retval State of bit (1 or 0).
4723 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)4724 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4725 {
4726 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4727 }
4728
4729 /**
4730 * @brief Enable capture/compare 3 DMA request (CC3DE).
4731 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4732 * @param TIMx Timer instance
4733 * @retval None
4734 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4735 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4736 {
4737 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4738 }
4739
4740 /**
4741 * @brief Disable capture/compare 3 DMA request (CC3DE).
4742 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4743 * @param TIMx Timer instance
4744 * @retval None
4745 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4746 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4747 {
4748 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4749 }
4750
4751 /**
4752 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4753 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4754 * @param TIMx Timer instance
4755 * @retval State of bit (1 or 0).
4756 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)4757 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4758 {
4759 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4760 }
4761
4762 /**
4763 * @brief Enable capture/compare 4 DMA request (CC4DE).
4764 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4765 * @param TIMx Timer instance
4766 * @retval None
4767 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4768 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4769 {
4770 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4771 }
4772
4773 /**
4774 * @brief Disable capture/compare 4 DMA request (CC4DE).
4775 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4776 * @param TIMx Timer instance
4777 * @retval None
4778 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4779 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4780 {
4781 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4782 }
4783
4784 /**
4785 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4786 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4787 * @param TIMx Timer instance
4788 * @retval State of bit (1 or 0).
4789 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)4790 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4791 {
4792 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4793 }
4794
4795 /**
4796 * @brief Enable commutation DMA request (COMDE).
4797 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4798 * @param TIMx Timer instance
4799 * @retval None
4800 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4801 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4802 {
4803 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4804 }
4805
4806 /**
4807 * @brief Disable commutation DMA request (COMDE).
4808 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4809 * @param TIMx Timer instance
4810 * @retval None
4811 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4812 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4813 {
4814 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4815 }
4816
4817 /**
4818 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4819 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4820 * @param TIMx Timer instance
4821 * @retval State of bit (1 or 0).
4822 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)4823 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4824 {
4825 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4826 }
4827
4828 /**
4829 * @brief Enable trigger interrupt (TDE).
4830 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4831 * @param TIMx Timer instance
4832 * @retval None
4833 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4834 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4835 {
4836 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4837 }
4838
4839 /**
4840 * @brief Disable trigger interrupt (TDE).
4841 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4842 * @param TIMx Timer instance
4843 * @retval None
4844 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4845 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4846 {
4847 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4848 }
4849
4850 /**
4851 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4852 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4853 * @param TIMx Timer instance
4854 * @retval State of bit (1 or 0).
4855 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)4856 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4857 {
4858 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4859 }
4860
4861 /**
4862 * @}
4863 */
4864
4865 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4866 * @{
4867 */
4868 /**
4869 * @brief Generate an update event.
4870 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4871 * @param TIMx Timer instance
4872 * @retval None
4873 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4874 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4875 {
4876 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4877 }
4878
4879 /**
4880 * @brief Generate Capture/Compare 1 event.
4881 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4882 * @param TIMx Timer instance
4883 * @retval None
4884 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4885 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4886 {
4887 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4888 }
4889
4890 /**
4891 * @brief Generate Capture/Compare 2 event.
4892 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4893 * @param TIMx Timer instance
4894 * @retval None
4895 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4896 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4897 {
4898 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4899 }
4900
4901 /**
4902 * @brief Generate Capture/Compare 3 event.
4903 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4904 * @param TIMx Timer instance
4905 * @retval None
4906 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4907 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4908 {
4909 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4910 }
4911
4912 /**
4913 * @brief Generate Capture/Compare 4 event.
4914 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4915 * @param TIMx Timer instance
4916 * @retval None
4917 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4918 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4919 {
4920 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4921 }
4922
4923 /**
4924 * @brief Generate commutation event.
4925 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4926 * @param TIMx Timer instance
4927 * @retval None
4928 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4929 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4930 {
4931 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4932 }
4933
4934 /**
4935 * @brief Generate trigger event.
4936 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4937 * @param TIMx Timer instance
4938 * @retval None
4939 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4940 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4941 {
4942 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4943 }
4944
4945 /**
4946 * @brief Generate break event.
4947 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4948 * @param TIMx Timer instance
4949 * @retval None
4950 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4951 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4952 {
4953 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4954 }
4955
4956 /**
4957 * @brief Generate break 2 event.
4958 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4959 * @param TIMx Timer instance
4960 * @retval None
4961 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4962 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4963 {
4964 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4965 }
4966
4967 /**
4968 * @}
4969 */
4970
4971 #if defined(USE_FULL_LL_DRIVER)
4972 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4973 * @{
4974 */
4975
4976 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4977 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4978 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4979 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4980 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4981 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4982 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4983 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4984 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4985 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4986 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4987 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4988 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4989 /**
4990 * @}
4991 */
4992 #endif /* USE_FULL_LL_DRIVER */
4993
4994 /**
4995 * @}
4996 */
4997
4998 /**
4999 * @}
5000 */
5001
5002 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
5003
5004 /**
5005 * @}
5006 */
5007
5008 #ifdef __cplusplus
5009 }
5010 #endif
5011
5012 #endif /* __STM32L4xx_LL_TIM_H */
5013 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
5014