1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16 (+) Access to VREFBUF registers
17
18 @endverbatim
19 ******************************************************************************
20 * @attention
21 *
22 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
23 * All rights reserved.</center></h2>
24 *
25 * This software component is licensed by ST under BSD 3-Clause license,
26 * the "License"; You may not use this file except in compliance with the
27 * License. You may obtain a copy of the License at:
28 * opensource.org/licenses/BSD-3-Clause
29 *
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef STM32L4xx_LL_SYSTEM_H
35 #define STM32L4xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32l4xx.h"
43
44 /** @addtogroup STM32L4xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /**
63 * @brief Power-down in Run mode Flash key
64 */
65 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
66 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
67 to unlock the RUN_PD bit in FLASH_ACR */
68
69 /**
70 * @}
71 */
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /* Exported types ------------------------------------------------------------*/
76 /* Exported constants --------------------------------------------------------*/
77 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
78 * @{
79 */
80
81 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
82 * @{
83 */
84 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
85 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
86 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
87 #if defined(FMC_Bank1_R)
88 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
89 #endif /* FMC_Bank1_R */
90 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
91 /**
92 * @}
93 */
94
95 #if defined(SYSCFG_MEMRMP_FB_MODE)
96 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
97 * @{
98 */
99 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
100 and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
101 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
102 and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
103 /**
104 * @}
105 */
106
107 #endif /* SYSCFG_MEMRMP_FB_MODE */
108 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
109 * @{
110 */
111 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
112 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
113 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
115 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
116 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
117 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
118 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
119 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
120 #if defined(I2C2)
121 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
122 #endif /* I2C2 */
123 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
124 #if defined(I2C4)
125 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
126 #endif /* I2C4 */
127 /**
128 * @}
129 */
130
131 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
132 * @{
133 */
134 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
135 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
136 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
137 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
138 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
139 #if defined(GPIOF)
140 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
141 #endif /* GPIOF */
142 #if defined(GPIOG)
143 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
144 #endif /* GPIOG */
145 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
146 #if defined(GPIOI)
147 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
148 #endif /* GPIOI */
149 /**
150 * @}
151 */
152
153 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
154 * @{
155 */
156 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
157 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
158 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
159 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
160 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
161 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
162 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
163 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
164 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
165 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
166 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
167 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
168 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
169 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
170 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
171 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
172 /**
173 * @}
174 */
175
176 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
177 * @{
178 */
179 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
180 with Break Input of TIM1/8/15/16/17 */
181 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
182 with TIM1/8/15/16/17 Break Input
183 and also the PVDE and PLS bits of the Power Control Interface */
184 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
185 with Break Input of TIM1/8/15/16/17 */
186 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
187 with Break Input of TIM1/15/16/17 */
188 /**
189 * @}
190 */
191
192 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
193 * @{
194 */
195 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
196 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
197 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
198 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
199 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
200 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
201 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
202 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
203 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
204 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
205 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
206 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
207 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
208 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
209 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
210 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
211 #if defined(SYSCFG_SWPR_PAGE31)
212 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
213 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
214 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
215 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
216 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
217 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
218 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
219 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
220 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
221 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
222 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
223 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
224 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
225 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
226 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
227 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
228 #endif /* SYSCFG_SWPR_PAGE31 */
229 #if defined(SYSCFG_SWPR2_PAGE63)
230 #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
231 #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
232 #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
233 #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
234 #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
235 #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
236 #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
237 #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
238 #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
239 #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
240 #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
241 #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
242 #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
243 #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
244 #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
245 #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
246 #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
247 #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
248 #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
249 #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
250 #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
251 #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
252 #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
253 #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
254 #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
255 #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
256 #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
257 #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
258 #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
259 #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
260 #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
261 #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
262 #endif /* SYSCFG_SWPR2_PAGE63 */
263 /**
264 * @}
265 */
266
267 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
268 * @{
269 */
270 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
271 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
272 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
273 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
274 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
275 /**
276 * @}
277 */
278
279 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
280 * @{
281 */
282 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
283 #if defined(TIM3)
284 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
285 #endif /* TIM3 */
286 #if defined(TIM4)
287 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
288 #endif /* TIM4 */
289 #if defined(TIM5)
290 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
291 #endif /* TIM5 */
292 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
293 #if defined(TIM7)
294 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
295 #endif /* TIM7 */
296 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
297 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
298 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
299 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
300 #if defined(I2C2)
301 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
302 #endif /* I2C2 */
303 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
304 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/
305 #if defined(CAN2)
306 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /*!< The bxCAN2 receive registers are frozen*/
307 #endif /* CAN2 */
308 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
309 /**
310 * @}
311 */
312
313 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
314 * @{
315 */
316 #if defined(I2C4)
317 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
318 #endif /* I2C4 */
319 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
320 /**
321 * @}
322 */
323
324 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
325 * @{
326 */
327 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
328 #if defined(TIM8)
329 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
330 #endif /* TIM8 */
331 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
332 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
333 #if defined(TIM17)
334 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
335 #endif /* TIM17 */
336 /**
337 * @}
338 */
339
340 #if defined(VREFBUF)
341 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
342 * @{
343 */
344 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
345 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
346 /**
347 * @}
348 */
349 #endif /* VREFBUF */
350
351 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
352 * @{
353 */
354 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
355 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
356 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
357 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
358 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
359 #if defined(FLASH_ACR_LATENCY_5WS)
360 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
361 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
362 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
363 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
364 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
365 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
366 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
367 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
368 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
369 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
370 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
371 #endif
372 /**
373 * @}
374 */
375
376 /**
377 * @}
378 */
379
380 /* Exported macro ------------------------------------------------------------*/
381
382 /* Exported functions --------------------------------------------------------*/
383 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
384 * @{
385 */
386
387 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
388 * @{
389 */
390
391 /**
392 * @brief Set memory mapping at address 0x00000000
393 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
394 * @param Memory This parameter can be one of the following values:
395 * @arg @ref LL_SYSCFG_REMAP_FLASH
396 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
397 * @arg @ref LL_SYSCFG_REMAP_SRAM
398 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
399 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
400 *
401 * (*) value not defined in all devices
402 * @retval None
403 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)404 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
405 {
406 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
407 }
408
409 /**
410 * @brief Get memory mapping at address 0x00000000
411 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
412 * @retval Returned value can be one of the following values:
413 * @arg @ref LL_SYSCFG_REMAP_FLASH
414 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
415 * @arg @ref LL_SYSCFG_REMAP_SRAM
416 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
417 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
418 *
419 * (*) value not defined in all devices
420 */
LL_SYSCFG_GetRemapMemory(void)421 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
422 {
423 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
424 }
425
426 #if defined(SYSCFG_MEMRMP_FB_MODE)
427 /**
428 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
429 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
430 * @param Bank This parameter can be one of the following values:
431 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
432 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
433 * @retval None
434 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)435 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
436 {
437 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
438 }
439
440 /**
441 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
442 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
443 * @retval Returned value can be one of the following values:
444 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
445 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
446 */
LL_SYSCFG_GetFlashBankMode(void)447 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
448 {
449 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
450 }
451 #endif /* SYSCFG_MEMRMP_FB_MODE */
452
453 /**
454 * @brief Firewall protection enabled
455 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
456 * @retval None
457 */
LL_SYSCFG_EnableFirewall(void)458 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
459 {
460 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
461 }
462
463 /**
464 * @brief Check if Firewall protection is enabled or not
465 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
466 * @retval State of bit (1 or 0).
467 */
LL_SYSCFG_IsEnabledFirewall(void)468 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
469 {
470 return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
471 }
472
473 /**
474 * @brief Enable I/O analog switch voltage booster.
475 * @note When voltage booster is enabled, I/O analog switches are supplied
476 * by a dedicated voltage booster, from VDD power domain. This is
477 * the recommended configuration with low VDDA voltage operation.
478 * @note The I/O analog switch voltage booster is relevant for peripherals
479 * using I/O in analog input: ADC, COMP, OPAMP.
480 * However, COMP and OPAMP inputs have a high impedance and
481 * voltage booster do not impact performance significantly.
482 * Therefore, the voltage booster is mainly intended for
483 * usage with ADC.
484 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
485 * @retval None
486 */
LL_SYSCFG_EnableAnalogBooster(void)487 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
488 {
489 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
490 }
491
492 /**
493 * @brief Disable I/O analog switch voltage booster.
494 * @note When voltage booster is enabled, I/O analog switches are supplied
495 * by a dedicated voltage booster, from VDD power domain. This is
496 * the recommended configuration with low VDDA voltage operation.
497 * @note The I/O analog switch voltage booster is relevant for peripherals
498 * using I/O in analog input: ADC, COMP, OPAMP.
499 * However, COMP and OPAMP inputs have a high impedance and
500 * voltage booster do not impact performance significantly.
501 * Therefore, the voltage booster is mainly intended for
502 * usage with ADC.
503 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
504 * @retval None
505 */
LL_SYSCFG_DisableAnalogBooster(void)506 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
507 {
508 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
509 }
510
511 /**
512 * @brief Enable the I2C fast mode plus driving capability.
513 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
514 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
515 * @param ConfigFastModePlus This parameter can be a combination of the following values:
516 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
517 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
518 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
519 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
520 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
521 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
522 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
523 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
524 *
525 * (*) value not defined in all devices
526 * @retval None
527 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)528 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
529 {
530 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
531 }
532
533 /**
534 * @brief Disable the I2C fast mode plus driving capability.
535 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
536 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
537 * @param ConfigFastModePlus This parameter can be a combination of the following values:
538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
540 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
541 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
542 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
543 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
544 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
545 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
546 *
547 * (*) value not defined in all devices
548 * @retval None
549 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)550 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
551 {
552 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
553 }
554
555 /**
556 * @brief Enable Floating Point Unit Invalid operation Interrupt
557 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
558 * @retval None
559 */
LL_SYSCFG_EnableIT_FPU_IOC(void)560 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
561 {
562 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
563 }
564
565 /**
566 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
567 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
568 * @retval None
569 */
LL_SYSCFG_EnableIT_FPU_DZC(void)570 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
571 {
572 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
573 }
574
575 /**
576 * @brief Enable Floating Point Unit Underflow Interrupt
577 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
578 * @retval None
579 */
LL_SYSCFG_EnableIT_FPU_UFC(void)580 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
581 {
582 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
583 }
584
585 /**
586 * @brief Enable Floating Point Unit Overflow Interrupt
587 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
588 * @retval None
589 */
LL_SYSCFG_EnableIT_FPU_OFC(void)590 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
591 {
592 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
593 }
594
595 /**
596 * @brief Enable Floating Point Unit Input denormal Interrupt
597 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
598 * @retval None
599 */
LL_SYSCFG_EnableIT_FPU_IDC(void)600 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
601 {
602 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
603 }
604
605 /**
606 * @brief Enable Floating Point Unit Inexact Interrupt
607 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
608 * @retval None
609 */
LL_SYSCFG_EnableIT_FPU_IXC(void)610 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
611 {
612 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
613 }
614
615 /**
616 * @brief Disable Floating Point Unit Invalid operation Interrupt
617 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
618 * @retval None
619 */
LL_SYSCFG_DisableIT_FPU_IOC(void)620 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
621 {
622 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
623 }
624
625 /**
626 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
627 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
628 * @retval None
629 */
LL_SYSCFG_DisableIT_FPU_DZC(void)630 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
631 {
632 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
633 }
634
635 /**
636 * @brief Disable Floating Point Unit Underflow Interrupt
637 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
638 * @retval None
639 */
LL_SYSCFG_DisableIT_FPU_UFC(void)640 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
641 {
642 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
643 }
644
645 /**
646 * @brief Disable Floating Point Unit Overflow Interrupt
647 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
648 * @retval None
649 */
LL_SYSCFG_DisableIT_FPU_OFC(void)650 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
651 {
652 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
653 }
654
655 /**
656 * @brief Disable Floating Point Unit Input denormal Interrupt
657 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
658 * @retval None
659 */
LL_SYSCFG_DisableIT_FPU_IDC(void)660 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
661 {
662 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
663 }
664
665 /**
666 * @brief Disable Floating Point Unit Inexact Interrupt
667 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
668 * @retval None
669 */
LL_SYSCFG_DisableIT_FPU_IXC(void)670 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
671 {
672 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
673 }
674
675 /**
676 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
677 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
678 * @retval State of bit (1 or 0).
679 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)680 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
681 {
682 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
683 }
684
685 /**
686 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
687 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
688 * @retval State of bit (1 or 0).
689 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)690 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
691 {
692 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
693 }
694
695 /**
696 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
697 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
698 * @retval State of bit (1 or 0).
699 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)700 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
701 {
702 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
703 }
704
705 /**
706 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
707 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
708 * @retval State of bit (1 or 0).
709 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)710 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
711 {
712 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
713 }
714
715 /**
716 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
717 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
718 * @retval State of bit (1 or 0).
719 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)720 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
721 {
722 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
723 }
724
725 /**
726 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
727 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
728 * @retval State of bit (1 or 0).
729 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)730 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
731 {
732 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
733 }
734
735 /**
736 * @brief Configure source input for the EXTI external interrupt.
737 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
738 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
739 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
740 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
741 * @param Port This parameter can be one of the following values:
742 * @arg @ref LL_SYSCFG_EXTI_PORTA
743 * @arg @ref LL_SYSCFG_EXTI_PORTB
744 * @arg @ref LL_SYSCFG_EXTI_PORTC
745 * @arg @ref LL_SYSCFG_EXTI_PORTD
746 * @arg @ref LL_SYSCFG_EXTI_PORTE
747 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
748 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
749 * @arg @ref LL_SYSCFG_EXTI_PORTH
750 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
751 *
752 * (*) value not defined in all devices
753 * @param Line This parameter can be one of the following values:
754 * @arg @ref LL_SYSCFG_EXTI_LINE0
755 * @arg @ref LL_SYSCFG_EXTI_LINE1
756 * @arg @ref LL_SYSCFG_EXTI_LINE2
757 * @arg @ref LL_SYSCFG_EXTI_LINE3
758 * @arg @ref LL_SYSCFG_EXTI_LINE4
759 * @arg @ref LL_SYSCFG_EXTI_LINE5
760 * @arg @ref LL_SYSCFG_EXTI_LINE6
761 * @arg @ref LL_SYSCFG_EXTI_LINE7
762 * @arg @ref LL_SYSCFG_EXTI_LINE8
763 * @arg @ref LL_SYSCFG_EXTI_LINE9
764 * @arg @ref LL_SYSCFG_EXTI_LINE10
765 * @arg @ref LL_SYSCFG_EXTI_LINE11
766 * @arg @ref LL_SYSCFG_EXTI_LINE12
767 * @arg @ref LL_SYSCFG_EXTI_LINE13
768 * @arg @ref LL_SYSCFG_EXTI_LINE14
769 * @arg @ref LL_SYSCFG_EXTI_LINE15
770 * @retval None
771 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)772 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
773 {
774 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
775 }
776
777 /**
778 * @brief Get the configured defined for specific EXTI Line
779 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
780 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
781 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
782 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
783 * @param Line This parameter can be one of the following values:
784 * @arg @ref LL_SYSCFG_EXTI_LINE0
785 * @arg @ref LL_SYSCFG_EXTI_LINE1
786 * @arg @ref LL_SYSCFG_EXTI_LINE2
787 * @arg @ref LL_SYSCFG_EXTI_LINE3
788 * @arg @ref LL_SYSCFG_EXTI_LINE4
789 * @arg @ref LL_SYSCFG_EXTI_LINE5
790 * @arg @ref LL_SYSCFG_EXTI_LINE6
791 * @arg @ref LL_SYSCFG_EXTI_LINE7
792 * @arg @ref LL_SYSCFG_EXTI_LINE8
793 * @arg @ref LL_SYSCFG_EXTI_LINE9
794 * @arg @ref LL_SYSCFG_EXTI_LINE10
795 * @arg @ref LL_SYSCFG_EXTI_LINE11
796 * @arg @ref LL_SYSCFG_EXTI_LINE12
797 * @arg @ref LL_SYSCFG_EXTI_LINE13
798 * @arg @ref LL_SYSCFG_EXTI_LINE14
799 * @arg @ref LL_SYSCFG_EXTI_LINE15
800 * @retval Returned value can be one of the following values:
801 * @arg @ref LL_SYSCFG_EXTI_PORTA
802 * @arg @ref LL_SYSCFG_EXTI_PORTB
803 * @arg @ref LL_SYSCFG_EXTI_PORTC
804 * @arg @ref LL_SYSCFG_EXTI_PORTD
805 * @arg @ref LL_SYSCFG_EXTI_PORTE
806 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
807 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
808 * @arg @ref LL_SYSCFG_EXTI_PORTH
809 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
810 *
811 * (*) value not defined in all devices
812 */
LL_SYSCFG_GetEXTISource(uint32_t Line)813 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
814 {
815 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
816 }
817
818 /**
819 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
820 * automatically cleared at the end of the SRAM2 erase operation.)
821 * @note This bit is write-protected: setting this bit is possible only after the
822 * correct key sequence is written in the SYSCFG_SKR register as described in
823 * the Reference Manual.
824 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
825 * @retval None
826 */
LL_SYSCFG_EnableSRAM2Erase(void)827 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
828 {
829 /* Starts a hardware SRAM2 erase operation*/
830 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
831 }
832
833 /**
834 * @brief Check if SRAM2 erase operation is on going
835 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
836 * @retval State of bit (1 or 0).
837 */
LL_SYSCFG_IsSRAM2EraseOngoing(void)838 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
839 {
840 return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
841 }
842
843 /**
844 * @brief Set connections to TIM1/8/15/16/17 Break inputs
845 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
846 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
847 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
848 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
849 * @param Break This parameter can be a combination of the following values:
850 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
851 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
852 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
853 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
854 * @retval None
855 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)856 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
857 {
858 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
859 }
860
861 /**
862 * @brief Get connections to TIM1/8/15/16/17 Break inputs
863 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
864 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
865 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
866 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
867 * @retval Returned value can be can be a combination of the following values:
868 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
869 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
870 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
871 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
872 */
LL_SYSCFG_GetTIMBreakInputs(void)873 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
874 {
875 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
876 }
877
878 /**
879 * @brief Check if SRAM2 parity error detected
880 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
881 * @retval State of bit (1 or 0).
882 */
LL_SYSCFG_IsActiveFlag_SP(void)883 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
884 {
885 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
886 }
887
888 /**
889 * @brief Clear SRAM2 parity error flag
890 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
891 * @retval None
892 */
LL_SYSCFG_ClearFlag_SP(void)893 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
894 {
895 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
896 }
897
898 /**
899 * @brief Enable SRAM2 page write protection for Pages in range 0 to 31
900 * @note Write protection is cleared only by a system reset
901 * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
902 * @param SRAM2WRP This parameter can be a combination of the following values:
903 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
904 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
905 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
906 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
907 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
908 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
909 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
910 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
911 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
912 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
913 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
914 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
915 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
916 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
917 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
918 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
919 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
920 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
921 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
922 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
923 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
924 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
925 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
926 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
927 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
928 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
929 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
930 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
931 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
932 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
933 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
934 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
935 *
936 * (*) value not defined in all devices
937 * @retval None
938 */
939 /* Legacy define */
940 #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)941 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
942 {
943 SET_BIT(SYSCFG->SWPR, SRAM2WRP);
944 }
945
946 #if defined(SYSCFG_SWPR2_PAGE63)
947 /**
948 * @brief Enable SRAM2 page write protection for Pages in range 32 to 63
949 * @note Write protection is cleared only by a system reset
950 * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
951 * @param SRAM2WRP This parameter can be a combination of the following values:
952 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
953 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
954 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
955 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
956 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
957 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
958 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
959 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
960 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
961 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
962 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
963 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
964 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
965 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
966 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
967 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
968 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
969 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
970 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
971 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
972 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
973 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
974 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
975 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
976 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
977 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
978 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
979 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
980 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
981 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
982 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
983 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
984 *
985 * (*) value not defined in all devices
986 * @retval None
987 */
LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)988 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
989 {
990 SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
991 }
992 #endif /* SYSCFG_SWPR2_PAGE63 */
993
994 /**
995 * @brief SRAM2 page write protection lock prior to erase
996 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
997 * @retval None
998 */
LL_SYSCFG_LockSRAM2WRP(void)999 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
1000 {
1001 /* Writing a wrong key reactivates the write protection */
1002 WRITE_REG(SYSCFG->SKR, 0x00);
1003 }
1004
1005 /**
1006 * @brief SRAM2 page write protection unlock prior to erase
1007 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
1008 * @retval None
1009 */
LL_SYSCFG_UnlockSRAM2WRP(void)1010 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
1011 {
1012 /* unlock the write protection of the SRAM2ER bit */
1013 WRITE_REG(SYSCFG->SKR, 0xCA);
1014 WRITE_REG(SYSCFG->SKR, 0x53);
1015 }
1016
1017 /**
1018 * @}
1019 */
1020
1021
1022 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1023 * @{
1024 */
1025
1026 /**
1027 * @brief Return the device identifier
1028 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1029 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1030 */
LL_DBGMCU_GetDeviceID(void)1031 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1032 {
1033 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1034 }
1035
1036 /**
1037 * @brief Return the device revision identifier
1038 * @note This field indicates the revision of the device.
1039 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1040 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1041 */
LL_DBGMCU_GetRevisionID(void)1042 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1043 {
1044 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1045 }
1046
1047 /**
1048 * @brief Enable the Debug Module during SLEEP mode
1049 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1050 * @retval None
1051 */
LL_DBGMCU_EnableDBGSleepMode(void)1052 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1053 {
1054 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1055 }
1056
1057 /**
1058 * @brief Disable the Debug Module during SLEEP mode
1059 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1060 * @retval None
1061 */
LL_DBGMCU_DisableDBGSleepMode(void)1062 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1063 {
1064 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1065 }
1066
1067 /**
1068 * @brief Enable the Debug Module during STOP mode
1069 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1070 * @retval None
1071 */
LL_DBGMCU_EnableDBGStopMode(void)1072 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1073 {
1074 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1075 }
1076
1077 /**
1078 * @brief Disable the Debug Module during STOP mode
1079 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1080 * @retval None
1081 */
LL_DBGMCU_DisableDBGStopMode(void)1082 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1083 {
1084 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1085 }
1086
1087 /**
1088 * @brief Enable the Debug Module during STANDBY mode
1089 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1090 * @retval None
1091 */
LL_DBGMCU_EnableDBGStandbyMode(void)1092 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1093 {
1094 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1095 }
1096
1097 /**
1098 * @brief Disable the Debug Module during STANDBY mode
1099 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1100 * @retval None
1101 */
LL_DBGMCU_DisableDBGStandbyMode(void)1102 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1103 {
1104 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1105 }
1106
1107 /**
1108 * @brief Set Trace pin assignment control
1109 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1110 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1111 * @param PinAssignment This parameter can be one of the following values:
1112 * @arg @ref LL_DBGMCU_TRACE_NONE
1113 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1114 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1115 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1116 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1117 * @retval None
1118 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1119 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1120 {
1121 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1122 }
1123
1124 /**
1125 * @brief Get Trace pin assignment control
1126 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1127 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1128 * @retval Returned value can be one of the following values:
1129 * @arg @ref LL_DBGMCU_TRACE_NONE
1130 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1131 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1132 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1133 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1134 */
LL_DBGMCU_GetTracePinAssignment(void)1135 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1136 {
1137 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1138 }
1139
1140 /**
1141 * @brief Freeze APB1 peripherals (group1 peripherals)
1142 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1143 * @param Periphs This parameter can be a combination of the following values:
1144 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1145 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1146 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1147 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1148 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1149 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1150 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1151 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1152 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1153 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1154 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1155 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1156 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1157 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1158 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1159 *
1160 * (*) value not defined in all devices.
1161 * @retval None
1162 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1163 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1164 {
1165 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1166 }
1167
1168 /**
1169 * @brief Freeze APB1 peripherals (group2 peripherals)
1170 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1171 * @param Periphs This parameter can be a combination of the following values:
1172 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1173 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1174 *
1175 * (*) value not defined in all devices.
1176 * @retval None
1177 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1178 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1179 {
1180 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1181 }
1182
1183 /**
1184 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1185 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1186 * @param Periphs This parameter can be a combination of the following values:
1187 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1188 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1189 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1190 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1191 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1192 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1193 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1194 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1195 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1196 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1197 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1198 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1199 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1200 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1201 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1202 *
1203 * (*) value not defined in all devices.
1204 * @retval None
1205 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1206 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1207 {
1208 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1209 }
1210
1211 /**
1212 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1213 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1214 * @param Periphs This parameter can be a combination of the following values:
1215 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1216 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1217 *
1218 * (*) value not defined in all devices.
1219 * @retval None
1220 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1221 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1222 {
1223 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1224 }
1225
1226 /**
1227 * @brief Freeze APB2 peripherals
1228 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1229 * @param Periphs This parameter can be a combination of the following values:
1230 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1231 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1232 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1233 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1234 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1235 *
1236 * (*) value not defined in all devices.
1237 * @retval None
1238 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1239 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1240 {
1241 SET_BIT(DBGMCU->APB2FZ, Periphs);
1242 }
1243
1244 /**
1245 * @brief Unfreeze APB2 peripherals
1246 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1247 * @param Periphs This parameter can be a combination of the following values:
1248 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1249 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1250 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1251 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1252 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1253 *
1254 * (*) value not defined in all devices.
1255 * @retval None
1256 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1257 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1258 {
1259 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1260 }
1261
1262 /**
1263 * @}
1264 */
1265
1266 #if defined(VREFBUF)
1267 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1268 * @{
1269 */
1270
1271 /**
1272 * @brief Enable Internal voltage reference
1273 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1274 * @retval None
1275 */
LL_VREFBUF_Enable(void)1276 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1277 {
1278 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1279 }
1280
1281 /**
1282 * @brief Disable Internal voltage reference
1283 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1284 * @retval None
1285 */
LL_VREFBUF_Disable(void)1286 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1287 {
1288 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1289 }
1290
1291 /**
1292 * @brief Enable high impedance (VREF+pin is high impedance)
1293 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1294 * @retval None
1295 */
LL_VREFBUF_EnableHIZ(void)1296 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1297 {
1298 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1299 }
1300
1301 /**
1302 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1303 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1304 * @retval None
1305 */
LL_VREFBUF_DisableHIZ(void)1306 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1307 {
1308 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1309 }
1310
1311 /**
1312 * @brief Set the Voltage reference scale
1313 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1314 * @param Scale This parameter can be one of the following values:
1315 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1316 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1317 * @retval None
1318 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1319 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1320 {
1321 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1322 }
1323
1324 /**
1325 * @brief Get the Voltage reference scale
1326 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1327 * @retval Returned value can be one of the following values:
1328 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1329 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1330 */
LL_VREFBUF_GetVoltageScaling(void)1331 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1332 {
1333 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1334 }
1335
1336 /**
1337 * @brief Check if Voltage reference buffer is ready
1338 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1339 * @retval State of bit (1 or 0).
1340 */
LL_VREFBUF_IsVREFReady(void)1341 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1342 {
1343 return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
1344 }
1345
1346 /**
1347 * @brief Get the trimming code for VREFBUF calibration
1348 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1349 * @retval Between 0 and 0x3F
1350 */
LL_VREFBUF_GetTrimming(void)1351 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1352 {
1353 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1354 }
1355
1356 /**
1357 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1358 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1359 * @param Value Between 0 and 0x3F
1360 * @retval None
1361 */
LL_VREFBUF_SetTrimming(uint32_t Value)1362 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1363 {
1364 WRITE_REG(VREFBUF->CCR, Value);
1365 }
1366
1367 /**
1368 * @}
1369 */
1370 #endif /* VREFBUF */
1371
1372 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1373 * @{
1374 */
1375
1376 /**
1377 * @brief Set FLASH Latency
1378 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1379 * @param Latency This parameter can be one of the following values:
1380 * @arg @ref LL_FLASH_LATENCY_0
1381 * @arg @ref LL_FLASH_LATENCY_1
1382 * @arg @ref LL_FLASH_LATENCY_2
1383 * @arg @ref LL_FLASH_LATENCY_3
1384 * @arg @ref LL_FLASH_LATENCY_4
1385 * @arg @ref LL_FLASH_LATENCY_5 (*)
1386 * @arg @ref LL_FLASH_LATENCY_6 (*)
1387 * @arg @ref LL_FLASH_LATENCY_7 (*)
1388 * @arg @ref LL_FLASH_LATENCY_8 (*)
1389 * @arg @ref LL_FLASH_LATENCY_9 (*)
1390 * @arg @ref LL_FLASH_LATENCY_10 (*)
1391 * @arg @ref LL_FLASH_LATENCY_11 (*)
1392 * @arg @ref LL_FLASH_LATENCY_12 (*)
1393 * @arg @ref LL_FLASH_LATENCY_13 (*)
1394 * @arg @ref LL_FLASH_LATENCY_14 (*)
1395 * @arg @ref LL_FLASH_LATENCY_15 (*)
1396 *
1397 * (*) value not defined in all devices.
1398 * @retval None
1399 */
LL_FLASH_SetLatency(uint32_t Latency)1400 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1401 {
1402 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1403 }
1404
1405 /**
1406 * @brief Get FLASH Latency
1407 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1408 * @retval Returned value can be one of the following values:
1409 * @arg @ref LL_FLASH_LATENCY_0
1410 * @arg @ref LL_FLASH_LATENCY_1
1411 * @arg @ref LL_FLASH_LATENCY_2
1412 * @arg @ref LL_FLASH_LATENCY_3
1413 * @arg @ref LL_FLASH_LATENCY_4
1414 * @arg @ref LL_FLASH_LATENCY_5 (*)
1415 * @arg @ref LL_FLASH_LATENCY_6 (*)
1416 * @arg @ref LL_FLASH_LATENCY_7 (*)
1417 * @arg @ref LL_FLASH_LATENCY_8 (*)
1418 * @arg @ref LL_FLASH_LATENCY_9 (*)
1419 * @arg @ref LL_FLASH_LATENCY_10 (*)
1420 * @arg @ref LL_FLASH_LATENCY_11 (*)
1421 * @arg @ref LL_FLASH_LATENCY_12 (*)
1422 * @arg @ref LL_FLASH_LATENCY_13 (*)
1423 * @arg @ref LL_FLASH_LATENCY_14 (*)
1424 * @arg @ref LL_FLASH_LATENCY_15 (*)
1425 *
1426 * (*) value not defined in all devices.
1427 */
LL_FLASH_GetLatency(void)1428 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1429 {
1430 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1431 }
1432
1433 /**
1434 * @brief Enable Prefetch
1435 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1436 * @retval None
1437 */
LL_FLASH_EnablePrefetch(void)1438 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1439 {
1440 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1441 }
1442
1443 /**
1444 * @brief Disable Prefetch
1445 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1446 * @retval None
1447 */
LL_FLASH_DisablePrefetch(void)1448 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1449 {
1450 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1451 }
1452
1453 /**
1454 * @brief Check if Prefetch buffer is enabled
1455 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1456 * @retval State of bit (1 or 0).
1457 */
LL_FLASH_IsPrefetchEnabled(void)1458 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1459 {
1460 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1461 }
1462
1463 /**
1464 * @brief Enable Instruction cache
1465 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1466 * @retval None
1467 */
LL_FLASH_EnableInstCache(void)1468 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1469 {
1470 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1471 }
1472
1473 /**
1474 * @brief Disable Instruction cache
1475 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1476 * @retval None
1477 */
LL_FLASH_DisableInstCache(void)1478 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1479 {
1480 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1481 }
1482
1483 /**
1484 * @brief Enable Data cache
1485 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1486 * @retval None
1487 */
LL_FLASH_EnableDataCache(void)1488 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1489 {
1490 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1491 }
1492
1493 /**
1494 * @brief Disable Data cache
1495 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1496 * @retval None
1497 */
LL_FLASH_DisableDataCache(void)1498 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1499 {
1500 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1501 }
1502
1503 /**
1504 * @brief Enable Instruction cache reset
1505 * @note bit can be written only when the instruction cache is disabled
1506 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1507 * @retval None
1508 */
LL_FLASH_EnableInstCacheReset(void)1509 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1510 {
1511 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1512 }
1513
1514 /**
1515 * @brief Disable Instruction cache reset
1516 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1517 * @retval None
1518 */
LL_FLASH_DisableInstCacheReset(void)1519 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1520 {
1521 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1522 }
1523
1524 /**
1525 * @brief Enable Data cache reset
1526 * @note bit can be written only when the data cache is disabled
1527 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1528 * @retval None
1529 */
LL_FLASH_EnableDataCacheReset(void)1530 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1531 {
1532 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1533 }
1534
1535 /**
1536 * @brief Disable Data cache reset
1537 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1538 * @retval None
1539 */
LL_FLASH_DisableDataCacheReset(void)1540 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1541 {
1542 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1543 }
1544
1545 /**
1546 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1547 * @note Flash memory can be put in power-down mode only when the code is executed
1548 * from RAM
1549 * @note Flash must not be accessed when power down is enabled
1550 * @note Flash must not be put in power-down while a program or an erase operation
1551 * is on-going
1552 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1553 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
1554 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
1555 * @retval None
1556 */
LL_FLASH_EnableRunPowerDown(void)1557 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1558 {
1559 /* Following values must be written consecutively to unlock the RUN_PD bit in
1560 FLASH_ACR */
1561 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1562 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1563 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1564 }
1565
1566 /**
1567 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
1568 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
1569 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
1570 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
1571 * @retval None
1572 */
LL_FLASH_DisableRunPowerDown(void)1573 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1574 {
1575 /* Following values must be written consecutively to unlock the RUN_PD bit in
1576 FLASH_ACR */
1577 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1578 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1579 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1580 }
1581
1582 /**
1583 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1584 * @note Flash must not be put in power-down while a program or an erase operation
1585 * is on-going
1586 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1587 * @retval None
1588 */
LL_FLASH_EnableSleepPowerDown(void)1589 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1590 {
1591 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1592 }
1593
1594 /**
1595 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1596 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1597 * @retval None
1598 */
LL_FLASH_DisableSleepPowerDown(void)1599 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1600 {
1601 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1602 }
1603
1604 /**
1605 * @}
1606 */
1607
1608 /**
1609 * @}
1610 */
1611
1612 /**
1613 * @}
1614 */
1615
1616 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1617
1618 /**
1619 * @}
1620 */
1621
1622 #ifdef __cplusplus
1623 }
1624 #endif
1625
1626 #endif /* STM32L4xx_LL_SYSTEM_H */
1627
1628 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1629