1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_swpmi.h
4 * @author MCD Application Team
5 * @brief Header file of SWPMI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_SWPMI_H
22 #define STM32L4xx_LL_SWPMI_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined(SWPMI1)
36
37 /** @defgroup SWPMI_LL SWPMI
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
47 * @{
48 */
49 /**
50 * @}
51 */
52 #endif /*USE_FULL_LL_DRIVER*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
57 * @{
58 */
59
60 /**
61 * @brief SWPMI Init structures definition
62 */
63 typedef struct
64 {
65 uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class.
66 This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
67
68 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
69
70 uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler.
71 This parameter must be a number between Min_Data=0 and Max_Data=63U.
72
73 The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
74
75 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
76
77 uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode.
78 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
79
80 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
81
82 uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
83 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
84
85 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
86 } LL_SWPMI_InitTypeDef;
87
88 /**
89 * @}
90 */
91 #endif /* USE_FULL_LL_DRIVER */
92
93 /* Exported constants --------------------------------------------------------*/
94 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
95 * @{
96 */
97
98 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
99 * @brief Flags defines which can be used with LL_SWPMI_WriteReg function
100 * @{
101 */
102 #define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF /*!< Clear receive buffer full flag */
103 #define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF /*!< Clear transmit buffer empty flag */
104 #define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag */
105 #define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag */
106 #define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
107 #define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF /*!< Clear transfer complete flag */
108 #define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF /*!< Clear slave resume flag */
109 /**
110 * @}
111 */
112
113 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
114 * @brief Flags defines which can be used with LL_SWPMI_ReadReg function
115 * @{
116 */
117 #define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF /*!< Receive buffer full flag */
118 #define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF /*!< Transmit buffer empty flag */
119 #define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF /*!< Receive CRC error flag */
120 #define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF /*!< Receive overrun error flag */
121 #define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF /*!< Transmit underrun error flag */
122 #define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE /*!< Receive data register not empty */
123 #define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE /*!< Transmit data register empty */
124 #define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF /*!< Transfer complete flag */
125 #define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF /*!< Slave resume flag */
126 #define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP /*!< SUSPEND flag */
127 #define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF /*!< DEACTIVATED flag */
128 /**
129 * @}
130 */
131
132 /** @defgroup SWPMI_LL_EC_IT IT Defines
133 * @brief IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions
134 * @{
135 */
136 #define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE /*!< Slave resume interrupt enable */
137 #define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE /*!< Transmit complete interrupt enable */
138 #define LL_SWPMI_IER_TIE SWPMI_IER_TIE /*!< Transmit interrupt enable */
139 #define LL_SWPMI_IER_RIE SWPMI_IER_RIE /*!< Receive interrupt enable */
140 #define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
141 #define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable */
142 #define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable */
143 #define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE /*!< Transmit buffer empty interrupt enable */
144 #define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE /*!< Receive buffer full interrupt enable */
145 /**
146 * @}
147 */
148
149 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
150 * @{
151 */
152 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for reception */
153 #define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE /*!< Multi software buffermode for reception */
154 /**
155 * @}
156 */
157
158 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
159 * @{
160 */
161 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for transmission */
162 #define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE /*!< Multi software buffermode for transmission */
163 /**
164 * @}
165 */
166
167 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
168 * @{
169 */
170 #define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000) /*!< SWPMI_IO uses directly VDD voltage to operate in class C */
171 #define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
172 /**
173 * @}
174 */
175
176 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
177 * @{
178 */
179 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0 /*!< Get address of data register used for transmission */
180 #define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1 /*!< Get address of data register used for reception */
181 /**
182 * @}
183 */
184
185 /**
186 * @}
187 */
188
189 /* Exported macro ------------------------------------------------------------*/
190 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
191 * @{
192 */
193
194 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
195 * @{
196 */
197
198 /**
199 * @brief Write a value in SWPMI register
200 * @param __INSTANCE__ SWPMI Instance
201 * @param __REG__ Register to be written
202 * @param __VALUE__ Value to be written in the register
203 * @retval None
204 */
205 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
206
207 /**
208 * @brief Read a value in SWPMI register
209 * @param __INSTANCE__ SWPMI Instance
210 * @param __REG__ Register to be read
211 * @retval Register value
212 */
213 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
214 /**
215 * @}
216 */
217
218 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
219 * @{
220 */
221
222 /**
223 * @brief Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
224 * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
225 * @param __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
226 * @param __FSWPCLK__ PCLK or HSI frequency (in Hz)
227 * @retval Bitrate prescaler (BRR register)
228 */
229 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
230
231 /**
232 * @}
233 */
234
235 /**
236 * @}
237 */
238
239 /* Exported functions --------------------------------------------------------*/
240 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
241 * @{
242 */
243
244 /** @defgroup SWPMI_LL_EF_Configuration Configuration
245 * @{
246 */
247
248 /**
249 * @brief Set Reception buffering mode
250 * @note If Multi software buffer mode is chosen, RXDMA bits must also be set.
251 * @rmtoll CR RXMODE LL_SWPMI_SetReceptionMode
252 * @param SWPMIx SWPMI Instance
253 * @param RxBufferingMode This parameter can be one of the following values:
254 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
255 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
256 * @retval None
257 */
LL_SWPMI_SetReceptionMode(SWPMI_TypeDef * SWPMIx,uint32_t RxBufferingMode)258 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
259 {
260 MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
261 }
262
263 /**
264 * @brief Get Reception buffering mode
265 * @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode
266 * @param SWPMIx SWPMI Instance
267 * @retval Returned value can be one of the following values:
268 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
269 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
270 */
LL_SWPMI_GetReceptionMode(SWPMI_TypeDef * SWPMIx)271 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
272 {
273 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
274 }
275
276 /**
277 * @brief Set Transmission buffering mode
278 * @note If Multi software buffer mode is chosen, TXDMA bits must also be set.
279 * @rmtoll CR TXMODE LL_SWPMI_SetTransmissionMode
280 * @param SWPMIx SWPMI Instance
281 * @param TxBufferingMode This parameter can be one of the following values:
282 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
283 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
284 * @retval None
285 */
LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef * SWPMIx,uint32_t TxBufferingMode)286 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
287 {
288 MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
289 }
290
291 /**
292 * @brief Get Transmission buffering mode
293 * @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode
294 * @param SWPMIx SWPMI Instance
295 * @retval Returned value can be one of the following values:
296 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
297 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
298 */
LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef * SWPMIx)299 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
300 {
301 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
302 }
303
304 /**
305 * @brief Enable loopback mode
306 * @rmtoll CR LPBK LL_SWPMI_EnableLoopback
307 * @param SWPMIx SWPMI Instance
308 * @retval None
309 */
LL_SWPMI_EnableLoopback(SWPMI_TypeDef * SWPMIx)310 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
311 {
312 SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
313 }
314
315 /**
316 * @brief Disable loopback mode
317 * @rmtoll CR LPBK LL_SWPMI_DisableLoopback
318 * @param SWPMIx SWPMI Instance
319 * @retval None
320 */
LL_SWPMI_DisableLoopback(SWPMI_TypeDef * SWPMIx)321 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
322 {
323 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
324 }
325
326 /**
327 * @brief Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
328 * @note SWP bus stays in the ACTIVATED state as long as there is a communication
329 * with the slave, either in transmission or in reception. The SWP bus switches back
330 * to the SUSPENDED state as soon as there is no more transmission or reception
331 * activity, after 7 idle bits.
332 * @rmtoll CR SWPACT LL_SWPMI_Activate
333 * @param SWPMIx SWPMI Instance
334 * @retval None
335 */
LL_SWPMI_Activate(SWPMI_TypeDef * SWPMIx)336 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
337 {
338 /* In order to activate SWP again, the software must clear DEACT bit*/
339 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
340
341 /* Set SWACT bit */
342 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
343 }
344
345 /**
346 * @brief Check if Single wire protocol bus is in ACTIVATED state.
347 * @rmtoll CR SWPACT LL_SWPMI_Activate
348 * @param SWPMIx SWPMI Instance
349 * @retval State of bit (1 or 0).
350 */
LL_SWPMI_IsActivated(SWPMI_TypeDef * SWPMIx)351 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
352 {
353 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);
354 }
355
356 /**
357 * @brief Deactivate immediately Single wire protocol bus (immediate transition to
358 * DEACTIVATED state)
359 * @rmtoll CR SWPACT LL_SWPMI_Deactivate
360 * @param SWPMIx SWPMI Instance
361 * @retval None
362 */
LL_SWPMI_Deactivate(SWPMI_TypeDef * SWPMIx)363 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
364 {
365 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
366 }
367
368 /**
369 * @brief Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
370 * state if no resume from slave)
371 * @rmtoll CR DEACT LL_SWPMI_RequestDeactivation
372 * @param SWPMIx SWPMI Instance
373 * @retval None
374 */
LL_SWPMI_RequestDeactivation(SWPMI_TypeDef * SWPMIx)375 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
376 {
377 SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
378 }
379
380 /**
381 * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
382 * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler
383 * @param SWPMIx SWPMI Instance
384 * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63U
385 * @retval None
386 */
LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef * SWPMIx,uint32_t BitRatePrescaler)387 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
388 {
389 WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
390 }
391
392 /**
393 * @brief Get Bitrate prescaler
394 * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler
395 * @param SWPMIx SWPMI Instance
396 * @retval A number between Min_Data=0 and Max_Data=63U
397 */
LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef * SWPMIx)398 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
399 {
400 return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
401 }
402
403 /**
404 * @brief Set SWP Voltage Class
405 * @rmtoll OR CLASS LL_SWPMI_SetVoltageClass
406 * @param SWPMIx SWPMI Instance
407 * @param VoltageClass This parameter can be one of the following values:
408 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
409 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
410 * @retval None
411 */
LL_SWPMI_SetVoltageClass(SWPMI_TypeDef * SWPMIx,uint32_t VoltageClass)412 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
413 {
414 MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
415 }
416
417 /**
418 * @brief Get SWP Voltage Class
419 * @rmtoll OR CLASS LL_SWPMI_GetVoltageClass
420 * @param SWPMIx SWPMI Instance
421 * @retval Returned value can be one of the following values:
422 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
423 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
424 */
LL_SWPMI_GetVoltageClass(SWPMI_TypeDef * SWPMIx)425 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
426 {
427 return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
428 }
429
430 /**
431 * @}
432 */
433
434 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
435 * @{
436 */
437
438 /**
439 * @brief Check if the last word of the frame under reception has arrived in SWPMI_RDR.
440 * @rmtoll ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF
441 * @param SWPMIx SWPMI Instance
442 * @retval State of bit (1 or 0).
443 */
LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef * SWPMIx)444 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
445 {
446 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);
447 }
448
449 /**
450 * @brief Check if Frame transmission buffer has been emptied
451 * @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE
452 * @param SWPMIx SWPMI Instance
453 * @retval State of bit (1 or 0).
454 */
LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef * SWPMIx)455 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
456 {
457 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);
458 }
459
460 /**
461 * @brief Check if CRC error in reception has been detected
462 * @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER
463 * @param SWPMIx SWPMI Instance
464 * @retval State of bit (1 or 0).
465 */
LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef * SWPMIx)466 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
467 {
468 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);
469 }
470
471 /**
472 * @brief Check if Overrun in reception has been detected
473 * @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR
474 * @param SWPMIx SWPMI Instance
475 * @retval State of bit (1 or 0).
476 */
LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef * SWPMIx)477 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
478 {
479 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);
480 }
481
482 /**
483 * @brief Check if underrun error in transmission has been detected
484 * @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR
485 * @param SWPMIx SWPMI Instance
486 * @retval State of bit (1 or 0).
487 */
LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef * SWPMIx)488 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
489 {
490 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);
491 }
492
493 /**
494 * @brief Check if Receive data register not empty (it means that Received data is ready
495 * to be read in the SWPMI_RDR register)
496 * @rmtoll ISR RXNE LL_SWPMI_IsActiveFlag_RXNE
497 * @param SWPMIx SWPMI Instance
498 * @retval State of bit (1 or 0).
499 */
LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef * SWPMIx)500 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
501 {
502 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);
503 }
504
505 /**
506 * @brief Check if Transmit data register is empty (it means that Data written in transmit
507 * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
508 * @rmtoll ISR TXE LL_SWPMI_IsActiveFlag_TXE
509 * @param SWPMIx SWPMI Instance
510 * @retval State of bit (1 or 0).
511 */
LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef * SWPMIx)512 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
513 {
514 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);
515 }
516
517 /**
518 * @brief Check if Both transmission and reception are completed and SWP is switched to
519 * the SUSPENDED state
520 * @rmtoll ISR TCF LL_SWPMI_IsActiveFlag_TC
521 * @param SWPMIx SWPMI Instance
522 * @retval State of bit (1 or 0).
523 */
LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef * SWPMIx)524 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
525 {
526 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);
527 }
528
529 /**
530 * @brief Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
531 * state
532 * @rmtoll ISR SRF LL_SWPMI_IsActiveFlag_SR
533 * @param SWPMIx SWPMI Instance
534 * @retval State of bit (1 or 0).
535 */
LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef * SWPMIx)536 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
537 {
538 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);
539 }
540
541 /**
542 * @brief Check if SWP bus is in SUSPENDED or DEACTIVATED state
543 * @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP
544 * @param SWPMIx SWPMI Instance
545 * @retval State of bit (1 or 0).
546 */
LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef * SWPMIx)547 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
548 {
549 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);
550 }
551
552 /**
553 * @brief Check if SWP bus is in DEACTIVATED state
554 * @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT
555 * @param SWPMIx SWPMI Instance
556 * @retval State of bit (1 or 0).
557 */
LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef * SWPMIx)558 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
559 {
560 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Clear receive buffer full flag
565 * @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF
566 * @param SWPMIx SWPMI Instance
567 * @retval None
568 */
LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef * SWPMIx)569 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
570 {
571 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
572 }
573
574 /**
575 * @brief Clear transmit buffer empty flag
576 * @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE
577 * @param SWPMIx SWPMI Instance
578 * @retval None
579 */
LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef * SWPMIx)580 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
581 {
582 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
583 }
584
585 /**
586 * @brief Clear receive CRC error flag
587 * @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER
588 * @param SWPMIx SWPMI Instance
589 * @retval None
590 */
LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef * SWPMIx)591 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
592 {
593 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
594 }
595
596 /**
597 * @brief Clear receive overrun error flag
598 * @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR
599 * @param SWPMIx SWPMI Instance
600 * @retval None
601 */
LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef * SWPMIx)602 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
603 {
604 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
605 }
606
607 /**
608 * @brief Clear transmit underrun error flag
609 * @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR
610 * @param SWPMIx SWPMI Instance
611 * @retval None
612 */
LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef * SWPMIx)613 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
614 {
615 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
616 }
617
618 /**
619 * @brief Clear transfer complete flag
620 * @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC
621 * @param SWPMIx SWPMI Instance
622 * @retval None
623 */
LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef * SWPMIx)624 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
625 {
626 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
627 }
628
629 /**
630 * @brief Clear slave resume flag
631 * @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR
632 * @param SWPMIx SWPMI Instance
633 * @retval None
634 */
LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef * SWPMIx)635 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
636 {
637 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
638 }
639
640 /**
641 * @}
642 */
643
644 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
645 * @{
646 */
647
648 /**
649 * @brief Enable Slave resume interrupt
650 * @rmtoll IER SRIE LL_SWPMI_EnableIT_SR
651 * @param SWPMIx SWPMI Instance
652 * @retval None
653 */
LL_SWPMI_EnableIT_SR(SWPMI_TypeDef * SWPMIx)654 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
655 {
656 SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
657 }
658
659 /**
660 * @brief Enable Transmit complete interrupt
661 * @rmtoll IER TCIE LL_SWPMI_EnableIT_TC
662 * @param SWPMIx SWPMI Instance
663 * @retval None
664 */
LL_SWPMI_EnableIT_TC(SWPMI_TypeDef * SWPMIx)665 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
666 {
667 SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
668 }
669
670 /**
671 * @brief Enable Transmit interrupt
672 * @rmtoll IER TIE LL_SWPMI_EnableIT_TX
673 * @param SWPMIx SWPMI Instance
674 * @retval None
675 */
LL_SWPMI_EnableIT_TX(SWPMI_TypeDef * SWPMIx)676 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
677 {
678 SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
679 }
680
681 /**
682 * @brief Enable Receive interrupt
683 * @rmtoll IER RIE LL_SWPMI_EnableIT_RX
684 * @param SWPMIx SWPMI Instance
685 * @retval None
686 */
LL_SWPMI_EnableIT_RX(SWPMI_TypeDef * SWPMIx)687 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
688 {
689 SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
690 }
691
692 /**
693 * @brief Enable Transmit underrun error interrupt
694 * @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR
695 * @param SWPMIx SWPMI Instance
696 * @retval None
697 */
LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef * SWPMIx)698 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
699 {
700 SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
701 }
702
703 /**
704 * @brief Enable Receive overrun error interrupt
705 * @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR
706 * @param SWPMIx SWPMI Instance
707 * @retval None
708 */
LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef * SWPMIx)709 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
710 {
711 SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
712 }
713
714 /**
715 * @brief Enable Receive CRC error interrupt
716 * @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER
717 * @param SWPMIx SWPMI Instance
718 * @retval None
719 */
LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef * SWPMIx)720 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
721 {
722 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
723 }
724
725 /**
726 * @brief Enable Transmit buffer empty interrupt
727 * @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE
728 * @param SWPMIx SWPMI Instance
729 * @retval None
730 */
LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef * SWPMIx)731 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
732 {
733 SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
734 }
735
736 /**
737 * @brief Enable Receive buffer full interrupt
738 * @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF
739 * @param SWPMIx SWPMI Instance
740 * @retval None
741 */
LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef * SWPMIx)742 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
743 {
744 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
745 }
746
747 /**
748 * @brief Disable Slave resume interrupt
749 * @rmtoll IER SRIE LL_SWPMI_DisableIT_SR
750 * @param SWPMIx SWPMI Instance
751 * @retval None
752 */
LL_SWPMI_DisableIT_SR(SWPMI_TypeDef * SWPMIx)753 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
754 {
755 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
756 }
757
758 /**
759 * @brief Disable Transmit complete interrupt
760 * @rmtoll IER TCIE LL_SWPMI_DisableIT_TC
761 * @param SWPMIx SWPMI Instance
762 * @retval None
763 */
LL_SWPMI_DisableIT_TC(SWPMI_TypeDef * SWPMIx)764 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
765 {
766 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
767 }
768
769 /**
770 * @brief Disable Transmit interrupt
771 * @rmtoll IER TIE LL_SWPMI_DisableIT_TX
772 * @param SWPMIx SWPMI Instance
773 * @retval None
774 */
LL_SWPMI_DisableIT_TX(SWPMI_TypeDef * SWPMIx)775 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
776 {
777 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
778 }
779
780 /**
781 * @brief Disable Receive interrupt
782 * @rmtoll IER RIE LL_SWPMI_DisableIT_RX
783 * @param SWPMIx SWPMI Instance
784 * @retval None
785 */
LL_SWPMI_DisableIT_RX(SWPMI_TypeDef * SWPMIx)786 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
787 {
788 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
789 }
790
791 /**
792 * @brief Disable Transmit underrun error interrupt
793 * @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR
794 * @param SWPMIx SWPMI Instance
795 * @retval None
796 */
LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef * SWPMIx)797 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
798 {
799 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
800 }
801
802 /**
803 * @brief Disable Receive overrun error interrupt
804 * @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR
805 * @param SWPMIx SWPMI Instance
806 * @retval None
807 */
LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef * SWPMIx)808 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
809 {
810 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
811 }
812
813 /**
814 * @brief Disable Receive CRC error interrupt
815 * @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER
816 * @param SWPMIx SWPMI Instance
817 * @retval None
818 */
LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef * SWPMIx)819 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
820 {
821 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
822 }
823
824 /**
825 * @brief Disable Transmit buffer empty interrupt
826 * @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE
827 * @param SWPMIx SWPMI Instance
828 * @retval None
829 */
LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef * SWPMIx)830 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
831 {
832 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
833 }
834
835 /**
836 * @brief Disable Receive buffer full interrupt
837 * @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF
838 * @param SWPMIx SWPMI Instance
839 * @retval None
840 */
LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef * SWPMIx)841 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
842 {
843 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
844 }
845
846 /**
847 * @brief Check if Slave resume interrupt is enabled
848 * @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR
849 * @param SWPMIx SWPMI Instance
850 * @retval State of bit (1 or 0).
851 */
LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef * SWPMIx)852 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
853 {
854 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);
855 }
856
857 /**
858 * @brief Check if Transmit complete interrupt is enabled
859 * @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC
860 * @param SWPMIx SWPMI Instance
861 * @retval State of bit (1 or 0).
862 */
LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef * SWPMIx)863 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
864 {
865 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);
866 }
867
868 /**
869 * @brief Check if Transmit interrupt is enabled
870 * @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX
871 * @param SWPMIx SWPMI Instance
872 * @retval State of bit (1 or 0).
873 */
LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef * SWPMIx)874 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
875 {
876 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);
877 }
878
879 /**
880 * @brief Check if Receive interrupt is enabled
881 * @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX
882 * @param SWPMIx SWPMI Instance
883 * @retval State of bit (1 or 0).
884 */
LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef * SWPMIx)885 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
886 {
887 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);
888 }
889
890 /**
891 * @brief Check if Transmit underrun error interrupt is enabled
892 * @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR
893 * @param SWPMIx SWPMI Instance
894 * @retval State of bit (1 or 0).
895 */
LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef * SWPMIx)896 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
897 {
898 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);
899 }
900
901 /**
902 * @brief Check if Receive overrun error interrupt is enabled
903 * @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR
904 * @param SWPMIx SWPMI Instance
905 * @retval State of bit (1 or 0).
906 */
LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef * SWPMIx)907 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
908 {
909 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);
910 }
911
912 /**
913 * @brief Check if Receive CRC error interrupt is enabled
914 * @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER
915 * @param SWPMIx SWPMI Instance
916 * @retval State of bit (1 or 0).
917 */
LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef * SWPMIx)918 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
919 {
920 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);
921 }
922
923 /**
924 * @brief Check if Transmit buffer empty interrupt is enabled
925 * @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE
926 * @param SWPMIx SWPMI Instance
927 * @retval State of bit (1 or 0).
928 */
LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef * SWPMIx)929 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
930 {
931 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);
932 }
933
934 /**
935 * @brief Check if Receive buffer full interrupt is enabled
936 * @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF
937 * @param SWPMIx SWPMI Instance
938 * @retval State of bit (1 or 0).
939 */
LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef * SWPMIx)940 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
941 {
942 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);
943 }
944
945 /**
946 * @}
947 */
948
949 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
950 * @{
951 */
952
953 /**
954 * @brief Enable DMA mode for reception
955 * @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX
956 * @param SWPMIx SWPMI Instance
957 * @retval None
958 */
LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef * SWPMIx)959 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
960 {
961 SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
962 }
963
964 /**
965 * @brief Disable DMA mode for reception
966 * @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX
967 * @param SWPMIx SWPMI Instance
968 * @retval None
969 */
LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef * SWPMIx)970 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
971 {
972 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
973 }
974
975 /**
976 * @brief Check if DMA mode for reception is enabled
977 * @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX
978 * @param SWPMIx SWPMI Instance
979 * @retval State of bit (1 or 0).
980 */
LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef * SWPMIx)981 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
982 {
983 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);
984 }
985
986 /**
987 * @brief Enable DMA mode for transmission
988 * @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX
989 * @param SWPMIx SWPMI Instance
990 * @retval None
991 */
LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef * SWPMIx)992 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
993 {
994 SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
995 }
996
997 /**
998 * @brief Disable DMA mode for transmission
999 * @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX
1000 * @param SWPMIx SWPMI Instance
1001 * @retval None
1002 */
LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef * SWPMIx)1003 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1004 {
1005 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1006 }
1007
1008 /**
1009 * @brief Check if DMA mode for transmission is enabled
1010 * @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX
1011 * @param SWPMIx SWPMI Instance
1012 * @retval State of bit (1 or 0).
1013 */
LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef * SWPMIx)1014 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1015 {
1016 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);
1017 }
1018
1019 /**
1020 * @brief Get the data register address used for DMA transfer
1021 * @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr\n
1022 * RDR RD LL_SWPMI_DMA_GetRegAddr
1023 * @param SWPMIx SWPMI Instance
1024 * @param Direction This parameter can be one of the following values:
1025 * @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
1026 * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
1027 * @retval Address of data register
1028 */
LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef * SWPMIx,uint32_t Direction)1029 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
1030 {
1031 uint32_t data_reg_addr;
1032
1033 if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
1034 {
1035 /* return address of TDR register */
1036 data_reg_addr = (uint32_t)&(SWPMIx->TDR);
1037 }
1038 else
1039 {
1040 /* return address of RDR register */
1041 data_reg_addr = (uint32_t)&(SWPMIx->RDR);
1042 }
1043
1044 return data_reg_addr;
1045 }
1046
1047 /**
1048 * @}
1049 */
1050
1051 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
1052 * @{
1053 */
1054
1055 /**
1056 * @brief Retrieve number of data bytes present in payload of received frame
1057 * @rmtoll RFL RFL LL_SWPMI_GetReceiveFrameLength
1058 * @param SWPMIx SWPMI Instance
1059 * @retval Value between Min_Data=0x00 and Max_Data=0x1F
1060 */
LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef * SWPMIx)1061 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
1062 {
1063 return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
1064 }
1065
1066 /**
1067 * @brief Transmit Data Register
1068 * @rmtoll TDR TD LL_SWPMI_TransmitData32
1069 * @param SWPMIx SWPMI Instance
1070 * @param TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1071 * @retval None
1072 */
LL_SWPMI_TransmitData32(SWPMI_TypeDef * SWPMIx,uint32_t TxData)1073 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
1074 {
1075 WRITE_REG(SWPMIx->TDR, TxData);
1076 }
1077
1078 /**
1079 * @brief Receive Data Register
1080 * @rmtoll RDR RD LL_SWPMI_ReceiveData32
1081 * @param SWPMIx SWPMI Instance
1082 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1083 */
LL_SWPMI_ReceiveData32(SWPMI_TypeDef * SWPMIx)1084 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
1085 {
1086 return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
1087 }
1088
1089 /**
1090 * @brief Enable SWP Transceiver Bypass
1091 * @note The external interface for SWPMI is SWPMI_IO
1092 * (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
1093 * @rmtoll OR TBYP LL_SWPMI_EnableTXBypass
1094 * @param SWPMIx SWPMI Instance
1095 * @retval None
1096 */
LL_SWPMI_EnableTXBypass(SWPMI_TypeDef * SWPMIx)1097 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
1098 {
1099 CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1100 }
1101
1102 /**
1103 * @brief Disable SWP Transceiver Bypass
1104 * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
1105 * function on GPIOs. This configuration is selected to connect an external transceiver
1106 * @rmtoll OR TBYP LL_SWPMI_DisableTXBypass
1107 * @param SWPMIx SWPMI Instance
1108 * @retval None
1109 */
LL_SWPMI_DisableTXBypass(SWPMI_TypeDef * SWPMIx)1110 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
1111 {
1112 SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1113 }
1114
1115 /**
1116 * @}
1117 */
1118
1119 #if defined(USE_FULL_LL_DRIVER)
1120 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
1121 * @{
1122 */
1123
1124 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
1125 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1126 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1127
1128 /**
1129 * @}
1130 */
1131 #endif /*USE_FULL_LL_DRIVER*/
1132
1133 /**
1134 * @}
1135 */
1136
1137 /**
1138 * @}
1139 */
1140
1141 #endif /* SWPMI1 */
1142
1143 /**
1144 * @}
1145 */
1146
1147 #ifdef __cplusplus
1148 }
1149 #endif
1150
1151 #endif /* STM32L4xx_LL_SWPMI_H */
1152
1153 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1154