1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_RCC_H
22 #define STM32L4xx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined(RCC)
36
37 /** @defgroup RCC_LL RCC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
45 * @{
46 */
47 /* Defines used to perform offsets*/
48 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
49 #define RCC_OFFSET_CCIPR 0U
50 #define RCC_OFFSET_CCIPR2 0x14U
51
52 /**
53 * @}
54 */
55
56 /* Private macros ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
59 * @{
60 */
61 /**
62 * @}
63 */
64 #endif /*USE_FULL_LL_DRIVER*/
65
66 /* Exported types ------------------------------------------------------------*/
67 #if defined(USE_FULL_LL_DRIVER)
68 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
69 * @{
70 */
71
72 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
73 * @{
74 */
75
76 /**
77 * @brief RCC Clocks Frequency Structure
78 */
79 typedef struct
80 {
81 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
82 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
83 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
84 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
85 } LL_RCC_ClocksTypeDef;
86
87 /**
88 * @}
89 */
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
98 * @{
99 */
100
101 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
102 * @brief Defines used to adapt values of different oscillators
103 * @note These values could be modified in the user environment according to
104 * HW set-up.
105 * @{
106 */
107 #if !defined (HSE_VALUE)
108 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
109 #endif /* HSE_VALUE */
110
111 #if !defined (HSI_VALUE)
112 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
113 #endif /* HSI_VALUE */
114
115 #if !defined (LSE_VALUE)
116 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
117 #endif /* LSE_VALUE */
118
119 #if !defined (LSI_VALUE)
120 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
121 #endif /* LSI_VALUE */
122 #if defined(RCC_HSI48_SUPPORT)
123
124 #if !defined (HSI48_VALUE)
125 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
126 #endif /* HSI48_VALUE */
127 #endif /* RCC_HSI48_SUPPORT */
128
129 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
130 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
131 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
132
133 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
134 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
135 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
136 /**
137 * @}
138 */
139
140 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
141 * @brief Flags defines which can be used with LL_RCC_WriteReg function
142 * @{
143 */
144 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
145 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
146 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
147 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
148 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
149 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
150 #if defined(RCC_HSI48_SUPPORT)
151 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
152 #endif /* RCC_HSI48_SUPPORT */
153 #if defined(RCC_PLLSAI1_SUPPORT)
154 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */
155 #endif /* RCC_PLLSAI1_SUPPORT */
156 #if defined(RCC_PLLSAI2_SUPPORT)
157 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */
158 #endif /* RCC_PLLSAI2_SUPPORT */
159 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
160 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
161 /**
162 * @}
163 */
164
165 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
166 * @brief Flags defines which can be used with LL_RCC_ReadReg function
167 * @{
168 */
169 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
170 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
171 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
172 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
173 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
174 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
175 #if defined(RCC_HSI48_SUPPORT)
176 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
177 #endif /* RCC_HSI48_SUPPORT */
178 #if defined(RCC_PLLSAI1_SUPPORT)
179 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */
180 #endif /* RCC_PLLSAI1_SUPPORT */
181 #if defined(RCC_PLLSAI2_SUPPORT)
182 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */
183 #endif /* RCC_PLLSAI2_SUPPORT */
184 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
185 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
186 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */
187 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
188 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
189 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
190 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
191 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
192 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
193 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
194 /**
195 * @}
196 */
197
198 /** @defgroup RCC_LL_EC_IT IT Defines
199 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
200 * @{
201 */
202 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
203 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
204 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
205 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
206 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
207 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
208 #if defined(RCC_HSI48_SUPPORT)
209 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
210 #endif /* RCC_HSI48_SUPPORT */
211 #if defined(RCC_PLLSAI1_SUPPORT)
212 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */
213 #endif /* RCC_PLLSAI1_SUPPORT */
214 #if defined(RCC_PLLSAI2_SUPPORT)
215 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */
216 #endif /* RCC_PLLSAI2_SUPPORT */
217 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
218 /**
219 * @}
220 */
221
222 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
223 * @{
224 */
225 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
226 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
227 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
228 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
229 /**
230 * @}
231 */
232
233 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
234 * @{
235 */
236 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
237 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
238 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
239 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
240 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
241 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
242 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
243 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
244 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
245 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
246 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
247 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
248 /**
249 * @}
250 */
251
252 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
253 * @{
254 */
255 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */
256 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */
257 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */
258 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */
259 /**
260 * @}
261 */
262
263 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
264 * @{
265 */
266 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
267 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
268 /**
269 * @}
270 */
271
272 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
273 * @{
274 */
275 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
276 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
277 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
278 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
279 /**
280 * @}
281 */
282
283 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
284 * @{
285 */
286 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
287 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
288 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
289 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
290 /**
291 * @}
292 */
293
294 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
295 * @{
296 */
297 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
298 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
299 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
300 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
301 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
302 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
303 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
304 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
305 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
306 /**
307 * @}
308 */
309
310 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
311 * @{
312 */
313 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
314 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
315 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
316 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
317 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
318 /**
319 * @}
320 */
321
322 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
323 * @{
324 */
325 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
326 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
327 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
328 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
329 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
330 /**
331 * @}
332 */
333
334 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
335 * @{
336 */
337 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
338 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
339 /**
340 * @}
341 */
342
343 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
344 * @{
345 */
346 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
347 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
348 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
349 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
350 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
351 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
352 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
353 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
354 #if defined(RCC_HSI48_SUPPORT)
355 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
356 #endif /* RCC_HSI48_SUPPORT */
357 /**
358 * @}
359 */
360
361 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
362 * @{
363 */
364 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
365 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
366 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
367 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
368 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
369 /**
370 * @}
371 */
372
373 #if defined(USE_FULL_LL_DRIVER)
374 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
375 * @{
376 */
377 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
378 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
379 /**
380 * @}
381 */
382 #endif /* USE_FULL_LL_DRIVER */
383
384 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
385 * @{
386 */
387 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
388 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
389 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
390 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
391 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
392 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
393 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
394 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
395 #if defined(RCC_CCIPR_USART3SEL)
396 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
397 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
398 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
399 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
400 #endif /* RCC_CCIPR_USART3SEL */
401 /**
402 * @}
403 */
404
405 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
406 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
407 * @{
408 */
409 #if defined(RCC_CCIPR_UART4SEL)
410 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
411 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
412 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
413 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
414 #endif /* RCC_CCIPR_UART4SEL */
415 #if defined(RCC_CCIPR_UART5SEL)
416 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
417 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
418 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
419 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
420 #endif /* RCC_CCIPR_UART5SEL */
421 /**
422 * @}
423 */
424 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
425
426 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
427 * @{
428 */
429 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
430 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
431 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
432 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
433 /**
434 * @}
435 */
436
437 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
438 * @{
439 */
440 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
441 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
442 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
443 #if defined(RCC_CCIPR_I2C2SEL)
444 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
445 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
446 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
447 #endif /* RCC_CCIPR_I2C2SEL */
448 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
449 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
450 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
451 #if defined(RCC_CCIPR2_I2C4SEL)
452 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
453 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
454 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
455 #endif /* RCC_CCIPR2_I2C4SEL */
456 /**
457 * @}
458 */
459
460 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
461 * @{
462 */
463 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /*!< PCLK1 clock used as LPTIM1 clock source */
464 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */
465 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */
466 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE clock used as LPTIM1 clock source */
467 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /*!< PCLK1 clock used as LPTIM2 clock source */
468 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */
469 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */
470 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE clock used as LPTIM2 clock source */
471 /**
472 * @}
473 */
474
475 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
476 * @{
477 */
478 #if defined(RCC_CCIPR2_SAI1SEL)
479 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL clock used as SAI1 clock source */
480 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */
481 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */
482 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
483 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
484 #elif defined(RCC_CCIPR_SAI1SEL)
485 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */
486 #if defined(RCC_PLLSAI2_SUPPORT)
487 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */
488 #endif /* RCC_PLLSAI2_SUPPORT */
489 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */
490 #define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */
491 #endif /* RCC_CCIPR2_SAI1SEL */
492
493 #if defined(RCC_CCIPR2_SAI2SEL)
494 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL clock used as SAI2 clock source */
495 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */
496 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */
497 #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
498 #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
499 #elif defined(RCC_CCIPR_SAI2SEL)
500 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */
501 #if defined(RCC_PLLSAI2_SUPPORT)
502 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */
503 #endif /* RCC_PLLSAI2_SUPPORT */
504 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */
505 #define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */
506 #endif /* RCC_CCIPR2_SAI2SEL */
507 /**
508 * @}
509 */
510
511 #if defined(RCC_CCIPR2_SDMMCSEL)
512 /** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
513 * @{
514 */
515 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
516 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */
517 /**
518 * @}
519 */
520 #endif /* RCC_CCIPR2_SDMMCSEL */
521
522 #if defined(SDMMC1)
523 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
524 * @{
525 */
526 #if defined(RCC_HSI48_SUPPORT)
527 #define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source */
528 #else
529 #define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */
530 #endif
531 #if defined(RCC_PLLSAI1_SUPPORT)
532 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */
533 #endif /* RCC_PLLSAI1_SUPPORT */
534 #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */
535 #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */
536 /**
537 * @}
538 */
539 #endif /* SDMMC1 */
540
541 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
542 * @{
543 */
544 #if defined(RCC_HSI48_SUPPORT)
545 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
546 #else
547 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */
548 #endif
549 #if defined(RCC_PLLSAI1_SUPPORT)
550 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */
551 #endif /* RCC_PLLSAI1_SUPPORT */
552 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
553 #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */
554 /**
555 * @}
556 */
557
558 #if defined(USB_OTG_FS) || defined(USB)
559 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
560 * @{
561 */
562 #if defined(RCC_HSI48_SUPPORT)
563 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
564 #else
565 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */
566 #endif
567 #if defined(RCC_PLLSAI1_SUPPORT)
568 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */
569 #endif /* RCC_PLLSAI1_SUPPORT */
570 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
571 #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */
572 /**
573 * @}
574 */
575
576 #endif /* USB_OTG_FS || USB */
577
578 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
579 * @{
580 */
581 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */
582 #if defined(RCC_PLLSAI1_SUPPORT)
583 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */
584 #endif /* RCC_PLLSAI1_SUPPORT */
585 #if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
586 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */
587 #endif /* RCC_PLLSAI2_SUPPORT */
588 #if defined(RCC_CCIPR_ADCSEL)
589 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */
590 #else
591 #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x30000000U /*!< SYSCLK clock used as ADC clock source */
592 #endif
593 /**
594 * @}
595 */
596
597 #if defined(SWPMI1)
598 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection
599 * @{
600 */
601 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 used as SWPMI1 clock source */
602 #define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /*!< HSI used as SWPMI1 clock source */
603 /**
604 * @}
605 */
606 #endif /* SWPMI1 */
607
608 #if defined(DFSDM1_Channel0)
609 #if defined(RCC_CCIPR2_ADFSDM1SEL)
610 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection
611 * @{
612 */
613 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
614 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */
615 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */
616 /**
617 * @}
618 */
619 #endif /* RCC_CCIPR2_ADFSDM1SEL */
620
621 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
622 * @{
623 */
624 #if defined(RCC_CCIPR2_DFSDM1SEL)
625 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
626 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
627 #else
628 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */
629 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */
630 #endif /* RCC_CCIPR2_DFSDM1SEL */
631 /**
632 * @}
633 */
634 #endif /* DFSDM1_Channel0 */
635
636 #if defined(DSI)
637 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
638 * @{
639 */
640 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
641 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */
642 /**
643 * @}
644 */
645 #endif /* DSI */
646
647 #if defined(LTDC)
648 /** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
649 * @{
650 */
651 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */
652 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */
653 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */
654 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */
655 /**
656 * @}
657 */
658 #endif /* LTDC */
659
660 #if defined(OCTOSPI1)
661 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
662 * @{
663 */
664 #define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */
665 #define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */
666 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */
667 /**
668 * @}
669 */
670 #endif /* OCTOSPI1 */
671
672 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
673 * @{
674 */
675 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
676 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
677 #if defined(RCC_CCIPR_USART3SEL)
678 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
679 #endif /* RCC_CCIPR_USART3SEL */
680 /**
681 * @}
682 */
683
684 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
685 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
686 * @{
687 */
688 #if defined(RCC_CCIPR_UART4SEL)
689 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
690 #endif /* RCC_CCIPR_UART4SEL */
691 #if defined(RCC_CCIPR_UART5SEL)
692 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
693 #endif /* RCC_CCIPR_UART5SEL */
694 /**
695 * @}
696 */
697 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
698
699 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
700 * @{
701 */
702 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
703 /**
704 * @}
705 */
706
707 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
708 * @{
709 */
710 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
711 #if defined(RCC_CCIPR_I2C2SEL)
712 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
713 #endif /* RCC_CCIPR_I2C2SEL */
714 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
715 #if defined(RCC_CCIPR2_I2C4SEL)
716 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
717 #endif /* RCC_CCIPR2_I2C4SEL */
718 /**
719 * @}
720 */
721
722 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
723 * @{
724 */
725 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
726 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
727 /**
728 * @}
729 */
730
731 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
732 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
733 * @{
734 */
735 #if defined(RCC_CCIPR2_SAI1SEL)
736 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
737 #else
738 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
739 #endif /* RCC_CCIPR2_SAI1SEL */
740 #if defined(RCC_CCIPR2_SAI2SEL)
741 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */
742 #elif defined(RCC_CCIPR_SAI2SEL)
743 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */
744 #endif /* RCC_CCIPR2_SAI2SEL */
745 /**
746 * @}
747 */
748 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
749
750 #if defined(SDMMC1)
751 #if defined(RCC_CCIPR2_SDMMCSEL)
752 /** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
753 * @{
754 */
755 #define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */
756 /**
757 * @}
758 */
759 #endif /* RCC_CCIPR2_SDMMCSEL */
760
761 /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
762 * @{
763 */
764 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */
765 /**
766 * @}
767 */
768 #endif /* SDMMC1 */
769
770 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
771 * @{
772 */
773 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
774 /**
775 * @}
776 */
777
778 #if defined(USB_OTG_FS) || defined(USB)
779 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
780 * @{
781 */
782 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
783 /**
784 * @}
785 */
786 #endif /* USB_OTG_FS || USB */
787
788 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
789 * @{
790 */
791 #if defined(RCC_CCIPR_ADCSEL)
792 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */
793 #else
794 #define LL_RCC_ADC_CLKSOURCE 0x30000000U /*!< ADC Clock source selection */
795 #endif
796 /**
797 * @}
798 */
799
800 #if defined(SWPMI1)
801 /** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source
802 * @{
803 */
804 #define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */
805 /**
806 * @}
807 */
808 #endif /* SWPMI1 */
809
810 #if defined(DFSDM1_Channel0)
811 #if defined(RCC_CCIPR2_ADFSDM1SEL)
812 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source
813 * @{
814 */
815 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
816 /**
817 * @}
818 */
819
820 #endif /* RCC_CCIPR2_ADFSDM1SEL */
821 /** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
822 * @{
823 */
824 #if defined(RCC_CCIPR2_DFSDM1SEL)
825 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */
826 #else
827 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */
828 #endif /* RCC_CCIPR2_DFSDM1SEL */
829 /**
830 * @}
831 */
832 #endif /* DFSDM1_Channel0 */
833
834 #if defined(DSI)
835 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
836 * @{
837 */
838 #define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */
839 /**
840 * @}
841 */
842 #endif /* DSI */
843
844 #if defined(LTDC)
845 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
846 * @{
847 */
848 #define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */
849 /**
850 * @}
851 */
852 #endif /* LTDC */
853
854 #if defined(OCTOSPI1)
855 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
856 * @{
857 */
858 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */
859 /**
860 * @}
861 */
862 #endif /* OCTOSPI1 */
863
864
865 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
866 * @{
867 */
868 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
869 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
870 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
871 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
872 /**
873 * @}
874 */
875
876
877 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
878 * @{
879 */
880 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
881 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
882 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
883 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
884 /**
885 * @}
886 */
887
888 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
889 * @{
890 */
891 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */
892 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */
893 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */
894 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */
895 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */
896 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */
897 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */
898 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */
899 #if defined(RCC_PLLM_DIV_1_16_SUPPORT)
900 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */
901 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */
902 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */
903 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */
904 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */
905 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */
906 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */
907 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */
908 #endif /* RCC_PLLM_DIV_1_16_SUPPORT */
909 /**
910 * @}
911 */
912
913 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
914 * @{
915 */
916 #define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
917 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
918 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
919 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
920 /**
921 * @}
922 */
923
924 #if defined(RCC_PLLP_SUPPORT)
925 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
926 * @{
927 */
928 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
929 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
930 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
931 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
932 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
933 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
934 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
935 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
936 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
937 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
938 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
939 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
940 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
941 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
942 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
943 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
944 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
945 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
946 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
947 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
948 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
949 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
950 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
951 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
952 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
953 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
954 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
955 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
956 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
957 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
958 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
959 #else
960 #define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */
961 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */
962 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
963 /**
964 * @}
965 */
966 #endif /* RCC_PLLP_SUPPORT */
967
968 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
969 * @{
970 */
971 #define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
972 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
973 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
974 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
975 /**
976 * @}
977 */
978
979 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
980 /** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
981 * @{
982 */
983 #define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */
984 #define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */
985 #define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */
986 #define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */
987 #define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */
988 #define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */
989 #define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */
990 #define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */
991 #define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */
992 #define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */
993 #define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */
994 #define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */
995 #define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */
996 #define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */
997 #define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */
998 #define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */
999 /**
1000 * @}
1001 */
1002 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1003
1004 #if defined(RCC_PLLSAI1_SUPPORT)
1005 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
1006 * @{
1007 */
1008 #define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
1009 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
1010 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
1011 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
1012 /**
1013 * @}
1014 */
1015
1016 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
1017 * @{
1018 */
1019 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1020 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */
1021 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */
1022 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */
1023 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */
1024 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */
1025 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
1026 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */
1027 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */
1028 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */
1029 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */
1030 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */
1031 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */
1032 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */
1033 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */
1034 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */
1035 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
1036 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */
1037 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */
1038 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */
1039 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */
1040 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */
1041 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */
1042 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */
1043 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */
1044 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */
1045 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */
1046 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */
1047 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */
1048 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */
1049 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
1050 #else
1051 #define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */
1052 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */
1053 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
1054 /**
1055 * @}
1056 */
1057
1058 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
1059 * @{
1060 */
1061 #define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
1062 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
1063 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
1064 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
1065 /**
1066 * @}
1067 */
1068 #endif /* RCC_PLLSAI1_SUPPORT */
1069
1070 #if defined(RCC_PLLSAI2_SUPPORT)
1071 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1072 /** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M)
1073 * @{
1074 */
1075 #define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */
1076 #define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */
1077 #define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */
1078 #define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */
1079 #define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */
1080 #define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */
1081 #define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */
1082 #define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */
1083 #define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */
1084 #define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */
1085 #define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */
1086 #define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */
1087 #define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */
1088 #define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */
1089 #define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */
1090 #define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */
1091 /**
1092 * @}
1093 */
1094 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
1095
1096 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
1097 /** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q)
1098 * @{
1099 */
1100 #define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */
1101 #define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */
1102 #define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */
1103 #define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */
1104 /**
1105 * @}
1106 */
1107 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
1108
1109 /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
1110 * @{
1111 */
1112 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1113 #define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */
1114 #define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */
1115 #define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */
1116 #define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */
1117 #define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */
1118 #define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
1119 #define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */
1120 #define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */
1121 #define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */
1122 #define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */
1123 #define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */
1124 #define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */
1125 #define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */
1126 #define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */
1127 #define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */
1128 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
1129 #define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */
1130 #define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */
1131 #define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */
1132 #define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */
1133 #define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */
1134 #define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */
1135 #define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */
1136 #define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */
1137 #define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */
1138 #define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */
1139 #define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */
1140 #define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */
1141 #define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */
1142 #define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */
1143 #else
1144 #define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */
1145 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */
1146 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
1147 /**
1148 * @}
1149 */
1150
1151 /** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
1152 * @{
1153 */
1154 #define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */
1155 #define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */
1156 #define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */
1157 #define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */
1158 /**
1159 * @}
1160 */
1161
1162 #if defined(RCC_CCIPR2_PLLSAI2DIVR)
1163 /** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR)
1164 * @{
1165 */
1166 #define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */
1167 #define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */
1168 #define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */
1169 #define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */
1170 /**
1171 * @}
1172 */
1173 #endif /* RCC_CCIPR2_PLLSAI2DIVR */
1174 #endif /* RCC_PLLSAI2_SUPPORT */
1175
1176 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
1177 * @{
1178 */
1179 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
1180 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
1181 /**
1182 * @}
1183 */
1184
1185 #if defined(RCC_CSR_LSIPREDIV)
1186 /** @defgroup RCC_LL_EC_LSIPREDIV LSI division factor
1187 * @{
1188 */
1189 #define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */
1190 #define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPREDIV /*!< LSI division factor by 128 */
1191 /**
1192 * @}
1193 */
1194 #endif /* RCC_CSR_LSIPREDIV */
1195
1196 /** Legacy definitions for compatibility purpose
1197 @cond 0
1198 */
1199 #if defined(DFSDM1_Channel0)
1200 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
1201 #define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
1202 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
1203 #define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
1204 #endif /* DFSDM1_Channel0 */
1205 #if defined(SWPMI1)
1206 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
1207 #endif /* SWPMI1 */
1208 /**
1209 @endcond
1210 */
1211
1212 /**
1213 * @}
1214 */
1215
1216 /* Exported macro ------------------------------------------------------------*/
1217 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1218 * @{
1219 */
1220
1221 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1222 * @{
1223 */
1224
1225 /**
1226 * @brief Write a value in RCC register
1227 * @param __REG__ Register to be written
1228 * @param __VALUE__ Value to be written in the register
1229 * @retval None
1230 */
1231 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1232
1233 /**
1234 * @brief Read a value in RCC register
1235 * @param __REG__ Register to be read
1236 * @retval Register value
1237 */
1238 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1244 * @{
1245 */
1246
1247 /**
1248 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1249 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1250 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1251 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1252 * @param __PLLM__ This parameter can be one of the following values:
1253 * @arg @ref LL_RCC_PLLM_DIV_1
1254 * @arg @ref LL_RCC_PLLM_DIV_2
1255 * @arg @ref LL_RCC_PLLM_DIV_3
1256 * @arg @ref LL_RCC_PLLM_DIV_4
1257 * @arg @ref LL_RCC_PLLM_DIV_5
1258 * @arg @ref LL_RCC_PLLM_DIV_6
1259 * @arg @ref LL_RCC_PLLM_DIV_7
1260 * @arg @ref LL_RCC_PLLM_DIV_8
1261 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
1262 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
1263 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
1264 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
1265 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
1266 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
1267 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
1268 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
1269 *
1270 * (*) value not defined in all devices.
1271 * @param __PLLN__ Between 8 and 86
1272 * @param __PLLR__ This parameter can be one of the following values:
1273 * @arg @ref LL_RCC_PLLR_DIV_2
1274 * @arg @ref LL_RCC_PLLR_DIV_4
1275 * @arg @ref LL_RCC_PLLR_DIV_6
1276 * @arg @ref LL_RCC_PLLR_DIV_8
1277 * @retval PLL clock frequency (in Hz)
1278 */
1279 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1280 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
1281
1282 #if defined(RCC_PLLSAI1_SUPPORT)
1283 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
1284 /**
1285 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
1286 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1287 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1288 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1289 * @param __PLLM__ This parameter can be one of the following values:
1290 * @arg @ref LL_RCC_PLLM_DIV_1
1291 * @arg @ref LL_RCC_PLLM_DIV_2
1292 * @arg @ref LL_RCC_PLLM_DIV_3
1293 * @arg @ref LL_RCC_PLLM_DIV_4
1294 * @arg @ref LL_RCC_PLLM_DIV_5
1295 * @arg @ref LL_RCC_PLLM_DIV_6
1296 * @arg @ref LL_RCC_PLLM_DIV_7
1297 * @arg @ref LL_RCC_PLLM_DIV_8
1298 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
1299 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
1300 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
1301 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
1302 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
1303 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
1304 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
1305 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
1306 *
1307 * (*) value not defined in all devices.
1308 * @param __PLLN__ Between 8 and 86
1309 * @param __PLLP__ This parameter can be one of the following values:
1310 * @arg @ref LL_RCC_PLLP_DIV_2
1311 * @arg @ref LL_RCC_PLLP_DIV_3
1312 * @arg @ref LL_RCC_PLLP_DIV_4
1313 * @arg @ref LL_RCC_PLLP_DIV_5
1314 * @arg @ref LL_RCC_PLLP_DIV_6
1315 * @arg @ref LL_RCC_PLLP_DIV_7
1316 * @arg @ref LL_RCC_PLLP_DIV_8
1317 * @arg @ref LL_RCC_PLLP_DIV_9
1318 * @arg @ref LL_RCC_PLLP_DIV_10
1319 * @arg @ref LL_RCC_PLLP_DIV_11
1320 * @arg @ref LL_RCC_PLLP_DIV_12
1321 * @arg @ref LL_RCC_PLLP_DIV_13
1322 * @arg @ref LL_RCC_PLLP_DIV_14
1323 * @arg @ref LL_RCC_PLLP_DIV_15
1324 * @arg @ref LL_RCC_PLLP_DIV_16
1325 * @arg @ref LL_RCC_PLLP_DIV_17
1326 * @arg @ref LL_RCC_PLLP_DIV_18
1327 * @arg @ref LL_RCC_PLLP_DIV_19
1328 * @arg @ref LL_RCC_PLLP_DIV_20
1329 * @arg @ref LL_RCC_PLLP_DIV_21
1330 * @arg @ref LL_RCC_PLLP_DIV_22
1331 * @arg @ref LL_RCC_PLLP_DIV_23
1332 * @arg @ref LL_RCC_PLLP_DIV_24
1333 * @arg @ref LL_RCC_PLLP_DIV_25
1334 * @arg @ref LL_RCC_PLLP_DIV_26
1335 * @arg @ref LL_RCC_PLLP_DIV_27
1336 * @arg @ref LL_RCC_PLLP_DIV_28
1337 * @arg @ref LL_RCC_PLLP_DIV_29
1338 * @arg @ref LL_RCC_PLLP_DIV_30
1339 * @arg @ref LL_RCC_PLLP_DIV_31
1340 * @retval PLL clock frequency (in Hz)
1341 */
1342 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1343 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
1344
1345 #else
1346 /**
1347 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
1348 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1349 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1350 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1351 * @param __PLLM__ This parameter can be one of the following values:
1352 * @arg @ref LL_RCC_PLLM_DIV_1
1353 * @arg @ref LL_RCC_PLLM_DIV_2
1354 * @arg @ref LL_RCC_PLLM_DIV_3
1355 * @arg @ref LL_RCC_PLLM_DIV_4
1356 * @arg @ref LL_RCC_PLLM_DIV_5
1357 * @arg @ref LL_RCC_PLLM_DIV_6
1358 * @arg @ref LL_RCC_PLLM_DIV_7
1359 * @arg @ref LL_RCC_PLLM_DIV_8
1360 * @param __PLLN__ Between 8 and 86
1361 * @param __PLLP__ This parameter can be one of the following values:
1362 * @arg @ref LL_RCC_PLLP_DIV_7
1363 * @arg @ref LL_RCC_PLLP_DIV_17
1364 * @retval PLL clock frequency (in Hz)
1365 */
1366 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1367 (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
1368
1369 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
1370 #endif /* RCC_PLLSAI1_SUPPORT */
1371
1372 /**
1373 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1374 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1375 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1376 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1377 * @param __PLLM__ This parameter can be one of the following values:
1378 * @arg @ref LL_RCC_PLLM_DIV_1
1379 * @arg @ref LL_RCC_PLLM_DIV_2
1380 * @arg @ref LL_RCC_PLLM_DIV_3
1381 * @arg @ref LL_RCC_PLLM_DIV_4
1382 * @arg @ref LL_RCC_PLLM_DIV_5
1383 * @arg @ref LL_RCC_PLLM_DIV_6
1384 * @arg @ref LL_RCC_PLLM_DIV_7
1385 * @arg @ref LL_RCC_PLLM_DIV_8
1386 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
1387 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
1388 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
1389 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
1390 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
1391 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
1392 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
1393 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
1394 *
1395 * (*) value not defined in all devices.
1396 * @param __PLLN__ Between 8 and 86
1397 * @param __PLLQ__ This parameter can be one of the following values:
1398 * @arg @ref LL_RCC_PLLQ_DIV_2
1399 * @arg @ref LL_RCC_PLLQ_DIV_4
1400 * @arg @ref LL_RCC_PLLQ_DIV_6
1401 * @arg @ref LL_RCC_PLLQ_DIV_8
1402 * @retval PLL clock frequency (in Hz)
1403 */
1404 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
1405 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
1406
1407 #if defined(RCC_PLLSAI1_SUPPORT)
1408 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1409 /**
1410 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
1411 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1412 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1413 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1414 * @param __PLLSAI1M__ This parameter can be one of the following values:
1415 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1416 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1417 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1418 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1419 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1420 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1421 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1422 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1423 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1424 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1425 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1426 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1427 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1428 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1429 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1430 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1431 * @param __PLLSAI1N__ Between 8 and 86
1432 * @param __PLLSAI1P__ This parameter can be one of the following values:
1433 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1434 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1435 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1436 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1437 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1438 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1439 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1440 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1441 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1442 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1443 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1444 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1445 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1446 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1447 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1448 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1449 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1450 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1451 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1452 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1453 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1454 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1455 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1456 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1457 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1458 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1459 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1460 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1461 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1462 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1463 * @retval PLLSAI1 clock frequency (in Hz)
1464 */
1465 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
1466 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1467 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
1468
1469 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
1470 /**
1471 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
1472 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1473 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1474 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1475 * @param __PLLM__ This parameter can be one of the following values:
1476 * @arg @ref LL_RCC_PLLM_DIV_1
1477 * @arg @ref LL_RCC_PLLM_DIV_2
1478 * @arg @ref LL_RCC_PLLM_DIV_3
1479 * @arg @ref LL_RCC_PLLM_DIV_4
1480 * @arg @ref LL_RCC_PLLM_DIV_5
1481 * @arg @ref LL_RCC_PLLM_DIV_6
1482 * @arg @ref LL_RCC_PLLM_DIV_7
1483 * @arg @ref LL_RCC_PLLM_DIV_8
1484 * @param __PLLSAI1N__ Between 8 and 86
1485 * @param __PLLSAI1P__ This parameter can be one of the following values:
1486 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
1487 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
1488 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
1489 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
1490 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
1491 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1492 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
1493 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
1494 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
1495 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
1496 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
1497 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
1498 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
1499 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
1500 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
1501 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1502 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
1503 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
1504 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
1505 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
1506 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
1507 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
1508 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
1509 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
1510 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
1511 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
1512 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
1513 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
1514 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
1515 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
1516 * @retval PLLSAI1 clock frequency (in Hz)
1517 */
1518 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1519 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1520 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
1521
1522 #else
1523 /**
1524 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
1525 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1526 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
1527 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1528 * @param __PLLM__ This parameter can be one of the following values:
1529 * @arg @ref LL_RCC_PLLM_DIV_1
1530 * @arg @ref LL_RCC_PLLM_DIV_2
1531 * @arg @ref LL_RCC_PLLM_DIV_3
1532 * @arg @ref LL_RCC_PLLM_DIV_4
1533 * @arg @ref LL_RCC_PLLM_DIV_5
1534 * @arg @ref LL_RCC_PLLM_DIV_6
1535 * @arg @ref LL_RCC_PLLM_DIV_7
1536 * @arg @ref LL_RCC_PLLM_DIV_8
1537 * @param __PLLSAI1N__ Between 8 and 86
1538 * @param __PLLSAI1P__ This parameter can be one of the following values:
1539 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
1540 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
1541 * @retval PLLSAI1 clock frequency (in Hz)
1542 */
1543 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
1544 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1545 (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
1546
1547 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
1548
1549 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1550 /**
1551 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
1552 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1553 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1554 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1555 * @param __PLLSAI1M__ This parameter can be one of the following values:
1556 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1557 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1558 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1559 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1560 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1561 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1562 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1563 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1564 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1565 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1566 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1567 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1568 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1569 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1570 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1571 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1572 * @param __PLLSAI1N__ Between 8 and 86
1573 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1574 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1575 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1576 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1577 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1578 * @retval PLLSAI1 clock frequency (in Hz)
1579 */
1580 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
1581 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1582 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
1583
1584 #else
1585 /**
1586 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
1587 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1588 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
1589 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1590 * @param __PLLM__ This parameter can be one of the following values:
1591 * @arg @ref LL_RCC_PLLM_DIV_1
1592 * @arg @ref LL_RCC_PLLM_DIV_2
1593 * @arg @ref LL_RCC_PLLM_DIV_3
1594 * @arg @ref LL_RCC_PLLM_DIV_4
1595 * @arg @ref LL_RCC_PLLM_DIV_5
1596 * @arg @ref LL_RCC_PLLM_DIV_6
1597 * @arg @ref LL_RCC_PLLM_DIV_7
1598 * @arg @ref LL_RCC_PLLM_DIV_8
1599 * @param __PLLSAI1N__ Between 8 and 86
1600 * @param __PLLSAI1Q__ This parameter can be one of the following values:
1601 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
1602 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
1603 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
1604 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
1605 * @retval PLLSAI1 clock frequency (in Hz)
1606 */
1607 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
1608 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1609 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
1610
1611 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1612
1613 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
1614 /**
1615 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
1616 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
1617 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1618 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1619 * @param __PLLSAI1M__ This parameter can be one of the following values:
1620 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
1621 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
1622 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
1623 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
1624 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
1625 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
1626 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
1627 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
1628 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
1629 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
1630 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
1631 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
1632 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
1633 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
1634 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
1635 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
1636 * @param __PLLSAI1N__ Between 8 and 86
1637 * @param __PLLSAI1R__ This parameter can be one of the following values:
1638 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1639 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1640 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1641 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1642 * @retval PLLSAI1 clock frequency (in Hz)
1643 */
1644 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
1645 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
1646 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
1647
1648 #else
1649 /**
1650 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
1651 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1652 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
1653 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1654 * @param __PLLM__ This parameter can be one of the following values:
1655 * @arg @ref LL_RCC_PLLM_DIV_1
1656 * @arg @ref LL_RCC_PLLM_DIV_2
1657 * @arg @ref LL_RCC_PLLM_DIV_3
1658 * @arg @ref LL_RCC_PLLM_DIV_4
1659 * @arg @ref LL_RCC_PLLM_DIV_5
1660 * @arg @ref LL_RCC_PLLM_DIV_6
1661 * @arg @ref LL_RCC_PLLM_DIV_7
1662 * @arg @ref LL_RCC_PLLM_DIV_8
1663 * @param __PLLSAI1N__ Between 8 and 86
1664 * @param __PLLSAI1R__ This parameter can be one of the following values:
1665 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
1666 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
1667 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
1668 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
1669 * @retval PLLSAI1 clock frequency (in Hz)
1670 */
1671 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
1672 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
1673 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
1674
1675 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
1676 #endif /* RCC_PLLSAI1_SUPPORT */
1677
1678 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1679 /**
1680 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
1681 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
1682 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
1683 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1684 * @param __PLLSAI2M__ This parameter can be one of the following values:
1685 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
1686 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
1687 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
1688 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
1689 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
1690 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
1691 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
1692 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
1693 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
1694 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
1695 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
1696 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
1697 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
1698 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
1699 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
1700 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
1701 * @param __PLLSAI2N__ Between 8 and 86
1702 * @param __PLLSAI2P__ This parameter can be one of the following values:
1703 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
1704 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
1705 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
1706 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
1707 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
1708 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
1709 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
1710 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
1711 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
1712 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
1713 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
1714 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
1715 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
1716 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
1717 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
1718 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
1719 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
1720 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
1721 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
1722 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
1723 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
1724 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
1725 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
1726 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
1727 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
1728 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
1729 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
1730 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
1731 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
1732 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
1733 * @retval PLLSAI2 clock frequency (in Hz)
1734 */
1735 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
1736 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1737 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
1738
1739 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
1740 /**
1741 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
1742 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1743 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
1744 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1745 * @param __PLLM__ This parameter can be one of the following values:
1746 * @arg @ref LL_RCC_PLLM_DIV_1
1747 * @arg @ref LL_RCC_PLLM_DIV_2
1748 * @arg @ref LL_RCC_PLLM_DIV_3
1749 * @arg @ref LL_RCC_PLLM_DIV_4
1750 * @arg @ref LL_RCC_PLLM_DIV_5
1751 * @arg @ref LL_RCC_PLLM_DIV_6
1752 * @arg @ref LL_RCC_PLLM_DIV_7
1753 * @arg @ref LL_RCC_PLLM_DIV_8
1754 * @param __PLLSAI2N__ Between 8 and 86
1755 * @param __PLLSAI2P__ This parameter can be one of the following values:
1756 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
1757 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
1758 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
1759 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
1760 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
1761 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
1762 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
1763 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
1764 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
1765 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
1766 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
1767 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
1768 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
1769 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
1770 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
1771 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
1772 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
1773 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
1774 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
1775 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
1776 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
1777 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
1778 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
1779 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
1780 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
1781 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
1782 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
1783 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
1784 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
1785 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
1786 * @retval PLLSAI2 clock frequency (in Hz)
1787 */
1788 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
1789 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
1790 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
1791
1792 #else
1793 /**
1794 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
1795 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1796 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
1797 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1798 * @param __PLLM__ This parameter can be one of the following values:
1799 * @arg @ref LL_RCC_PLLM_DIV_1
1800 * @arg @ref LL_RCC_PLLM_DIV_2
1801 * @arg @ref LL_RCC_PLLM_DIV_3
1802 * @arg @ref LL_RCC_PLLM_DIV_4
1803 * @arg @ref LL_RCC_PLLM_DIV_5
1804 * @arg @ref LL_RCC_PLLM_DIV_6
1805 * @arg @ref LL_RCC_PLLM_DIV_7
1806 * @arg @ref LL_RCC_PLLM_DIV_8
1807 * @param __PLLSAI2N__ Between 8 and 86
1808 * @param __PLLSAI2P__ This parameter can be one of the following values:
1809 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
1810 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
1811 * @retval PLLSAI2 clock frequency (in Hz)
1812 */
1813 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
1814 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
1815 (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
1816
1817 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
1818
1819 #if defined(LTDC)
1820 /**
1821 * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain
1822 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
1823 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());
1824 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
1825 * @param __PLLSAI2M__ This parameter can be one of the following values:
1826 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
1827 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
1828 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
1829 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
1830 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
1831 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
1832 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
1833 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
1834 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
1835 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
1836 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
1837 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
1838 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
1839 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
1840 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
1841 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
1842 * @param __PLLSAI2N__ Between 8 and 86
1843 * @param __PLLSAI2R__ This parameter can be one of the following values:
1844 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
1845 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
1846 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
1847 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
1848 * @param __PLLSAI2DIVR__ This parameter can be one of the following values:
1849 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
1850 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
1851 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
1852 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
1853 * @retval PLLSAI2 clock frequency (in Hz)
1854 */
1855 #define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
1856 (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1857 (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (2UL << ((__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos))))
1858 #elif defined(RCC_PLLSAI2_SUPPORT)
1859 /**
1860 * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
1861 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1862 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
1863 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
1864 * @param __PLLM__ This parameter can be one of the following values:
1865 * @arg @ref LL_RCC_PLLM_DIV_1
1866 * @arg @ref LL_RCC_PLLM_DIV_2
1867 * @arg @ref LL_RCC_PLLM_DIV_3
1868 * @arg @ref LL_RCC_PLLM_DIV_4
1869 * @arg @ref LL_RCC_PLLM_DIV_5
1870 * @arg @ref LL_RCC_PLLM_DIV_6
1871 * @arg @ref LL_RCC_PLLM_DIV_7
1872 * @arg @ref LL_RCC_PLLM_DIV_8
1873 * @param __PLLSAI2N__ Between 8 and 86
1874 * @param __PLLSAI2R__ This parameter can be one of the following values:
1875 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
1876 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
1877 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
1878 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
1879 * @retval PLLSAI2 clock frequency (in Hz)
1880 */
1881 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
1882 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
1883 ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
1884
1885 #endif /* LTDC */
1886
1887 #if defined(DSI)
1888 /**
1889 * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI
1890 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
1891 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());
1892 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
1893 * @param __PLLSAI2M__ This parameter can be one of the following values:
1894 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
1895 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
1896 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
1897 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
1898 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
1899 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
1900 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
1901 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
1902 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
1903 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
1904 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
1905 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
1906 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
1907 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
1908 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
1909 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
1910 * @param __PLLSAI2N__ Between 8 and 86
1911 * @param __PLLSAI2Q__ This parameter can be one of the following values:
1912 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
1913 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
1914 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
1915 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
1916 * @retval PLL clock frequency (in Hz)
1917 */
1918 #define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
1919 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
1920 ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
1921 #endif /* DSI */
1922
1923
1924
1925 /**
1926 * @brief Helper macro to calculate the HCLK frequency
1927 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
1928 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1929 * @arg @ref LL_RCC_SYSCLK_DIV_1
1930 * @arg @ref LL_RCC_SYSCLK_DIV_2
1931 * @arg @ref LL_RCC_SYSCLK_DIV_4
1932 * @arg @ref LL_RCC_SYSCLK_DIV_8
1933 * @arg @ref LL_RCC_SYSCLK_DIV_16
1934 * @arg @ref LL_RCC_SYSCLK_DIV_64
1935 * @arg @ref LL_RCC_SYSCLK_DIV_128
1936 * @arg @ref LL_RCC_SYSCLK_DIV_256
1937 * @arg @ref LL_RCC_SYSCLK_DIV_512
1938 * @retval HCLK clock frequency (in Hz)
1939 */
1940 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1941
1942 /**
1943 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1944 * @param __HCLKFREQ__ HCLK frequency
1945 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1946 * @arg @ref LL_RCC_APB1_DIV_1
1947 * @arg @ref LL_RCC_APB1_DIV_2
1948 * @arg @ref LL_RCC_APB1_DIV_4
1949 * @arg @ref LL_RCC_APB1_DIV_8
1950 * @arg @ref LL_RCC_APB1_DIV_16
1951 * @retval PCLK1 clock frequency (in Hz)
1952 */
1953 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
1954
1955 /**
1956 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1957 * @param __HCLKFREQ__ HCLK frequency
1958 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1959 * @arg @ref LL_RCC_APB2_DIV_1
1960 * @arg @ref LL_RCC_APB2_DIV_2
1961 * @arg @ref LL_RCC_APB2_DIV_4
1962 * @arg @ref LL_RCC_APB2_DIV_8
1963 * @arg @ref LL_RCC_APB2_DIV_16
1964 * @retval PCLK2 clock frequency (in Hz)
1965 */
1966 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1967
1968 /**
1969 * @brief Helper macro to calculate the MSI frequency (in Hz)
1970 * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
1971 * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
1972 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
1973 * else by LL_RCC_MSI_GetRange()
1974 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1975 * (LL_RCC_MSI_IsEnabledRangeSelect()?
1976 * LL_RCC_MSI_GetRange():
1977 * LL_RCC_MSI_GetRangeAfterStandby()))
1978 * @param __MSISEL__ This parameter can be one of the following values:
1979 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
1980 * @arg @ref LL_RCC_MSIRANGESEL_RUN
1981 * @param __MSIRANGE__ This parameter can be one of the following values:
1982 * @arg @ref LL_RCC_MSIRANGE_0
1983 * @arg @ref LL_RCC_MSIRANGE_1
1984 * @arg @ref LL_RCC_MSIRANGE_2
1985 * @arg @ref LL_RCC_MSIRANGE_3
1986 * @arg @ref LL_RCC_MSIRANGE_4
1987 * @arg @ref LL_RCC_MSIRANGE_5
1988 * @arg @ref LL_RCC_MSIRANGE_6
1989 * @arg @ref LL_RCC_MSIRANGE_7
1990 * @arg @ref LL_RCC_MSIRANGE_8
1991 * @arg @ref LL_RCC_MSIRANGE_9
1992 * @arg @ref LL_RCC_MSIRANGE_10
1993 * @arg @ref LL_RCC_MSIRANGE_11
1994 * @arg @ref LL_RCC_MSISRANGE_4
1995 * @arg @ref LL_RCC_MSISRANGE_5
1996 * @arg @ref LL_RCC_MSISRANGE_6
1997 * @arg @ref LL_RCC_MSISRANGE_7
1998 * @retval MSI clock frequency (in Hz)
1999 */
2000 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
2001 (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
2002 (MSIRangeTable[(__MSIRANGE__) >> 4U]))
2003
2004 /**
2005 * @}
2006 */
2007
2008 /**
2009 * @}
2010 */
2011
2012 /* Exported functions --------------------------------------------------------*/
2013 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
2014 * @{
2015 */
2016
2017 /** @defgroup RCC_LL_EF_HSE HSE
2018 * @{
2019 */
2020
2021 /**
2022 * @brief Enable the Clock Security System.
2023 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
2024 * @retval None
2025 */
LL_RCC_HSE_EnableCSS(void)2026 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2027 {
2028 SET_BIT(RCC->CR, RCC_CR_CSSON);
2029 }
2030
2031 /**
2032 * @brief Enable HSE external oscillator (HSE Bypass)
2033 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
2034 * @retval None
2035 */
LL_RCC_HSE_EnableBypass(void)2036 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2037 {
2038 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2039 }
2040
2041 /**
2042 * @brief Disable HSE external oscillator (HSE Bypass)
2043 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
2044 * @retval None
2045 */
LL_RCC_HSE_DisableBypass(void)2046 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2047 {
2048 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2049 }
2050
2051 /**
2052 * @brief Enable HSE crystal oscillator (HSE ON)
2053 * @rmtoll CR HSEON LL_RCC_HSE_Enable
2054 * @retval None
2055 */
LL_RCC_HSE_Enable(void)2056 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2057 {
2058 SET_BIT(RCC->CR, RCC_CR_HSEON);
2059 }
2060
2061 /**
2062 * @brief Disable HSE crystal oscillator (HSE ON)
2063 * @rmtoll CR HSEON LL_RCC_HSE_Disable
2064 * @retval None
2065 */
LL_RCC_HSE_Disable(void)2066 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2067 {
2068 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2069 }
2070
2071 /**
2072 * @brief Check if HSE oscillator Ready
2073 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2074 * @retval State of bit (1 or 0).
2075 */
LL_RCC_HSE_IsReady(void)2076 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2077 {
2078 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
2079 }
2080
2081 /**
2082 * @}
2083 */
2084
2085 /** @defgroup RCC_LL_EF_HSI HSI
2086 * @{
2087 */
2088
2089 /**
2090 * @brief Enable HSI even in stop mode
2091 * @note HSI oscillator is forced ON even in Stop mode
2092 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
2093 * @retval None
2094 */
LL_RCC_HSI_EnableInStopMode(void)2095 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
2096 {
2097 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
2098 }
2099
2100 /**
2101 * @brief Disable HSI in stop mode
2102 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
2103 * @retval None
2104 */
LL_RCC_HSI_DisableInStopMode(void)2105 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
2106 {
2107 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
2108 }
2109
2110 /**
2111 * @brief Check if HSI is enabled in stop mode
2112 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
2113 * @retval State of bit (1 or 0).
2114 */
LL_RCC_HSI_IsEnabledInStopMode(void)2115 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
2116 {
2117 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
2118 }
2119
2120 /**
2121 * @brief Enable HSI oscillator
2122 * @rmtoll CR HSION LL_RCC_HSI_Enable
2123 * @retval None
2124 */
LL_RCC_HSI_Enable(void)2125 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2126 {
2127 SET_BIT(RCC->CR, RCC_CR_HSION);
2128 }
2129
2130 /**
2131 * @brief Disable HSI oscillator
2132 * @rmtoll CR HSION LL_RCC_HSI_Disable
2133 * @retval None
2134 */
LL_RCC_HSI_Disable(void)2135 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2136 {
2137 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
2138 }
2139
2140 /**
2141 * @brief Check if HSI clock is ready
2142 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
2143 * @retval State of bit (1 or 0).
2144 */
LL_RCC_HSI_IsReady(void)2145 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
2146 {
2147 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
2148 }
2149
2150 /**
2151 * @brief Enable HSI Automatic from stop mode
2152 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
2153 * @retval None
2154 */
LL_RCC_HSI_EnableAutoFromStop(void)2155 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
2156 {
2157 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
2158 }
2159
2160 /**
2161 * @brief Disable HSI Automatic from stop mode
2162 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
2163 * @retval None
2164 */
LL_RCC_HSI_DisableAutoFromStop(void)2165 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
2166 {
2167 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
2168 }
2169 /**
2170 * @brief Get HSI Calibration value
2171 * @note When HSITRIM is written, HSICAL is updated with the sum of
2172 * HSITRIM and the factory trim value
2173 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
2174 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
2175 */
LL_RCC_HSI_GetCalibration(void)2176 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
2177 {
2178 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
2179 }
2180
2181 /**
2182 * @brief Set HSI Calibration trimming
2183 * @note user-programmable trimming value that is added to the HSICAL
2184 * @note Default value is 16, which, when added to the HSICAL value,
2185 * should trim the HSI to 16 MHz +/- 1 %
2186 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
2187 * @param Value Between Min_Data = 0 and Max_Data = 31
2188 * @retval None
2189 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)2190 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
2191 {
2192 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
2193 }
2194
2195 /**
2196 * @brief Get HSI Calibration trimming
2197 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
2198 * @retval Between Min_Data = 0 and Max_Data = 31
2199 */
LL_RCC_HSI_GetCalibTrimming(void)2200 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
2201 {
2202 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
2203 }
2204
2205 /**
2206 * @}
2207 */
2208
2209 #if defined(RCC_HSI48_SUPPORT)
2210 /** @defgroup RCC_LL_EF_HSI48 HSI48
2211 * @{
2212 */
2213
2214 /**
2215 * @brief Enable HSI48
2216 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
2217 * @retval None
2218 */
LL_RCC_HSI48_Enable(void)2219 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
2220 {
2221 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2222 }
2223
2224 /**
2225 * @brief Disable HSI48
2226 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
2227 * @retval None
2228 */
LL_RCC_HSI48_Disable(void)2229 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
2230 {
2231 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
2232 }
2233
2234 /**
2235 * @brief Check if HSI48 oscillator Ready
2236 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
2237 * @retval State of bit (1 or 0).
2238 */
LL_RCC_HSI48_IsReady(void)2239 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
2240 {
2241 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL);
2242 }
2243
2244 /**
2245 * @brief Get HSI48 Calibration value
2246 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
2247 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
2248 */
LL_RCC_HSI48_GetCalibration(void)2249 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
2250 {
2251 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
2252 }
2253
2254 /**
2255 * @}
2256 */
2257 #endif /* RCC_HSI48_SUPPORT */
2258
2259 /** @defgroup RCC_LL_EF_LSE LSE
2260 * @{
2261 */
2262
2263 /**
2264 * @brief Enable Low Speed External (LSE) crystal.
2265 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2266 * @retval None
2267 */
LL_RCC_LSE_Enable(void)2268 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2269 {
2270 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2271 }
2272
2273 /**
2274 * @brief Disable Low Speed External (LSE) crystal.
2275 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2276 * @retval None
2277 */
LL_RCC_LSE_Disable(void)2278 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2279 {
2280 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2281 }
2282
2283 /**
2284 * @brief Enable external clock source (LSE bypass).
2285 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2286 * @retval None
2287 */
LL_RCC_LSE_EnableBypass(void)2288 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2289 {
2290 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2291 }
2292
2293 /**
2294 * @brief Disable external clock source (LSE bypass).
2295 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2296 * @retval None
2297 */
LL_RCC_LSE_DisableBypass(void)2298 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2299 {
2300 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2301 }
2302
2303 /**
2304 * @brief Set LSE oscillator drive capability
2305 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2306 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2307 * @param LSEDrive This parameter can be one of the following values:
2308 * @arg @ref LL_RCC_LSEDRIVE_LOW
2309 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2310 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2311 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2312 * @retval None
2313 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)2314 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2315 {
2316 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2317 }
2318
2319 /**
2320 * @brief Get LSE oscillator drive capability
2321 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2322 * @retval Returned value can be one of the following values:
2323 * @arg @ref LL_RCC_LSEDRIVE_LOW
2324 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2325 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2326 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2327 */
LL_RCC_LSE_GetDriveCapability(void)2328 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2329 {
2330 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2331 }
2332
2333 /**
2334 * @brief Enable Clock security system on LSE.
2335 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
2336 * @retval None
2337 */
LL_RCC_LSE_EnableCSS(void)2338 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2339 {
2340 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2341 }
2342
2343 /**
2344 * @brief Disable Clock security system on LSE.
2345 * @note Clock security system can be disabled only after a LSE
2346 * failure detection. In that case it MUST be disabled by software.
2347 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
2348 * @retval None
2349 */
LL_RCC_LSE_DisableCSS(void)2350 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
2351 {
2352 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2353 }
2354
2355 /**
2356 * @brief Check if LSE oscillator Ready
2357 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2358 * @retval State of bit (1 or 0).
2359 */
LL_RCC_LSE_IsReady(void)2360 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2361 {
2362 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
2363 }
2364
2365 /**
2366 * @brief Check if CSS on LSE failure Detection
2367 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
2368 * @retval State of bit (1 or 0).
2369 */
LL_RCC_LSE_IsCSSDetected(void)2370 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
2371 {
2372 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
2373 }
2374
2375 #if defined(RCC_BDCR_LSESYSDIS)
2376 /**
2377 * @brief Disable LSE oscillator propagation
2378 * @note LSE clock is not propagated to any peripheral except to RTC which remains clocked
2379 * @note A 2 LSE-clock delay is needed for LSESYSDIS setting to be taken into account
2380 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_DisablePropagation
2381 * @retval None
2382 */
LL_RCC_LSE_DisablePropagation(void)2383 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
2384 {
2385 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
2386 }
2387
2388 /**
2389 * @brief Enable LSE oscillator propagation
2390 * @note A 2 LSE-clock delay is needed for LSESYSDIS resetting to be taken into account
2391 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_EnablePropagation
2392 * @retval None
2393 */
LL_RCC_LSE_EnablePropagation(void)2394 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
2395 {
2396 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
2397 }
2398
2399 /**
2400 * @brief Check if LSE oscillator propagation is enabled
2401 * @rmtoll BDCR LSESYSDIS LL_RCC_LSE_IsPropagationEnabled
2402 * @retval State of bit (1 or 0).
2403 */
LL_RCC_LSE_IsPropagationEnabled(void)2404 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationEnabled(void)
2405 {
2406 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0U) ? 1UL : 0UL);
2407 }
2408 #endif /* RCC_BDCR_LSESYSDIS */
2409 /**
2410 * @}
2411 */
2412
2413 /** @defgroup RCC_LL_EF_LSI LSI
2414 * @{
2415 */
2416
2417 /**
2418 * @brief Enable LSI Oscillator
2419 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2420 * @retval None
2421 */
LL_RCC_LSI_Enable(void)2422 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2423 {
2424 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2425 }
2426
2427 /**
2428 * @brief Disable LSI Oscillator
2429 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2430 * @retval None
2431 */
LL_RCC_LSI_Disable(void)2432 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2433 {
2434 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2435 }
2436
2437 /**
2438 * @brief Check if LSI is Ready
2439 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2440 * @retval State of bit (1 or 0).
2441 */
LL_RCC_LSI_IsReady(void)2442 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2443 {
2444 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
2445 }
2446
2447 #if defined(RCC_CSR_LSIPREDIV)
2448 /**
2449 * @brief Set LSI division factor
2450 * @rmtoll CSR LSIPREDIV LL_RCC_LSI_SetPrediv
2451 * @param LSI_PREDIV This parameter can be one of the following values:
2452 * @arg @ref LL_RCC_LSI_PREDIV_1
2453 * @arg @ref LL_RCC_LSI_PREDIV_128
2454 * @retval None
2455 */
LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)2456 __STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)
2457 {
2458 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV);
2459 }
2460
2461 /**
2462 * @brief Get LSI division factor
2463 * @rmtoll CSR LSIPREDIV LL_RCC_LSI_GetPrediv
2464 * @retval Returned value can be one of the following values:
2465 * @arg @ref LL_RCC_LSI_PREDIV_1
2466 * @arg @ref LL_RCC_LSI_PREDIV_128
2467 */
LL_RCC_LSI_GetPrediv(void)2468 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void)
2469 {
2470 return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV));
2471 }
2472 #endif /* RCC_CSR_LSIPREDIV */
2473
2474 /**
2475 * @}
2476 */
2477
2478 /** @defgroup RCC_LL_EF_MSI MSI
2479 * @{
2480 */
2481
2482 /**
2483 * @brief Enable MSI oscillator
2484 * @rmtoll CR MSION LL_RCC_MSI_Enable
2485 * @retval None
2486 */
LL_RCC_MSI_Enable(void)2487 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
2488 {
2489 SET_BIT(RCC->CR, RCC_CR_MSION);
2490 }
2491
2492 /**
2493 * @brief Disable MSI oscillator
2494 * @rmtoll CR MSION LL_RCC_MSI_Disable
2495 * @retval None
2496 */
LL_RCC_MSI_Disable(void)2497 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
2498 {
2499 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
2500 }
2501
2502 /**
2503 * @brief Check if MSI oscillator Ready
2504 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
2505 * @retval State of bit (1 or 0).
2506 */
LL_RCC_MSI_IsReady(void)2507 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
2508 {
2509 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
2510 }
2511
2512 /**
2513 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
2514 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
2515 * and ready (LSERDY set by hardware)
2516 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
2517 * ready
2518 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
2519 * @retval None
2520 */
LL_RCC_MSI_EnablePLLMode(void)2521 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
2522 {
2523 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2524 }
2525
2526 /**
2527 * @brief Disable MSI-PLL mode
2528 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
2529 * the Clock Security System on LSE detects a LSE failure
2530 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
2531 * @retval None
2532 */
LL_RCC_MSI_DisablePLLMode(void)2533 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
2534 {
2535 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
2536 }
2537
2538 /**
2539 * @brief Enable MSI clock range selection with MSIRANGE register
2540 * @note Write 0 has no effect. After a standby or a reset
2541 * MSIRGSEL is at 0 and the MSI range value is provided by
2542 * MSISRANGE
2543 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
2544 * @retval None
2545 */
LL_RCC_MSI_EnableRangeSelection(void)2546 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
2547 {
2548 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
2549 }
2550
2551 /**
2552 * @brief Check if MSI clock range is selected with MSIRANGE register
2553 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
2554 * @retval State of bit (1 or 0).
2555 */
LL_RCC_MSI_IsEnabledRangeSelect(void)2556 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
2557 {
2558 return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RCC_CR_MSIRGSEL) ? 1UL : 0UL);
2559 }
2560
2561 /**
2562 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
2563 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
2564 * @param Range This parameter can be one of the following values:
2565 * @arg @ref LL_RCC_MSIRANGE_0
2566 * @arg @ref LL_RCC_MSIRANGE_1
2567 * @arg @ref LL_RCC_MSIRANGE_2
2568 * @arg @ref LL_RCC_MSIRANGE_3
2569 * @arg @ref LL_RCC_MSIRANGE_4
2570 * @arg @ref LL_RCC_MSIRANGE_5
2571 * @arg @ref LL_RCC_MSIRANGE_6
2572 * @arg @ref LL_RCC_MSIRANGE_7
2573 * @arg @ref LL_RCC_MSIRANGE_8
2574 * @arg @ref LL_RCC_MSIRANGE_9
2575 * @arg @ref LL_RCC_MSIRANGE_10
2576 * @arg @ref LL_RCC_MSIRANGE_11
2577 * @retval None
2578 */
LL_RCC_MSI_SetRange(uint32_t Range)2579 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
2580 {
2581 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
2582 }
2583
2584 /**
2585 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
2586 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
2587 * @retval Returned value can be one of the following values:
2588 * @arg @ref LL_RCC_MSIRANGE_0
2589 * @arg @ref LL_RCC_MSIRANGE_1
2590 * @arg @ref LL_RCC_MSIRANGE_2
2591 * @arg @ref LL_RCC_MSIRANGE_3
2592 * @arg @ref LL_RCC_MSIRANGE_4
2593 * @arg @ref LL_RCC_MSIRANGE_5
2594 * @arg @ref LL_RCC_MSIRANGE_6
2595 * @arg @ref LL_RCC_MSIRANGE_7
2596 * @arg @ref LL_RCC_MSIRANGE_8
2597 * @arg @ref LL_RCC_MSIRANGE_9
2598 * @arg @ref LL_RCC_MSIRANGE_10
2599 * @arg @ref LL_RCC_MSIRANGE_11
2600 */
LL_RCC_MSI_GetRange(void)2601 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
2602 {
2603 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
2604 }
2605
2606 /**
2607 * @brief Configure MSI range used after standby
2608 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
2609 * @param Range This parameter can be one of the following values:
2610 * @arg @ref LL_RCC_MSISRANGE_4
2611 * @arg @ref LL_RCC_MSISRANGE_5
2612 * @arg @ref LL_RCC_MSISRANGE_6
2613 * @arg @ref LL_RCC_MSISRANGE_7
2614 * @retval None
2615 */
LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)2616 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
2617 {
2618 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
2619 }
2620
2621 /**
2622 * @brief Get MSI range used after standby
2623 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
2624 * @retval Returned value can be one of the following values:
2625 * @arg @ref LL_RCC_MSISRANGE_4
2626 * @arg @ref LL_RCC_MSISRANGE_5
2627 * @arg @ref LL_RCC_MSISRANGE_6
2628 * @arg @ref LL_RCC_MSISRANGE_7
2629 */
LL_RCC_MSI_GetRangeAfterStandby(void)2630 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
2631 {
2632 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
2633 }
2634
2635 /**
2636 * @brief Get MSI Calibration value
2637 * @note When MSITRIM is written, MSICAL is updated with the sum of
2638 * MSITRIM and the factory trim value
2639 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
2640 * @retval Between Min_Data = 0 and Max_Data = 255
2641 */
LL_RCC_MSI_GetCalibration(void)2642 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
2643 {
2644 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
2645 }
2646
2647 /**
2648 * @brief Set MSI Calibration trimming
2649 * @note user-programmable trimming value that is added to the MSICAL
2650 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
2651 * @param Value Between Min_Data = 0 and Max_Data = 255
2652 * @retval None
2653 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)2654 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
2655 {
2656 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
2657 }
2658
2659 /**
2660 * @brief Get MSI Calibration trimming
2661 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
2662 * @retval Between 0 and 255
2663 */
LL_RCC_MSI_GetCalibTrimming(void)2664 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
2665 {
2666 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
2667 }
2668
2669 /**
2670 * @}
2671 */
2672
2673 /** @defgroup RCC_LL_EF_LSCO LSCO
2674 * @{
2675 */
2676
2677 /**
2678 * @brief Enable Low speed clock
2679 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
2680 * @retval None
2681 */
LL_RCC_LSCO_Enable(void)2682 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
2683 {
2684 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2685 }
2686
2687 /**
2688 * @brief Disable Low speed clock
2689 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
2690 * @retval None
2691 */
LL_RCC_LSCO_Disable(void)2692 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
2693 {
2694 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2695 }
2696
2697 /**
2698 * @brief Configure Low speed clock selection
2699 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2700 * @param Source This parameter can be one of the following values:
2701 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2702 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2703 * @retval None
2704 */
LL_RCC_LSCO_SetSource(uint32_t Source)2705 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2706 {
2707 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2708 }
2709
2710 /**
2711 * @brief Get Low speed clock selection
2712 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2713 * @retval Returned value can be one of the following values:
2714 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2715 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2716 */
LL_RCC_LSCO_GetSource(void)2717 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2718 {
2719 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2720 }
2721
2722 /**
2723 * @}
2724 */
2725
2726 /** @defgroup RCC_LL_EF_System System
2727 * @{
2728 */
2729
2730 /**
2731 * @brief Configure the system clock source
2732 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2733 * @param Source This parameter can be one of the following values:
2734 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
2735 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2736 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2737 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2738 * @retval None
2739 */
LL_RCC_SetSysClkSource(uint32_t Source)2740 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2741 {
2742 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2743 }
2744
2745 /**
2746 * @brief Get the system clock source
2747 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2748 * @retval Returned value can be one of the following values:
2749 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
2750 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2751 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2752 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2753 */
LL_RCC_GetSysClkSource(void)2754 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2755 {
2756 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2757 }
2758
2759 /**
2760 * @brief Set AHB prescaler
2761 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2762 * @param Prescaler This parameter can be one of the following values:
2763 * @arg @ref LL_RCC_SYSCLK_DIV_1
2764 * @arg @ref LL_RCC_SYSCLK_DIV_2
2765 * @arg @ref LL_RCC_SYSCLK_DIV_4
2766 * @arg @ref LL_RCC_SYSCLK_DIV_8
2767 * @arg @ref LL_RCC_SYSCLK_DIV_16
2768 * @arg @ref LL_RCC_SYSCLK_DIV_64
2769 * @arg @ref LL_RCC_SYSCLK_DIV_128
2770 * @arg @ref LL_RCC_SYSCLK_DIV_256
2771 * @arg @ref LL_RCC_SYSCLK_DIV_512
2772 * @retval None
2773 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2774 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2775 {
2776 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2777 }
2778
2779 /**
2780 * @brief Set APB1 prescaler
2781 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2782 * @param Prescaler This parameter can be one of the following values:
2783 * @arg @ref LL_RCC_APB1_DIV_1
2784 * @arg @ref LL_RCC_APB1_DIV_2
2785 * @arg @ref LL_RCC_APB1_DIV_4
2786 * @arg @ref LL_RCC_APB1_DIV_8
2787 * @arg @ref LL_RCC_APB1_DIV_16
2788 * @retval None
2789 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2790 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2791 {
2792 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2793 }
2794
2795 /**
2796 * @brief Set APB2 prescaler
2797 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2798 * @param Prescaler This parameter can be one of the following values:
2799 * @arg @ref LL_RCC_APB2_DIV_1
2800 * @arg @ref LL_RCC_APB2_DIV_2
2801 * @arg @ref LL_RCC_APB2_DIV_4
2802 * @arg @ref LL_RCC_APB2_DIV_8
2803 * @arg @ref LL_RCC_APB2_DIV_16
2804 * @retval None
2805 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2806 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2807 {
2808 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2809 }
2810
2811 /**
2812 * @brief Get AHB prescaler
2813 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2814 * @retval Returned value can be one of the following values:
2815 * @arg @ref LL_RCC_SYSCLK_DIV_1
2816 * @arg @ref LL_RCC_SYSCLK_DIV_2
2817 * @arg @ref LL_RCC_SYSCLK_DIV_4
2818 * @arg @ref LL_RCC_SYSCLK_DIV_8
2819 * @arg @ref LL_RCC_SYSCLK_DIV_16
2820 * @arg @ref LL_RCC_SYSCLK_DIV_64
2821 * @arg @ref LL_RCC_SYSCLK_DIV_128
2822 * @arg @ref LL_RCC_SYSCLK_DIV_256
2823 * @arg @ref LL_RCC_SYSCLK_DIV_512
2824 */
LL_RCC_GetAHBPrescaler(void)2825 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2826 {
2827 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2828 }
2829
2830 /**
2831 * @brief Get APB1 prescaler
2832 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2833 * @retval Returned value can be one of the following values:
2834 * @arg @ref LL_RCC_APB1_DIV_1
2835 * @arg @ref LL_RCC_APB1_DIV_2
2836 * @arg @ref LL_RCC_APB1_DIV_4
2837 * @arg @ref LL_RCC_APB1_DIV_8
2838 * @arg @ref LL_RCC_APB1_DIV_16
2839 */
LL_RCC_GetAPB1Prescaler(void)2840 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2841 {
2842 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2843 }
2844
2845 /**
2846 * @brief Get APB2 prescaler
2847 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2848 * @retval Returned value can be one of the following values:
2849 * @arg @ref LL_RCC_APB2_DIV_1
2850 * @arg @ref LL_RCC_APB2_DIV_2
2851 * @arg @ref LL_RCC_APB2_DIV_4
2852 * @arg @ref LL_RCC_APB2_DIV_8
2853 * @arg @ref LL_RCC_APB2_DIV_16
2854 */
LL_RCC_GetAPB2Prescaler(void)2855 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2856 {
2857 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2858 }
2859
2860 /**
2861 * @brief Set Clock After Wake-Up From Stop mode
2862 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2863 * @param Clock This parameter can be one of the following values:
2864 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2865 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2866 * @retval None
2867 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2868 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2869 {
2870 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
2871 }
2872
2873 /**
2874 * @brief Get Clock After Wake-Up From Stop mode
2875 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2876 * @retval Returned value can be one of the following values:
2877 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
2878 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
2879 */
LL_RCC_GetClkAfterWakeFromStop(void)2880 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2881 {
2882 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2883 }
2884
2885 /**
2886 * @}
2887 */
2888
2889 /** @defgroup RCC_LL_EF_MCO MCO
2890 * @{
2891 */
2892
2893 /**
2894 * @brief Configure MCOx
2895 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
2896 * CFGR MCOPRE LL_RCC_ConfigMCO
2897 * @param MCOxSource This parameter can be one of the following values:
2898 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
2899 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
2900 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2901 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2902 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2903 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
2904 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2905 * @arg @ref LL_RCC_MCO1SOURCE_LSI
2906 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2907 *
2908 * (*) value not defined in all devices.
2909 * @param MCOxPrescaler This parameter can be one of the following values:
2910 * @arg @ref LL_RCC_MCO1_DIV_1
2911 * @arg @ref LL_RCC_MCO1_DIV_2
2912 * @arg @ref LL_RCC_MCO1_DIV_4
2913 * @arg @ref LL_RCC_MCO1_DIV_8
2914 * @arg @ref LL_RCC_MCO1_DIV_16
2915 * @retval None
2916 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2917 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2918 {
2919 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2920 }
2921
2922 /**
2923 * @}
2924 */
2925
2926 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2927 * @{
2928 */
2929
2930 /**
2931 * @brief Configure USARTx clock source
2932 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
2933 * @param USARTxSource This parameter can be one of the following values:
2934 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2935 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2936 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2937 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2938 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2939 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2940 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2941 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2942 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
2943 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
2944 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
2945 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
2946 *
2947 * (*) value not defined in all devices.
2948 * @retval None
2949 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2950 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2951 {
2952 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
2953 }
2954
2955 #if defined(UART4) || defined(UART5)
2956 /**
2957 * @brief Configure UARTx clock source
2958 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
2959 * @param UARTxSource This parameter can be one of the following values:
2960 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2961 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2962 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2963 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2964 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2965 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2966 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2967 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2968 * @retval None
2969 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)2970 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2971 {
2972 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
2973 }
2974 #endif /* UART4 || UART5 */
2975
2976 /**
2977 * @brief Configure LPUART1x clock source
2978 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2979 * @param LPUARTxSource This parameter can be one of the following values:
2980 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2981 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2982 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2983 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2984 * @retval None
2985 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2986 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2987 {
2988 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
2989 }
2990
2991 /**
2992 * @brief Configure I2Cx clock source
2993 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
2994 * @param I2CxSource This parameter can be one of the following values:
2995 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2996 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2997 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2998 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
2999 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
3000 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
3001 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
3002 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
3003 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
3004 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
3005 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
3006 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3007 *
3008 * (*) value not defined in all devices.
3009 * @retval None
3010 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)3011 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
3012 {
3013 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
3014 MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
3015 }
3016
3017 /**
3018 * @brief Configure LPTIMx clock source
3019 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
3020 * @param LPTIMxSource This parameter can be one of the following values:
3021 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3022 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3023 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3024 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3025 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3026 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3027 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
3028 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3029 * @retval None
3030 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)3031 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3032 {
3033 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
3034 }
3035
3036 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
3037 /**
3038 * @brief Configure SAIx clock source
3039 @if STM32L4S9xx
3040 * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource
3041 @else
3042 * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
3043 @endif
3044 * @param SAIxSource This parameter can be one of the following values:
3045 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
3046 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
3047 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
3048 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
3049 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
3050 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
3051 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3052 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
3053 *
3054 * (*) value not defined in all devices.
3055 * @retval None
3056 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)3057 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3058 {
3059 #if defined(RCC_CCIPR2_SAI1SEL)
3060 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
3061 #else
3062 MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3063 #endif /* RCC_CCIPR2_SAI1SEL */
3064 }
3065 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
3066
3067 #if defined(RCC_CCIPR2_SDMMCSEL)
3068 /**
3069 * @brief Configure SDMMC1 kernel clock source
3070 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
3071 * @param SDMMCxSource This parameter can be one of the following values:
3072 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
3073 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
3074 *
3075 * (*) value not defined in all devices.
3076 * @retval None
3077 */
LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)3078 __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
3079 {
3080 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
3081 }
3082 #endif /* RCC_CCIPR2_SDMMCSEL */
3083
3084 /**
3085 * @brief Configure SDMMC1 clock source
3086 * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
3087 * @param SDMMCxSource This parameter can be one of the following values:
3088 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
3089 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
3090 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
3091 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
3092 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
3093 *
3094 * (*) value not defined in all devices.
3095 * @retval None
3096 */
LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)3097 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
3098 {
3099 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
3100 }
3101
3102 /**
3103 * @brief Configure RNG clock source
3104 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
3105 * @param RNGxSource This parameter can be one of the following values:
3106 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
3107 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
3108 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*)
3109 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3110 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
3111 *
3112 * (*) value not defined in all devices.
3113 * @retval None
3114 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3115 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3116 {
3117 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
3118 }
3119
3120 #if defined(USB_OTG_FS) || defined(USB)
3121 /**
3122 * @brief Configure USB clock source
3123 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
3124 * @param USBxSource This parameter can be one of the following values:
3125 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
3126 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
3127 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*)
3128 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3129 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
3130 *
3131 * (*) value not defined in all devices.
3132 * @retval None
3133 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)3134 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3135 {
3136 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
3137 }
3138 #endif /* USB_OTG_FS || USB */
3139
3140 #if defined(RCC_CCIPR_ADCSEL)
3141 /**
3142 * @brief Configure ADC clock source
3143 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
3144 * @param ADCxSource This parameter can be one of the following values:
3145 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
3146 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
3147 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
3148 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
3149 *
3150 * (*) value not defined in all devices.
3151 * @retval None
3152 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)3153 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
3154 {
3155 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
3156 }
3157 #endif /* RCC_CCIPR_ADCSEL */
3158
3159 #if defined(SWPMI1)
3160 /**
3161 * @brief Configure SWPMI clock source
3162 * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
3163 * @param SWPMIxSource This parameter can be one of the following values:
3164 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
3165 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
3166 * @retval None
3167 */
LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)3168 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
3169 {
3170 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
3171 }
3172 #endif /* SWPMI1 */
3173
3174 #if defined(DFSDM1_Channel0)
3175 #if defined(RCC_CCIPR2_ADFSDM1SEL)
3176 /**
3177 * @brief Configure DFSDM Audio clock source
3178 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
3179 * @param Source This parameter can be one of the following values:
3180 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
3181 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
3182 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
3183 * @retval None
3184 */
LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)3185 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3186 {
3187 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
3188 }
3189 #endif /* RCC_CCIPR2_ADFSDM1SEL */
3190
3191 /**
3192 * @brief Configure DFSDM Kernel clock source
3193 @if STM32L4S9xx
3194 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
3195 @else
3196 * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
3197 @endif
3198 * @param DFSDMxSource This parameter can be one of the following values:
3199 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3200 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3201 * @retval None
3202 */
LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)3203 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
3204 {
3205 #if defined(RCC_CCIPR2_DFSDM1SEL)
3206 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
3207 #else
3208 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
3209 #endif /* RCC_CCIPR2_DFSDM1SEL */
3210 }
3211 #endif /* DFSDM1_Channel0 */
3212
3213 #if defined(DSI)
3214 /**
3215 * @brief Configure DSI clock source
3216 * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
3217 * @param Source This parameter can be one of the following values:
3218 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3219 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3220 * @retval None
3221 */
LL_RCC_SetDSIClockSource(uint32_t Source)3222 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3223 {
3224 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
3225 }
3226 #endif /* DSI */
3227
3228 #if defined(LTDC)
3229 /**
3230 * @brief Configure LTDC Clock Source
3231 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource
3232 * @param Source This parameter can be one of the following values:
3233 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
3234 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
3235 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
3236 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
3237 * @retval None
3238 */
LL_RCC_SetLTDCClockSource(uint32_t Source)3239 __STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
3240 {
3241 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
3242 }
3243 #endif /* LTDC */
3244
3245 #if defined(OCTOSPI1)
3246 /**
3247 * @brief Configure OCTOSPI clock source
3248 * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
3249 * @param Source This parameter can be one of the following values:
3250 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
3251 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
3252 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
3253 * @retval None
3254 */
LL_RCC_SetOCTOSPIClockSource(uint32_t Source)3255 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
3256 {
3257 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
3258 }
3259 #endif /* OCTOSPI1 */
3260
3261 /**
3262 * @brief Get USARTx clock source
3263 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
3264 * @param USARTx This parameter can be one of the following values:
3265 * @arg @ref LL_RCC_USART1_CLKSOURCE
3266 * @arg @ref LL_RCC_USART2_CLKSOURCE
3267 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
3268 *
3269 * (*) value not defined in all devices.
3270 * @retval Returned value can be one of the following values:
3271 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3272 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
3273 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3274 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3275 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3276 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
3277 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3278 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3279 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
3280 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
3281 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
3282 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
3283 *
3284 * (*) value not defined in all devices.
3285 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)3286 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
3287 {
3288 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
3289 }
3290
3291 #if defined(UART4) || defined(UART5)
3292 /**
3293 * @brief Get UARTx clock source
3294 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
3295 * @param UARTx This parameter can be one of the following values:
3296 * @arg @ref LL_RCC_UART4_CLKSOURCE
3297 * @arg @ref LL_RCC_UART5_CLKSOURCE
3298 * @retval Returned value can be one of the following values:
3299 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
3300 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
3301 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
3302 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
3303 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
3304 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
3305 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
3306 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
3307 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)3308 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
3309 {
3310 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
3311 }
3312 #endif /* UART4 || UART5 */
3313
3314 /**
3315 * @brief Get LPUARTx clock source
3316 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
3317 * @param LPUARTx This parameter can be one of the following values:
3318 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3319 * @retval Returned value can be one of the following values:
3320 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
3321 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
3322 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3323 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3324 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)3325 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
3326 {
3327 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
3328 }
3329
3330 /**
3331 * @brief Get I2Cx clock source
3332 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
3333 * @param I2Cx This parameter can be one of the following values:
3334 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3335 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
3336 * @arg @ref LL_RCC_I2C3_CLKSOURCE
3337 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
3338 *
3339 * (*) value not defined in all devices.
3340 * @retval Returned value can be one of the following values:
3341 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3342 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
3343 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3344 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
3345 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
3346 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
3347 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
3348 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
3349 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
3350 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
3351 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
3352 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3353 *
3354 * (*) value not defined in all devices.
3355 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)3356 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
3357 {
3358 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
3359 return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
3360 }
3361
3362 /**
3363 * @brief Get LPTIMx clock source
3364 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
3365 * @param LPTIMx This parameter can be one of the following values:
3366 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3367 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3368 * @retval Returned value can be one of the following values:
3369 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3370 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3371 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3372 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3373 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3374 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3375 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
3376 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3377 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3378 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3379 {
3380 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
3381 }
3382
3383 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
3384 /**
3385 * @brief Get SAIx clock source
3386 @if STM32L4S9xx
3387 * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
3388 @else
3389 * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
3390 @endif
3391 * @param SAIx This parameter can be one of the following values:
3392 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3393 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3394 *
3395 * (*) value not defined in all devices.
3396 * @retval Returned value can be one of the following values:
3397 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
3398 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
3399 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
3400 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
3401 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
3402 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
3403 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3404 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
3405 *
3406 * (*) value not defined in all devices.
3407 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)3408 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3409 {
3410 #if defined(RCC_CCIPR2_SAI1SEL)
3411 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
3412 #else
3413 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx);
3414 #endif /* RCC_CCIPR2_SAI1SEL */
3415 }
3416 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR2_SAI1SEL */
3417
3418 #if defined(SDMMC1)
3419 #if defined(RCC_CCIPR2_SDMMCSEL)
3420 /**
3421 * @brief Get SDMMCx kernel clock source
3422 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
3423 * @param SDMMCx This parameter can be one of the following values:
3424 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
3425 * @retval Returned value can be one of the following values:
3426 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
3427 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
3428 *
3429 * (*) value not defined in all devices.
3430 */
LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)3431 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
3432 {
3433 return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
3434 }
3435 #endif /* RCC_CCIPR2_SDMMCSEL */
3436
3437 /**
3438 * @brief Get SDMMCx clock source
3439 * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
3440 * @param SDMMCx This parameter can be one of the following values:
3441 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
3442 * @retval Returned value can be one of the following values:
3443 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
3444 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
3445 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
3446 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
3447 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
3448 *
3449 * (*) value not defined in all devices.
3450 */
LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)3451 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
3452 {
3453 return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
3454 }
3455 #endif /* SDMMC1 */
3456
3457 /**
3458 * @brief Get RNGx clock source
3459 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
3460 * @param RNGx This parameter can be one of the following values:
3461 * @arg @ref LL_RCC_RNG_CLKSOURCE
3462 * @retval Returned value can be one of the following values:
3463 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
3464 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
3465 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 (*)
3466 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3467 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
3468 *
3469 * (*) value not defined in all devices.
3470 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)3471 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3472 {
3473 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
3474 }
3475
3476 #if defined(USB_OTG_FS) || defined(USB)
3477 /**
3478 * @brief Get USBx clock source
3479 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
3480 * @param USBx This parameter can be one of the following values:
3481 * @arg @ref LL_RCC_USB_CLKSOURCE
3482 * @retval Returned value can be one of the following values:
3483 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
3484 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
3485 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 (*)
3486 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3487 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI
3488 *
3489 * (*) value not defined in all devices.
3490 */
LL_RCC_GetUSBClockSource(uint32_t USBx)3491 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3492 {
3493 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
3494 }
3495 #endif /* USB_OTG_FS || USB */
3496
3497 /**
3498 * @brief Get ADCx clock source
3499 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
3500 * @param ADCx This parameter can be one of the following values:
3501 * @arg @ref LL_RCC_ADC_CLKSOURCE
3502 * @retval Returned value can be one of the following values:
3503 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
3504 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)
3505 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
3506 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
3507 *
3508 * (*) value not defined in all devices.
3509 */
LL_RCC_GetADCClockSource(uint32_t ADCx)3510 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
3511 {
3512 #if defined(RCC_CCIPR_ADCSEL)
3513 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
3514 #else
3515 (void)ADCx; /* unused */
3516 return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE);
3517 #endif /* RCC_CCIPR_ADCSEL */
3518 }
3519
3520 #if defined(SWPMI1)
3521 /**
3522 * @brief Get SWPMIx clock source
3523 * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
3524 * @param SPWMIx This parameter can be one of the following values:
3525 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
3526 * @retval Returned value can be one of the following values:
3527 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
3528 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
3529 */
LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)3530 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
3531 {
3532 return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
3533 }
3534 #endif /* SWPMI1 */
3535
3536 #if defined(DFSDM1_Channel0)
3537 #if defined(RCC_CCIPR2_ADFSDM1SEL)
3538 /**
3539 * @brief Get DFSDM Audio Clock Source
3540 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
3541 * @param DFSDMx This parameter can be one of the following values:
3542 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
3543 * @retval Returned value can be one of the following values:
3544 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
3545 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
3546 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
3547 */
LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)3548 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3549 {
3550 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
3551 }
3552 #endif /* RCC_CCIPR2_ADFSDM1SEL */
3553
3554 /**
3555 * @brief Get DFSDMx Kernel clock source
3556 @if STM32L4S9xx
3557 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
3558 @else
3559 * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
3560 @endif
3561 * @param DFSDMx This parameter can be one of the following values:
3562 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3563 * @retval Returned value can be one of the following values:
3564 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3565 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3566 */
LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)3567 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3568 {
3569 #if defined(RCC_CCIPR2_DFSDM1SEL)
3570 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
3571 #else
3572 return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
3573 #endif /* RCC_CCIPR2_DFSDM1SEL */
3574 }
3575 #endif /* DFSDM1_Channel0 */
3576
3577 #if defined(DSI)
3578 /**
3579 * @brief Get DSI Clock Source
3580 * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
3581 * @param DSIx This parameter can be one of the following values:
3582 * @arg @ref LL_RCC_DSI_CLKSOURCE
3583 * @retval Returned value can be one of the following values:
3584 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3585 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3586 */
LL_RCC_GetDSIClockSource(uint32_t DSIx)3587 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3588 {
3589 return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
3590 }
3591 #endif /* DSI */
3592
3593 #if defined(LTDC)
3594 /**
3595 * @brief Get LTDC Clock Source
3596 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource
3597 * @param LTDCx This parameter can be one of the following values:
3598 * @arg @ref LL_RCC_LTDC_CLKSOURCE
3599 * @retval Returned value can be one of the following values:
3600 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
3601 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
3602 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
3603 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
3604 */
LL_RCC_GetLTDCClockSource(uint32_t LTDCx)3605 __STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
3606 {
3607 return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
3608 }
3609 #endif /* LTDC */
3610
3611 #if defined(OCTOSPI1)
3612 /**
3613 * @brief Get OCTOSPI clock source
3614 * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
3615 * @param OCTOSPIx This parameter can be one of the following values:
3616 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
3617 * @retval Returned value can be one of the following values:
3618 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
3619 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
3620 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
3621 */
LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)3622 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
3623 {
3624 return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
3625 }
3626 #endif /* OCTOSPI1 */
3627 /**
3628 * @}
3629 */
3630
3631 /** @defgroup RCC_LL_EF_RTC RTC
3632 * @{
3633 */
3634
3635 /**
3636 * @brief Set RTC Clock Source
3637 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3638 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3639 * set). The BDRST bit can be used to reset them.
3640 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3641 * @param Source This parameter can be one of the following values:
3642 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3643 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3644 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3645 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
3646 * @retval None
3647 */
LL_RCC_SetRTCClockSource(uint32_t Source)3648 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3649 {
3650 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3651 }
3652
3653 /**
3654 * @brief Get RTC Clock Source
3655 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3656 * @retval Returned value can be one of the following values:
3657 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3658 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3659 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3660 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
3661 */
LL_RCC_GetRTCClockSource(void)3662 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3663 {
3664 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
3665 }
3666
3667 /**
3668 * @brief Enable RTC
3669 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
3670 * @retval None
3671 */
LL_RCC_EnableRTC(void)3672 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3673 {
3674 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3675 }
3676
3677 /**
3678 * @brief Disable RTC
3679 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
3680 * @retval None
3681 */
LL_RCC_DisableRTC(void)3682 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3683 {
3684 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3685 }
3686
3687 /**
3688 * @brief Check if RTC has been enabled or not
3689 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
3690 * @retval State of bit (1 or 0).
3691 */
LL_RCC_IsEnabledRTC(void)3692 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3693 {
3694 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
3695 }
3696
3697 /**
3698 * @brief Force the Backup domain reset
3699 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
3700 * @retval None
3701 */
LL_RCC_ForceBackupDomainReset(void)3702 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3703 {
3704 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3705 }
3706
3707 /**
3708 * @brief Release the Backup domain reset
3709 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
3710 * @retval None
3711 */
LL_RCC_ReleaseBackupDomainReset(void)3712 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3713 {
3714 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3715 }
3716
3717 /**
3718 * @}
3719 */
3720
3721
3722 /** @defgroup RCC_LL_EF_PLL PLL
3723 * @{
3724 */
3725
3726 /**
3727 * @brief Enable PLL
3728 * @rmtoll CR PLLON LL_RCC_PLL_Enable
3729 * @retval None
3730 */
LL_RCC_PLL_Enable(void)3731 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
3732 {
3733 SET_BIT(RCC->CR, RCC_CR_PLLON);
3734 }
3735
3736 /**
3737 * @brief Disable PLL
3738 * @note Cannot be disabled if the PLL clock is used as the system clock
3739 * @rmtoll CR PLLON LL_RCC_PLL_Disable
3740 * @retval None
3741 */
LL_RCC_PLL_Disable(void)3742 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
3743 {
3744 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
3745 }
3746
3747 /**
3748 * @brief Check if PLL Ready
3749 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
3750 * @retval State of bit (1 or 0).
3751 */
LL_RCC_PLL_IsReady(void)3752 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
3753 {
3754 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL);
3755 }
3756
3757 /**
3758 * @brief Configure PLL used for SYSCLK Domain
3759 * @note PLL Source and PLLM Divider can be written only when PLL,
3760 * PLLSAI1 and PLLSAI2 (*) are disabled.
3761 * @note PLLN/PLLR can be written only when PLL is disabled.
3762 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
3763 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
3764 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
3765 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
3766 * @param Source This parameter can be one of the following values:
3767 * @arg @ref LL_RCC_PLLSOURCE_NONE
3768 * @arg @ref LL_RCC_PLLSOURCE_MSI
3769 * @arg @ref LL_RCC_PLLSOURCE_HSI
3770 * @arg @ref LL_RCC_PLLSOURCE_HSE
3771 * @param PLLM This parameter can be one of the following values:
3772 * @arg @ref LL_RCC_PLLM_DIV_1
3773 * @arg @ref LL_RCC_PLLM_DIV_2
3774 * @arg @ref LL_RCC_PLLM_DIV_3
3775 * @arg @ref LL_RCC_PLLM_DIV_4
3776 * @arg @ref LL_RCC_PLLM_DIV_5
3777 * @arg @ref LL_RCC_PLLM_DIV_6
3778 * @arg @ref LL_RCC_PLLM_DIV_7
3779 * @arg @ref LL_RCC_PLLM_DIV_8
3780 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
3781 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
3782 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
3783 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
3784 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
3785 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
3786 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
3787 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
3788 *
3789 * (*) value not defined in all devices.
3790 * @param PLLN Between 8 and 86
3791 * @param PLLR This parameter can be one of the following values:
3792 * @arg @ref LL_RCC_PLLR_DIV_2
3793 * @arg @ref LL_RCC_PLLR_DIV_4
3794 * @arg @ref LL_RCC_PLLR_DIV_6
3795 * @arg @ref LL_RCC_PLLR_DIV_8
3796 * @retval None
3797 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)3798 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3799 {
3800 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3801 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
3802 }
3803
3804 #if defined(RCC_PLLP_SUPPORT)
3805 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3806 /**
3807 * @brief Configure PLL used for SAI domain clock
3808 * @note PLL Source and PLLM Divider can be written only when PLL,
3809 * PLLSAI1 and PLLSAI2 (*) are disabled.
3810 * @note PLLN/PLLP can be written only when PLL is disabled.
3811 * @note This can be selected for SAI1 or SAI2 (*)
3812 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
3813 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
3814 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
3815 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
3816 * @param Source This parameter can be one of the following values:
3817 * @arg @ref LL_RCC_PLLSOURCE_NONE
3818 * @arg @ref LL_RCC_PLLSOURCE_MSI
3819 * @arg @ref LL_RCC_PLLSOURCE_HSI
3820 * @arg @ref LL_RCC_PLLSOURCE_HSE
3821 * @param PLLM This parameter can be one of the following values:
3822 * @arg @ref LL_RCC_PLLM_DIV_1
3823 * @arg @ref LL_RCC_PLLM_DIV_2
3824 * @arg @ref LL_RCC_PLLM_DIV_3
3825 * @arg @ref LL_RCC_PLLM_DIV_4
3826 * @arg @ref LL_RCC_PLLM_DIV_5
3827 * @arg @ref LL_RCC_PLLM_DIV_6
3828 * @arg @ref LL_RCC_PLLM_DIV_7
3829 * @arg @ref LL_RCC_PLLM_DIV_8
3830 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
3831 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
3832 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
3833 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
3834 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
3835 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
3836 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
3837 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
3838 *
3839 * (*) value not defined in all devices.
3840 * @param PLLN Between 8 and 86
3841 * @param PLLP This parameter can be one of the following values:
3842 * @arg @ref LL_RCC_PLLP_DIV_2
3843 * @arg @ref LL_RCC_PLLP_DIV_3
3844 * @arg @ref LL_RCC_PLLP_DIV_4
3845 * @arg @ref LL_RCC_PLLP_DIV_5
3846 * @arg @ref LL_RCC_PLLP_DIV_6
3847 * @arg @ref LL_RCC_PLLP_DIV_7
3848 * @arg @ref LL_RCC_PLLP_DIV_8
3849 * @arg @ref LL_RCC_PLLP_DIV_9
3850 * @arg @ref LL_RCC_PLLP_DIV_10
3851 * @arg @ref LL_RCC_PLLP_DIV_11
3852 * @arg @ref LL_RCC_PLLP_DIV_12
3853 * @arg @ref LL_RCC_PLLP_DIV_13
3854 * @arg @ref LL_RCC_PLLP_DIV_14
3855 * @arg @ref LL_RCC_PLLP_DIV_15
3856 * @arg @ref LL_RCC_PLLP_DIV_16
3857 * @arg @ref LL_RCC_PLLP_DIV_17
3858 * @arg @ref LL_RCC_PLLP_DIV_18
3859 * @arg @ref LL_RCC_PLLP_DIV_19
3860 * @arg @ref LL_RCC_PLLP_DIV_20
3861 * @arg @ref LL_RCC_PLLP_DIV_21
3862 * @arg @ref LL_RCC_PLLP_DIV_22
3863 * @arg @ref LL_RCC_PLLP_DIV_23
3864 * @arg @ref LL_RCC_PLLP_DIV_24
3865 * @arg @ref LL_RCC_PLLP_DIV_25
3866 * @arg @ref LL_RCC_PLLP_DIV_26
3867 * @arg @ref LL_RCC_PLLP_DIV_27
3868 * @arg @ref LL_RCC_PLLP_DIV_28
3869 * @arg @ref LL_RCC_PLLP_DIV_29
3870 * @arg @ref LL_RCC_PLLP_DIV_30
3871 * @arg @ref LL_RCC_PLLP_DIV_31
3872 * @retval None
3873 */
3874 #else
3875 /**
3876 * @brief Configure PLL used for SAI domain clock
3877 * @note PLL Source and PLLM Divider can be written only when PLL,
3878 * PLLSAI1 and PLLSAI2 (*) are disabled.
3879 * @note PLLN/PLLP can be written only when PLL is disabled.
3880 * @note This can be selected for SAI1 or SAI2 (*)
3881 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
3882 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
3883 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
3884 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
3885 * @param Source This parameter can be one of the following values:
3886 * @arg @ref LL_RCC_PLLSOURCE_NONE
3887 * @arg @ref LL_RCC_PLLSOURCE_MSI
3888 * @arg @ref LL_RCC_PLLSOURCE_HSI
3889 * @arg @ref LL_RCC_PLLSOURCE_HSE
3890 * @param PLLM This parameter can be one of the following values:
3891 * @arg @ref LL_RCC_PLLM_DIV_1
3892 * @arg @ref LL_RCC_PLLM_DIV_2
3893 * @arg @ref LL_RCC_PLLM_DIV_3
3894 * @arg @ref LL_RCC_PLLM_DIV_4
3895 * @arg @ref LL_RCC_PLLM_DIV_5
3896 * @arg @ref LL_RCC_PLLM_DIV_6
3897 * @arg @ref LL_RCC_PLLM_DIV_7
3898 * @arg @ref LL_RCC_PLLM_DIV_8
3899 * @param PLLN Between 8 and 86
3900 * @param PLLP This parameter can be one of the following values:
3901 * @arg @ref LL_RCC_PLLP_DIV_7
3902 * @arg @ref LL_RCC_PLLP_DIV_17
3903 * @retval None
3904 */
3905 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)3906 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3907 {
3908 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
3909 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
3910 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3911 #else
3912 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3913 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
3914 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
3915 }
3916 #endif /* RCC_PLLP_SUPPORT */
3917
3918 /**
3919 * @brief Configure PLL used for 48Mhz domain clock
3920 * @note PLL Source and PLLM Divider can be written only when PLL,
3921 * PLLSAI1 and PLLSAI2 (*) are disabled.
3922 * @note PLLN/PLLQ can be written only when PLL is disabled.
3923 * @note This can be selected for USB, RNG, SDMMC
3924 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3925 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3926 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3927 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3928 * @param Source This parameter can be one of the following values:
3929 * @arg @ref LL_RCC_PLLSOURCE_NONE
3930 * @arg @ref LL_RCC_PLLSOURCE_MSI
3931 * @arg @ref LL_RCC_PLLSOURCE_HSI
3932 * @arg @ref LL_RCC_PLLSOURCE_HSE
3933 * @param PLLM This parameter can be one of the following values:
3934 * @arg @ref LL_RCC_PLLM_DIV_1
3935 * @arg @ref LL_RCC_PLLM_DIV_2
3936 * @arg @ref LL_RCC_PLLM_DIV_3
3937 * @arg @ref LL_RCC_PLLM_DIV_4
3938 * @arg @ref LL_RCC_PLLM_DIV_5
3939 * @arg @ref LL_RCC_PLLM_DIV_6
3940 * @arg @ref LL_RCC_PLLM_DIV_7
3941 * @arg @ref LL_RCC_PLLM_DIV_8
3942 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
3943 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
3944 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
3945 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
3946 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
3947 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
3948 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
3949 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
3950 *
3951 * (*) value not defined in all devices.
3952 * @param PLLN Between 8 and 86
3953 * @param PLLQ This parameter can be one of the following values:
3954 * @arg @ref LL_RCC_PLLQ_DIV_2
3955 * @arg @ref LL_RCC_PLLQ_DIV_4
3956 * @arg @ref LL_RCC_PLLQ_DIV_6
3957 * @arg @ref LL_RCC_PLLQ_DIV_8
3958 * @retval None
3959 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)3960 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3961 {
3962 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3963 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
3964 }
3965
3966 /**
3967 * @brief Configure PLL clock source
3968 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
3969 * @param PLLSource This parameter can be one of the following values:
3970 * @arg @ref LL_RCC_PLLSOURCE_NONE
3971 * @arg @ref LL_RCC_PLLSOURCE_MSI
3972 * @arg @ref LL_RCC_PLLSOURCE_HSI
3973 * @arg @ref LL_RCC_PLLSOURCE_HSE
3974 * @retval None
3975 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)3976 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
3977 {
3978 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
3979 }
3980
3981 /**
3982 * @brief Get the oscillator used as PLL clock source.
3983 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3984 * @retval Returned value can be one of the following values:
3985 * @arg @ref LL_RCC_PLLSOURCE_NONE
3986 * @arg @ref LL_RCC_PLLSOURCE_MSI
3987 * @arg @ref LL_RCC_PLLSOURCE_HSI
3988 * @arg @ref LL_RCC_PLLSOURCE_HSE
3989 */
LL_RCC_PLL_GetMainSource(void)3990 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3991 {
3992 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3993 }
3994
3995 /**
3996 * @brief Get Main PLL multiplication factor for VCO
3997 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3998 * @retval Between 8 and 86
3999 */
LL_RCC_PLL_GetN(void)4000 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4001 {
4002 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4003 }
4004
4005 #if defined(RCC_PLLP_SUPPORT)
4006 #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
4007 /**
4008 * @brief Get Main PLL division factor for PLLP
4009 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
4010 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
4011 * @retval Returned value can be one of the following values:
4012 * @arg @ref LL_RCC_PLLP_DIV_2
4013 * @arg @ref LL_RCC_PLLP_DIV_3
4014 * @arg @ref LL_RCC_PLLP_DIV_4
4015 * @arg @ref LL_RCC_PLLP_DIV_5
4016 * @arg @ref LL_RCC_PLLP_DIV_6
4017 * @arg @ref LL_RCC_PLLP_DIV_7
4018 * @arg @ref LL_RCC_PLLP_DIV_8
4019 * @arg @ref LL_RCC_PLLP_DIV_9
4020 * @arg @ref LL_RCC_PLLP_DIV_10
4021 * @arg @ref LL_RCC_PLLP_DIV_11
4022 * @arg @ref LL_RCC_PLLP_DIV_12
4023 * @arg @ref LL_RCC_PLLP_DIV_13
4024 * @arg @ref LL_RCC_PLLP_DIV_14
4025 * @arg @ref LL_RCC_PLLP_DIV_15
4026 * @arg @ref LL_RCC_PLLP_DIV_16
4027 * @arg @ref LL_RCC_PLLP_DIV_17
4028 * @arg @ref LL_RCC_PLLP_DIV_18
4029 * @arg @ref LL_RCC_PLLP_DIV_19
4030 * @arg @ref LL_RCC_PLLP_DIV_20
4031 * @arg @ref LL_RCC_PLLP_DIV_21
4032 * @arg @ref LL_RCC_PLLP_DIV_22
4033 * @arg @ref LL_RCC_PLLP_DIV_23
4034 * @arg @ref LL_RCC_PLLP_DIV_24
4035 * @arg @ref LL_RCC_PLLP_DIV_25
4036 * @arg @ref LL_RCC_PLLP_DIV_26
4037 * @arg @ref LL_RCC_PLLP_DIV_27
4038 * @arg @ref LL_RCC_PLLP_DIV_28
4039 * @arg @ref LL_RCC_PLLP_DIV_29
4040 * @arg @ref LL_RCC_PLLP_DIV_30
4041 * @arg @ref LL_RCC_PLLP_DIV_31
4042 */
LL_RCC_PLL_GetP(void)4043 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4044 {
4045 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
4046 }
4047 #else
4048 /**
4049 * @brief Get Main PLL division factor for PLLP
4050 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
4051 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
4052 * @retval Returned value can be one of the following values:
4053 * @arg @ref LL_RCC_PLLP_DIV_7
4054 * @arg @ref LL_RCC_PLLP_DIV_17
4055 */
LL_RCC_PLL_GetP(void)4056 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4057 {
4058 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4059 }
4060 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
4061 #endif /* RCC_PLLP_SUPPORT */
4062
4063 /**
4064 * @brief Get Main PLL division factor for PLLQ
4065 * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
4066 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
4067 * @retval Returned value can be one of the following values:
4068 * @arg @ref LL_RCC_PLLQ_DIV_2
4069 * @arg @ref LL_RCC_PLLQ_DIV_4
4070 * @arg @ref LL_RCC_PLLQ_DIV_6
4071 * @arg @ref LL_RCC_PLLQ_DIV_8
4072 */
LL_RCC_PLL_GetQ(void)4073 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4074 {
4075 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4076 }
4077
4078 /**
4079 * @brief Get Main PLL division factor for PLLR
4080 * @note Used for PLLCLK (system clock)
4081 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
4082 * @retval Returned value can be one of the following values:
4083 * @arg @ref LL_RCC_PLLR_DIV_2
4084 * @arg @ref LL_RCC_PLLR_DIV_4
4085 * @arg @ref LL_RCC_PLLR_DIV_6
4086 * @arg @ref LL_RCC_PLLR_DIV_8
4087 */
LL_RCC_PLL_GetR(void)4088 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4089 {
4090 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4091 }
4092
4093 /**
4094 * @brief Get Division factor for the main PLL and other PLL
4095 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
4096 * @retval Returned value can be one of the following values:
4097 * @arg @ref LL_RCC_PLLM_DIV_1
4098 * @arg @ref LL_RCC_PLLM_DIV_2
4099 * @arg @ref LL_RCC_PLLM_DIV_3
4100 * @arg @ref LL_RCC_PLLM_DIV_4
4101 * @arg @ref LL_RCC_PLLM_DIV_5
4102 * @arg @ref LL_RCC_PLLM_DIV_6
4103 * @arg @ref LL_RCC_PLLM_DIV_7
4104 * @arg @ref LL_RCC_PLLM_DIV_8
4105 * @arg @ref LL_RCC_PLLM_DIV_9 (*)
4106 * @arg @ref LL_RCC_PLLM_DIV_10 (*)
4107 * @arg @ref LL_RCC_PLLM_DIV_11 (*)
4108 * @arg @ref LL_RCC_PLLM_DIV_12 (*)
4109 * @arg @ref LL_RCC_PLLM_DIV_13 (*)
4110 * @arg @ref LL_RCC_PLLM_DIV_14 (*)
4111 * @arg @ref LL_RCC_PLLM_DIV_15 (*)
4112 * @arg @ref LL_RCC_PLLM_DIV_16 (*)
4113 *
4114 * (*) value not defined in all devices.
4115 */
LL_RCC_PLL_GetDivider(void)4116 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
4117 {
4118 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
4119 }
4120
4121 #if defined(RCC_PLLP_SUPPORT)
4122 /**
4123 * @brief Enable PLL output mapped on SAI domain clock
4124 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
4125 * @retval None
4126 */
LL_RCC_PLL_EnableDomain_SAI(void)4127 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
4128 {
4129 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
4130 }
4131
4132 /**
4133 * @brief Disable PLL output mapped on SAI domain clock
4134 * @note Cannot be disabled if the PLL clock is used as the system
4135 * clock
4136 * @note In order to save power, when the PLLCLK of the PLL is
4137 * not used, should be 0
4138 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
4139 * @retval None
4140 */
LL_RCC_PLL_DisableDomain_SAI(void)4141 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
4142 {
4143 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
4144 }
4145 #endif /* RCC_PLLP_SUPPORT */
4146
4147 /**
4148 * @brief Enable PLL output mapped on 48MHz domain clock
4149 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
4150 * @retval None
4151 */
LL_RCC_PLL_EnableDomain_48M(void)4152 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
4153 {
4154 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
4155 }
4156
4157 /**
4158 * @brief Disable PLL output mapped on 48MHz domain clock
4159 * @note Cannot be disabled if the PLL clock is used as the system
4160 * clock
4161 * @note In order to save power, when the PLLCLK of the PLL is
4162 * not used, should be 0
4163 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
4164 * @retval None
4165 */
LL_RCC_PLL_DisableDomain_48M(void)4166 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
4167 {
4168 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
4169 }
4170
4171 /**
4172 * @brief Enable PLL output mapped on SYSCLK domain
4173 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
4174 * @retval None
4175 */
LL_RCC_PLL_EnableDomain_SYS(void)4176 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
4177 {
4178 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
4179 }
4180
4181 /**
4182 * @brief Disable PLL output mapped on SYSCLK domain
4183 * @note Cannot be disabled if the PLL clock is used as the system
4184 * clock
4185 * @note In order to save power, when the PLLCLK of the PLL is
4186 * not used, Main PLL should be 0
4187 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
4188 * @retval None
4189 */
LL_RCC_PLL_DisableDomain_SYS(void)4190 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
4191 {
4192 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
4193 }
4194
4195 /**
4196 * @}
4197 */
4198
4199 #if defined(RCC_PLLSAI1_SUPPORT)
4200 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
4201 * @{
4202 */
4203
4204 /**
4205 * @brief Enable PLLSAI1
4206 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
4207 * @retval None
4208 */
LL_RCC_PLLSAI1_Enable(void)4209 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
4210 {
4211 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
4212 }
4213
4214 /**
4215 * @brief Disable PLLSAI1
4216 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
4217 * @retval None
4218 */
LL_RCC_PLLSAI1_Disable(void)4219 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
4220 {
4221 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
4222 }
4223
4224 /**
4225 * @brief Check if PLLSAI1 Ready
4226 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
4227 * @retval State of bit (1 or 0).
4228 */
LL_RCC_PLLSAI1_IsReady(void)4229 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
4230 {
4231 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RCC_CR_PLLSAI1RDY) ? 1UL : 0UL);
4232 }
4233
4234 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4235 /**
4236 * @brief Configure PLLSAI1 used for 48Mhz domain clock
4237 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4238 * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
4239 * @note This can be selected for USB, RNG, SDMMC
4240 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
4241 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
4242 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
4243 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
4244 * @param Source This parameter can be one of the following values:
4245 * @arg @ref LL_RCC_PLLSOURCE_NONE
4246 * @arg @ref LL_RCC_PLLSOURCE_MSI
4247 * @arg @ref LL_RCC_PLLSOURCE_HSI
4248 * @arg @ref LL_RCC_PLLSOURCE_HSE
4249 * @param PLLM This parameter can be one of the following values:
4250 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4251 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4252 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4253 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4254 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4255 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4256 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4257 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4258 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4259 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4260 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4261 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4262 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4263 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4264 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4265 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4266 * @param PLLN Between 8 and 86
4267 * @param PLLQ This parameter can be one of the following values:
4268 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
4269 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
4270 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
4271 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
4272 * @retval None
4273 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4274 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4275 {
4276 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4277 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
4278 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLQ);
4279 }
4280 #else
4281 /**
4282 * @brief Configure PLLSAI1 used for 48Mhz domain clock
4283 * @note PLL Source and PLLM Divider can be written only when PLL,
4284 * PLLSAI1 and PLLSAI2 (*) are disabled.
4285 * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
4286 * @note This can be selected for USB, RNG, SDMMC
4287 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
4288 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
4289 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
4290 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
4291 * @param Source This parameter can be one of the following values:
4292 * @arg @ref LL_RCC_PLLSOURCE_NONE
4293 * @arg @ref LL_RCC_PLLSOURCE_MSI
4294 * @arg @ref LL_RCC_PLLSOURCE_HSI
4295 * @arg @ref LL_RCC_PLLSOURCE_HSE
4296 * @param PLLM This parameter can be one of the following values:
4297 * @arg @ref LL_RCC_PLLM_DIV_1
4298 * @arg @ref LL_RCC_PLLM_DIV_2
4299 * @arg @ref LL_RCC_PLLM_DIV_3
4300 * @arg @ref LL_RCC_PLLM_DIV_4
4301 * @arg @ref LL_RCC_PLLM_DIV_5
4302 * @arg @ref LL_RCC_PLLM_DIV_6
4303 * @arg @ref LL_RCC_PLLM_DIV_7
4304 * @arg @ref LL_RCC_PLLM_DIV_8
4305 * @param PLLN Between 8 and 86
4306 * @param PLLQ This parameter can be one of the following values:
4307 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
4308 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
4309 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
4310 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
4311 * @retval None
4312 */
LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)4313 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4314 {
4315 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4316 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);
4317 }
4318 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4319
4320 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4321 /**
4322 * @brief Configure PLLSAI1 used for SAI domain clock
4323 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4324 * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
4325 * @note This can be selected for SAI1 or SAI2
4326 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4327 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4328 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4329 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
4330 * @param Source This parameter can be one of the following values:
4331 * @arg @ref LL_RCC_PLLSOURCE_NONE
4332 * @arg @ref LL_RCC_PLLSOURCE_MSI
4333 * @arg @ref LL_RCC_PLLSOURCE_HSI
4334 * @arg @ref LL_RCC_PLLSOURCE_HSE
4335 * @param PLLM This parameter can be one of the following values:
4336 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4337 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4338 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4339 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4340 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4341 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4342 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4343 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4344 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4345 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4346 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4347 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4348 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4349 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4350 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4351 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4352 * @param PLLN Between 8 and 86
4353 * @param PLLP This parameter can be one of the following values:
4354 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
4355 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
4356 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
4357 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
4358 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
4359 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4360 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
4361 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
4362 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
4363 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
4364 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
4365 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
4366 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
4367 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
4368 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
4369 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4370 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
4371 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
4372 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
4373 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
4374 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
4375 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
4376 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
4377 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
4378 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
4379 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
4380 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
4381 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
4382 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
4383 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
4384 * @retval None
4385 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4386 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4387 {
4388 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4389 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
4390 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLP);
4391 }
4392 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4393 /**
4394 * @brief Configure PLLSAI1 used for SAI domain clock
4395 * @note PLL Source and PLLM Divider can be written only when PLL,
4396 * PLLSAI1 and PLLSAI2 (*) are disabled.
4397 * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
4398 * @note This can be selected for SAI1 or SAI2 (*)
4399 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4400 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4401 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4402 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
4403 * @param Source This parameter can be one of the following values:
4404 * @arg @ref LL_RCC_PLLSOURCE_NONE
4405 * @arg @ref LL_RCC_PLLSOURCE_MSI
4406 * @arg @ref LL_RCC_PLLSOURCE_HSI
4407 * @arg @ref LL_RCC_PLLSOURCE_HSE
4408 * @param PLLM This parameter can be one of the following values:
4409 * @arg @ref LL_RCC_PLLM_DIV_1
4410 * @arg @ref LL_RCC_PLLM_DIV_2
4411 * @arg @ref LL_RCC_PLLM_DIV_3
4412 * @arg @ref LL_RCC_PLLM_DIV_4
4413 * @arg @ref LL_RCC_PLLM_DIV_5
4414 * @arg @ref LL_RCC_PLLM_DIV_6
4415 * @arg @ref LL_RCC_PLLM_DIV_7
4416 * @arg @ref LL_RCC_PLLM_DIV_8
4417 * @param PLLN Between 8 and 86
4418 * @param PLLP This parameter can be one of the following values:
4419 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
4420 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
4421 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
4422 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
4423 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
4424 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4425 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
4426 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
4427 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
4428 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
4429 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
4430 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
4431 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
4432 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
4433 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
4434 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4435 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
4436 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
4437 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
4438 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
4439 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
4440 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
4441 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
4442 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
4443 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
4444 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
4445 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
4446 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
4447 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
4448 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
4449 * @retval None
4450 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4451 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4452 {
4453 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4454 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
4455 PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
4456 }
4457 #else
4458 /**
4459 * @brief Configure PLLSAI1 used for SAI domain clock
4460 * @note PLL Source and PLLM Divider can be written only when PLL,
4461 * PLLSAI1 and PLLSAI2 (*) are disabled.
4462 * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.
4463 * @note This can be selected for SAI1 or SAI2 (*)
4464 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4465 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4466 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
4467 * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
4468 * @param Source This parameter can be one of the following values:
4469 * @arg @ref LL_RCC_PLLSOURCE_NONE
4470 * @arg @ref LL_RCC_PLLSOURCE_MSI
4471 * @arg @ref LL_RCC_PLLSOURCE_HSI
4472 * @arg @ref LL_RCC_PLLSOURCE_HSE
4473 * @param PLLM This parameter can be one of the following values:
4474 * @arg @ref LL_RCC_PLLM_DIV_1
4475 * @arg @ref LL_RCC_PLLM_DIV_2
4476 * @arg @ref LL_RCC_PLLM_DIV_3
4477 * @arg @ref LL_RCC_PLLM_DIV_4
4478 * @arg @ref LL_RCC_PLLM_DIV_5
4479 * @arg @ref LL_RCC_PLLM_DIV_6
4480 * @arg @ref LL_RCC_PLLM_DIV_7
4481 * @arg @ref LL_RCC_PLLM_DIV_8
4482 * @param PLLN Between 8 and 86
4483 * @param PLLP This parameter can be one of the following values:
4484 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4485 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4486 * @retval None
4487 */
LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4488 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4489 {
4490 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4491 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);
4492 }
4493 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
4494
4495 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4496 /**
4497 * @brief Configure PLLSAI1 used for ADC domain clock
4498 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4499 * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
4500 * @note This can be selected for ADC
4501 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4502 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4503 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4504 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
4505 * @param Source This parameter can be one of the following values:
4506 * @arg @ref LL_RCC_PLLSOURCE_NONE
4507 * @arg @ref LL_RCC_PLLSOURCE_MSI
4508 * @arg @ref LL_RCC_PLLSOURCE_HSI
4509 * @arg @ref LL_RCC_PLLSOURCE_HSE
4510 * @param PLLM This parameter can be one of the following values:
4511 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4512 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4513 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4514 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4515 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4516 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4517 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4518 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4519 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4520 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4521 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4522 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4523 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4524 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4525 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4526 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4527 * @param PLLN Between 8 and 86
4528 * @param PLLR This parameter can be one of the following values:
4529 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
4530 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
4531 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
4532 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
4533 * @retval None
4534 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4535 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4536 {
4537 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4538 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
4539 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR);
4540 }
4541 #else
4542 /**
4543 * @brief Configure PLLSAI1 used for ADC domain clock
4544 * @note PLL Source and PLLM Divider can be written only when PLL,
4545 * PLLSAI1 and PLLSAI2 (*) are disabled.
4546 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled.
4547 * @note This can be selected for ADC
4548 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4549 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4550 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
4551 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
4552 * @param Source This parameter can be one of the following values:
4553 * @arg @ref LL_RCC_PLLSOURCE_NONE
4554 * @arg @ref LL_RCC_PLLSOURCE_MSI
4555 * @arg @ref LL_RCC_PLLSOURCE_HSI
4556 * @arg @ref LL_RCC_PLLSOURCE_HSE
4557 * @param PLLM This parameter can be one of the following values:
4558 * @arg @ref LL_RCC_PLLM_DIV_1
4559 * @arg @ref LL_RCC_PLLM_DIV_2
4560 * @arg @ref LL_RCC_PLLM_DIV_3
4561 * @arg @ref LL_RCC_PLLM_DIV_4
4562 * @arg @ref LL_RCC_PLLM_DIV_5
4563 * @arg @ref LL_RCC_PLLM_DIV_6
4564 * @arg @ref LL_RCC_PLLM_DIV_7
4565 * @arg @ref LL_RCC_PLLM_DIV_8
4566 * @param PLLN Between 8 and 86
4567 * @param PLLR This parameter can be one of the following values:
4568 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
4569 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
4570 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
4571 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
4572 * @retval None
4573 */
LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)4574 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4575 {
4576 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4577 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);
4578 }
4579 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4580
4581 /**
4582 * @brief Get SAI1PLL multiplication factor for VCO
4583 * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
4584 * @retval Between 8 and 86
4585 */
LL_RCC_PLLSAI1_GetN(void)4586 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
4587 {
4588 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
4589 }
4590
4591 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
4592 /**
4593 * @brief Get SAI1PLL division factor for PLLSAI1P
4594 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
4595 * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
4596 * @retval Returned value can be one of the following values:
4597 * @arg @ref LL_RCC_PLLSAI1P_DIV_2
4598 * @arg @ref LL_RCC_PLLSAI1P_DIV_3
4599 * @arg @ref LL_RCC_PLLSAI1P_DIV_4
4600 * @arg @ref LL_RCC_PLLSAI1P_DIV_5
4601 * @arg @ref LL_RCC_PLLSAI1P_DIV_6
4602 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4603 * @arg @ref LL_RCC_PLLSAI1P_DIV_8
4604 * @arg @ref LL_RCC_PLLSAI1P_DIV_9
4605 * @arg @ref LL_RCC_PLLSAI1P_DIV_10
4606 * @arg @ref LL_RCC_PLLSAI1P_DIV_11
4607 * @arg @ref LL_RCC_PLLSAI1P_DIV_12
4608 * @arg @ref LL_RCC_PLLSAI1P_DIV_13
4609 * @arg @ref LL_RCC_PLLSAI1P_DIV_14
4610 * @arg @ref LL_RCC_PLLSAI1P_DIV_15
4611 * @arg @ref LL_RCC_PLLSAI1P_DIV_16
4612 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4613 * @arg @ref LL_RCC_PLLSAI1P_DIV_18
4614 * @arg @ref LL_RCC_PLLSAI1P_DIV_19
4615 * @arg @ref LL_RCC_PLLSAI1P_DIV_20
4616 * @arg @ref LL_RCC_PLLSAI1P_DIV_21
4617 * @arg @ref LL_RCC_PLLSAI1P_DIV_22
4618 * @arg @ref LL_RCC_PLLSAI1P_DIV_23
4619 * @arg @ref LL_RCC_PLLSAI1P_DIV_24
4620 * @arg @ref LL_RCC_PLLSAI1P_DIV_25
4621 * @arg @ref LL_RCC_PLLSAI1P_DIV_26
4622 * @arg @ref LL_RCC_PLLSAI1P_DIV_27
4623 * @arg @ref LL_RCC_PLLSAI1P_DIV_28
4624 * @arg @ref LL_RCC_PLLSAI1P_DIV_29
4625 * @arg @ref LL_RCC_PLLSAI1P_DIV_30
4626 * @arg @ref LL_RCC_PLLSAI1P_DIV_31
4627 */
LL_RCC_PLLSAI1_GetP(void)4628 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
4629 {
4630 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
4631 }
4632 #else
4633 /**
4634 * @brief Get SAI1PLL division factor for PLLSAI1P
4635 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
4636 * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
4637 * @retval Returned value can be one of the following values:
4638 * @arg @ref LL_RCC_PLLSAI1P_DIV_7
4639 * @arg @ref LL_RCC_PLLSAI1P_DIV_17
4640 */
LL_RCC_PLLSAI1_GetP(void)4641 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
4642 {
4643 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
4644 }
4645 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
4646
4647 /**
4648 * @brief Get SAI1PLL division factor for PLLSAI1Q
4649 * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
4650 * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
4651 * @retval Returned value can be one of the following values:
4652 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2
4653 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4
4654 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6
4655 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8
4656 */
LL_RCC_PLLSAI1_GetQ(void)4657 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
4658 {
4659 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
4660 }
4661
4662 /**
4663 * @brief Get PLLSAI1 division factor for PLLSAIR
4664 * @note Used for PLLADC1CLK (ADC clock)
4665 * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
4666 * @retval Returned value can be one of the following values:
4667 * @arg @ref LL_RCC_PLLSAI1R_DIV_2
4668 * @arg @ref LL_RCC_PLLSAI1R_DIV_4
4669 * @arg @ref LL_RCC_PLLSAI1R_DIV_6
4670 * @arg @ref LL_RCC_PLLSAI1R_DIV_8
4671 */
LL_RCC_PLLSAI1_GetR(void)4672 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
4673 {
4674 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
4675 }
4676
4677 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
4678 /**
4679 * @brief Get Division factor for the PLLSAI1
4680 * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
4681 * @retval Returned value can be one of the following values:
4682 * @arg @ref LL_RCC_PLLSAI1M_DIV_1
4683 * @arg @ref LL_RCC_PLLSAI1M_DIV_2
4684 * @arg @ref LL_RCC_PLLSAI1M_DIV_3
4685 * @arg @ref LL_RCC_PLLSAI1M_DIV_4
4686 * @arg @ref LL_RCC_PLLSAI1M_DIV_5
4687 * @arg @ref LL_RCC_PLLSAI1M_DIV_6
4688 * @arg @ref LL_RCC_PLLSAI1M_DIV_7
4689 * @arg @ref LL_RCC_PLLSAI1M_DIV_8
4690 * @arg @ref LL_RCC_PLLSAI1M_DIV_9
4691 * @arg @ref LL_RCC_PLLSAI1M_DIV_10
4692 * @arg @ref LL_RCC_PLLSAI1M_DIV_11
4693 * @arg @ref LL_RCC_PLLSAI1M_DIV_12
4694 * @arg @ref LL_RCC_PLLSAI1M_DIV_13
4695 * @arg @ref LL_RCC_PLLSAI1M_DIV_14
4696 * @arg @ref LL_RCC_PLLSAI1M_DIV_15
4697 * @arg @ref LL_RCC_PLLSAI1M_DIV_16
4698 */
LL_RCC_PLLSAI1_GetDivider(void)4699 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
4700 {
4701 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
4702 }
4703 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
4704
4705 /**
4706 * @brief Enable PLLSAI1 output mapped on SAI domain clock
4707 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
4708 * @retval None
4709 */
LL_RCC_PLLSAI1_EnableDomain_SAI(void)4710 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
4711 {
4712 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
4713 }
4714
4715 /**
4716 * @brief Disable PLLSAI1 output mapped on SAI domain clock
4717 * @note In order to save power, when of the PLLSAI1 is
4718 * not used, should be 0
4719 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
4720 * @retval None
4721 */
LL_RCC_PLLSAI1_DisableDomain_SAI(void)4722 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
4723 {
4724 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
4725 }
4726
4727 /**
4728 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock
4729 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
4730 * @retval None
4731 */
LL_RCC_PLLSAI1_EnableDomain_48M(void)4732 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
4733 {
4734 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
4735 }
4736
4737 /**
4738 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock
4739 * @note In order to save power, when of the PLLSAI1 is
4740 * not used, should be 0
4741 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
4742 * @retval None
4743 */
LL_RCC_PLLSAI1_DisableDomain_48M(void)4744 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
4745 {
4746 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
4747 }
4748
4749 /**
4750 * @brief Enable PLLSAI1 output mapped on ADC domain clock
4751 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
4752 * @retval None
4753 */
LL_RCC_PLLSAI1_EnableDomain_ADC(void)4754 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
4755 {
4756 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
4757 }
4758
4759 /**
4760 * @brief Disable PLLSAI1 output mapped on ADC domain clock
4761 * @note In order to save power, when of the PLLSAI1 is
4762 * not used, Main PLLSAI1 should be 0
4763 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
4764 * @retval None
4765 */
LL_RCC_PLLSAI1_DisableDomain_ADC(void)4766 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
4767 {
4768 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
4769 }
4770
4771 /**
4772 * @}
4773 */
4774 #endif /* RCC_PLLSAI1_SUPPORT */
4775
4776 #if defined(RCC_PLLSAI2_SUPPORT)
4777 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
4778 * @{
4779 */
4780
4781 /**
4782 * @brief Enable PLLSAI2
4783 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
4784 * @retval None
4785 */
LL_RCC_PLLSAI2_Enable(void)4786 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
4787 {
4788 SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4789 }
4790
4791 /**
4792 * @brief Disable PLLSAI2
4793 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
4794 * @retval None
4795 */
LL_RCC_PLLSAI2_Disable(void)4796 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
4797 {
4798 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
4799 }
4800
4801 /**
4802 * @brief Check if PLLSAI2 Ready
4803 * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
4804 * @retval State of bit (1 or 0).
4805 */
LL_RCC_PLLSAI2_IsReady(void)4806 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
4807 {
4808 return ((READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY) ? 1UL : 0UL);
4809 }
4810
4811 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
4812 /**
4813 * @brief Configure PLLSAI2 used for SAI domain clock
4814 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4815 * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
4816 * @note This can be selected for SAI1 or SAI2
4817 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4818 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4819 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4820 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
4821 * @param Source This parameter can be one of the following values:
4822 * @arg @ref LL_RCC_PLLSOURCE_NONE
4823 * @arg @ref LL_RCC_PLLSOURCE_MSI
4824 * @arg @ref LL_RCC_PLLSOURCE_HSI
4825 * @arg @ref LL_RCC_PLLSOURCE_HSE
4826 * @param PLLM This parameter can be one of the following values:
4827 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
4828 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
4829 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
4830 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
4831 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
4832 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
4833 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
4834 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
4835 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
4836 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
4837 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
4838 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
4839 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
4840 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
4841 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
4842 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
4843 * @param PLLN Between 8 and 86
4844 * @param PLLP This parameter can be one of the following values:
4845 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
4846 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
4847 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
4848 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
4849 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
4850 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
4851 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
4852 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
4853 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
4854 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
4855 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
4856 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
4857 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
4858 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
4859 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
4860 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
4861 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
4862 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
4863 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
4864 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
4865 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
4866 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
4867 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
4868 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
4869 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
4870 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
4871 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
4872 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
4873 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
4874 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
4875 * @retval None
4876 */
LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4877 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4878 {
4879 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
4880 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
4881 PLLM | (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLP);
4882 }
4883 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
4884 /**
4885 * @brief Configure PLLSAI2 used for SAI domain clock
4886 * @note PLL Source and PLLM Divider can be written only when PLL,
4887 * PLLSAI1 and PLLSAI2 are disabled.
4888 * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
4889 * @note This can be selected for SAI1 or SAI2
4890 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4891 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4892 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4893 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
4894 * @param Source This parameter can be one of the following values:
4895 * @arg @ref LL_RCC_PLLSOURCE_NONE
4896 * @arg @ref LL_RCC_PLLSOURCE_MSI
4897 * @arg @ref LL_RCC_PLLSOURCE_HSI
4898 * @arg @ref LL_RCC_PLLSOURCE_HSE
4899 * @param PLLM This parameter can be one of the following values:
4900 * @arg @ref LL_RCC_PLLM_DIV_1
4901 * @arg @ref LL_RCC_PLLM_DIV_2
4902 * @arg @ref LL_RCC_PLLM_DIV_3
4903 * @arg @ref LL_RCC_PLLM_DIV_4
4904 * @arg @ref LL_RCC_PLLM_DIV_5
4905 * @arg @ref LL_RCC_PLLM_DIV_6
4906 * @arg @ref LL_RCC_PLLM_DIV_7
4907 * @arg @ref LL_RCC_PLLM_DIV_8
4908 * @param PLLN Between 8 and 86
4909 * @param PLLP This parameter can be one of the following values:
4910 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
4911 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
4912 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
4913 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
4914 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
4915 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
4916 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
4917 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
4918 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
4919 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
4920 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
4921 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
4922 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
4923 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
4924 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
4925 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
4926 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
4927 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
4928 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
4929 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
4930 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
4931 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
4932 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
4933 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
4934 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
4935 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
4936 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
4937 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
4938 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
4939 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
4940 * @retval None
4941 */
LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4942 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4943 {
4944 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4945 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
4946 }
4947 #else
4948 /**
4949 * @brief Configure PLLSAI2 used for SAI domain clock
4950 * @note PLL Source and PLLM Divider can be written only when PLL,
4951 * PLLSAI2 and PLLSAI2 are disabled.
4952 * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
4953 * @note This can be selected for SAI1 or SAI2
4954 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4955 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4956 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
4957 * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
4958 * @param Source This parameter can be one of the following values:
4959 * @arg @ref LL_RCC_PLLSOURCE_NONE
4960 * @arg @ref LL_RCC_PLLSOURCE_MSI
4961 * @arg @ref LL_RCC_PLLSOURCE_HSI
4962 * @arg @ref LL_RCC_PLLSOURCE_HSE
4963 * @param PLLM This parameter can be one of the following values:
4964 * @arg @ref LL_RCC_PLLM_DIV_1
4965 * @arg @ref LL_RCC_PLLM_DIV_2
4966 * @arg @ref LL_RCC_PLLM_DIV_3
4967 * @arg @ref LL_RCC_PLLM_DIV_4
4968 * @arg @ref LL_RCC_PLLM_DIV_5
4969 * @arg @ref LL_RCC_PLLM_DIV_6
4970 * @arg @ref LL_RCC_PLLM_DIV_7
4971 * @arg @ref LL_RCC_PLLM_DIV_8
4972 * @param PLLN Between 8 and 86
4973 * @param PLLP This parameter can be one of the following values:
4974 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
4975 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
4976 * @retval None
4977 */
LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)4978 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4979 {
4980 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4981 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);
4982 }
4983 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
4984
4985 #if defined(DSI)
4986 /**
4987 * @brief Configure PLLSAI2 used for DSI domain clock
4988 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
4989 * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
4990 * @note This can be selected for DSI
4991 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n
4992 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n
4993 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n
4994 * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
4995 * @param Source This parameter can be one of the following values:
4996 * @arg @ref LL_RCC_PLLSOURCE_NONE
4997 * @arg @ref LL_RCC_PLLSOURCE_MSI
4998 * @arg @ref LL_RCC_PLLSOURCE_HSI
4999 * @arg @ref LL_RCC_PLLSOURCE_HSE
5000 * @param PLLM This parameter can be one of the following values:
5001 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
5002 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
5003 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
5004 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
5005 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
5006 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
5007 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
5008 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
5009 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
5010 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
5011 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
5012 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
5013 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
5014 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
5015 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
5016 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
5017 * @param PLLN Between 8 and 86
5018 * @param PLLQ This parameter can be one of the following values:
5019 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
5020 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
5021 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
5022 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
5023 * @retval None
5024 */
LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)5025 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5026 {
5027 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5028 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q,
5029 (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLQ | PLLM);
5030 }
5031 #endif /* DSI */
5032
5033 #if defined(LTDC)
5034 /**
5035 * @brief Configure PLLSAI2 used for LTDC domain clock
5036 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
5037 * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
5038 * @note This can be selected for LTDC
5039 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5040 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5041 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5042 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
5043 * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
5044 * @param Source This parameter can be one of the following values:
5045 * @arg @ref LL_RCC_PLLSOURCE_NONE
5046 * @arg @ref LL_RCC_PLLSOURCE_MSI
5047 * @arg @ref LL_RCC_PLLSOURCE_HSI
5048 * @arg @ref LL_RCC_PLLSOURCE_HSE
5049 * @param PLLM This parameter can be one of the following values:
5050 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
5051 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
5052 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
5053 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
5054 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
5055 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
5056 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
5057 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
5058 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
5059 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
5060 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
5061 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
5062 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
5063 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
5064 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
5065 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
5066 * @param PLLN Between 8 and 86
5067 * @param PLLR This parameter can be one of the following values:
5068 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
5069 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
5070 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
5071 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
5072 * @param PLLDIVR This parameter can be one of the following values:
5073 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
5074 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
5075 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
5076 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
5077 * @retval None
5078 */
LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR,uint32_t PLLDIVR)5079 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
5080 {
5081 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5082 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
5083 (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM);
5084 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
5085 }
5086 #else
5087 /**
5088 * @brief Configure PLLSAI2 used for ADC domain clock
5089 * @note PLL Source and PLLM Divider can be written only when PLL,
5090 * PLLSAI2 and PLLSAI2 are disabled.
5091 * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
5092 * @note This can be selected for ADC
5093 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
5094 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
5095 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
5096 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
5097 * @param Source This parameter can be one of the following values:
5098 * @arg @ref LL_RCC_PLLSOURCE_NONE
5099 * @arg @ref LL_RCC_PLLSOURCE_MSI
5100 * @arg @ref LL_RCC_PLLSOURCE_HSI
5101 * @arg @ref LL_RCC_PLLSOURCE_HSE
5102 * @param PLLM This parameter can be one of the following values:
5103 * @arg @ref LL_RCC_PLLM_DIV_1
5104 * @arg @ref LL_RCC_PLLM_DIV_2
5105 * @arg @ref LL_RCC_PLLM_DIV_3
5106 * @arg @ref LL_RCC_PLLM_DIV_4
5107 * @arg @ref LL_RCC_PLLM_DIV_5
5108 * @arg @ref LL_RCC_PLLM_DIV_6
5109 * @arg @ref LL_RCC_PLLM_DIV_7
5110 * @arg @ref LL_RCC_PLLM_DIV_8
5111 * @param PLLN Between 8 and 86
5112 * @param PLLR This parameter can be one of the following values:
5113 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
5114 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
5115 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
5116 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
5117 * @retval None
5118 */
LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)5119 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5120 {
5121 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
5122 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);
5123 }
5124 #endif /* LTDC */
5125
5126 /**
5127 * @brief Get SAI2PLL multiplication factor for VCO
5128 * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
5129 * @retval Between 8 and 86
5130 */
LL_RCC_PLLSAI2_GetN(void)5131 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
5132 {
5133 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
5134 }
5135
5136 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
5137 /**
5138 * @brief Get SAI2PLL division factor for PLLSAI2P
5139 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
5140 * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
5141 * @retval Returned value can be one of the following values:
5142 * @arg @ref LL_RCC_PLLSAI2P_DIV_2
5143 * @arg @ref LL_RCC_PLLSAI2P_DIV_3
5144 * @arg @ref LL_RCC_PLLSAI2P_DIV_4
5145 * @arg @ref LL_RCC_PLLSAI2P_DIV_5
5146 * @arg @ref LL_RCC_PLLSAI2P_DIV_6
5147 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
5148 * @arg @ref LL_RCC_PLLSAI2P_DIV_8
5149 * @arg @ref LL_RCC_PLLSAI2P_DIV_9
5150 * @arg @ref LL_RCC_PLLSAI2P_DIV_10
5151 * @arg @ref LL_RCC_PLLSAI2P_DIV_11
5152 * @arg @ref LL_RCC_PLLSAI2P_DIV_12
5153 * @arg @ref LL_RCC_PLLSAI2P_DIV_13
5154 * @arg @ref LL_RCC_PLLSAI2P_DIV_14
5155 * @arg @ref LL_RCC_PLLSAI2P_DIV_15
5156 * @arg @ref LL_RCC_PLLSAI2P_DIV_16
5157 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
5158 * @arg @ref LL_RCC_PLLSAI2P_DIV_18
5159 * @arg @ref LL_RCC_PLLSAI2P_DIV_19
5160 * @arg @ref LL_RCC_PLLSAI2P_DIV_20
5161 * @arg @ref LL_RCC_PLLSAI2P_DIV_21
5162 * @arg @ref LL_RCC_PLLSAI2P_DIV_22
5163 * @arg @ref LL_RCC_PLLSAI2P_DIV_23
5164 * @arg @ref LL_RCC_PLLSAI2P_DIV_24
5165 * @arg @ref LL_RCC_PLLSAI2P_DIV_25
5166 * @arg @ref LL_RCC_PLLSAI2P_DIV_26
5167 * @arg @ref LL_RCC_PLLSAI2P_DIV_27
5168 * @arg @ref LL_RCC_PLLSAI2P_DIV_28
5169 * @arg @ref LL_RCC_PLLSAI2P_DIV_29
5170 * @arg @ref LL_RCC_PLLSAI2P_DIV_30
5171 * @arg @ref LL_RCC_PLLSAI2P_DIV_31
5172 */
LL_RCC_PLLSAI2_GetP(void)5173 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
5174 {
5175 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
5176 }
5177 #else
5178 /**
5179 * @brief Get SAI2PLL division factor for PLLSAI2P
5180 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
5181 * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
5182 * @retval Returned value can be one of the following values:
5183 * @arg @ref LL_RCC_PLLSAI2P_DIV_7
5184 * @arg @ref LL_RCC_PLLSAI2P_DIV_17
5185 */
LL_RCC_PLLSAI2_GetP(void)5186 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
5187 {
5188 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
5189 }
5190 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
5191
5192 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
5193 /**
5194 * @brief Get division factor for PLLSAI2Q
5195 * @note Used for PLLDSICLK (DSI clock)
5196 * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
5197 * @retval Returned value can be one of the following values:
5198 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2
5199 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4
5200 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6
5201 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8
5202 */
LL_RCC_PLLSAI2_GetQ(void)5203 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
5204 {
5205 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
5206 }
5207 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
5208
5209 /**
5210 * @brief Get SAI2PLL division factor for PLLSAI2R
5211 * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices
5212 * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
5213 * @retval Returned value can be one of the following values:
5214 * @arg @ref LL_RCC_PLLSAI2R_DIV_2
5215 * @arg @ref LL_RCC_PLLSAI2R_DIV_4
5216 * @arg @ref LL_RCC_PLLSAI2R_DIV_6
5217 * @arg @ref LL_RCC_PLLSAI2R_DIV_8
5218 */
LL_RCC_PLLSAI2_GetR(void)5219 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
5220 {
5221 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
5222 }
5223
5224 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
5225 /**
5226 * @brief Get Division factor for the PLLSAI2
5227 * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
5228 * @retval Returned value can be one of the following values:
5229 * @arg @ref LL_RCC_PLLSAI2M_DIV_1
5230 * @arg @ref LL_RCC_PLLSAI2M_DIV_2
5231 * @arg @ref LL_RCC_PLLSAI2M_DIV_3
5232 * @arg @ref LL_RCC_PLLSAI2M_DIV_4
5233 * @arg @ref LL_RCC_PLLSAI2M_DIV_5
5234 * @arg @ref LL_RCC_PLLSAI2M_DIV_6
5235 * @arg @ref LL_RCC_PLLSAI2M_DIV_7
5236 * @arg @ref LL_RCC_PLLSAI2M_DIV_8
5237 * @arg @ref LL_RCC_PLLSAI2M_DIV_9
5238 * @arg @ref LL_RCC_PLLSAI2M_DIV_10
5239 * @arg @ref LL_RCC_PLLSAI2M_DIV_11
5240 * @arg @ref LL_RCC_PLLSAI2M_DIV_12
5241 * @arg @ref LL_RCC_PLLSAI2M_DIV_13
5242 * @arg @ref LL_RCC_PLLSAI2M_DIV_14
5243 * @arg @ref LL_RCC_PLLSAI2M_DIV_15
5244 * @arg @ref LL_RCC_PLLSAI2M_DIV_16
5245 */
LL_RCC_PLLSAI2_GetDivider(void)5246 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
5247 {
5248 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
5249 }
5250 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
5251
5252 #if defined(RCC_CCIPR2_PLLSAI2DIVR)
5253 /**
5254 * @brief Get PLLSAI2 division factor for PLLSAI2DIVR
5255 * @note Used for LTDC domain clock
5256 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
5257 * @retval Returned value can be one of the following values:
5258 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
5259 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
5260 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
5261 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
5262 */
LL_RCC_PLLSAI2_GetDIVR(void)5263 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
5264 {
5265 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
5266 }
5267 #endif /* RCC_CCIPR2_PLLSAI2DIVR */
5268
5269 /**
5270 * @brief Enable PLLSAI2 output mapped on SAI domain clock
5271 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
5272 * @retval None
5273 */
LL_RCC_PLLSAI2_EnableDomain_SAI(void)5274 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
5275 {
5276 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5277 }
5278
5279 /**
5280 * @brief Disable PLLSAI2 output mapped on SAI domain clock
5281 * @note In order to save power, when of the PLLSAI2 is
5282 * not used, should be 0
5283 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
5284 * @retval None
5285 */
LL_RCC_PLLSAI2_DisableDomain_SAI(void)5286 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
5287 {
5288 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
5289 }
5290
5291 #if defined(DSI)
5292 /**
5293 * @brief Enable PLLSAI2 output mapped on DSI domain clock
5294 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI
5295 * @retval None
5296 */
LL_RCC_PLLSAI2_EnableDomain_DSI(void)5297 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
5298 {
5299 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5300 }
5301
5302 /**
5303 * @brief Disable PLLSAI2 output mapped on DSI domain clock
5304 * @note In order to save power, when of the PLLSAI2 is
5305 * not used, Main PLLSAI2 should be 0
5306 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
5307 * @retval None
5308 */
LL_RCC_PLLSAI2_DisableDomain_DSI(void)5309 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
5310 {
5311 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
5312 }
5313 #endif /* DSI */
5314
5315 #if defined(LTDC)
5316 /**
5317 * @brief Enable PLLSAI2 output mapped on LTDC domain clock
5318 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC
5319 * @retval None
5320 */
LL_RCC_PLLSAI2_EnableDomain_LTDC(void)5321 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
5322 {
5323 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5324 }
5325
5326 /**
5327 * @brief Disable PLLSAI2 output mapped on LTDC domain clock
5328 * @note In order to save power, when of the PLLSAI2 is
5329 * not used, Main PLLSAI2 should be 0
5330 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
5331 * @retval None
5332 */
LL_RCC_PLLSAI2_DisableDomain_LTDC(void)5333 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
5334 {
5335 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5336 }
5337 #else
5338 /**
5339 * @brief Enable PLLSAI2 output mapped on ADC domain clock
5340 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
5341 * @retval None
5342 */
LL_RCC_PLLSAI2_EnableDomain_ADC(void)5343 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
5344 {
5345 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5346 }
5347
5348 /**
5349 * @brief Disable PLLSAI2 output mapped on ADC domain clock
5350 * @note In order to save power, when of the PLLSAI2 is
5351 * not used, Main PLLSAI2 should be 0
5352 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
5353 * @retval None
5354 */
LL_RCC_PLLSAI2_DisableDomain_ADC(void)5355 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
5356 {
5357 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
5358 }
5359 #endif /* LTDC */
5360
5361 /**
5362 * @}
5363 */
5364 #endif /* RCC_PLLSAI2_SUPPORT */
5365
5366 #if defined(OCTOSPI1)
5367 /** @defgroup RCC_LL_EF_OCTOSPI OCTOSPI
5368 * @{
5369 */
5370
5371 /**
5372 * @brief Configure OCTOSPI1 DQS delay
5373 * @rmtoll DLYCFGR OCTOSPI1_DLY LL_RCC_OCTOSPI1_DelayConfig
5374 * @param Delay OCTOSPI1 DQS delay between 0 and 15
5375 * @retval None
5376 */
LL_RCC_OCTOSPI1_DelayConfig(uint32_t Delay)5377 __STATIC_INLINE void LL_RCC_OCTOSPI1_DelayConfig(uint32_t Delay)
5378 {
5379 MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI1_DLY, Delay);
5380 }
5381
5382 #if defined(OCTOSPI2)
5383 /**
5384 * @brief Configure OCTOSPI2 DQS delay
5385 * @rmtoll DLYCFGR OCTOSPI2_DLY LL_RCC_OCTOSPI2_DelayConfig
5386 * @param Delay OCTOSPI2 DQS delay between 0 and 15
5387 * @retval None
5388 */
LL_RCC_OCTOSPI2_DelayConfig(uint32_t Delay)5389 __STATIC_INLINE void LL_RCC_OCTOSPI2_DelayConfig(uint32_t Delay)
5390 {
5391 MODIFY_REG(RCC->DLYCFGR, RCC_DLYCFGR_OCTOSPI2_DLY, (Delay << RCC_DLYCFGR_OCTOSPI2_DLY_Pos));
5392 }
5393 #endif /* OCTOSPI2 */
5394
5395 /**
5396 * @}
5397 */
5398 #endif /* OCTOSPI1 */
5399
5400 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5401 * @{
5402 */
5403
5404 /**
5405 * @brief Clear LSI ready interrupt flag
5406 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5407 * @retval None
5408 */
LL_RCC_ClearFlag_LSIRDY(void)5409 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5410 {
5411 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5412 }
5413
5414 /**
5415 * @brief Clear LSE ready interrupt flag
5416 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5417 * @retval None
5418 */
LL_RCC_ClearFlag_LSERDY(void)5419 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5420 {
5421 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5422 }
5423
5424 /**
5425 * @brief Clear MSI ready interrupt flag
5426 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
5427 * @retval None
5428 */
LL_RCC_ClearFlag_MSIRDY(void)5429 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
5430 {
5431 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
5432 }
5433
5434 /**
5435 * @brief Clear HSI ready interrupt flag
5436 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5437 * @retval None
5438 */
LL_RCC_ClearFlag_HSIRDY(void)5439 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5440 {
5441 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5442 }
5443
5444 /**
5445 * @brief Clear HSE ready interrupt flag
5446 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5447 * @retval None
5448 */
LL_RCC_ClearFlag_HSERDY(void)5449 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5450 {
5451 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5452 }
5453
5454 /**
5455 * @brief Clear PLL ready interrupt flag
5456 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
5457 * @retval None
5458 */
LL_RCC_ClearFlag_PLLRDY(void)5459 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
5460 {
5461 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
5462 }
5463
5464 #if defined(RCC_HSI48_SUPPORT)
5465 /**
5466 * @brief Clear HSI48 ready interrupt flag
5467 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5468 * @retval None
5469 */
LL_RCC_ClearFlag_HSI48RDY(void)5470 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5471 {
5472 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5473 }
5474 #endif /* RCC_HSI48_SUPPORT */
5475
5476 #if defined(RCC_PLLSAI1_SUPPORT)
5477 /**
5478 * @brief Clear PLLSAI1 ready interrupt flag
5479 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
5480 * @retval None
5481 */
LL_RCC_ClearFlag_PLLSAI1RDY(void)5482 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
5483 {
5484 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
5485 }
5486 #endif /* RCC_PLLSAI1_SUPPORT */
5487
5488 #if defined(RCC_PLLSAI2_SUPPORT)
5489 /**
5490 * @brief Clear PLLSAI1 ready interrupt flag
5491 * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
5492 * @retval None
5493 */
LL_RCC_ClearFlag_PLLSAI2RDY(void)5494 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
5495 {
5496 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
5497 }
5498 #endif /* RCC_PLLSAI2_SUPPORT */
5499
5500 /**
5501 * @brief Clear Clock security system interrupt flag
5502 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
5503 * @retval None
5504 */
LL_RCC_ClearFlag_HSECSS(void)5505 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5506 {
5507 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
5508 }
5509
5510 /**
5511 * @brief Clear LSE Clock security system interrupt flag
5512 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
5513 * @retval None
5514 */
LL_RCC_ClearFlag_LSECSS(void)5515 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5516 {
5517 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5518 }
5519
5520 /**
5521 * @brief Check if LSI ready interrupt occurred or not
5522 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5523 * @retval State of bit (1 or 0).
5524 */
LL_RCC_IsActiveFlag_LSIRDY(void)5525 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5526 {
5527 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
5528 }
5529
5530 /**
5531 * @brief Check if LSE ready interrupt occurred or not
5532 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5533 * @retval State of bit (1 or 0).
5534 */
LL_RCC_IsActiveFlag_LSERDY(void)5535 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5536 {
5537 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
5538 }
5539
5540 /**
5541 * @brief Check if MSI ready interrupt occurred or not
5542 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
5543 * @retval State of bit (1 or 0).
5544 */
LL_RCC_IsActiveFlag_MSIRDY(void)5545 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
5546 {
5547 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL);
5548 }
5549
5550 /**
5551 * @brief Check if HSI ready interrupt occurred or not
5552 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5553 * @retval State of bit (1 or 0).
5554 */
LL_RCC_IsActiveFlag_HSIRDY(void)5555 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5556 {
5557 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
5558 }
5559
5560 /**
5561 * @brief Check if HSE ready interrupt occurred or not
5562 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5563 * @retval State of bit (1 or 0).
5564 */
LL_RCC_IsActiveFlag_HSERDY(void)5565 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5566 {
5567 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
5568 }
5569
5570 /**
5571 * @brief Check if PLL ready interrupt occurred or not
5572 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
5573 * @retval State of bit (1 or 0).
5574 */
LL_RCC_IsActiveFlag_PLLRDY(void)5575 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
5576 {
5577 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL);
5578 }
5579
5580 #if defined(RCC_HSI48_SUPPORT)
5581 /**
5582 * @brief Check if HSI48 ready interrupt occurred or not
5583 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5584 * @retval State of bit (1 or 0).
5585 */
LL_RCC_IsActiveFlag_HSI48RDY(void)5586 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5587 {
5588 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
5589 }
5590 #endif /* RCC_HSI48_SUPPORT */
5591
5592 #if defined(RCC_PLLSAI1_SUPPORT)
5593 /**
5594 * @brief Check if PLLSAI1 ready interrupt occurred or not
5595 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
5596 * @retval State of bit (1 or 0).
5597 */
LL_RCC_IsActiveFlag_PLLSAI1RDY(void)5598 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
5599 {
5600 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) ? 1UL : 0UL);
5601 }
5602 #endif /* RCC_PLLSAI1_SUPPORT */
5603
5604 #if defined(RCC_PLLSAI2_SUPPORT)
5605 /**
5606 * @brief Check if PLLSAI1 ready interrupt occurred or not
5607 * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
5608 * @retval State of bit (1 or 0).
5609 */
LL_RCC_IsActiveFlag_PLLSAI2RDY(void)5610 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
5611 {
5612 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) ? 1UL : 0UL);
5613 }
5614 #endif /* RCC_PLLSAI2_SUPPORT */
5615
5616 /**
5617 * @brief Check if Clock security system interrupt occurred or not
5618 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
5619 * @retval State of bit (1 or 0).
5620 */
LL_RCC_IsActiveFlag_HSECSS(void)5621 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5622 {
5623 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
5624 }
5625
5626 /**
5627 * @brief Check if LSE Clock security system interrupt occurred or not
5628 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
5629 * @retval State of bit (1 or 0).
5630 */
LL_RCC_IsActiveFlag_LSECSS(void)5631 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5632 {
5633 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
5634 }
5635
5636 /**
5637 * @brief Check if RCC flag FW reset is set or not.
5638 * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
5639 * @retval State of bit (1 or 0).
5640 */
LL_RCC_IsActiveFlag_FWRST(void)5641 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
5642 {
5643 return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL);
5644 }
5645
5646 /**
5647 * @brief Check if RCC flag Independent Watchdog reset is set or not.
5648 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
5649 * @retval State of bit (1 or 0).
5650 */
LL_RCC_IsActiveFlag_IWDGRST(void)5651 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
5652 {
5653 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
5654 }
5655
5656 /**
5657 * @brief Check if RCC flag Low Power reset is set or not.
5658 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
5659 * @retval State of bit (1 or 0).
5660 */
LL_RCC_IsActiveFlag_LPWRRST(void)5661 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5662 {
5663 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
5664 }
5665
5666 /**
5667 * @brief Check if RCC flag is set or not.
5668 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
5669 * @retval State of bit (1 or 0).
5670 */
LL_RCC_IsActiveFlag_OBLRST(void)5671 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
5672 {
5673 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
5674 }
5675
5676 /**
5677 * @brief Check if RCC flag Pin reset is set or not.
5678 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5679 * @retval State of bit (1 or 0).
5680 */
LL_RCC_IsActiveFlag_PINRST(void)5681 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5682 {
5683 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
5684 }
5685
5686 /**
5687 * @brief Check if RCC flag Software reset is set or not.
5688 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
5689 * @retval State of bit (1 or 0).
5690 */
LL_RCC_IsActiveFlag_SFTRST(void)5691 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5692 {
5693 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
5694 }
5695
5696 /**
5697 * @brief Check if RCC flag Window Watchdog reset is set or not.
5698 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
5699 * @retval State of bit (1 or 0).
5700 */
LL_RCC_IsActiveFlag_WWDGRST(void)5701 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
5702 {
5703 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
5704 }
5705
5706 /**
5707 * @brief Check if RCC flag BOR reset is set or not.
5708 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5709 * @retval State of bit (1 or 0).
5710 */
LL_RCC_IsActiveFlag_BORRST(void)5711 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5712 {
5713 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
5714 }
5715
5716 /**
5717 * @brief Set RMVF bit to clear the reset flags.
5718 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
5719 * @retval None
5720 */
LL_RCC_ClearResetFlags(void)5721 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5722 {
5723 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
5724 }
5725
5726 /**
5727 * @}
5728 */
5729
5730 /** @defgroup RCC_LL_EF_IT_Management IT Management
5731 * @{
5732 */
5733
5734 /**
5735 * @brief Enable LSI ready interrupt
5736 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
5737 * @retval None
5738 */
LL_RCC_EnableIT_LSIRDY(void)5739 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5740 {
5741 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5742 }
5743
5744 /**
5745 * @brief Enable LSE ready interrupt
5746 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
5747 * @retval None
5748 */
LL_RCC_EnableIT_LSERDY(void)5749 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5750 {
5751 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5752 }
5753
5754 /**
5755 * @brief Enable MSI ready interrupt
5756 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
5757 * @retval None
5758 */
LL_RCC_EnableIT_MSIRDY(void)5759 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
5760 {
5761 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
5762 }
5763
5764 /**
5765 * @brief Enable HSI ready interrupt
5766 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
5767 * @retval None
5768 */
LL_RCC_EnableIT_HSIRDY(void)5769 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5770 {
5771 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5772 }
5773
5774 /**
5775 * @brief Enable HSE ready interrupt
5776 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
5777 * @retval None
5778 */
LL_RCC_EnableIT_HSERDY(void)5779 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5780 {
5781 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5782 }
5783
5784 /**
5785 * @brief Enable PLL ready interrupt
5786 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
5787 * @retval None
5788 */
LL_RCC_EnableIT_PLLRDY(void)5789 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
5790 {
5791 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
5792 }
5793
5794 #if defined(RCC_HSI48_SUPPORT)
5795 /**
5796 * @brief Enable HSI48 ready interrupt
5797 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
5798 * @retval None
5799 */
LL_RCC_EnableIT_HSI48RDY(void)5800 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
5801 {
5802 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5803 }
5804 #endif /* RCC_HSI48_SUPPORT */
5805
5806 #if defined(RCC_PLLSAI1_SUPPORT)
5807 /**
5808 * @brief Enable PLLSAI1 ready interrupt
5809 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
5810 * @retval None
5811 */
LL_RCC_EnableIT_PLLSAI1RDY(void)5812 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
5813 {
5814 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
5815 }
5816 #endif /* RCC_PLLSAI1_SUPPORT */
5817
5818 #if defined(RCC_PLLSAI2_SUPPORT)
5819 /**
5820 * @brief Enable PLLSAI2 ready interrupt
5821 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
5822 * @retval None
5823 */
LL_RCC_EnableIT_PLLSAI2RDY(void)5824 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
5825 {
5826 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
5827 }
5828 #endif /* RCC_PLLSAI2_SUPPORT */
5829
5830 /**
5831 * @brief Enable LSE clock security system interrupt
5832 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
5833 * @retval None
5834 */
LL_RCC_EnableIT_LSECSS(void)5835 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
5836 {
5837 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
5838 }
5839
5840 /**
5841 * @brief Disable LSI ready interrupt
5842 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
5843 * @retval None
5844 */
LL_RCC_DisableIT_LSIRDY(void)5845 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
5846 {
5847 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5848 }
5849
5850 /**
5851 * @brief Disable LSE ready interrupt
5852 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
5853 * @retval None
5854 */
LL_RCC_DisableIT_LSERDY(void)5855 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
5856 {
5857 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5858 }
5859
5860 /**
5861 * @brief Disable MSI ready interrupt
5862 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
5863 * @retval None
5864 */
LL_RCC_DisableIT_MSIRDY(void)5865 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
5866 {
5867 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
5868 }
5869
5870 /**
5871 * @brief Disable HSI ready interrupt
5872 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
5873 * @retval None
5874 */
LL_RCC_DisableIT_HSIRDY(void)5875 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
5876 {
5877 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5878 }
5879
5880 /**
5881 * @brief Disable HSE ready interrupt
5882 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
5883 * @retval None
5884 */
LL_RCC_DisableIT_HSERDY(void)5885 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5886 {
5887 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5888 }
5889
5890 /**
5891 * @brief Disable PLL ready interrupt
5892 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
5893 * @retval None
5894 */
LL_RCC_DisableIT_PLLRDY(void)5895 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
5896 {
5897 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
5898 }
5899
5900 #if defined(RCC_HSI48_SUPPORT)
5901 /**
5902 * @brief Disable HSI48 ready interrupt
5903 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
5904 * @retval None
5905 */
LL_RCC_DisableIT_HSI48RDY(void)5906 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
5907 {
5908 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5909 }
5910 #endif /* RCC_HSI48_SUPPORT */
5911
5912 #if defined(RCC_PLLSAI1_SUPPORT)
5913 /**
5914 * @brief Disable PLLSAI1 ready interrupt
5915 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
5916 * @retval None
5917 */
LL_RCC_DisableIT_PLLSAI1RDY(void)5918 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
5919 {
5920 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
5921 }
5922 #endif /* RCC_PLLSAI1_SUPPORT */
5923
5924 #if defined(RCC_PLLSAI2_SUPPORT)
5925 /**
5926 * @brief Disable PLLSAI2 ready interrupt
5927 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
5928 * @retval None
5929 */
LL_RCC_DisableIT_PLLSAI2RDY(void)5930 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
5931 {
5932 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
5933 }
5934 #endif /* RCC_PLLSAI2_SUPPORT */
5935
5936 /**
5937 * @brief Disable LSE clock security system interrupt
5938 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
5939 * @retval None
5940 */
LL_RCC_DisableIT_LSECSS(void)5941 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
5942 {
5943 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
5944 }
5945
5946 /**
5947 * @brief Checks if LSI ready interrupt source is enabled or disabled.
5948 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
5949 * @retval State of bit (1 or 0).
5950 */
LL_RCC_IsEnabledIT_LSIRDY(void)5951 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5952 {
5953 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
5954 }
5955
5956 /**
5957 * @brief Checks if LSE ready interrupt source is enabled or disabled.
5958 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
5959 * @retval State of bit (1 or 0).
5960 */
LL_RCC_IsEnabledIT_LSERDY(void)5961 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5962 {
5963 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
5964 }
5965
5966 /**
5967 * @brief Checks if MSI ready interrupt source is enabled or disabled.
5968 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
5969 * @retval State of bit (1 or 0).
5970 */
LL_RCC_IsEnabledIT_MSIRDY(void)5971 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
5972 {
5973 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL);
5974 }
5975
5976 /**
5977 * @brief Checks if HSI ready interrupt source is enabled or disabled.
5978 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
5979 * @retval State of bit (1 or 0).
5980 */
LL_RCC_IsEnabledIT_HSIRDY(void)5981 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5982 {
5983 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
5984 }
5985
5986 /**
5987 * @brief Checks if HSE ready interrupt source is enabled or disabled.
5988 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
5989 * @retval State of bit (1 or 0).
5990 */
LL_RCC_IsEnabledIT_HSERDY(void)5991 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5992 {
5993 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
5994 }
5995
5996 /**
5997 * @brief Checks if PLL ready interrupt source is enabled or disabled.
5998 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
5999 * @retval State of bit (1 or 0).
6000 */
LL_RCC_IsEnabledIT_PLLRDY(void)6001 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
6002 {
6003 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL);
6004 }
6005
6006 #if defined(RCC_HSI48_SUPPORT)
6007 /**
6008 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
6009 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
6010 * @retval State of bit (1 or 0).
6011 */
LL_RCC_IsEnabledIT_HSI48RDY(void)6012 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
6013 {
6014 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
6015 }
6016 #endif /* RCC_HSI48_SUPPORT */
6017
6018 #if defined(RCC_PLLSAI1_SUPPORT)
6019 /**
6020 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
6021 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
6022 * @retval State of bit (1 or 0).
6023 */
LL_RCC_IsEnabledIT_PLLSAI1RDY(void)6024 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
6025 {
6026 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == RCC_CIER_PLLSAI1RDYIE) ? 1UL : 0UL);
6027 }
6028 #endif /* RCC_PLLSAI1_SUPPORT */
6029
6030 #if defined(RCC_PLLSAI2_SUPPORT)
6031 /**
6032 * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
6033 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
6034 * @retval State of bit (1 or 0).
6035 */
LL_RCC_IsEnabledIT_PLLSAI2RDY(void)6036 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
6037 {
6038 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == RCC_CIER_PLLSAI2RDYIE) ? 1UL : 0UL);
6039 }
6040 #endif /* RCC_PLLSAI2_SUPPORT */
6041
6042 /**
6043 * @brief Checks if LSECSS interrupt source is enabled or disabled.
6044 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
6045 * @retval State of bit (1 or 0).
6046 */
LL_RCC_IsEnabledIT_LSECSS(void)6047 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
6048 {
6049 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
6050 }
6051
6052 /**
6053 * @}
6054 */
6055
6056 #if defined(USE_FULL_LL_DRIVER)
6057 /** @defgroup RCC_LL_EF_Init De-initialization function
6058 * @{
6059 */
6060 ErrorStatus LL_RCC_DeInit(void);
6061 /**
6062 * @}
6063 */
6064
6065 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6066 * @{
6067 */
6068 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
6069 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6070 #if defined(UART4) || defined(UART5)
6071 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
6072 #endif /* UART4 || UART5 */
6073 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6074 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6075 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6076 #if defined(SAI1)
6077 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6078 #endif /* SAI1 */
6079 #if defined(SDMMC1)
6080 #if defined(RCC_CCIPR2_SDMMCSEL)
6081 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
6082 #endif
6083 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6084 #endif /* SDMMC1 */
6085 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6086 #if defined(USB_OTG_FS) || defined(USB)
6087 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6088 #endif /* USB_OTG_FS || USB */
6089 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
6090 #if defined(SWPMI1)
6091 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
6092 #endif /* SWPMI1 */
6093 #if defined(DFSDM1_Channel0)
6094 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
6095 #if defined(RCC_CCIPR2_DFSDM1SEL)
6096 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
6097 #endif /* RCC_CCIPR2_DFSDM1SEL */
6098 #endif /* DFSDM1_Channel0 */
6099 #if defined(LTDC)
6100 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
6101 #endif /* LTDC */
6102 #if defined(DSI)
6103 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
6104 #endif /* DSI */
6105 #if defined(OCTOSPI1)
6106 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
6107 #endif /* OCTOSPI1 */
6108 /**
6109 * @}
6110 */
6111 #endif /* USE_FULL_LL_DRIVER */
6112
6113 /**
6114 * @}
6115 */
6116
6117 /**
6118 * @}
6119 */
6120
6121 #endif /* defined(RCC) */
6122
6123 /**
6124 * @}
6125 */
6126
6127 #ifdef __cplusplus
6128 }
6129 #endif
6130
6131 #endif /* STM32L4xx_LL_RCC_H */
6132
6133 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
6134