1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_DAC_H
22 #define STM32L4xx_LL_DAC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DAC1)
36
37 /** @defgroup DAC_LL DAC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
48
49 /* Internal masks for DAC channels definition */
50 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
52 /* - channel bits position into register SWTRIG */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 /* - channel register offset of sample-and-hold sample time register SHSRx */
56 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
58 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
59
60 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
61 #if defined(DAC_CHANNEL2_SUPPORT)
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64 #else
65 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
66 #endif /* DAC_CHANNEL2_SUPPORT */
67
68 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
69 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
70 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
71 #if defined(DAC_CHANNEL2_SUPPORT)
72 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
74 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
75 #endif /* DAC_CHANNEL2_SUPPORT */
76 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U
77 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
78 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
79 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
80
81 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
82 #if defined(DAC_CHANNEL2_SUPPORT)
83 #define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
84 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
85 #else
86 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
87 #endif /* DAC_CHANNEL2_SUPPORT */
88
89 #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */
90 #if defined(DAC_CHANNEL2_SUPPORT)
91 #define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
92 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
93 #else
94 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET)
95 #endif /* DAC_CHANNEL2_SUPPORT */
96
97 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */
99 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */
100
101 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
102 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
103 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
104 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
105 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
106
107 /* DAC registers bits positions */
108 #if defined(DAC_CHANNEL2_SUPPORT)
109 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
110 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
111 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
112 #endif /* DAC_CHANNEL2_SUPPORT */
113
114 /* Miscellaneous data */
115 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
116
117 /**
118 * @}
119 */
120
121
122 /* Private macros ------------------------------------------------------------*/
123 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
124 * @{
125 */
126
127 /**
128 * @brief Driver macro reserved for internal use: set a pointer to
129 * a register from a register basis from which an offset
130 * is applied.
131 * @param __REG__ Register basis from which the offset is applied.
132 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
133 * @retval Pointer to register address
134 */
135 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
136 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
137
138 /**
139 * @}
140 */
141
142
143 /* Exported types ------------------------------------------------------------*/
144 #if defined(USE_FULL_LL_DRIVER)
145 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
146 * @{
147 */
148
149 /**
150 * @brief Structure definition of some features of DAC instance.
151 */
152 typedef struct
153 {
154 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
155 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
156
157 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
158
159 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
160 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
161
162 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
163
164 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
165 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
166 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
167 @note If waveform automatic generation mode is disabled, this parameter is discarded.
168
169 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
170 depending on the wave automatic generation selected. */
171
172 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
173 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
174
175 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
176
177 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
178 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
179
180 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
181
182 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
183 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
184
185 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
186 } LL_DAC_InitTypeDef;
187
188 /**
189 * @}
190 */
191 #endif /* USE_FULL_LL_DRIVER */
192
193 /* Exported constants --------------------------------------------------------*/
194 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
195 * @{
196 */
197
198 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
199 * @brief Flags defines which can be used with LL_DAC_ReadReg function
200 * @{
201 */
202 /* DAC channel 1 flags */
203 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
204 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
205 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
206
207 #if defined(DAC_CHANNEL2_SUPPORT)
208 /* DAC channel 2 flags */
209 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
210 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
211 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
212 #endif /* DAC_CHANNEL2_SUPPORT */
213 /**
214 * @}
215 */
216
217 /** @defgroup DAC_LL_EC_IT DAC interruptions
218 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
219 * @{
220 */
221 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
222 #if defined(DAC_CHANNEL2_SUPPORT)
223 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
224 #endif /* DAC_CHANNEL2_SUPPORT */
225 /**
226 * @}
227 */
228
229 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
230 * @{
231 */
232 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
233 #if defined(DAC_CHANNEL2_SUPPORT)
234 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
235 #endif /* DAC_CHANNEL2_SUPPORT */
236 /**
237 * @}
238 */
239 #if defined (DAC_CR_HFSEL) /* High frequency interface mode */
240
241 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
242 * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
243 * @{
244 */
245 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */
246 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
247 /**
248 * @}
249 */
250 #endif /* High frequency interface mode */
251
252 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
253 * @{
254 */
255 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /*!< DAC channel in mode normal operation */
256 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
257 /**
258 * @}
259 */
260
261 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
262 * @{
263 */
264 #if defined (DAC_CR_TSEL1_3)
265 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */
266 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
267 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
268 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
269 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
270 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
271 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
272 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
273 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. */
274 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. */
275 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
276 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
277 #else
278 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
279 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
280 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
281 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
282 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
283 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
284 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
285 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
286 #endif
287
288 /**
289 * @}
290 */
291
292 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
293 * @{
294 */
295 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
296 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
297 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
298 /**
299 * @}
300 */
301
302 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
303 * @{
304 */
305 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
306 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
307 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
308 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
309 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
312 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
317 /**
318 * @}
319 */
320
321 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
322 * @{
323 */
324 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
325 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
326 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
327 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
328 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
329 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
330 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
331 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
332 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
333 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
335 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
336 /**
337 * @}
338 */
339
340 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
341 * @{
342 */
343 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */
344 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
345 /**
346 * @}
347 */
348
349 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
350 * @{
351 */
352 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
353 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
354 /**
355 * @}
356 */
357
358 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
359 * @{
360 */
361 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */
362 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
363 /**
364 * @}
365 */
366
367 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
368 * @{
369 */
370 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
371 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
372 /**
373 * @}
374 */
375
376 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
377 * @{
378 */
379 /* List of DAC registers intended to be used (most commonly) with */
380 /* DMA transfer. */
381 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
382 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
383 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
384 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
385 /**
386 * @}
387 */
388
389 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
390 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
391 * not timeout values.
392 * For details on delays values, refer to descriptions in source code
393 * above each literal definition.
394 * @{
395 */
396
397 /* Delay for DAC channel voltage settling time from DAC channel startup */
398 /* (transition from disable to enable). */
399 /* Note: DAC channel startup time depends on board application environment: */
400 /* impedance connected to DAC channel output. */
401 /* The delay below is specified under conditions: */
402 /* - voltage maximum transition (lowest to highest value) */
403 /* - until voltage reaches final value +-1LSB */
404 /* - DAC channel output buffer enabled */
405 /* - load impedance of 5kOhm (min), 50pF (max) */
406 /* Literal set to maximum value (refer to device datasheet, */
407 /* parameter "tWAKEUP"). */
408 /* Unit: us */
409 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
410
411
412 /* Delay for DAC channel voltage settling time. */
413 /* Note: DAC channel startup time depends on board application environment: */
414 /* impedance connected to DAC channel output. */
415 /* The delay below is specified under conditions: */
416 /* - voltage maximum transition (lowest to highest value) */
417 /* - until voltage reaches final value +-1LSB */
418 /* - DAC channel output buffer enabled */
419 /* - load impedance of 5kOhm min, 50pF max */
420 /* Literal set to maximum value (refer to device datasheet, */
421 /* parameter "tSETTLING"). */
422 /* Unit: us */
423 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */
424
425 /**
426 * @}
427 */
428
429 /**
430 * @}
431 */
432
433 /* Exported macro ------------------------------------------------------------*/
434 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
435 * @{
436 */
437
438 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
439 * @{
440 */
441
442 /**
443 * @brief Write a value in DAC register
444 * @param __INSTANCE__ DAC Instance
445 * @param __REG__ Register to be written
446 * @param __VALUE__ Value to be written in the register
447 * @retval None
448 */
449 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
450
451 /**
452 * @brief Read a value in DAC register
453 * @param __INSTANCE__ DAC Instance
454 * @param __REG__ Register to be read
455 * @retval Register value
456 */
457 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
458
459 /**
460 * @}
461 */
462
463 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
464 * @{
465 */
466
467 /**
468 * @brief Helper macro to get DAC channel number in decimal format
469 * from literals LL_DAC_CHANNEL_x.
470 * Example:
471 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
472 * will return decimal number "1".
473 * @note The input can be a value from functions where a channel
474 * number is returned.
475 * @param __CHANNEL__ This parameter can be one of the following values:
476 * @arg @ref LL_DAC_CHANNEL_1
477 * @arg @ref LL_DAC_CHANNEL_2
478 * @retval 1...2
479 */
480 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
481 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
482
483 /**
484 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
485 * from number in decimal format.
486 * Example:
487 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
488 * will return a data equivalent to "LL_DAC_CHANNEL_1".
489 * @note If the input parameter does not correspond to a DAC channel,
490 * this macro returns value '0'.
491 * @param __DECIMAL_NB__ 1...2
492 * @retval Returned value can be one of the following values:
493 * @arg @ref LL_DAC_CHANNEL_1
494 * @arg @ref LL_DAC_CHANNEL_2
495 */
496 #if defined(DAC_CHANNEL2_SUPPORT)
497 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
498 (((__DECIMAL_NB__) == 1U) \
499 ? ( \
500 LL_DAC_CHANNEL_1 \
501 ) \
502 : \
503 (((__DECIMAL_NB__) == 2U) \
504 ? ( \
505 LL_DAC_CHANNEL_2 \
506 ) \
507 : \
508 ( \
509 0U \
510 ) \
511 ) \
512 )
513 #else
514 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
515 (((__DECIMAL_NB__) == 1U) \
516 ? ( \
517 LL_DAC_CHANNEL_1 \
518 ) \
519 : \
520 ( \
521 0U \
522 ) \
523 )
524 #endif /* DAC_CHANNEL2_SUPPORT */
525
526 /**
527 * @brief Helper macro to define the DAC conversion data full-scale digital
528 * value corresponding to the selected DAC resolution.
529 * @note DAC conversion data full-scale corresponds to voltage range
530 * determined by analog voltage references Vref+ and Vref-
531 * (refer to reference manual).
532 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
533 * @arg @ref LL_DAC_RESOLUTION_12B
534 * @arg @ref LL_DAC_RESOLUTION_8B
535 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
536 */
537 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
538 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
539
540 /**
541 * @brief Helper macro to calculate the DAC conversion data (unit: digital
542 * value) corresponding to a voltage (unit: mVolt).
543 * @note This helper macro is intended to provide input data in voltage
544 * rather than digital value,
545 * to be used with LL DAC functions such as
546 * @ref LL_DAC_ConvertData12RightAligned().
547 * @note Analog reference voltage (Vref+) must be either known from
548 * user board environment or can be calculated using ADC measurement
549 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
550 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
551 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
552 * (unit: mVolt).
553 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
554 * @arg @ref LL_DAC_RESOLUTION_12B
555 * @arg @ref LL_DAC_RESOLUTION_8B
556 * @retval DAC conversion data (unit: digital value)
557 */
558 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
559 __DAC_VOLTAGE__,\
560 __DAC_RESOLUTION__) \
561 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
562 / (__VREFANALOG_VOLTAGE__) \
563 )
564
565 /**
566 * @}
567 */
568
569 /**
570 * @}
571 */
572
573
574 /* Exported functions --------------------------------------------------------*/
575 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
576 * @{
577 */
578
579 #if defined (DAC_CR_HFSEL) /* High frequency interface mode */
580
581 /** @defgroup DAC_LL_EF_High_Frequency_Configuration High Frequency Configuration of DAC instance
582 * @{
583 */
584 /**
585 * @brief Set the high frequency interface mode for the selected DAC instance
586 * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode
587 * @param DACx DAC instance
588 * @param HighFreqMode This parameter can be one of the following values:
589 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
590 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
591 * @retval None
592 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)593 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
594 {
595 MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode);
596 }
597
598 /**
599 * @brief Get the high frequency interface mode for the selected DAC instance
600 * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode
601 * @param DACx DAC instance
602 * @retval Returned value can be one of the following values:
603 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
604 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
605 */
LL_DAC_GetHighFrequencyMode(DAC_TypeDef * DACx)606 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
607 {
608 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL));
609 }
610 /**
611 * @}
612 */
613
614 #endif /* High frequency interface mode */
615
616 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
617 * @{
618 */
619
620 /**
621 * @brief Set the operating mode for the selected DAC channel:
622 * calibration or normal operating mode.
623 * @rmtoll CR CEN1 LL_DAC_SetMode\n
624 * CR CEN2 LL_DAC_SetMode
625 * @param DACx DAC instance
626 * @param DAC_Channel This parameter can be one of the following values:
627 * @arg @ref LL_DAC_CHANNEL_1
628 * @arg @ref LL_DAC_CHANNEL_2
629 * @param ChannelMode This parameter can be one of the following values:
630 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
631 * @arg @ref LL_DAC_MODE_CALIBRATION
632 * @retval None
633 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)634 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
635 {
636 MODIFY_REG(DACx->CR,
637 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
638 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
639 }
640
641 /**
642 * @brief Get the operating mode for the selected DAC channel:
643 * calibration or normal operating mode.
644 * @rmtoll CR CEN1 LL_DAC_GetMode\n
645 * CR CEN2 LL_DAC_GetMode
646 * @param DACx DAC instance
647 * @param DAC_Channel This parameter can be one of the following values:
648 * @arg @ref LL_DAC_CHANNEL_1
649 * @arg @ref LL_DAC_CHANNEL_2
650 * @retval Returned value can be one of the following values:
651 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
652 * @arg @ref LL_DAC_MODE_CALIBRATION
653 */
LL_DAC_GetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)654 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
655 {
656 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
657 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
658 );
659 }
660
661 /**
662 * @brief Set the offset trimming value for the selected DAC channel.
663 * Trimming has an impact when output buffer is enabled
664 * and is intended to replace factory calibration default values.
665 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
666 * CCR OTRIM2 LL_DAC_SetTrimmingValue
667 * @param DACx DAC instance
668 * @param DAC_Channel This parameter can be one of the following values:
669 * @arg @ref LL_DAC_CHANNEL_1
670 * @arg @ref LL_DAC_CHANNEL_2
671 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
672 * @retval None
673 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)674 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
675 {
676 MODIFY_REG(DACx->CCR,
677 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
678 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
679 }
680
681 /**
682 * @brief Get the offset trimming value for the selected DAC channel.
683 * Trimming has an impact when output buffer is enabled
684 * and is intended to replace factory calibration default values.
685 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
686 * CCR OTRIM2 LL_DAC_GetTrimmingValue
687 * @param DACx DAC instance
688 * @param DAC_Channel This parameter can be one of the following values:
689 * @arg @ref LL_DAC_CHANNEL_1
690 * @arg @ref LL_DAC_CHANNEL_2
691 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
692 */
LL_DAC_GetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel)693 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
694 {
695 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
696 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
697 );
698 }
699
700 /**
701 * @brief Set the conversion trigger source for the selected DAC channel.
702 * @note For conversion trigger source to be effective, DAC trigger
703 * must be enabled using function @ref LL_DAC_EnableTrigger().
704 * @note To set conversion trigger source, DAC channel must be disabled.
705 * Otherwise, the setting is discarded.
706 * @note Availability of parameters of trigger sources from timer
707 * depends on timers availability on the selected device.
708 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
709 * CR TSEL2 LL_DAC_SetTriggerSource
710 * @param DACx DAC instance
711 * @param DAC_Channel This parameter can be one of the following values:
712 * @arg @ref LL_DAC_CHANNEL_1
713 * @arg @ref LL_DAC_CHANNEL_2
714 * @param TriggerSource This parameter can be one of the following values:
715 * @arg @ref LL_DAC_TRIG_SOFTWARE
716 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
717 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
718 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
719 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
720 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
721 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
722 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
723 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
724 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
725 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
726 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
727 * @retval None
728 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)729 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
730 {
731 MODIFY_REG(DACx->CR,
732 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
733 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
734 }
735
736 /**
737 * @brief Get the conversion trigger source for the selected DAC channel.
738 * @note For conversion trigger source to be effective, DAC trigger
739 * must be enabled using function @ref LL_DAC_EnableTrigger().
740 * @note Availability of parameters of trigger sources from timer
741 * depends on timers availability on the selected device.
742 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
743 * CR TSEL2 LL_DAC_GetTriggerSource
744 * @param DACx DAC instance
745 * @param DAC_Channel This parameter can be one of the following values:
746 * @arg @ref LL_DAC_CHANNEL_1
747 * @arg @ref LL_DAC_CHANNEL_2 (1)
748 *
749 * (1) On this STM32 serie, parameter not available on all devices.
750 * Refer to device datasheet for channels availability.
751 * @retval Returned value can be one of the following values:
752 * @arg @ref LL_DAC_TRIG_SOFTWARE
753 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
754 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
755 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
756 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
757 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
758 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
759 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
760 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
761 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
762 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
763 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
764 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)765 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
766 {
767 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
768 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
769 );
770 }
771
772 /**
773 * @brief Set the waveform automatic generation mode
774 * for the selected DAC channel.
775 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
776 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
777 * @param DACx DAC instance
778 * @param DAC_Channel This parameter can be one of the following values:
779 * @arg @ref LL_DAC_CHANNEL_1
780 * @arg @ref LL_DAC_CHANNEL_2 (1)
781 *
782 * (1) On this STM32 serie, parameter not available on all devices.
783 * Refer to device datasheet for channels availability.
784 * @param WaveAutoGeneration This parameter can be one of the following values:
785 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
786 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
787 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
788 * @retval None
789 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)790 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
791 {
792 MODIFY_REG(DACx->CR,
793 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
794 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
795 }
796
797 /**
798 * @brief Get the waveform automatic generation mode
799 * for the selected DAC channel.
800 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
801 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
802 * @param DACx DAC instance
803 * @param DAC_Channel This parameter can be one of the following values:
804 * @arg @ref LL_DAC_CHANNEL_1
805 * @arg @ref LL_DAC_CHANNEL_2 (1)
806 *
807 * (1) On this STM32 serie, parameter not available on all devices.
808 * Refer to device datasheet for channels availability.
809 * @retval Returned value can be one of the following values:
810 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
811 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
812 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
813 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)814 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
815 {
816 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
817 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
818 );
819 }
820
821 /**
822 * @brief Set the noise waveform generation for the selected DAC channel:
823 * Noise mode and parameters LFSR (linear feedback shift register).
824 * @note For wave generation to be effective, DAC channel
825 * wave generation mode must be enabled using
826 * function @ref LL_DAC_SetWaveAutoGeneration().
827 * @note This setting can be set when the selected DAC channel is disabled
828 * (otherwise, the setting operation is ignored).
829 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
830 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
831 * @param DACx DAC instance
832 * @param DAC_Channel This parameter can be one of the following values:
833 * @arg @ref LL_DAC_CHANNEL_1
834 * @arg @ref LL_DAC_CHANNEL_2 (1)
835 *
836 * (1) On this STM32 serie, parameter not available on all devices.
837 * Refer to device datasheet for channels availability.
838 * @param NoiseLFSRMask This parameter can be one of the following values:
839 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
840 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
841 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
844 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
845 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
846 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
847 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
850 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
851 * @retval None
852 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)853 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
854 {
855 MODIFY_REG(DACx->CR,
856 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
857 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
858 }
859
860 /**
861 * @brief Get the noise waveform generation for the selected DAC channel:
862 * Noise mode and parameters LFSR (linear feedback shift register).
863 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
864 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
865 * @param DACx DAC instance
866 * @param DAC_Channel This parameter can be one of the following values:
867 * @arg @ref LL_DAC_CHANNEL_1
868 * @arg @ref LL_DAC_CHANNEL_2 (1)
869 *
870 * (1) On this STM32 serie, parameter not available on all devices.
871 * Refer to device datasheet for channels availability.
872 * @retval Returned value can be one of the following values:
873 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
874 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
875 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
876 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
877 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
878 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
879 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
880 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
881 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
882 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
883 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
884 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
885 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)886 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
887 {
888 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
889 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
890 );
891 }
892
893 /**
894 * @brief Set the triangle waveform generation for the selected DAC channel:
895 * triangle mode and amplitude.
896 * @note For wave generation to be effective, DAC channel
897 * wave generation mode must be enabled using
898 * function @ref LL_DAC_SetWaveAutoGeneration().
899 * @note This setting can be set when the selected DAC channel is disabled
900 * (otherwise, the setting operation is ignored).
901 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
902 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
903 * @param DACx DAC instance
904 * @param DAC_Channel This parameter can be one of the following values:
905 * @arg @ref LL_DAC_CHANNEL_1
906 * @arg @ref LL_DAC_CHANNEL_2 (1)
907 *
908 * (1) On this STM32 serie, parameter not available on all devices.
909 * Refer to device datasheet for channels availability.
910 * @param TriangleAmplitude This parameter can be one of the following values:
911 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
912 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
913 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
914 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
919 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
920 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
921 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
922 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
923 * @retval None
924 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)925 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
926 uint32_t TriangleAmplitude)
927 {
928 MODIFY_REG(DACx->CR,
929 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
930 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
931 }
932
933 /**
934 * @brief Get the triangle waveform generation for the selected DAC channel:
935 * triangle mode and amplitude.
936 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
937 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
938 * @param DACx DAC instance
939 * @param DAC_Channel This parameter can be one of the following values:
940 * @arg @ref LL_DAC_CHANNEL_1
941 * @arg @ref LL_DAC_CHANNEL_2 (1)
942 *
943 * (1) On this STM32 serie, parameter not available on all devices.
944 * Refer to device datasheet for channels availability.
945 * @retval Returned value can be one of the following values:
946 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
947 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
948 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
949 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
950 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
951 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
952 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
953 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
954 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
955 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
956 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
957 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
958 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)959 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
960 {
961 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
962 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
963 );
964 }
965
966 /**
967 * @brief Set the output for the selected DAC channel.
968 * @note This function set several features:
969 * - mode normal or sample-and-hold
970 * - buffer
971 * - connection to GPIO or internal path.
972 * These features can also be set individually using
973 * dedicated functions:
974 * - @ref LL_DAC_SetOutputBuffer()
975 * - @ref LL_DAC_SetOutputMode()
976 * - @ref LL_DAC_SetOutputConnection()
977 * @note On this STM32 serie, output connection depends on output mode
978 * (normal or sample and hold) and output buffer state.
979 * - if output connection is set to internal path and output buffer
980 * is enabled (whatever output mode):
981 * output connection is also connected to GPIO pin
982 * (both connections to GPIO pin and internal path).
983 * - if output connection is set to GPIO pin, output buffer
984 * is disabled, output mode set to sample and hold:
985 * output connection is also connected to internal path
986 * (both connections to GPIO pin and internal path).
987 * @note Mode sample-and-hold requires an external capacitor
988 * to be connected between DAC channel output and ground.
989 * Capacitor value depends on load on DAC channel output and
990 * sample-and-hold timings configured.
991 * As indication, capacitor typical value is 100nF
992 * (refer to device datasheet, parameter "CSH").
993 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
994 * CR MODE2 LL_DAC_ConfigOutput
995 * @param DACx DAC instance
996 * @param DAC_Channel This parameter can be one of the following values:
997 * @arg @ref LL_DAC_CHANNEL_1
998 * @arg @ref LL_DAC_CHANNEL_2 (1)
999 *
1000 * (1) On this STM32 serie, parameter not available on all devices.
1001 * Refer to device datasheet for channels availability.
1002 * @param OutputMode This parameter can be one of the following values:
1003 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1004 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1005 * @param OutputBuffer This parameter can be one of the following values:
1006 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1007 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1008 * @param OutputConnection This parameter can be one of the following values:
1009 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1010 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1011 * @retval None
1012 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)1013 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1014 uint32_t OutputBuffer, uint32_t OutputConnection)
1015 {
1016 MODIFY_REG(DACx->MCR,
1017 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1018 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1019 }
1020
1021 /**
1022 * @brief Set the output mode normal or sample-and-hold
1023 * for the selected DAC channel.
1024 * @note Mode sample-and-hold requires an external capacitor
1025 * to be connected between DAC channel output and ground.
1026 * Capacitor value depends on load on DAC channel output and
1027 * sample-and-hold timings configured.
1028 * As indication, capacitor typical value is 100nF
1029 * (refer to device datasheet, parameter "CSH").
1030 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
1031 * CR MODE2 LL_DAC_SetOutputMode
1032 * @param DACx DAC instance
1033 * @param DAC_Channel This parameter can be one of the following values:
1034 * @arg @ref LL_DAC_CHANNEL_1
1035 * @arg @ref LL_DAC_CHANNEL_2 (1)
1036 *
1037 * (1) On this STM32 serie, parameter not available on all devices.
1038 * Refer to device datasheet for channels availability.
1039 * @param OutputMode This parameter can be one of the following values:
1040 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1041 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1042 * @retval None
1043 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1044 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1045 {
1046 MODIFY_REG(DACx->MCR,
1047 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1048 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1049 }
1050
1051 /**
1052 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1053 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1054 * CR MODE2 LL_DAC_GetOutputMode
1055 * @param DACx DAC instance
1056 * @param DAC_Channel This parameter can be one of the following values:
1057 * @arg @ref LL_DAC_CHANNEL_1
1058 * @arg @ref LL_DAC_CHANNEL_2 (1)
1059 *
1060 * (1) On this STM32 serie, parameter not available on all devices.
1061 * Refer to device datasheet for channels availability.
1062 * @retval Returned value can be one of the following values:
1063 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1064 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1065 */
LL_DAC_GetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1066 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1067 {
1068 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1069 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1070 );
1071 }
1072
1073 /**
1074 * @brief Set the output buffer for the selected DAC channel.
1075 * @note On this STM32 serie, when buffer is enabled, its offset can be
1076 * trimmed: factory calibration default values can be
1077 * replaced by user trimming values, using function
1078 * @ref LL_DAC_SetTrimmingValue().
1079 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1080 * CR MODE2 LL_DAC_SetOutputBuffer
1081 * @param DACx DAC instance
1082 * @param DAC_Channel This parameter can be one of the following values:
1083 * @arg @ref LL_DAC_CHANNEL_1
1084 * @arg @ref LL_DAC_CHANNEL_2 (1)
1085 *
1086 * (1) On this STM32 serie, parameter not available on all devices.
1087 * Refer to device datasheet for channels availability.
1088 * @param OutputBuffer This parameter can be one of the following values:
1089 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1090 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1091 * @retval None
1092 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1093 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1094 {
1095 MODIFY_REG(DACx->MCR,
1096 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1097 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1098 }
1099
1100 /**
1101 * @brief Get the output buffer state for the selected DAC channel.
1102 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1103 * CR MODE2 LL_DAC_GetOutputBuffer
1104 * @param DACx DAC instance
1105 * @param DAC_Channel This parameter can be one of the following values:
1106 * @arg @ref LL_DAC_CHANNEL_1
1107 * @arg @ref LL_DAC_CHANNEL_2 (1)
1108 *
1109 * (1) On this STM32 serie, parameter not available on all devices.
1110 * Refer to device datasheet for channels availability.
1111 * @retval Returned value can be one of the following values:
1112 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1113 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1114 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)1115 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1116 {
1117 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1118 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1119 );
1120 }
1121
1122 /**
1123 * @brief Set the output connection for the selected DAC channel.
1124 * @note On this STM32 serie, output connection depends on output mode (normal or
1125 * sample and hold) and output buffer state.
1126 * - if output connection is set to internal path and output buffer
1127 * is enabled (whatever output mode):
1128 * output connection is also connected to GPIO pin
1129 * (both connections to GPIO pin and internal path).
1130 * - if output connection is set to GPIO pin, output buffer
1131 * is disabled, output mode set to sample and hold:
1132 * output connection is also connected to internal path
1133 * (both connections to GPIO pin and internal path).
1134 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1135 * CR MODE2 LL_DAC_SetOutputConnection
1136 * @param DACx DAC instance
1137 * @param DAC_Channel This parameter can be one of the following values:
1138 * @arg @ref LL_DAC_CHANNEL_1
1139 * @arg @ref LL_DAC_CHANNEL_2 (1)
1140 *
1141 * (1) On this STM32 serie, parameter not available on all devices.
1142 * Refer to device datasheet for channels availability.
1143 * @param OutputConnection This parameter can be one of the following values:
1144 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1145 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1146 * @retval None
1147 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1148 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1149 {
1150 MODIFY_REG(DACx->MCR,
1151 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1152 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1153 }
1154
1155 /**
1156 * @brief Get the output connection for the selected DAC channel.
1157 * @note On this STM32 serie, output connection depends on output mode (normal or
1158 * sample and hold) and output buffer state.
1159 * - if output connection is set to internal path and output buffer
1160 * is enabled (whatever output mode):
1161 * output connection is also connected to GPIO pin
1162 * (both connections to GPIO pin and internal path).
1163 * - if output connection is set to GPIO pin, output buffer
1164 * is disabled, output mode set to sample and hold:
1165 * output connection is also connected to internal path
1166 * (both connections to GPIO pin and internal path).
1167 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1168 * CR MODE2 LL_DAC_GetOutputConnection
1169 * @param DACx DAC instance
1170 * @param DAC_Channel This parameter can be one of the following values:
1171 * @arg @ref LL_DAC_CHANNEL_1
1172 * @arg @ref LL_DAC_CHANNEL_2 (1)
1173 *
1174 * (1) On this STM32 serie, parameter not available on all devices.
1175 * Refer to device datasheet for channels availability.
1176 * @retval Returned value can be one of the following values:
1177 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1178 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1179 */
LL_DAC_GetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel)1180 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1181 {
1182 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1183 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1184 );
1185 }
1186
1187 /**
1188 * @brief Set the sample-and-hold timing for the selected DAC channel:
1189 * sample time
1190 * @note Sample time must be set when DAC channel is disabled
1191 * or during DAC operation when DAC channel flag BWSTx is reset,
1192 * otherwise the setting is ignored.
1193 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1194 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1195 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1196 * @param DACx DAC instance
1197 * @param DAC_Channel This parameter can be one of the following values:
1198 * @arg @ref LL_DAC_CHANNEL_1
1199 * @arg @ref LL_DAC_CHANNEL_2 (1)
1200 *
1201 * (1) On this STM32 serie, parameter not available on all devices.
1202 * Refer to device datasheet for channels availability.
1203 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1204 * @retval None
1205 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1206 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1207 {
1208 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1209
1210 MODIFY_REG(*preg,
1211 DAC_SHSR1_TSAMPLE1,
1212 SampleTime);
1213 }
1214
1215 /**
1216 * @brief Get the sample-and-hold timing for the selected DAC channel:
1217 * sample time
1218 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1219 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1220 * @param DACx DAC instance
1221 * @param DAC_Channel This parameter can be one of the following values:
1222 * @arg @ref LL_DAC_CHANNEL_1
1223 * @arg @ref LL_DAC_CHANNEL_2 (1)
1224 *
1225 * (1) On this STM32 serie, parameter not available on all devices.
1226 * Refer to device datasheet for channels availability.
1227 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1228 */
LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1229 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1230 {
1231 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1232
1233 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1234 }
1235
1236 /**
1237 * @brief Set the sample-and-hold timing for the selected DAC channel:
1238 * hold time
1239 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1240 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1241 * @param DACx DAC instance
1242 * @param DAC_Channel This parameter can be one of the following values:
1243 * @arg @ref LL_DAC_CHANNEL_1
1244 * @arg @ref LL_DAC_CHANNEL_2 (1)
1245 *
1246 * (1) On this STM32 serie, parameter not available on all devices.
1247 * Refer to device datasheet for channels availability.
1248 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1249 * @retval None
1250 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1251 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1252 {
1253 MODIFY_REG(DACx->SHHR,
1254 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1255 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1256 }
1257
1258 /**
1259 * @brief Get the sample-and-hold timing for the selected DAC channel:
1260 * hold time
1261 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1262 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1263 * @param DACx DAC instance
1264 * @param DAC_Channel This parameter can be one of the following values:
1265 * @arg @ref LL_DAC_CHANNEL_1
1266 * @arg @ref LL_DAC_CHANNEL_2 (1)
1267 *
1268 * (1) On this STM32 serie, parameter not available on all devices.
1269 * Refer to device datasheet for channels availability.
1270 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1271 */
LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1272 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1273 {
1274 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1275 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1276 );
1277 }
1278
1279 /**
1280 * @brief Set the sample-and-hold timing for the selected DAC channel:
1281 * refresh time
1282 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1283 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1284 * @param DACx DAC instance
1285 * @param DAC_Channel This parameter can be one of the following values:
1286 * @arg @ref LL_DAC_CHANNEL_1
1287 * @arg @ref LL_DAC_CHANNEL_2 (1)
1288 *
1289 * (1) On this STM32 serie, parameter not available on all devices.
1290 * Refer to device datasheet for channels availability.
1291 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1292 * @retval None
1293 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1294 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1295 {
1296 MODIFY_REG(DACx->SHRR,
1297 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1298 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1299 }
1300
1301 /**
1302 * @brief Get the sample-and-hold timing for the selected DAC channel:
1303 * refresh time
1304 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1305 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1306 * @param DACx DAC instance
1307 * @param DAC_Channel This parameter can be one of the following values:
1308 * @arg @ref LL_DAC_CHANNEL_1
1309 * @arg @ref LL_DAC_CHANNEL_2 (1)
1310 *
1311 * (1) On this STM32 serie, parameter not available on all devices.
1312 * Refer to device datasheet for channels availability.
1313 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1314 */
LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1315 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1316 {
1317 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1318 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1319 );
1320 }
1321
1322 /**
1323 * @}
1324 */
1325
1326 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1327 * @{
1328 */
1329
1330 /**
1331 * @brief Enable DAC DMA transfer request of the selected channel.
1332 * @note To configure DMA source address (peripheral address),
1333 * use function @ref LL_DAC_DMA_GetRegAddr().
1334 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1335 * CR DMAEN2 LL_DAC_EnableDMAReq
1336 * @param DACx DAC instance
1337 * @param DAC_Channel This parameter can be one of the following values:
1338 * @arg @ref LL_DAC_CHANNEL_1
1339 * @arg @ref LL_DAC_CHANNEL_2 (1)
1340 *
1341 * (1) On this STM32 serie, parameter not available on all devices.
1342 * Refer to device datasheet for channels availability.
1343 * @retval None
1344 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1345 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1346 {
1347 SET_BIT(DACx->CR,
1348 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1349 }
1350
1351 /**
1352 * @brief Disable DAC DMA transfer request of the selected channel.
1353 * @note To configure DMA source address (peripheral address),
1354 * use function @ref LL_DAC_DMA_GetRegAddr().
1355 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1356 * CR DMAEN2 LL_DAC_DisableDMAReq
1357 * @param DACx DAC instance
1358 * @param DAC_Channel This parameter can be one of the following values:
1359 * @arg @ref LL_DAC_CHANNEL_1
1360 * @arg @ref LL_DAC_CHANNEL_2 (1)
1361 *
1362 * (1) On this STM32 serie, parameter not available on all devices.
1363 * Refer to device datasheet for channels availability.
1364 * @retval None
1365 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1366 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1367 {
1368 CLEAR_BIT(DACx->CR,
1369 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1370 }
1371
1372 /**
1373 * @brief Get DAC DMA transfer request state of the selected channel.
1374 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1375 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1376 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1377 * @param DACx DAC instance
1378 * @param DAC_Channel This parameter can be one of the following values:
1379 * @arg @ref LL_DAC_CHANNEL_1
1380 * @arg @ref LL_DAC_CHANNEL_2 (1)
1381 *
1382 * (1) On this STM32 serie, parameter not available on all devices.
1383 * Refer to device datasheet for channels availability.
1384 * @retval State of bit (1 or 0).
1385 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1386 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1387 {
1388 return ((READ_BIT(DACx->CR,
1389 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1390 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1391 }
1392
1393 /**
1394 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1395 * DAC register address from DAC instance and a list of DAC registers
1396 * intended to be used (most commonly) with DMA transfer.
1397 * @note These DAC registers are data holding registers:
1398 * when DAC conversion is requested, DAC generates a DMA transfer
1399 * request to have data available in DAC data holding registers.
1400 * @note This macro is intended to be used with LL DMA driver, refer to
1401 * function "LL_DMA_ConfigAddresses()".
1402 * Example:
1403 * LL_DMA_ConfigAddresses(DMA1,
1404 * LL_DMA_CHANNEL_1,
1405 * (uint32_t)&< array or variable >,
1406 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1407 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1408 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1409 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1410 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1411 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1412 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1413 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1414 * @param DACx DAC instance
1415 * @param DAC_Channel This parameter can be one of the following values:
1416 * @arg @ref LL_DAC_CHANNEL_1
1417 * @arg @ref LL_DAC_CHANNEL_2 (1)
1418 *
1419 * (1) On this STM32 serie, parameter not available on all devices.
1420 * Refer to device datasheet for channels availability.
1421 * @param Register This parameter can be one of the following values:
1422 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1423 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1424 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1425 * @retval DAC register address
1426 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1427 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1428 {
1429 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1430 /* DAC channel selected. */
1431 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,
1432 ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1433 }
1434 /**
1435 * @}
1436 */
1437
1438 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1439 * @{
1440 */
1441
1442 /**
1443 * @brief Enable DAC selected channel.
1444 * @rmtoll CR EN1 LL_DAC_Enable\n
1445 * CR EN2 LL_DAC_Enable
1446 * @note After enable from off state, DAC channel requires a delay
1447 * for output voltage to reach accuracy +/- 1 LSB.
1448 * Refer to device datasheet, parameter "tWAKEUP".
1449 * @param DACx DAC instance
1450 * @param DAC_Channel This parameter can be one of the following values:
1451 * @arg @ref LL_DAC_CHANNEL_1
1452 * @arg @ref LL_DAC_CHANNEL_2 (1)
1453 *
1454 * (1) On this STM32 serie, parameter not available on all devices.
1455 * Refer to device datasheet for channels availability.
1456 * @retval None
1457 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1458 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1459 {
1460 SET_BIT(DACx->CR,
1461 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1462 }
1463
1464 /**
1465 * @brief Disable DAC selected channel.
1466 * @rmtoll CR EN1 LL_DAC_Disable\n
1467 * CR EN2 LL_DAC_Disable
1468 * @param DACx DAC instance
1469 * @param DAC_Channel This parameter can be one of the following values:
1470 * @arg @ref LL_DAC_CHANNEL_1
1471 * @arg @ref LL_DAC_CHANNEL_2 (1)
1472 *
1473 * (1) On this STM32 serie, parameter not available on all devices.
1474 * Refer to device datasheet for channels availability.
1475 * @retval None
1476 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1477 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1478 {
1479 CLEAR_BIT(DACx->CR,
1480 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1481 }
1482
1483 /**
1484 * @brief Get DAC enable state of the selected channel.
1485 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1486 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1487 * CR EN2 LL_DAC_IsEnabled
1488 * @param DACx DAC instance
1489 * @param DAC_Channel This parameter can be one of the following values:
1490 * @arg @ref LL_DAC_CHANNEL_1
1491 * @arg @ref LL_DAC_CHANNEL_2 (1)
1492 *
1493 * (1) On this STM32 serie, parameter not available on all devices.
1494 * Refer to device datasheet for channels availability.
1495 * @retval State of bit (1 or 0).
1496 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1497 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1498 {
1499 return ((READ_BIT(DACx->CR,
1500 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1501 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1502 }
1503
1504 /**
1505 * @brief Enable DAC trigger of the selected channel.
1506 * @note - If DAC trigger is disabled, DAC conversion is performed
1507 * automatically once the data holding register is updated,
1508 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1509 * @ref LL_DAC_ConvertData12RightAligned(), ...
1510 * - If DAC trigger is enabled, DAC conversion is performed
1511 * only when a hardware of software trigger event is occurring.
1512 * Select trigger source using
1513 * function @ref LL_DAC_SetTriggerSource().
1514 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1515 * CR TEN2 LL_DAC_EnableTrigger
1516 * @param DACx DAC instance
1517 * @param DAC_Channel This parameter can be one of the following values:
1518 * @arg @ref LL_DAC_CHANNEL_1
1519 * @arg @ref LL_DAC_CHANNEL_2 (1)
1520 *
1521 * (1) On this STM32 serie, parameter not available on all devices.
1522 * Refer to device datasheet for channels availability.
1523 * @retval None
1524 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1525 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1526 {
1527 SET_BIT(DACx->CR,
1528 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1529 }
1530
1531 /**
1532 * @brief Disable DAC trigger of the selected channel.
1533 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1534 * CR TEN2 LL_DAC_DisableTrigger
1535 * @param DACx DAC instance
1536 * @param DAC_Channel This parameter can be one of the following values:
1537 * @arg @ref LL_DAC_CHANNEL_1
1538 * @arg @ref LL_DAC_CHANNEL_2 (1)
1539 *
1540 * (1) On this STM32 serie, parameter not available on all devices.
1541 * Refer to device datasheet for channels availability.
1542 * @retval None
1543 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1544 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1545 {
1546 CLEAR_BIT(DACx->CR,
1547 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1548 }
1549
1550 /**
1551 * @brief Get DAC trigger state of the selected channel.
1552 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1553 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1554 * CR TEN2 LL_DAC_IsTriggerEnabled
1555 * @param DACx DAC instance
1556 * @param DAC_Channel This parameter can be one of the following values:
1557 * @arg @ref LL_DAC_CHANNEL_1
1558 * @arg @ref LL_DAC_CHANNEL_2 (1)
1559 *
1560 * (1) On this STM32 serie, parameter not available on all devices.
1561 * Refer to device datasheet for channels availability.
1562 * @retval State of bit (1 or 0).
1563 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1564 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1565 {
1566 return ((READ_BIT(DACx->CR,
1567 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1568 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1569 }
1570
1571 /**
1572 * @brief Trig DAC conversion by software for the selected DAC channel.
1573 * @note Preliminarily, DAC trigger must be set to software trigger
1574 * using function
1575 * @ref LL_DAC_Init()
1576 * @ref LL_DAC_SetTriggerSource()
1577 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1578 * and DAC trigger must be enabled using
1579 * function @ref LL_DAC_EnableTrigger().
1580 * @note For devices featuring DAC with 2 channels: this function
1581 * can perform a SW start of both DAC channels simultaneously.
1582 * Two channels can be selected as parameter.
1583 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1584 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1585 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1586 * @param DACx DAC instance
1587 * @param DAC_Channel This parameter can a combination of the following values:
1588 * @arg @ref LL_DAC_CHANNEL_1
1589 * @arg @ref LL_DAC_CHANNEL_2 (1)
1590 *
1591 * (1) On this STM32 serie, parameter not available on all devices.
1592 * Refer to device datasheet for channels availability.
1593 * @retval None
1594 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1595 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1596 {
1597 SET_BIT(DACx->SWTRIGR,
1598 (DAC_Channel & DAC_SWTR_CHX_MASK));
1599 }
1600
1601 /**
1602 * @brief Set the data to be loaded in the data holding register
1603 * in format 12 bits left alignment (LSB aligned on bit 0),
1604 * for the selected DAC channel.
1605 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1606 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1607 * @param DACx DAC instance
1608 * @param DAC_Channel This parameter can be one of the following values:
1609 * @arg @ref LL_DAC_CHANNEL_1
1610 * @arg @ref LL_DAC_CHANNEL_2 (1)
1611 *
1612 * (1) On this STM32 serie, parameter not available on all devices.
1613 * Refer to device datasheet for channels availability.
1614 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1615 * @retval None
1616 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1617 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1618 {
1619 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1620
1621 MODIFY_REG(*preg,
1622 DAC_DHR12R1_DACC1DHR,
1623 Data);
1624 }
1625
1626 /**
1627 * @brief Set the data to be loaded in the data holding register
1628 * in format 12 bits left alignment (MSB aligned on bit 15),
1629 * for the selected DAC channel.
1630 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1631 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1632 * @param DACx DAC instance
1633 * @param DAC_Channel This parameter can be one of the following values:
1634 * @arg @ref LL_DAC_CHANNEL_1
1635 * @arg @ref LL_DAC_CHANNEL_2 (1)
1636 *
1637 * (1) On this STM32 serie, parameter not available on all devices.
1638 * Refer to device datasheet for channels availability.
1639 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1640 * @retval None
1641 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1642 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1643 {
1644 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1645
1646 MODIFY_REG(*preg,
1647 DAC_DHR12L1_DACC1DHR,
1648 Data);
1649 }
1650
1651 /**
1652 * @brief Set the data to be loaded in the data holding register
1653 * in format 8 bits left alignment (LSB aligned on bit 0),
1654 * for the selected DAC channel.
1655 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1656 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1657 * @param DACx DAC instance
1658 * @param DAC_Channel This parameter can be one of the following values:
1659 * @arg @ref LL_DAC_CHANNEL_1
1660 * @arg @ref LL_DAC_CHANNEL_2 (1)
1661 *
1662 * (1) On this STM32 serie, parameter not available on all devices.
1663 * Refer to device datasheet for channels availability.
1664 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1665 * @retval None
1666 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1667 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1668 {
1669 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1670
1671 MODIFY_REG(*preg,
1672 DAC_DHR8R1_DACC1DHR,
1673 Data);
1674 }
1675
1676 #if defined(DAC_CHANNEL2_SUPPORT)
1677 /**
1678 * @brief Set the data to be loaded in the data holding register
1679 * in format 12 bits left alignment (LSB aligned on bit 0),
1680 * for both DAC channels.
1681 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1682 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1683 * @param DACx DAC instance
1684 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1685 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1686 * @retval None
1687 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1688 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1689 uint32_t DataChannel2)
1690 {
1691 MODIFY_REG(DACx->DHR12RD,
1692 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1693 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1694 }
1695
1696 /**
1697 * @brief Set the data to be loaded in the data holding register
1698 * in format 12 bits left alignment (MSB aligned on bit 15),
1699 * for both DAC channels.
1700 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1701 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1702 * @param DACx DAC instance
1703 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1704 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1705 * @retval None
1706 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1707 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1708 {
1709 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1710 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1711 /* the 4 LSB must be taken into account for the shift value. */
1712 MODIFY_REG(DACx->DHR12LD,
1713 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1714 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1715 }
1716
1717 /**
1718 * @brief Set the data to be loaded in the data holding register
1719 * in format 8 bits left alignment (LSB aligned on bit 0),
1720 * for both DAC channels.
1721 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1722 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1723 * @param DACx DAC instance
1724 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1725 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1726 * @retval None
1727 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1728 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1729 {
1730 MODIFY_REG(DACx->DHR8RD,
1731 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1732 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1733 }
1734
1735 #endif /* DAC_CHANNEL2_SUPPORT */
1736 /**
1737 * @brief Retrieve output data currently generated for the selected DAC channel.
1738 * @note Whatever alignment and resolution settings
1739 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1740 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1741 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1742 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1743 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1744 * @param DACx DAC instance
1745 * @param DAC_Channel This parameter can be one of the following values:
1746 * @arg @ref LL_DAC_CHANNEL_1
1747 * @arg @ref LL_DAC_CHANNEL_2 (1)
1748 *
1749 * (1) On this STM32 serie, parameter not available on all devices.
1750 * Refer to device datasheet for channels availability.
1751 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1752 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1753 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1754 {
1755 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1756
1757 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1758 }
1759
1760 /**
1761 * @}
1762 */
1763
1764 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1765 * @{
1766 */
1767 /**
1768 * @brief Get DAC calibration offset flag for DAC channel 1
1769 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1770 * @param DACx DAC instance
1771 * @retval State of bit (1 or 0).
1772 */
LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef * DACx)1773 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
1774 {
1775 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1776 }
1777
1778 #if defined(DAC_CHANNEL2_SUPPORT)
1779 /**
1780 * @brief Get DAC calibration offset flag for DAC channel 2
1781 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1782 * @param DACx DAC instance
1783 * @retval State of bit (1 or 0).
1784 */
LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef * DACx)1785 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
1786 {
1787 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1788 }
1789
1790 #endif /* DAC_CHANNEL2_SUPPORT */
1791 /**
1792 * @brief Get DAC busy writing sample time flag for DAC channel 1
1793 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1794 * @param DACx DAC instance
1795 * @retval State of bit (1 or 0).
1796 */
LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef * DACx)1797 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
1798 {
1799 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1800 }
1801
1802 #if defined(DAC_CHANNEL2_SUPPORT)
1803 /**
1804 * @brief Get DAC busy writing sample time flag for DAC channel 2
1805 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1806 * @param DACx DAC instance
1807 * @retval State of bit (1 or 0).
1808 */
LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef * DACx)1809 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
1810 {
1811 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1812 }
1813
1814 #endif /* DAC_CHANNEL2_SUPPORT */
1815 /**
1816 * @brief Get DAC underrun flag for DAC channel 1
1817 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1818 * @param DACx DAC instance
1819 * @retval State of bit (1 or 0).
1820 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1821 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1822 {
1823 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1824 }
1825
1826 #if defined(DAC_CHANNEL2_SUPPORT)
1827 /**
1828 * @brief Get DAC underrun flag for DAC channel 2
1829 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1830 * @param DACx DAC instance
1831 * @retval State of bit (1 or 0).
1832 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1833 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1834 {
1835 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1836 }
1837 #endif /* DAC_CHANNEL2_SUPPORT */
1838
1839 /**
1840 * @brief Clear DAC underrun flag for DAC channel 1
1841 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1842 * @param DACx DAC instance
1843 * @retval None
1844 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1845 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1846 {
1847 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1848 }
1849
1850 #if defined(DAC_CHANNEL2_SUPPORT)
1851 /**
1852 * @brief Clear DAC underrun flag for DAC channel 2
1853 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1854 * @param DACx DAC instance
1855 * @retval None
1856 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1857 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1858 {
1859 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1860 }
1861 #endif /* DAC_CHANNEL2_SUPPORT */
1862
1863 /**
1864 * @}
1865 */
1866
1867 /** @defgroup DAC_LL_EF_IT_Management IT management
1868 * @{
1869 */
1870
1871 /**
1872 * @brief Enable DMA underrun interrupt for DAC channel 1
1873 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1874 * @param DACx DAC instance
1875 * @retval None
1876 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1877 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1878 {
1879 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1880 }
1881
1882 #if defined(DAC_CHANNEL2_SUPPORT)
1883 /**
1884 * @brief Enable DMA underrun interrupt for DAC channel 2
1885 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1886 * @param DACx DAC instance
1887 * @retval None
1888 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1889 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1890 {
1891 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1892 }
1893 #endif /* DAC_CHANNEL2_SUPPORT */
1894
1895 /**
1896 * @brief Disable DMA underrun interrupt for DAC channel 1
1897 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1898 * @param DACx DAC instance
1899 * @retval None
1900 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1901 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1902 {
1903 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1904 }
1905
1906 #if defined(DAC_CHANNEL2_SUPPORT)
1907 /**
1908 * @brief Disable DMA underrun interrupt for DAC channel 2
1909 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1910 * @param DACx DAC instance
1911 * @retval None
1912 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1913 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1914 {
1915 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1916 }
1917 #endif /* DAC_CHANNEL2_SUPPORT */
1918
1919 /**
1920 * @brief Get DMA underrun interrupt for DAC channel 1
1921 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1922 * @param DACx DAC instance
1923 * @retval State of bit (1 or 0).
1924 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1925 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1926 {
1927 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1928 }
1929
1930 #if defined(DAC_CHANNEL2_SUPPORT)
1931 /**
1932 * @brief Get DMA underrun interrupt for DAC channel 2
1933 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1934 * @param DACx DAC instance
1935 * @retval State of bit (1 or 0).
1936 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1937 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1938 {
1939 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1940 }
1941 #endif /* DAC_CHANNEL2_SUPPORT */
1942
1943 /**
1944 * @}
1945 */
1946
1947 #if defined(USE_FULL_LL_DRIVER)
1948 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1949 * @{
1950 */
1951
1952 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1953 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1954 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1955
1956 /**
1957 * @}
1958 */
1959 #endif /* USE_FULL_LL_DRIVER */
1960
1961 /**
1962 * @}
1963 */
1964
1965 /**
1966 * @}
1967 */
1968
1969 #endif /* DAC1 */
1970
1971 /**
1972 * @}
1973 */
1974
1975 #ifdef __cplusplus
1976 }
1977 #endif
1978
1979 #endif /* STM32L4xx_LL_DAC_H */
1980
1981 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1982