1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32L4xx_LL_BUS_H
39 #define STM32L4xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32l4xx.h"
47
48 /** @addtogroup STM32L4xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
75 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
76 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
77 #if defined(DMAMUX1)
78 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
79 #endif /* DMAMUX1 */
80 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
81 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
82 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
83 #if defined(DMA2D)
84 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
85 #endif /* DMA2D */
86 #if defined(GFXMMU)
87 #define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
88 #endif /* GFXMMU */
89 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
90 /**
91 * @}
92 */
93
94 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
95 * @{
96 */
97 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
98 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
99 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
100 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
101 #if defined(GPIOD)
102 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
103 #endif /*GPIOD*/
104 #if defined(GPIOE)
105 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
106 #endif /*GPIOE*/
107 #if defined(GPIOF)
108 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
109 #endif /* GPIOF */
110 #if defined(GPIOG)
111 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
112 #endif /* GPIOG */
113 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
114 #if defined(GPIOI)
115 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
116 #endif /* GPIOI */
117 #if defined(USB_OTG_FS)
118 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
119 #endif /* USB_OTG_FS */
120 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
121 #if defined(DCMI)
122 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
123 #endif /* DCMI */
124 #if defined(AES)
125 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
126 #endif /* AES */
127 #if defined(HASH)
128 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
129 #endif /* HASH */
130 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
131 #if defined(OCTOSPIM)
132 #define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN
133 #endif /* OCTOSPIM */
134 #if defined(PKA)
135 #define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN
136 #endif /* PKA */
137 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
138 #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN
139 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
140 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
141 #if defined(SRAM3_BASE)
142 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN
143 #endif /* SRAM3_BASE */
144 /**
145 * @}
146 */
147
148 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
149 * @{
150 */
151 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
152 #if defined(FMC_Bank1_R)
153 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
154 #endif /* FMC_Bank1_R */
155 #if defined(QUADSPI)
156 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
157 #endif /* QUADSPI */
158 #if defined(OCTOSPI1)
159 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
160 #endif /* OCTOSPI1 */
161 #if defined(OCTOSPI2)
162 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
163 #endif /* OCTOSPI2 */
164 /**
165 * @}
166 */
167
168 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
169 * @{
170 */
171 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
172 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
173 #if defined(TIM3)
174 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
175 #endif /* TIM3 */
176 #if defined(TIM4)
177 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
178 #endif /* TIM4 */
179 #if defined(TIM5)
180 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
181 #endif /* TIM5 */
182 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
183 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
184 #if defined(LCD)
185 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
186 #endif /* LCD */
187 #if defined(RCC_APB1ENR1_RTCAPBEN)
188 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
189 #endif /* RCC_APB1ENR1_RTCAPBEN */
190 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
191 #if defined(SPI2)
192 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
193 #endif /* SPI2 */
194 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
195 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
196 #if defined(USART3)
197 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
198 #endif /* USART3 */
199 #if defined(UART4)
200 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
201 #endif /* UART4 */
202 #if defined(UART5)
203 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
204 #endif /* UART5 */
205 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
206 #if defined(I2C2)
207 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
208 #endif /* I2C2 */
209 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
210 #if defined(CRS)
211 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
212 #endif /* CRS */
213 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
214 #if defined(CAN2)
215 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN
216 #endif /* CAN2 */
217 #if defined(USB)
218 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
219 #endif /* USB */
220 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
221 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
222 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
223 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
224 /**
225 * @}
226 */
227
228
229 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
230 * @{
231 */
232 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
233 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
234 #if defined(I2C4)
235 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
236 #endif /* I2C4 */
237 #if defined(SWPMI1)
238 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
239 #endif /* SWPMI1 */
240 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
241 /**
242 * @}
243 */
244
245 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
246 * @{
247 */
248 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
249 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
250 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
251 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
252 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
253 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
254 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
255 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
256 #if defined(TIM8)
257 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
258 #endif /* TIM8 */
259 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
260 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
261 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
262 #if defined(TIM17)
263 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
264 #endif /* TIM17 */
265 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
266 #if defined(SAI2)
267 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
268 #endif /* SAI2 */
269 #if defined(DFSDM1_Channel0)
270 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
271 #endif /* DFSDM1_Channel0 */
272 #if defined(LTDC)
273 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
274 #endif /* LTDC */
275 #if defined(DSI)
276 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
277 #endif /* DSI */
278 /**
279 * @}
280 */
281
282 /** Legacy definitions for compatibility purpose
283 @cond 0
284 */
285 #if defined(DFSDM1_Channel0)
286 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
287 #endif /* DFSDM1_Channel0 */
288 /**
289 @endcond
290 */
291
292 /**
293 * @}
294 */
295
296 /* Exported macro ------------------------------------------------------------*/
297 /* Exported functions --------------------------------------------------------*/
298 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
299 * @{
300 */
301
302 /** @defgroup BUS_LL_EF_AHB1 AHB1
303 * @{
304 */
305
306 /**
307 * @brief Enable AHB1 peripherals clock.
308 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
309 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
310 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
311 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
312 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
313 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
314 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
315 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock
316 * @param Periphs This parameter can be a combination of the following values:
317 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
318 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
319 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
320 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
321 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
322 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
323 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
324 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
325 *
326 * (*) value not defined in all devices.
327 * @retval None
328 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)329 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
330 {
331 __IO uint32_t tmpreg;
332 SET_BIT(RCC->AHB1ENR, Periphs);
333 /* Delay after an RCC peripheral clock enabling */
334 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
335 (void)tmpreg;
336 }
337
338 /**
339 * @brief Check if AHB1 peripheral clock is enabled or not
340 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
341 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
342 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
343 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
344 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
345 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
346 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
347 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock
348 * @param Periphs This parameter can be a combination of the following values:
349 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
350 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
351 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
352 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
353 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
354 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
355 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
356 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
357 *
358 * (*) value not defined in all devices.
359 * @retval State of Periphs (1 or 0).
360 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)361 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
362 {
363 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
364 }
365
366 /**
367 * @brief Disable AHB1 peripherals clock.
368 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
369 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
370 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
371 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
372 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
373 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
374 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
375 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock
376 * @param Periphs This parameter can be a combination of the following values:
377 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
378 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
379 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
380 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
381 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
382 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
383 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
384 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
385 *
386 * (*) value not defined in all devices.
387 * @retval None
388 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)389 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
390 {
391 CLEAR_BIT(RCC->AHB1ENR, Periphs);
392 }
393
394 /**
395 * @brief Force AHB1 peripherals reset.
396 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
397 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
398 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
399 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
400 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
401 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n
402 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
403 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset
404 * @param Periphs This parameter can be a combination of the following values:
405 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
406 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
407 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
408 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
409 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
410 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
411 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
412 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
413 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
414 *
415 * (*) value not defined in all devices.
416 * @retval None
417 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)418 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
419 {
420 SET_BIT(RCC->AHB1RSTR, Periphs);
421 }
422
423 /**
424 * @brief Release AHB1 peripherals reset.
425 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
426 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
427 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
428 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
429 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
430 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
431 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
432 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset
433 * @param Periphs This parameter can be a combination of the following values:
434 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
435 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
436 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
437 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
438 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
439 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
440 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
441 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
442 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
443 *
444 * (*) value not defined in all devices.
445 * @retval None
446 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)447 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
448 {
449 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
450 }
451
452 /**
453 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
454 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
455 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
456 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
457 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
458 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
459 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
460 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
461 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
462 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep
463 * @param Periphs This parameter can be a combination of the following values:
464 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
465 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
466 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
467 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
468 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
469 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
470 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
471 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
472 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
473 *
474 * (*) value not defined in all devices.
475 * @retval None
476 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)477 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
478 {
479 __IO uint32_t tmpreg;
480 SET_BIT(RCC->AHB1SMENR, Periphs);
481 /* Delay after an RCC peripheral clock enabling */
482 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
483 (void)tmpreg;
484 }
485
486 /**
487 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
488 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
489 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
490 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
491 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
492 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
493 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
494 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
495 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
496 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep
497 * @param Periphs This parameter can be a combination of the following values:
498 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
499 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
500 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
501 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
502 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
503 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
504 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
505 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
506 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
507 *
508 * (*) value not defined in all devices.
509 * @retval None
510 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)511 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
512 {
513 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
514 }
515
516 /**
517 * @}
518 */
519
520 /** @defgroup BUS_LL_EF_AHB2 AHB2
521 * @{
522 */
523
524 /**
525 * @brief Enable AHB2 peripherals clock.
526 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
527 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
528 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
529 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
530 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
531 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
532 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
533 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
534 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
535 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
536 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
537 * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
538 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
539 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
540 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
541 * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n
542 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock
543 * @param Periphs This parameter can be a combination of the following values:
544 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
545 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
546 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
547 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
548 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
549 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
550 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
551 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
552 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
553 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
554 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
555 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
556 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
557 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
558 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
559 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
560 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
561 *
562 * (*) value not defined in all devices.
563 * @retval None
564 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)565 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
566 {
567 __IO uint32_t tmpreg;
568 SET_BIT(RCC->AHB2ENR, Periphs);
569 /* Delay after an RCC peripheral clock enabling */
570 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
571 (void)tmpreg;
572 }
573
574 /**
575 * @brief Check if AHB2 peripheral clock is enabled or not
576 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
577 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
578 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
579 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
580 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
581 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
582 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
583 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
584 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
585 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
586 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
587 * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
588 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
589 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
590 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
591 * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
592 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock
593 * @param Periphs This parameter can be a combination of the following values:
594 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
595 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
596 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
597 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
598 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
599 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
600 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
601 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
602 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
603 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
604 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
605 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
606 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
607 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
608 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
609 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
610 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
611 *
612 * (*) value not defined in all devices.
613 * @retval State of Periphs (1 or 0).
614 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)615 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
616 {
617 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
618 }
619
620 /**
621 * @brief Disable AHB2 peripherals clock.
622 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
623 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
624 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
625 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
626 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
627 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
628 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
629 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
630 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
631 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
632 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
633 * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
634 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
635 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
636 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
637 * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n
638 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock
639 * @param Periphs This parameter can be a combination of the following values:
640 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
641 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
642 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
643 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
644 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
645 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
646 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
647 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
648 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
649 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
650 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
651 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
652 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
653 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
654 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
655 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
656 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
657 *
658 * (*) value not defined in all devices.
659 * @retval None
660 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)661 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
662 {
663 CLEAR_BIT(RCC->AHB2ENR, Periphs);
664 }
665
666 /**
667 * @brief Force AHB2 peripherals reset.
668 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
669 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
670 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
671 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
672 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
673 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
674 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
675 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
676 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n
677 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
678 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
679 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
680 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
681 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
682 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
683 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n
684 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset
685 * @param Periphs This parameter can be a combination of the following values:
686 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
687 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
688 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
689 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
690 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
691 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
692 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
693 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
694 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
695 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
696 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
697 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
698 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
699 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
700 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
701 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
702 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
703 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
704 *
705 * (*) value not defined in all devices.
706 * @retval None
707 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)708 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
709 {
710 SET_BIT(RCC->AHB2RSTR, Periphs);
711 }
712
713 /**
714 * @brief Release AHB2 peripherals reset.
715 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
716 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
717 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
718 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
719 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
720 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
721 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
722 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
723 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
724 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
725 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
726 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
727 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
728 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
729 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
730 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n
731 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset
732 * @param Periphs This parameter can be a combination of the following values:
733 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
734 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
735 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
736 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
737 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
738 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
739 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
740 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
741 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
742 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
743 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
744 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
745 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
746 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
747 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
748 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
749 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
750 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
751 *
752 * (*) value not defined in all devices.
753 * @retval None
754 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)755 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
756 {
757 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
758 }
759
760 /**
761 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
762 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
763 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
764 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
765 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
766 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
767 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
768 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
769 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
770 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
771 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
772 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
773 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
774 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
775 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
776 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
777 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
778 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
779 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
780 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
781 * @param Periphs This parameter can be a combination of the following values:
782 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
783 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
784 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
785 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
786 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
787 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
788 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
789 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
790 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
791 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
792 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
793 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
794 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
795 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
796 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
797 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
798 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
799 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
800 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
801 *
802 * (*) value not defined in all devices.
803 * @retval None
804 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)805 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
806 {
807 __IO uint32_t tmpreg;
808 SET_BIT(RCC->AHB2SMENR, Periphs);
809 /* Delay after an RCC peripheral clock enabling */
810 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
811 (void)tmpreg;
812 }
813
814 /**
815 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
816 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
817 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
818 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
819 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
820 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
821 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
822 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
823 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
824 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
825 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
826 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
827 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
828 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
829 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
830 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
831 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
832 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
833 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
834 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
835 * @param Periphs This parameter can be a combination of the following values:
836 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
837 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
838 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
839 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
840 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
841 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
842 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
843 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
844 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
845 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
846 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
847 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
848 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
849 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
850 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
851 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
852 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
853 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
854 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
855 *
856 * (*) value not defined in all devices.
857 * @retval None
858 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)859 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
860 {
861 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
862 }
863
864 /**
865 * @}
866 */
867
868 /** @defgroup BUS_LL_EF_AHB3 AHB3
869 * @{
870 */
871
872 /**
873 * @brief Enable AHB3 peripherals clock.
874 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
875 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n
876 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n
877 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock
878 * @param Periphs This parameter can be a combination of the following values:
879 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
880 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
881 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
882 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
883 *
884 * (*) value not defined in all devices.
885 * @retval None
886 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)887 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
888 {
889 __IO uint32_t tmpreg;
890 SET_BIT(RCC->AHB3ENR, Periphs);
891 /* Delay after an RCC peripheral clock enabling */
892 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
893 (void)tmpreg;
894 }
895
896 /**
897 * @brief Check if AHB3 peripheral clock is enabled or not
898 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
899 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n
900 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n
901 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock
902 * @param Periphs This parameter can be a combination of the following values:
903 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
904 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
905 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
906 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
907 *
908 * (*) value not defined in all devices.
909 * @retval State of Periphs (1 or 0).
910 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)911 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
912 {
913 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
914 }
915
916 /**
917 * @brief Disable AHB3 peripherals clock.
918 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
919 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n
920 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n
921 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock
922 * @param Periphs This parameter can be a combination of the following values:
923 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
924 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
925 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
926 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
927 *
928 * (*) value not defined in all devices.
929 * @retval None
930 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)931 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
932 {
933 CLEAR_BIT(RCC->AHB3ENR, Periphs);
934 }
935
936 /**
937 * @brief Force AHB3 peripherals reset.
938 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
939 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n
940 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n
941 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset
942 * @param Periphs This parameter can be a combination of the following values:
943 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
944 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
945 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
946 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
947 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
948 *
949 * (*) value not defined in all devices.
950 * @retval None
951 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)952 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
953 {
954 SET_BIT(RCC->AHB3RSTR, Periphs);
955 }
956
957 /**
958 * @brief Release AHB3 peripherals reset.
959 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
960 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
961 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n
962 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset
963 * @param Periphs This parameter can be a combination of the following values:
964 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
965 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
966 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
967 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
968 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
969 *
970 * (*) value not defined in all devices.
971 * @retval None
972 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)973 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
974 {
975 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
976 }
977
978 /**
979 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
980 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
981 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n
982 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
983 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep
984 * @param Periphs This parameter can be a combination of the following values:
985 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
986 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
987 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
988 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
989 *
990 * (*) value not defined in all devices.
991 * @retval None
992 */
LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)993 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
994 {
995 __IO uint32_t tmpreg;
996 SET_BIT(RCC->AHB3SMENR, Periphs);
997 /* Delay after an RCC peripheral clock enabling */
998 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
999 (void)tmpreg;
1000 }
1001
1002 /**
1003 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
1004 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1005 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1006 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1007 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1008 * @param Periphs This parameter can be a combination of the following values:
1009 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1010 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1011 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
1012 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
1013 *
1014 * (*) value not defined in all devices.
1015 * @retval None
1016 */
LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)1017 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
1018 {
1019 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
1020 }
1021
1022 /**
1023 * @}
1024 */
1025
1026 /** @defgroup BUS_LL_EF_APB1 APB1
1027 * @{
1028 */
1029
1030 /**
1031 * @brief Enable APB1 peripherals clock.
1032 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
1033 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
1034 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
1035 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
1036 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
1037 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
1038 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
1039 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
1040 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
1041 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
1042 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
1043 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
1044 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
1045 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
1046 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
1047 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
1048 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
1049 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
1050 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
1051 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
1052 * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
1053 * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n
1054 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
1055 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
1056 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
1057 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
1058 * @param Periphs This parameter can be a combination of the following values:
1059 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1060 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1061 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1062 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1063 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1064 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1065 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1066 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1067 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1068 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1069 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1070 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1071 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1072 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1073 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1074 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1075 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1076 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1077 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1078 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1079 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1080 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1081 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1082 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1083 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1084 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1085 *
1086 * (*) value not defined in all devices.
1087 * @retval None
1088 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1089 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1090 {
1091 __IO uint32_t tmpreg;
1092 SET_BIT(RCC->APB1ENR1, Periphs);
1093 /* Delay after an RCC peripheral clock enabling */
1094 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
1095 (void)tmpreg;
1096 }
1097
1098 /**
1099 * @brief Enable APB1 peripherals clock.
1100 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
1101 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
1102 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
1103 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
1104 * @param Periphs This parameter can be a combination of the following values:
1105 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1106 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1107 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1108 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1109 *
1110 * (*) value not defined in all devices.
1111 * @retval None
1112 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1113 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1114 {
1115 __IO uint32_t tmpreg;
1116 SET_BIT(RCC->APB1ENR2, Periphs);
1117 /* Delay after an RCC peripheral clock enabling */
1118 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
1119 (void)tmpreg;
1120 }
1121
1122 /**
1123 * @brief Check if APB1 peripheral clock is enabled or not
1124 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1125 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1126 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1127 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1128 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1129 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1130 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
1131 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
1132 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1133 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1134 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1135 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
1136 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
1137 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
1138 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
1139 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1140 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1141 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1142 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
1143 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1144 * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
1145 * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1146 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
1147 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
1148 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
1149 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
1150 * @param Periphs This parameter can be a combination of the following values:
1151 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1157 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1158 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1159 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1160 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1161 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1162 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1163 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1164 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1165 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1166 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1167 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1168 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1169 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1170 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1171 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1172 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1173 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1174 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1175 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1176 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1177 *
1178 * (*) value not defined in all devices.
1179 * @retval State of Periphs (1 or 0).
1180 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1181 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1182 {
1183 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
1184 }
1185
1186 /**
1187 * @brief Check if APB1 peripheral clock is enabled or not
1188 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
1189 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
1190 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
1191 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
1192 * @param Periphs This parameter can be a combination of the following values:
1193 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1194 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1195 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1196 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1197 *
1198 * (*) value not defined in all devices.
1199 * @retval State of Periphs (1 or 0).
1200 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1201 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1202 {
1203 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1204 }
1205
1206 /**
1207 * @brief Disable APB1 peripherals clock.
1208 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1209 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1210 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1211 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1212 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1213 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1214 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
1215 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
1216 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1217 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1218 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
1219 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1220 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1221 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1222 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1223 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1224 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1225 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1226 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
1227 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
1228 * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
1229 * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n
1230 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
1231 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
1232 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
1233 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1234 * @param Periphs This parameter can be a combination of the following values:
1235 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1236 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1237 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1238 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1239 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1240 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1241 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1242 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1243 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1244 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1245 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1246 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1247 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1248 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1249 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1250 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1251 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1252 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1253 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1254 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1255 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1256 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1257 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1258 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1259 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1260 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1261 *
1262 * (*) value not defined in all devices.
1263 * @retval None
1264 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1265 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1266 {
1267 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1268 }
1269
1270 /**
1271 * @brief Disable APB1 peripherals clock.
1272 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1273 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
1274 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
1275 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
1276 * @param Periphs This parameter can be a combination of the following values:
1277 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1278 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1279 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1280 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1281 *
1282 * (*) value not defined in all devices.
1283 * @retval None
1284 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1285 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1286 {
1287 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1288 }
1289
1290 /**
1291 * @brief Force APB1 peripherals reset.
1292 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1293 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1294 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
1295 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
1296 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
1297 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
1298 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
1299 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1300 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
1301 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1302 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
1303 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
1304 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
1305 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1306 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1307 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1308 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1309 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
1310 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
1311 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n
1312 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
1313 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
1314 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
1315 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1316 * @param Periphs This parameter can be a combination of the following values:
1317 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1318 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1319 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1320 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1321 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1322 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1323 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1324 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1325 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1326 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1327 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1328 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1329 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1330 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1331 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1332 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1333 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1334 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1335 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1336 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1337 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1338 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1339 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1340 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1341 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1342 *
1343 * (*) value not defined in all devices.
1344 * @retval None
1345 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1346 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1347 {
1348 SET_BIT(RCC->APB1RSTR1, Periphs);
1349 }
1350
1351 /**
1352 * @brief Force APB1 peripherals reset.
1353 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1354 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
1355 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
1356 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
1357 * @param Periphs This parameter can be a combination of the following values:
1358 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1359 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1360 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1361 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1362 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1363 *
1364 * (*) value not defined in all devices.
1365 * @retval None
1366 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1367 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1368 {
1369 SET_BIT(RCC->APB1RSTR2, Periphs);
1370 }
1371
1372 /**
1373 * @brief Release APB1 peripherals reset.
1374 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1375 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1376 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
1377 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
1378 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
1379 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
1380 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
1381 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1382 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
1383 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1384 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
1385 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
1386 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
1387 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1388 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1389 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1390 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1391 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
1392 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
1393 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n
1394 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
1395 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
1396 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
1397 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1398 * @param Periphs This parameter can be a combination of the following values:
1399 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1402 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1403 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1404 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1405 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1406 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1407 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1408 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1409 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1410 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1411 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1412 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1413 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1414 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1415 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1416 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1417 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1418 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1419 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1420 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1421 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1422 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1423 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1424 *
1425 * (*) value not defined in all devices.
1426 * @retval None
1427 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1428 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1429 {
1430 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1431 }
1432
1433 /**
1434 * @brief Release APB1 peripherals reset.
1435 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1436 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
1437 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
1438 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1439 * @param Periphs This parameter can be a combination of the following values:
1440 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1441 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1442 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1443 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1444 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1445 *
1446 * (*) value not defined in all devices.
1447 * @retval None
1448 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1449 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1450 {
1451 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1452 }
1453
1454 /**
1455 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1456 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1457 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1458 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1459 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1460 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1461 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1462 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1463 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1464 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1465 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1466 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1467 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1468 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1469 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1470 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1471 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1472 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1473 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1474 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1475 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1476 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1477 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1478 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1479 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1480 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1481 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
1482 * @param Periphs This parameter can be a combination of the following values:
1483 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1484 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1485 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1486 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1487 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1488 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1489 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1490 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1491 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1492 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1493 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1494 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1495 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1496 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1497 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1498 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1499 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1500 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1501 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1502 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1503 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1504 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1505 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1506 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1507 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1508 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1509 *
1510 * (*) value not defined in all devices.
1511 * @retval None
1512 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)1513 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1514 {
1515 __IO uint32_t tmpreg;
1516 SET_BIT(RCC->APB1SMENR1, Periphs);
1517 /* Delay after an RCC peripheral clock enabling */
1518 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1519 (void)tmpreg;
1520 }
1521
1522 /**
1523 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1524 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1525 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1526 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1527 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
1528 * @param Periphs This parameter can be a combination of the following values:
1529 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1530 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1531 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1532 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1533 *
1534 * (*) value not defined in all devices.
1535 * @retval None
1536 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1537 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1538 {
1539 __IO uint32_t tmpreg;
1540 SET_BIT(RCC->APB1SMENR2, Periphs);
1541 /* Delay after an RCC peripheral clock enabling */
1542 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1543 (void)tmpreg;
1544 }
1545
1546 /**
1547 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1548 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1549 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1550 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1551 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1552 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1553 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1554 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1555 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1556 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1557 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1558 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1559 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1560 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1561 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1562 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1563 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1564 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1565 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1566 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1567 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1568 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1569 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1570 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1571 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1572 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1573 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
1574 * @param Periphs This parameter can be a combination of the following values:
1575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1581 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1582 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1583 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1584 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1585 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1586 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1587 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1588 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1589 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1590 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1591 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1592 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1593 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1594 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1595 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1596 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1597 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1598 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1599 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1600 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1601 *
1602 * (*) value not defined in all devices.
1603 * @retval None
1604 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)1605 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1606 {
1607 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1608 }
1609
1610 /**
1611 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1612 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1613 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1614 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1615 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
1616 * @param Periphs This parameter can be a combination of the following values:
1617 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1618 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1619 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1620 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1621 *
1622 * (*) value not defined in all devices.
1623 * @retval None
1624 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1625 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1626 {
1627 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1628 }
1629
1630 /**
1631 * @}
1632 */
1633
1634 /** @defgroup BUS_LL_EF_APB2 APB2
1635 * @{
1636 */
1637
1638 /**
1639 * @brief Enable APB2 peripherals clock.
1640 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1641 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
1642 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
1643 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1644 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1645 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1646 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1647 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
1648 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1649 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1650 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1651 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1652 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1653 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1654 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock
1655 * @param Periphs This parameter can be a combination of the following values:
1656 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1657 * @arg @ref LL_APB2_GRP1_PERIPH_FW
1658 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1659 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1660 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1661 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1662 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1663 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1664 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1665 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1666 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1667 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1668 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1669 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1670 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1671 *
1672 * (*) value not defined in all devices.
1673 * @retval None
1674 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1675 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1676 {
1677 __IO uint32_t tmpreg;
1678 SET_BIT(RCC->APB2ENR, Periphs);
1679 /* Delay after an RCC peripheral clock enabling */
1680 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1681 (void)tmpreg;
1682 }
1683
1684 /**
1685 * @brief Check if APB2 peripheral clock is enabled or not
1686 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1687 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
1688 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
1689 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1690 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1691 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1692 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1693 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
1694 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1695 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1696 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1697 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1698 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1699 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1700 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock
1701 * @param Periphs This parameter can be a combination of the following values:
1702 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1703 * @arg @ref LL_APB2_GRP1_PERIPH_FW
1704 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1705 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1706 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1707 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1708 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1709 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1710 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1711 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1712 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1713 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1714 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1715 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1716 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1717 *
1718 * (*) value not defined in all devices.
1719 * @retval State of Periphs (1 or 0).
1720 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1721 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1722 {
1723 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1724 }
1725
1726 /**
1727 * @brief Disable APB2 peripherals clock.
1728 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1729 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
1730 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1731 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1732 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1733 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1734 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
1735 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1736 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1737 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1738 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1739 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1740 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1741 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock
1742 * @param Periphs This parameter can be a combination of the following values:
1743 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1744 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1745 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1746 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1747 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1748 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1749 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1750 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1751 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1752 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1753 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1754 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1755 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1756 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1757 *
1758 * (*) value not defined in all devices.
1759 * @retval None
1760 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1761 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1762 {
1763 CLEAR_BIT(RCC->APB2ENR, Periphs);
1764 }
1765
1766 /**
1767 * @brief Force APB2 peripherals reset.
1768 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1769 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
1770 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1771 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1772 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1773 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1774 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1775 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1776 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1777 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1778 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1779 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1780 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1781 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset
1782 * @param Periphs This parameter can be a combination of the following values:
1783 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1784 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1785 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1786 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1787 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1788 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1789 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1790 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1791 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1792 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1793 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1794 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1795 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1796 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1797 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1798 *
1799 * (*) value not defined in all devices.
1800 * @retval None
1801 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1802 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1803 {
1804 SET_BIT(RCC->APB2RSTR, Periphs);
1805 }
1806
1807 /**
1808 * @brief Release APB2 peripherals reset.
1809 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1810 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
1811 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1812 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1813 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1814 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1815 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
1816 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1817 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1818 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1819 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1820 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1821 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1822 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset
1823 * @param Periphs This parameter can be a combination of the following values:
1824 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1825 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1826 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1827 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1828 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1829 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1830 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1831 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1832 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1833 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1834 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1835 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1836 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1837 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1838 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1839 *
1840 * (*) value not defined in all devices.
1841 * @retval None
1842 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1843 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1844 {
1845 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1846 }
1847
1848 /**
1849 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1850 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1851 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1852 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1853 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1854 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1855 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1856 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1857 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1858 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1859 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1860 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1861 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1862 * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1863 * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep
1864 * @param Periphs This parameter can be a combination of the following values:
1865 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1866 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1867 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1868 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1869 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1870 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1871 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1872 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1873 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1874 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1875 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1876 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1877 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1878 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1879 *
1880 * (*) value not defined in all devices.
1881 * @retval None
1882 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1883 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1884 {
1885 __IO uint32_t tmpreg;
1886 SET_BIT(RCC->APB2SMENR, Periphs);
1887 /* Delay after an RCC peripheral clock enabling */
1888 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1889 (void)tmpreg;
1890 }
1891
1892 /**
1893 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1894 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1895 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1896 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1897 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1898 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1899 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1900 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1901 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1902 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1903 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1904 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1905 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1906 * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1907 * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep
1908 * @param Periphs This parameter can be a combination of the following values:
1909 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1910 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1911 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1912 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1913 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1914 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1915 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1916 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1917 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1918 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1919 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1920 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1921 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1922 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1923 *
1924 * (*) value not defined in all devices.
1925 * @retval None
1926 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1927 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1928 {
1929 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1930 }
1931
1932 /**
1933 * @}
1934 */
1935
1936
1937 /**
1938 * @}
1939 */
1940
1941 /**
1942 * @}
1943 */
1944
1945 #endif /* defined(RCC) */
1946
1947 /**
1948 * @}
1949 */
1950
1951 #ifdef __cplusplus
1952 }
1953 #endif
1954
1955 #endif /* STM32L4xx_LL_BUS_H */
1956
1957 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1958