xref: /btstack/port/stm32-l451-miromico-sx1280/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h (revision 2fd737d36a1de5d778cacc671d4b4d8c4f3fed82)
1 /**
2   ******************************************************************************
3   * @file    stm32l4xx_hal_nor.h
4   * @author  MCD Application Team
5   * @brief   Header file of NOR HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10   * All rights reserved.</center></h2>
11   *
12   * This software component is licensed by ST under BSD 3-Clause license,
13   * the "License"; You may not use this file except in compliance with the
14   * License. You may obtain a copy of the License at:
15   *                       opensource.org/licenses/BSD-3-Clause
16   *
17   ******************************************************************************
18   */
19 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_HAL_NOR_H
22 #define STM32L4xx_HAL_NOR_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 #if defined FMC_BANK1
29 
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32l4xx_ll_fmc.h"
32 
33 /** @addtogroup STM32L4xx_HAL_Driver
34   * @{
35   */
36 
37 /** @addtogroup NOR
38   * @{
39   */
40 
41 /* Exported typedef ----------------------------------------------------------*/
42 /** @defgroup NOR_Exported_Types NOR Exported Types
43   * @{
44   */
45 
46 /**
47   * @brief  HAL SRAM State structures definition
48   */
49 typedef enum
50 {
51   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
52   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
53   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
54   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
55   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
56 } HAL_NOR_StateTypeDef;
57 
58 /**
59   * @brief  FMC NOR Status typedef
60   */
61 typedef enum
62 {
63   HAL_NOR_STATUS_SUCCESS  = 0U,
64   HAL_NOR_STATUS_ONGOING,
65   HAL_NOR_STATUS_ERROR,
66   HAL_NOR_STATUS_TIMEOUT
67 } HAL_NOR_StatusTypeDef;
68 
69 /**
70   * @brief  FMC NOR ID typedef
71   */
72 typedef struct
73 {
74   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
75 
76   uint16_t Device_Code1;
77 
78   uint16_t Device_Code2;
79 
80   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
81                                     These codes can be accessed by performing read operations with specific
82                                     control signals and addresses set.They can also be accessed by issuing
83                                     an Auto Select command                                                   */
84 } NOR_IDTypeDef;
85 
86 /**
87   * @brief  FMC NOR CFI typedef
88   */
89 typedef struct
90 {
91   /*!< Defines the information stored in the memory's Common flash interface
92        which contains a description of various electrical and timing parameters,
93        density information and functions supported by the memory                   */
94 
95   uint16_t CFI_1;
96 
97   uint16_t CFI_2;
98 
99   uint16_t CFI_3;
100 
101   uint16_t CFI_4;
102 } NOR_CFITypeDef;
103 
104 /**
105   * @brief  NOR handle Structure definition
106   */
107 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
108 typedef struct __NOR_HandleTypeDef
109 #else
110 typedef struct
111 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
112 
113 {
114   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
115 
116   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
117 
118   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
119 
120   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
121 
122   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
123 
124 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
125   void  (* MspInitCallback)        ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp Init callback              */
126   void  (* MspDeInitCallback)      ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp DeInit callback            */
127 #endif
128 } NOR_HandleTypeDef;
129 
130 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
131 /**
132   * @brief  HAL NOR Callback ID enumeration definition
133   */
134 typedef enum
135 {
136   HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
137   HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
138 }HAL_NOR_CallbackIDTypeDef;
139 
140 /**
141   * @brief  HAL NOR Callback pointer definition
142   */
143 typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
144 #endif
145 /**
146   * @}
147   */
148 
149 /* Exported constants --------------------------------------------------------*/
150 /* Exported macro ------------------------------------------------------------*/
151 /** @defgroup NOR_Exported_Macros NOR Exported Macros
152   * @{
153   */
154 /** @brief Reset NOR handle state
155   * @param  __HANDLE__ specifies the NOR handle.
156   * @retval None
157   */
158 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
159 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
160                                                                (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
161                                                                (__HANDLE__)->MspInitCallback = NULL;       \
162                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
163                                                              } while(0)
164 #else
165 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
166 #endif
167 /**
168   * @}
169   */
170 
171 /* Exported functions --------------------------------------------------------*/
172 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
173   * @{
174   */
175 
176 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
177   * @{
178   */
179 
180 /* Initialization/de-initialization functions  ********************************/
181 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
182 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
183 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
184 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
185 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
186 /**
187   * @}
188   */
189 
190 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
191   * @{
192   */
193 
194 /* I/O operation functions  ***************************************************/
195 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
196 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
197 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
198 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
199 
200 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
201 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
202 
203 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
204 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
205 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
206 
207 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
208 /* NOR callback registering/unregistering */
209 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
210 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
211 #endif
212 /**
213   * @}
214   */
215 
216 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
217   * @{
218   */
219 
220 /* NOR Control functions  *****************************************************/
221 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
222 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
223 /**
224   * @}
225   */
226 
227 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
228   * @{
229   */
230 
231 /* NOR State functions ********************************************************/
232 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
233 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
234 /**
235   * @}
236   */
237 
238 /**
239   * @}
240   */
241 
242 /* Private types -------------------------------------------------------------*/
243 /* Private variables ---------------------------------------------------------*/
244 /* Private constants ---------------------------------------------------------*/
245 /** @defgroup NOR_Private_Constants NOR Private Constants
246   * @{
247   */
248 /* NOR device IDs addresses */
249 #define MC_ADDRESS               ((uint16_t)0x0000U)
250 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
251 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
252 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
253 
254 /* NOR CFI IDs addresses */
255 #define CFI1_ADDRESS             ((uint16_t)0x61U)
256 #define CFI2_ADDRESS             ((uint16_t)0x62U)
257 #define CFI3_ADDRESS             ((uint16_t)0x63U)
258 #define CFI4_ADDRESS             ((uint16_t)0x64U)
259 
260 /* NOR operation wait timeout */
261 #define NOR_TMEOUT               ((uint16_t)0xFFFFU)
262 
263 /* NOR memory data width */
264 #define NOR_MEMORY_8B            ((uint8_t)0x0U)
265 #define NOR_MEMORY_16B           ((uint8_t)0x1U)
266 
267 /* NOR memory device read/write start address */
268 #define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)
269 #define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)
270 #define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)
271 #define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)
272 /**
273   * @}
274   */
275 
276 /* Private macros ------------------------------------------------------------*/
277 /** @defgroup NOR_Private_Macros NOR Private Macros
278   * @{
279   */
280 /**
281   * @brief  NOR memory address shifting.
282   * @param  __NOR_ADDRESS NOR base address
283   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
284   * @param  __ADDRESS__ NOR memory address
285   * @retval NOR shifted address value
286   */
287 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
288               ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
289               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
290               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
291 
292 /**
293   * @brief  NOR memory write data to specified address.
294   * @param  __ADDRESS__ NOR memory address
295   * @param  __DATA__ Data to write
296   * @retval None
297   */
298 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
299                                                (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
300                                                __DSB();                                                    \
301                                              } while(0)
302 
303 /**
304   * @}
305   */
306 
307 /**
308   * @}
309   */
310 
311 /**
312   * @}
313   */
314 
315 #endif /* FMC_BANK1 */
316 
317 #ifdef __cplusplus
318 }
319 #endif
320 
321 #endif /* STM32L4xx_HAL_NOR_H */
322 
323 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
324