1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_DMA2D_H 22 #define STM32L4xx_HAL_DMA2D_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 #if defined (DMA2D) 36 37 /** @addtogroup DMA2D DMA2D 38 * @brief DMA2D HAL module driver 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 44 * @{ 45 */ 46 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 47 48 /** 49 * @brief DMA2D CLUT Structure definition 50 */ 51 typedef struct 52 { 53 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 54 55 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 56 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 57 58 uint32_t Size; /*!< Configures the DMA2D CLUT size. 59 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 60 } DMA2D_CLUTCfgTypeDef; 61 62 /** 63 * @brief DMA2D Init structure definition 64 */ 65 typedef struct 66 { 67 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 68 This parameter can be one value of @ref DMA2D_Mode. */ 69 70 uint32_t ColorMode; /*!< Configures the color format of the output image. 71 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 72 73 uint32_t OutputOffset; /*!< Specifies the Offset value. 74 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 76 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 77 78 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 79 for the output pixel format converter. 80 This parameter can be one value of @ref DMA2D_RB_Swap. */ 81 82 83 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 84 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 85 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 86 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 87 88 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 89 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. 90 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 91 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 92 93 } DMA2D_InitTypeDef; 94 95 96 /** 97 * @brief DMA2D Layer structure definition 98 */ 99 typedef struct 100 { 101 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 102 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 103 104 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 105 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 106 107 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 108 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 109 110 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. 111 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. 112 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between 113 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 114 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 115 - InputAlpha[16:23] is the red value RED[0:7] 116 - InputAlpha[8:15] is the green value GREEN[0:7] 117 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 118 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 119 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 120 121 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 122 This parameter can be one value of @ref DMA2D_RB_Swap. */ 123 124 125 } DMA2D_LayerCfgTypeDef; 126 127 /** 128 * @brief HAL DMA2D State structures definition 129 */ 130 typedef enum 131 { 132 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 133 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 134 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 135 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 136 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 137 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 138 }HAL_DMA2D_StateTypeDef; 139 140 /** 141 * @brief DMA2D handle Structure definition 142 */ 143 typedef struct __DMA2D_HandleTypeDef 144 { 145 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 146 147 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 148 149 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ 150 151 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ 152 153 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 154 void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ 155 156 void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ 157 158 void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ 159 160 void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ 161 162 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 163 164 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 165 166 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 167 168 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 169 170 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 171 } DMA2D_HandleTypeDef; 172 173 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 174 /** 175 * @brief HAL DMA2D Callback pointer definition 176 */ 177 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ 178 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 179 /** 180 * @} 181 */ 182 183 /* Exported constants --------------------------------------------------------*/ 184 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 185 * @{ 186 */ 187 188 /** @defgroup DMA2D_Error_Code DMA2D Error Code 189 * @{ 190 */ 191 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 192 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 193 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 194 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 195 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 196 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 197 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 198 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 199 200 /** 201 * @} 202 */ 203 204 /** @defgroup DMA2D_Mode DMA2D Mode 205 * @{ 206 */ 207 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 208 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 209 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 210 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 211 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 212 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 213 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 214 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 220 * @{ 221 */ 222 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 223 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 224 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 225 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 226 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 232 * @{ 233 */ 234 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 235 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 236 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 237 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 238 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 239 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 240 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 241 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 242 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 243 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 244 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 250 * @{ 251 */ 252 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 253 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 254 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 255 with original alpha channel value */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 261 * @{ 262 */ 263 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 264 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 270 * @{ 271 */ 272 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 273 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 274 /** 275 * @} 276 */ 277 278 279 280 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 281 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 282 * @{ 283 */ 284 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 285 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 286 /** 287 * @} 288 */ 289 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 290 291 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 292 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 293 * @{ 294 */ 295 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 296 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 297 /** 298 * @} 299 */ 300 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 301 302 303 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 304 * @{ 305 */ 306 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 307 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 313 * @{ 314 */ 315 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 316 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 317 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 318 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 319 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 320 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 321 /** 322 * @} 323 */ 324 325 /** @defgroup DMA2D_Flags DMA2D Flags 326 * @{ 327 */ 328 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 329 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 330 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 331 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 332 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 333 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup DMA2D_Aliases DMA2D API Aliases 339 * @{ 340 */ 341 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ 342 /** 343 * @} 344 */ 345 346 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 347 /** 348 * @brief HAL DMA2D common Callback ID enumeration definition 349 */ 350 typedef enum 351 { 352 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 353 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 354 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 355 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 356 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 357 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 358 }HAL_DMA2D_CallbackIDTypeDef; 359 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 360 361 362 /** 363 * @} 364 */ 365 /* Exported macros ------------------------------------------------------------*/ 366 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 367 * @{ 368 */ 369 370 /** @brief Reset DMA2D handle state 371 * @param __HANDLE__ specifies the DMA2D handle. 372 * @retval None 373 */ 374 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 375 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 376 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 377 (__HANDLE__)->MspInitCallback = NULL; \ 378 (__HANDLE__)->MspDeInitCallback = NULL; \ 379 }while(0) 380 #else 381 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 382 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 383 384 385 /** 386 * @brief Enable the DMA2D. 387 * @param __HANDLE__ DMA2D handle 388 * @retval None. 389 */ 390 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 391 392 393 /* Interrupt & Flag management */ 394 /** 395 * @brief Get the DMA2D pending flags. 396 * @param __HANDLE__ DMA2D handle 397 * @param __FLAG__ flag to check. 398 * This parameter can be any combination of the following values: 399 * @arg DMA2D_FLAG_CE: Configuration error flag 400 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 401 * @arg DMA2D_FLAG_CAE: CLUT access error flag 402 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 403 * @arg DMA2D_FLAG_TC: Transfer complete flag 404 * @arg DMA2D_FLAG_TE: Transfer error flag 405 * @retval The state of FLAG. 406 */ 407 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 408 409 /** 410 * @brief Clear the DMA2D pending flags. 411 * @param __HANDLE__ DMA2D handle 412 * @param __FLAG__ specifies the flag to clear. 413 * This parameter can be any combination of the following values: 414 * @arg DMA2D_FLAG_CE: Configuration error flag 415 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 416 * @arg DMA2D_FLAG_CAE: CLUT access error flag 417 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 418 * @arg DMA2D_FLAG_TC: Transfer complete flag 419 * @arg DMA2D_FLAG_TE: Transfer error flag 420 * @retval None 421 */ 422 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 423 424 /** 425 * @brief Enable the specified DMA2D interrupts. 426 * @param __HANDLE__ DMA2D handle 427 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 428 * This parameter can be any combination of the following values: 429 * @arg DMA2D_IT_CE: Configuration error interrupt mask 430 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 431 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 432 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 433 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 434 * @arg DMA2D_IT_TE: Transfer error interrupt mask 435 * @retval None 436 */ 437 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 438 439 /** 440 * @brief Disable the specified DMA2D interrupts. 441 * @param __HANDLE__ DMA2D handle 442 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 443 * This parameter can be any combination of the following values: 444 * @arg DMA2D_IT_CE: Configuration error interrupt mask 445 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 446 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 447 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 448 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 449 * @arg DMA2D_IT_TE: Transfer error interrupt mask 450 * @retval None 451 */ 452 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 453 454 /** 455 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 456 * @param __HANDLE__ DMA2D handle 457 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 458 * This parameter can be one of the following values: 459 * @arg DMA2D_IT_CE: Configuration error interrupt mask 460 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 461 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 462 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 463 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 464 * @arg DMA2D_IT_TE: Transfer error interrupt mask 465 * @retval The state of INTERRUPT source. 466 */ 467 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 468 469 /** 470 * @} 471 */ 472 473 /* Exported functions --------------------------------------------------------*/ 474 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 475 * @{ 476 */ 477 478 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 479 * @{ 480 */ 481 482 /* Initialization and de-initialization functions *******************************/ 483 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 484 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); 485 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); 486 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); 487 /* Callbacks Register/UnRegister functions ***********************************/ 488 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 489 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); 490 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 491 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 492 493 /** 494 * @} 495 */ 496 497 498 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 499 * @{ 500 */ 501 502 /* IO operation functions *******************************************************/ 503 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 504 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 505 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 506 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 507 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 508 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 509 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 510 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 511 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); 512 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); 513 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 514 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 515 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 516 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 517 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 518 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 519 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 520 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 521 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 522 523 /** 524 * @} 525 */ 526 527 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 528 * @{ 529 */ 530 531 /* Peripheral Control functions *************************************************/ 532 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 533 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 534 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 535 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 536 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 537 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 538 539 /** 540 * @} 541 */ 542 543 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 544 * @{ 545 */ 546 547 /* Peripheral State functions ***************************************************/ 548 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 549 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 550 551 /** 552 * @} 553 */ 554 555 /** 556 * @} 557 */ 558 559 /* Private constants ---------------------------------------------------------*/ 560 561 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 562 * @{ 563 */ 564 565 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 566 * @{ 567 */ 568 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 569 /** 570 * @} 571 */ 572 573 /** @defgroup DMA2D_Color_Value DMA2D Color Value 574 * @{ 575 */ 576 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 582 * @{ 583 */ 584 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup DMA2D_Layers DMA2D Layers 590 * @{ 591 */ 592 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 593 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 594 /** 595 * @} 596 */ 597 598 /** @defgroup DMA2D_Offset DMA2D Offset 599 * @{ 600 */ 601 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 602 /** 603 * @} 604 */ 605 606 /** @defgroup DMA2D_Size DMA2D Size 607 * @{ 608 */ 609 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 610 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 611 /** 612 * @} 613 */ 614 615 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 616 * @{ 617 */ 618 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 619 /** 620 * @} 621 */ 622 623 /** 624 * @} 625 */ 626 627 628 /* Private macros ------------------------------------------------------------*/ 629 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 630 * @{ 631 */ 632 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 633 634 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 635 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 636 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 637 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 638 #else 639 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 640 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 641 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 642 643 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 644 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 645 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 646 647 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 648 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 649 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 650 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 651 652 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 653 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 654 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ 655 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 656 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ 657 ((INPUT_CM) == DMA2D_INPUT_A4)) 658 659 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 660 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 661 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 662 663 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 664 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 665 666 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 667 ((RB_Swap) == DMA2D_RB_SWAP)) 668 669 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 670 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 671 ((LOM) == DMA2D_LOM_BYTES)) 672 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 673 674 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 675 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 676 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 677 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 678 679 680 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 681 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 682 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 683 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 684 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 685 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 686 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 687 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 688 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 689 /** 690 * @} 691 */ 692 693 /** 694 * @} 695 */ 696 697 #endif /* defined (DMA2D) */ 698 699 /** 700 * @} 701 */ 702 703 #ifdef __cplusplus 704 } 705 #endif 706 707 #endif /* STM32L4xx_HAL_DMA2D_H */ 708 709 710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 711