1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dac.h 4 * @author MCD Application Team 5 * @brief Header file of DAC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_DAC_H 22 #define STM32L4xx_HAL_DAC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /** @addtogroup STM32L4xx_HAL_Driver 29 * @{ 30 */ 31 32 /* Includes ------------------------------------------------------------------*/ 33 #include "stm32l4xx_hal_def.h" 34 35 #if defined(DAC1) 36 37 /** @addtogroup DAC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 43 /** @defgroup DAC_Exported_Types DAC Exported Types 44 * @{ 45 */ 46 47 /** 48 * @brief HAL State structures definition 49 */ 50 typedef enum 51 { 52 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ 53 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ 54 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ 55 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ 56 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ 57 58 } HAL_DAC_StateTypeDef; 59 60 /** 61 * @brief DAC handle Structure definition 62 */ 63 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 64 typedef struct __DAC_HandleTypeDef 65 #else 66 typedef struct 67 #endif 68 { 69 DAC_TypeDef *Instance; /*!< Register base address */ 70 71 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ 72 73 HAL_LockTypeDef Lock; /*!< DAC locking object */ 74 75 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ 76 77 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ 78 79 __IO uint32_t ErrorCode; /*!< DAC Error code */ 80 81 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 82 void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 83 void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 84 void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 85 void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 86 void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 87 void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 88 void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 89 void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 90 91 void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); 92 void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); 93 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 94 95 } DAC_HandleTypeDef; 96 97 /** 98 * @brief DAC Configuration sample and hold Channel structure definition 99 */ 100 typedef struct 101 { 102 uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. 103 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 104 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 105 106 uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel 107 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 108 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 109 110 uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel 111 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 112 This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ 113 } DAC_SampleAndHoldConfTypeDef; 114 115 /** 116 * @brief DAC Configuration regular Channel structure definition 117 */ 118 typedef struct 119 { 120 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 121 uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode 122 This parameter can be a value of @ref DAC_HighFrequency */ 123 #endif /* STM32L4P5xx STM32L4Q5xx STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 124 125 uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. 126 This parameter can be a value of @ref DAC_SampleAndHold */ 127 128 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. 129 This parameter can be a value of @ref DAC_trigger_selection */ 130 131 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. 132 This parameter can be a value of @ref DAC_output_buffer */ 133 134 uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . 135 This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ 136 137 uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode 138 This parameter must be a value of @ref DAC_UserTrimming 139 DAC_UserTrimming is either factory or user trimming */ 140 141 uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value 142 i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 143 This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ 144 145 DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ 146 147 } DAC_ChannelConfTypeDef; 148 149 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 150 /** 151 * @brief HAL DAC Callback ID enumeration definition 152 */ 153 typedef enum 154 { 155 HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ 156 HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ 157 HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ 158 HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ 159 HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ 160 HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ 161 HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ 162 HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ 163 HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ 164 HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ 165 HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ 166 } HAL_DAC_CallbackIDTypeDef; 167 168 /** 169 * @brief HAL DAC Callback pointer definition 170 */ 171 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); 172 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 173 174 /** 175 * @} 176 */ 177 178 /* Exported constants --------------------------------------------------------*/ 179 180 /** @defgroup DAC_Exported_Constants DAC Exported Constants 181 * @{ 182 */ 183 184 /** @defgroup DAC_Error_Code DAC Error Code 185 * @{ 186 */ 187 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ 188 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ 189 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ 190 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ 191 #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ 192 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 193 #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ 194 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 195 196 /** 197 * @} 198 */ 199 200 /** @defgroup DAC_trigger_selection DAC trigger selection 201 * @{ 202 */ 203 204 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 205 #define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register 206 has been loaded, and not by external trigger */ 207 #define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 208 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 209 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ 210 #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 211 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ 212 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 213 214 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 215 #define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register 216 has been loaded, and not by external trigger */ 217 #define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 218 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 219 #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 220 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ 221 #endif /* STM32L451xx STM32L452xx STM32L462xx */ 222 223 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 224 #define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register 225 has been loaded, and not by external trigger */ 226 #define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 227 #define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ 228 #define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ 229 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 230 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ 231 #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ 232 #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 233 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ 234 #endif /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx*/ 235 236 237 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 238 #define DAC_TRIGGER_NONE 0x00000000U /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ 239 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */ 240 #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */ 241 #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 242 #define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ 243 #define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ 244 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 245 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ 246 #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ 247 #define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ 248 #define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ 249 #define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ 250 #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 251 252 #endif /* STM32L4P5xx STM32L4Q5xx STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 253 254 255 /** 256 * @} 257 */ 258 259 /** @defgroup DAC_output_buffer DAC output buffer 260 * @{ 261 */ 262 #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U 263 #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) 264 265 /** 266 * @} 267 */ 268 269 /** @defgroup DAC_Channel_selection DAC Channel selection 270 * @{ 271 */ 272 #define DAC_CHANNEL_1 0x00000000U 273 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 274 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 275 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 276 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 277 #define DAC_CHANNEL_2 0x00000010U 278 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 279 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 280 /* STM32L4P5xx STM32L4Q5xx */ 281 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 282 283 /** 284 * @} 285 */ 286 287 /** @defgroup DAC_data_alignment DAC data alignment 288 * @{ 289 */ 290 #define DAC_ALIGN_12B_R 0x00000000U 291 #define DAC_ALIGN_12B_L 0x00000004U 292 #define DAC_ALIGN_8B_R 0x00000008U 293 294 /** 295 * @} 296 */ 297 298 /** @defgroup DAC_flags_definition DAC flags definition 299 * @{ 300 */ 301 #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) 302 #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) 303 304 /** 305 * @} 306 */ 307 308 /** @defgroup DAC_IT_definition DAC IT definition 309 * @{ 310 */ 311 #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) 312 #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) 313 314 /** 315 * @} 316 */ 317 318 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral 319 * @{ 320 */ 321 #define DAC_CHIPCONNECT_DISABLE 0x00000000U 322 #define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) 323 324 /** 325 * @} 326 */ 327 328 /** @defgroup DAC_UserTrimming DAC User Trimming 329 * @{ 330 */ 331 #define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ 332 #define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ 333 334 /** 335 * @} 336 */ 337 338 /** @defgroup DAC_SampleAndHold DAC power mode 339 * @{ 340 */ 341 #define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U 342 #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) 343 344 /** 345 * @} 346 */ 347 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 348 /** @defgroup DAC_HighFrequency DAC high frequency interface mode 349 * @{ 350 */ 351 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ 352 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ 353 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002U /*!< High frequency interface mode automatic */ 354 355 /** 356 * @} 357 */ 358 #endif /* STM32L4P5xx STM32L4Q5xx STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 359 360 /** 361 * @} 362 */ 363 364 /* Exported macro ------------------------------------------------------------*/ 365 366 /** @defgroup DAC_Exported_Macros DAC Exported Macros 367 * @{ 368 */ 369 370 /** @brief Reset DAC handle state. 371 * @param __HANDLE__ specifies the DAC handle. 372 * @retval None 373 */ 374 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 375 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ 376 (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ 377 (__HANDLE__)->MspInitCallback = NULL; \ 378 (__HANDLE__)->MspDeInitCallback = NULL; \ 379 } while(0) 380 #else 381 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) 382 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 383 384 /** @brief Enable the DAC channel. 385 * @param __HANDLE__ specifies the DAC handle. 386 * @param __DAC_Channel__ specifies the DAC channel 387 * @retval None 388 */ 389 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ 390 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 391 392 /** @brief Disable the DAC channel. 393 * @param __HANDLE__ specifies the DAC handle 394 * @param __DAC_Channel__ specifies the DAC channel. 395 * @retval None 396 */ 397 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ 398 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 399 400 /** @brief Set DHR12R1 alignment. 401 * @param __ALIGNMENT__ specifies the DAC alignment 402 * @retval None 403 */ 404 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) 405 406 /** @brief Set DHR12R2 alignment. 407 * @param __ALIGNMENT__ specifies the DAC alignment 408 * @retval None 409 */ 410 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) 411 412 /** @brief Set DHR12RD alignment. 413 * @param __ALIGNMENT__ specifies the DAC alignment 414 * @retval None 415 */ 416 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) 417 418 /** @brief Enable the DAC interrupt. 419 * @param __HANDLE__ specifies the DAC handle 420 * @param __INTERRUPT__ specifies the DAC interrupt. 421 * This parameter can be any combination of the following values: 422 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt 423 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt 424 * @retval None 425 */ 426 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) 427 428 /** @brief Disable the DAC interrupt. 429 * @param __HANDLE__ specifies the DAC handle 430 * @param __INTERRUPT__ specifies the DAC interrupt. 431 * This parameter can be any combination of the following values: 432 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt 433 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt 434 * @retval None 435 */ 436 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) 437 438 /** @brief Check whether the specified DAC interrupt source is enabled or not. 439 * @param __HANDLE__ DAC handle 440 * @param __INTERRUPT__ DAC interrupt source to check 441 * This parameter can be any combination of the following values: 442 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt 443 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt 444 * @retval State of interruption (SET or RESET) 445 */ 446 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) 447 448 /** @brief Get the selected DAC's flag status. 449 * @param __HANDLE__ specifies the DAC handle. 450 * @param __FLAG__ specifies the DAC flag to get. 451 * This parameter can be any combination of the following values: 452 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag 453 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag 454 * @retval None 455 */ 456 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 457 458 /** @brief Clear the DAC's flag. 459 * @param __HANDLE__ specifies the DAC handle. 460 * @param __FLAG__ specifies the DAC flag to clear. 461 * This parameter can be any combination of the following values: 462 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag 463 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag 464 * @retval None 465 */ 466 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) 467 468 /** 469 * @} 470 */ 471 472 /* Private macro -------------------------------------------------------------*/ 473 474 /** @defgroup DAC_Private_Macros DAC Private Macros 475 * @{ 476 */ 477 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ 478 ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) 479 480 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 481 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 482 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 483 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 484 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ 485 ((CHANNEL) == DAC_CHANNEL_2)) 486 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 487 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 488 /* STM32L4P5xx STM32L4Q5xx */ 489 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 490 491 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 492 #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) 493 #endif /* STM32L451xx STM32L452xx STM32L462xx */ 494 495 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ 496 ((ALIGN) == DAC_ALIGN_12B_L) || \ 497 ((ALIGN) == DAC_ALIGN_8B_R)) 498 499 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) 500 501 #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU) 502 503 /** 504 * @} 505 */ 506 507 /* Include DAC HAL Extended module */ 508 #include "stm32l4xx_hal_dac_ex.h" 509 510 /* Exported functions --------------------------------------------------------*/ 511 512 /** @addtogroup DAC_Exported_Functions 513 * @{ 514 */ 515 516 /** @addtogroup DAC_Exported_Functions_Group1 517 * @{ 518 */ 519 /* Initialization and de-initialization functions *****************************/ 520 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); 521 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); 522 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); 523 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); 524 525 /** 526 * @} 527 */ 528 529 /** @addtogroup DAC_Exported_Functions_Group2 530 * @{ 531 */ 532 /* IO operation functions *****************************************************/ 533 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); 534 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); 535 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, 536 uint32_t Alignment); 537 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); 538 539 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); 540 541 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); 542 543 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); 544 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); 545 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); 546 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); 547 548 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 549 /* DAC callback registering/unregistering */ 550 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, 551 pDAC_CallbackTypeDef pCallback); 552 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); 553 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 554 555 /** 556 * @} 557 */ 558 559 /** @addtogroup DAC_Exported_Functions_Group3 560 * @{ 561 */ 562 /* Peripheral Control functions ***********************************************/ 563 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); 564 565 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); 566 /** 567 * @} 568 */ 569 570 /** @addtogroup DAC_Exported_Functions_Group4 571 * @{ 572 */ 573 /* Peripheral State and Error functions ***************************************/ 574 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); 575 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); 576 577 /** 578 * @} 579 */ 580 581 /** 582 * @} 583 */ 584 585 /** @defgroup DAC_Private_Functions DAC Private Functions 586 * @{ 587 */ 588 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); 589 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); 590 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 591 /** 592 * @} 593 */ 594 595 /** 596 * @} 597 */ 598 599 #endif /* DAC1 */ 600 601 /** 602 * @} 603 */ 604 605 #ifdef __cplusplus 606 } 607 #endif 608 609 610 #endif /*STM32L4xx_HAL_DAC_H */ 611 612 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 613 614