1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef __STM32L0xx_HAL_H 23 #define __STM32L0xx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32l0xx_hal_conf.h" 31 32 /** @addtogroup STM32L0xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @defgroup HAL HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /* Exported constants --------------------------------------------------------*/ 42 /** @defgroup HAL_Exported_Constants HAL Exported Constants 43 * @{ 44 */ 45 46 /** @defgroup SYSCFG_BootMode Boot Mode 47 * @{ 48 */ 49 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U) 50 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0) 51 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) 52 53 /** 54 * @} 55 */ 56 57 /** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration 58 * @{ 59 */ 60 #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP 61 #define DBGMCU_STOP DBGMCU_CR_DBG_STOP 62 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY 63 #define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U)) 64 65 66 /** 67 * @} 68 */ 69 70 #if defined (LCD_BASE) /* STM32L0x3xx only */ 71 /** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors 72 * @{ 73 */ 74 #define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ 75 #define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ 76 #define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ 77 #define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ 78 #if defined (SYSCFG_CFGR2_CAPA_3) 79 #define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ 80 #endif 81 #if defined (SYSCFG_CFGR2_CAPA_4) 82 #define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ 83 #endif 84 85 /** 86 * @} 87 */ 88 #endif 89 90 /** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection 91 * @{ 92 */ 93 #define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */ 94 #define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */ 95 #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ 96 #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ 97 98 #define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \ 99 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \ 100 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \ 101 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)) 102 /** 103 * @} 104 */ 105 106 /** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition 107 * @{ 108 */ 109 #define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF 110 111 #define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY)) 112 113 /** 114 * @} 115 */ 116 117 /** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO 118 * @{ 119 */ 120 /** @brief Fast mode Plus driving capability on a specific GPIO 121 */ 122 #if defined (SYSCFG_CFGR2_I2C_PB6_FMP) 123 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ 124 #endif 125 #if defined (SYSCFG_CFGR2_I2C_PB7_FMP) 126 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ 127 #endif 128 #if defined (SYSCFG_CFGR2_I2C_PB8_FMP) 129 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ 130 #endif 131 #if defined (SYSCFG_CFGR2_I2C_PB9_FMP) 132 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ 133 #endif 134 135 #define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \ 136 (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \ 137 (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \ 138 (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) ) 139 /** 140 * @} 141 */ 142 /** 143 * @} 144 */ 145 146 /* Exported macros -----------------------------------------------------------*/ 147 /** @defgroup HAL_Exported_Macros HAL Exported Macros 148 * @{ 149 */ 150 151 /** @brief Freeze/Unfreeze Peripherals in Debug mode 152 */ 153 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) 154 /** 155 * @brief TIM2 Peripherals Debug mode 156 */ 157 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) 158 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) 159 #endif 160 161 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) 162 /** 163 * @brief TIM3 Peripherals Debug mode 164 */ 165 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) 166 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) 167 #endif 168 169 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) 170 /** 171 * @brief TIM6 Peripherals Debug mode 172 */ 173 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 174 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 175 #endif 176 177 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) 178 /** 179 * @brief TIM7 Peripherals Debug mode 180 */ 181 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 182 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 183 #endif 184 185 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) 186 /** 187 * @brief RTC Peripherals Debug mode 188 */ 189 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 190 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 191 #endif 192 193 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) 194 /** 195 * @brief WWDG Peripherals Debug mode 196 */ 197 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 198 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 199 #endif 200 201 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) 202 /** 203 * @brief IWDG Peripherals Debug mode 204 */ 205 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 206 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 207 #endif 208 209 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP) 210 /** 211 * @brief I2C1 Peripherals Debug mode 212 */ 213 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 214 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 215 #endif 216 217 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP) 218 /** 219 * @brief I2C2 Peripherals Debug mode 220 */ 221 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 222 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 223 #endif 224 225 #if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP) 226 /** 227 * @brief I2C3 Peripherals Debug mode 228 */ 229 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 230 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 231 #endif 232 233 #if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 234 /** 235 * @brief LPTIMER Peripherals Debug mode 236 */ 237 #define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 238 #define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 239 #endif 240 241 #if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP) 242 /** 243 * @brief TIM22 Peripherals Debug mode 244 */ 245 #define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) 246 #define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) 247 #endif 248 249 #if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP) 250 /** 251 * @brief TIM21 Peripherals Debug mode 252 */ 253 #define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) 254 #define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) 255 #endif 256 257 /** @brief Main Flash memory mapped at 0x00000000 258 */ 259 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 260 261 /** @brief System Flash memory mapped at 0x00000000 262 */ 263 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) 264 265 266 /** @brief Embedded SRAM mapped at 0x00000000 267 */ 268 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1) 269 270 /** @brief Configuration of the DBG Low Power mode. 271 * @param __DBGLPMODE__ bit field to indicate in wich Low Power mode DBG is still active. 272 * This parameter can be a value of 273 * - DBGMCU_SLEEP 274 * - DBGMCU_STOP 275 * - DBGMCU_STANDBY 276 */ 277 #define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ 278 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \ 279 } while (0) 280 281 #if defined (LCD_BASE) /* STM32L0x3xx only */ 282 283 /** @brief Macro to configure the VLCD Decoupling capacitance connection. 284 * 285 * @param __SYSCFG_VLCD_CAPA__ specifies the decoupling of LCD capacitance for rails connection on GPIO. 286 * This parameter can be a combination of following values (when available): 287 * @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 288 * @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 289 * @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 290 * @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 291 * @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 292 * @retval None 293 */ 294 #define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \ 295 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__)) 296 297 /** 298 * @brief Returns the decoupling of LCD capacitance configured by user. 299 * @retval The LCD capacitance connection as configured by user. The returned can be a combination of : 300 * SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 301 * SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 302 * SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 303 * SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 304 * SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 305 */ 306 #define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA) 307 308 #endif 309 310 /** 311 * @brief Returns the boot mode as configured by user. 312 * @retval The boot mode as configured by user. The returned can be a value of : 313 * - SYSCFG_BOOT_MAINFLASH 314 * - SYSCFG_BOOT_SYSTEMFLASH 315 * - SYSCFG_BOOT_SRAM 316 */ 317 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE) 318 319 320 /** @brief Check whether the specified SYSCFG flag is set or not. 321 * @param __FLAG__ specifies the flag to check. 322 * The only parameter supported is SYSCFG_FLAG_VREFINT_READY 323 * @retval The new state of __FLAG__ (TRUE or FALSE). 324 */ 325 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__)) 326 327 /** @brief Fast mode Plus driving capability enable macro 328 * @param __FASTMODEPLUS__ This parameter can be a value of : 329 * @arg SYSCFG_FASTMODEPLUS_PB6 330 * @arg SYSCFG_FASTMODEPLUS_PB7 331 * @arg SYSCFG_FASTMODEPLUS_PB8 332 * @arg SYSCFG_FASTMODEPLUS_PB9 333 */ 334 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 335 SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ 336 }while(0) 337 /** @brief Fast mode Plus driving capability disable macro 338 * @param __FASTMODEPLUS__ This parameter can be a value of : 339 * @arg SYSCFG_FASTMODEPLUS_PB6 340 * @arg SYSCFG_FASTMODEPLUS_PB7 341 * @arg SYSCFG_FASTMODEPLUS_PB8 342 * @arg SYSCFG_FASTMODEPLUS_PB9 343 */ 344 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 345 CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ 346 }while(0) 347 348 349 /** 350 * @} 351 */ 352 353 /* Exported variables --------------------------------------------------------*/ 354 /** @defgroup HAL_Exported_Variables HAL Exported Variables 355 * @{ 356 */ 357 extern __IO uint32_t uwTick; 358 /** 359 * @} 360 */ 361 362 /* Exported functions --------------------------------------------------------*/ 363 /** @defgroup HAL_Exported_Functions HAL Exported Functions 364 * @{ 365 */ 366 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions 367 * @brief Initialization and de-initialization functions 368 * @{ 369 */ 370 HAL_StatusTypeDef HAL_Init(void); 371 HAL_StatusTypeDef HAL_DeInit(void); 372 void HAL_MspInit(void); 373 void HAL_MspDeInit(void); 374 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 375 376 /** 377 * @} 378 */ 379 380 /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions 381 * @brief Peripheral Control functions 382 * @{ 383 */ 384 void HAL_IncTick(void); 385 void HAL_Delay(uint32_t Delay); 386 uint32_t HAL_GetTick(void); 387 void HAL_SuspendTick(void); 388 void HAL_ResumeTick(void); 389 uint32_t HAL_GetHalVersion(void); 390 uint32_t HAL_GetREVID(void); 391 uint32_t HAL_GetDEVID(void); 392 uint32_t HAL_GetUIDw0(void); 393 uint32_t HAL_GetUIDw1(void); 394 uint32_t HAL_GetUIDw2(void); 395 /** 396 * @} 397 */ 398 399 /** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions 400 * @brief DBGMCU Peripheral Control functions 401 * @{ 402 */ 403 void HAL_DBGMCU_EnableDBGSleepMode(void); 404 void HAL_DBGMCU_DisableDBGSleepMode(void); 405 void HAL_DBGMCU_EnableDBGStopMode(void); 406 void HAL_DBGMCU_DisableDBGStopMode(void); 407 void HAL_DBGMCU_EnableDBGStandbyMode(void); 408 void HAL_DBGMCU_DisableDBGStandbyMode(void); 409 void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); 410 void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); 411 /** 412 * @} 413 */ 414 415 /** @defgroup HAL_Exported_Functions_Group4 SYSCFG Peripheral Control functions 416 * @brief SYSCFG Peripheral Control functions 417 * @{ 418 */ 419 uint32_t HAL_SYSCFG_GetBootMode(void); 420 void HAL_SYSCFG_Enable_Lock_VREFINT(void); 421 void HAL_SYSCFG_Disable_Lock_VREFINT(void); 422 void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); 423 /** 424 * @} 425 */ 426 /** 427 * @} 428 */ 429 430 /* Define the private group ***********************************/ 431 /**************************************************************/ 432 /** @defgroup HAL_Private HAL Private 433 * @{ 434 */ 435 /** 436 * @} 437 */ 438 /**************************************************************/ 439 440 441 /** 442 * @} 443 */ 444 445 /** 446 * @} 447 */ 448 449 #ifdef __cplusplus 450 } 451 #endif 452 453 #endif /* __STM32L0xx_HAL_H */ 454 455 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 456 457