1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL UTILS driver contains a set of generic APIs that can be
12 used by user:
13 (+) Device electronic signature
14 (+) Timing functions
15 (+) PLL configuration functions
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
22 * All rights reserved.</center></h2>
23 *
24 * This software component is licensed by ST under BSD 3-Clause license,
25 * the "License"; You may not use this file except in compliance with the
26 * License. You may obtain a copy of the License at:
27 * opensource.org/licenses/BSD-3-Clause
28 *
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32F4xx_LL_UTILS_H
34 #define __STM32F4xx_LL_UTILS_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32f4xx.h"
42
43 /** @addtogroup STM32F4xx_LL_Driver
44 * @{
45 */
46
47 /** @defgroup UTILS_LL UTILS
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
56 * @{
57 */
58
59 /* Max delay can be used in LL_mDelay */
60 #define LL_MAX_DELAY 0xFFFFFFFFU
61
62 /**
63 * @brief Unique device ID register base address
64 */
65 #define UID_BASE_ADDRESS UID_BASE
66
67 /**
68 * @brief Flash size data register base address
69 */
70 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
71
72 /**
73 * @brief Package data register base address
74 */
75 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
76
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
83 * @{
84 */
85 /**
86 * @}
87 */
88 /* Exported types ------------------------------------------------------------*/
89 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
90 * @{
91 */
92 /**
93 * @brief UTILS PLL structure definition
94 */
95 typedef struct
96 {
97 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
98 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
99
100 This feature can be modified afterwards using unitary function
101 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
102
103 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
104 This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE
105 and Max_Data = @ref RCC_PLLN_MIN_VALUE
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
109
110 uint32_t PLLP; /*!< Division for the main system clock.
111 This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
115 } LL_UTILS_PLLInitTypeDef;
116
117 /**
118 * @brief UTILS System, AHB and APB buses clock configuration structure definition
119 */
120 typedef struct
121 {
122 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
123 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
124
125 This feature can be modified afterwards using unitary function
126 @ref LL_RCC_SetAHBPrescaler(). */
127
128 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
129 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
130
131 This feature can be modified afterwards using unitary function
132 @ref LL_RCC_SetAPB1Prescaler(). */
133
134 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
135 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
136
137 This feature can be modified afterwards using unitary function
138 @ref LL_RCC_SetAPB2Prescaler(). */
139
140 } LL_UTILS_ClkInitTypeDef;
141
142 /**
143 * @}
144 */
145
146 /* Exported constants --------------------------------------------------------*/
147 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
148 * @{
149 */
150
151 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
152 * @{
153 */
154 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
155 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
156 /**
157 * @}
158 */
159
160 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
161 * @{
162 */
163 #define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */
164 #define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */
165 #define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */
166 #define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */
167 #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */
168 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */
169 #define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */
170 /**
171 * @}
172 */
173
174 /**
175 * @}
176 */
177
178 /* Exported macro ------------------------------------------------------------*/
179
180 /* Exported functions --------------------------------------------------------*/
181 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
182 * @{
183 */
184
185 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
186 * @{
187 */
188
189 /**
190 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
191 * @retval UID[31:0]
192 */
LL_GetUID_Word0(void)193 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
194 {
195 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
196 }
197
198 /**
199 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
200 * @retval UID[63:32]
201 */
LL_GetUID_Word1(void)202 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
203 {
204 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
205 }
206
207 /**
208 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
209 * @retval UID[95:64]
210 */
LL_GetUID_Word2(void)211 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
212 {
213 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
214 }
215
216 /**
217 * @brief Get Flash memory size
218 * @note This bitfield indicates the size of the device Flash memory expressed in
219 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
220 * @retval FLASH_SIZE[15:0]: Flash memory size
221 */
LL_GetFlashSize(void)222 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
223 {
224 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
225 }
226
227 /**
228 * @brief Get Package type
229 * @retval Returned value can be one of the following values:
230 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)
231 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)
232 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)
233 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)
234 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
235 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
236 * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
237 *
238 * (*) value not defined in all devices.
239 */
LL_GetPackageType(void)240 __STATIC_INLINE uint32_t LL_GetPackageType(void)
241 {
242 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
243 }
244
245 /**
246 * @}
247 */
248
249 /** @defgroup UTILS_LL_EF_DELAY DELAY
250 * @{
251 */
252
253 /**
254 * @brief This function configures the Cortex-M SysTick source of the time base.
255 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
256 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
257 * configuration by calling this function, for a delay use rather osDelay RTOS service.
258 * @param Ticks Number of ticks
259 * @retval None
260 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)261 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
262 {
263 /* Configure the SysTick to have interrupt in 1ms time base */
264 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
265 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
266 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
267 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
268 }
269
270 void LL_Init1msTick(uint32_t HCLKFrequency);
271 void LL_mDelay(uint32_t Delay);
272
273 /**
274 * @}
275 */
276
277 /** @defgroup UTILS_EF_SYSTEM SYSTEM
278 * @{
279 */
280
281 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
282 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
283 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
284 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
285 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
286
287 /**
288 * @}
289 */
290
291 /**
292 * @}
293 */
294
295 /**
296 * @}
297 */
298
299 /**
300 * @}
301 */
302
303 #ifdef __cplusplus
304 }
305 #endif
306
307 #endif /* __STM32F4xx_LL_UTILS_H */
308
309 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
310