1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_LL_TIM_H
22 #define __STM32F4xx_LL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
36
37 /** @defgroup TIM_LL TIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
44 * @{
45 */
46 static const uint8_t OFFSET_TAB_CCMRx[] =
47 {
48 0x00U, /* 0: TIMx_CH1 */
49 0x00U, /* 1: TIMx_CH1N */
50 0x00U, /* 2: TIMx_CH2 */
51 0x00U, /* 3: TIMx_CH2N */
52 0x04U, /* 4: TIMx_CH3 */
53 0x04U, /* 5: TIMx_CH3N */
54 0x04U /* 6: TIMx_CH4 */
55 };
56
57 static const uint8_t SHIFT_TAB_OCxx[] =
58 {
59 0U, /* 0: OC1M, OC1FE, OC1PE */
60 0U, /* 1: - NA */
61 8U, /* 2: OC2M, OC2FE, OC2PE */
62 0U, /* 3: - NA */
63 0U, /* 4: OC3M, OC3FE, OC3PE */
64 0U, /* 5: - NA */
65 8U /* 6: OC4M, OC4FE, OC4PE */
66 };
67
68 static const uint8_t SHIFT_TAB_ICxx[] =
69 {
70 0U, /* 0: CC1S, IC1PSC, IC1F */
71 0U, /* 1: - NA */
72 8U, /* 2: CC2S, IC2PSC, IC2F */
73 0U, /* 3: - NA */
74 0U, /* 4: CC3S, IC3PSC, IC3F */
75 0U, /* 5: - NA */
76 8U /* 6: CC4S, IC4PSC, IC4F */
77 };
78
79 static const uint8_t SHIFT_TAB_CCxP[] =
80 {
81 0U, /* 0: CC1P */
82 2U, /* 1: CC1NP */
83 4U, /* 2: CC2P */
84 6U, /* 3: CC2NP */
85 8U, /* 4: CC3P */
86 10U, /* 5: CC3NP */
87 12U /* 6: CC4P */
88 };
89
90 static const uint8_t SHIFT_TAB_OISx[] =
91 {
92 0U, /* 0: OIS1 */
93 1U, /* 1: OIS1N */
94 2U, /* 2: OIS2 */
95 3U, /* 3: OIS2N */
96 4U, /* 4: OIS3 */
97 5U, /* 5: OIS3N */
98 6U /* 6: OIS4 */
99 };
100 /**
101 * @}
102 */
103
104 /* Private constants ---------------------------------------------------------*/
105 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
106 * @{
107 */
108
109
110 /* Remap mask definitions */
111 #define TIMx_OR_RMP_SHIFT 16U
112 #define TIMx_OR_RMP_MASK 0x0000FFFFU
113 #define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
114 #define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
115 #define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
116
117 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
118 #define DT_DELAY_1 ((uint8_t)0x7F)
119 #define DT_DELAY_2 ((uint8_t)0x3F)
120 #define DT_DELAY_3 ((uint8_t)0x1F)
121 #define DT_DELAY_4 ((uint8_t)0x1F)
122
123 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
124 #define DT_RANGE_1 ((uint8_t)0x00)
125 #define DT_RANGE_2 ((uint8_t)0x80)
126 #define DT_RANGE_3 ((uint8_t)0xC0)
127 #define DT_RANGE_4 ((uint8_t)0xE0)
128
129
130 /**
131 * @}
132 */
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
136 * @{
137 */
138 /** @brief Convert channel id into channel index.
139 * @param __CHANNEL__ This parameter can be one of the following values:
140 * @arg @ref LL_TIM_CHANNEL_CH1
141 * @arg @ref LL_TIM_CHANNEL_CH1N
142 * @arg @ref LL_TIM_CHANNEL_CH2
143 * @arg @ref LL_TIM_CHANNEL_CH2N
144 * @arg @ref LL_TIM_CHANNEL_CH3
145 * @arg @ref LL_TIM_CHANNEL_CH3N
146 * @arg @ref LL_TIM_CHANNEL_CH4
147 * @retval none
148 */
149 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
150 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
151 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
152 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
153 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
154 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
155 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
156
157 /** @brief Calculate the deadtime sampling period(in ps).
158 * @param __TIMCLK__ timer input clock frequency (in Hz).
159 * @param __CKD__ This parameter can be one of the following values:
160 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
161 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
162 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
163 * @retval none
164 */
165 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
166 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
167 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
168 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
169 /**
170 * @}
171 */
172
173
174 /* Exported types ------------------------------------------------------------*/
175 #if defined(USE_FULL_LL_DRIVER)
176 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
177 * @{
178 */
179
180 /**
181 * @brief TIM Time Base configuration structure definition.
182 */
183 typedef struct
184 {
185 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
186 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
187
188 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
189
190 uint32_t CounterMode; /*!< Specifies the counter mode.
191 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
192
193 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
194
195 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
196 Auto-Reload Register at the next update event.
197 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
198 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
199
200 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
201
202 uint32_t ClockDivision; /*!< Specifies the clock division.
203 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
204
205 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
206
207 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
208 reaches zero, an update event is generated and counting restarts
209 from the RCR value (N).
210 This means in PWM mode that (N+1) corresponds to:
211 - the number of PWM periods in edge-aligned mode
212 - the number of half PWM period in center-aligned mode
213 This parameter must be a number between 0x00 and 0xFF.
214
215 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
216 } LL_TIM_InitTypeDef;
217
218 /**
219 * @brief TIM Output Compare configuration structure definition.
220 */
221 typedef struct
222 {
223 uint32_t OCMode; /*!< Specifies the output mode.
224 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
225
226 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
227
228 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
229 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
230
231 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
232
233 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
234 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
235
236 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
237
238 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
239 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
240
241 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
242
243 uint32_t OCPolarity; /*!< Specifies the output polarity.
244 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
245
246 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
247
248 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
249 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
250
251 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
252
253
254 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
255 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
256
257 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
258
259 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
260 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
261
262 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
263 } LL_TIM_OC_InitTypeDef;
264
265 /**
266 * @brief TIM Input Capture configuration structure definition.
267 */
268
269 typedef struct
270 {
271
272 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
273 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
274
275 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
276
277 uint32_t ICActiveInput; /*!< Specifies the input.
278 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
279
280 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
281
282 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
283 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
284
285 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
286
287 uint32_t ICFilter; /*!< Specifies the input capture filter.
288 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
289
290 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
291 } LL_TIM_IC_InitTypeDef;
292
293
294 /**
295 * @brief TIM Encoder interface configuration structure definition.
296 */
297 typedef struct
298 {
299 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
300 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
301
302 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
303
304 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
305 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
306
307 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
308
309 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
310 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
311
312 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
313
314 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
315 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
316
317 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
318
319 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
320 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
321
322 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
323
324 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
325 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
326
327 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
328
329 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
330 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
331
332 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
333
334 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
335 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
336
337 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
338
339 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
340 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
341
342 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
343
344 } LL_TIM_ENCODER_InitTypeDef;
345
346 /**
347 * @brief TIM Hall sensor interface configuration structure definition.
348 */
349 typedef struct
350 {
351
352 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
353 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
354
355 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
356
357 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
358 Prescaler must be set to get a maximum counter period longer than the
359 time interval between 2 consecutive changes on the Hall inputs.
360 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
361
362 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
363
364 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
365 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
366
367 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
368
369 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
370 A positive pulse (TRGO event) is generated with a programmable delay every time
371 a change occurs on the Hall inputs.
372 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
373
374 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
375 } LL_TIM_HALLSENSOR_InitTypeDef;
376
377 /**
378 * @brief BDTR (Break and Dead Time) structure definition
379 */
380 typedef struct
381 {
382 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
383 This parameter can be a value of @ref TIM_LL_EC_OSSR
384
385 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
386
387 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
388
389 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
390 This parameter can be a value of @ref TIM_LL_EC_OSSI
391
392 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
393
394 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
395
396 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
397 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
398
399 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
400 has been written, their content is frozen until the next reset.*/
401
402 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
403 switching-on of the outputs.
404 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
405
406 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
407
408 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
409
410 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
411 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
412
413 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
414
415 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
416
417 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
418 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
419
420 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
421
422 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
423
424 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
425 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
426
427 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
428
429 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
430 } LL_TIM_BDTR_InitTypeDef;
431
432 /**
433 * @}
434 */
435 #endif /* USE_FULL_LL_DRIVER */
436
437 /* Exported constants --------------------------------------------------------*/
438 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
439 * @{
440 */
441
442 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
443 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
444 * @{
445 */
446 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
447 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
448 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
449 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
450 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
451 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
452 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
453 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
454 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
455 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
456 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
457 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
458 /**
459 * @}
460 */
461
462 #if defined(USE_FULL_LL_DRIVER)
463 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
464 * @{
465 */
466 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
467 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
468 /**
469 * @}
470 */
471
472 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
473 * @{
474 */
475 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
476 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
477 /**
478 * @}
479 */
480 #endif /* USE_FULL_LL_DRIVER */
481
482 /** @defgroup TIM_LL_EC_IT IT Defines
483 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
484 * @{
485 */
486 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
487 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
488 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
489 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
490 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
491 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
492 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
493 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
494 /**
495 * @}
496 */
497
498 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
499 * @{
500 */
501 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
502 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
503 /**
504 * @}
505 */
506
507 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
508 * @{
509 */
510 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
511 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
512 /**
513 * @}
514 */
515
516 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
517 * @{
518 */
519 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
520 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
521 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
522 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
523 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
524 /**
525 * @}
526 */
527
528 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
529 * @{
530 */
531 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
532 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
533 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
534 /**
535 * @}
536 */
537
538 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
539 * @{
540 */
541 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
542 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
543 /**
544 * @}
545 */
546
547 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
548 * @{
549 */
550 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
551 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
552 /**
553 * @}
554 */
555
556 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
557 * @{
558 */
559 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
560 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
561 /**
562 * @}
563 */
564
565 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
566 * @{
567 */
568 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
569 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
570 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
571 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
572 /**
573 * @}
574 */
575
576 /** @defgroup TIM_LL_EC_CHANNEL Channel
577 * @{
578 */
579 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
580 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
581 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
582 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
583 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
584 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
585 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
586 /**
587 * @}
588 */
589
590 #if defined(USE_FULL_LL_DRIVER)
591 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
592 * @{
593 */
594 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
595 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
596 /**
597 * @}
598 */
599 #endif /* USE_FULL_LL_DRIVER */
600
601 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
602 * @{
603 */
604 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
605 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
606 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
607 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
608 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
609 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
610 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
611 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
612 /**
613 * @}
614 */
615
616 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
617 * @{
618 */
619 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
620 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
621 /**
622 * @}
623 */
624
625 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
626 * @{
627 */
628 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
629 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
630 /**
631 * @}
632 */
633
634
635 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
636 * @{
637 */
638 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
639 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
640 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
641 /**
642 * @}
643 */
644
645 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
646 * @{
647 */
648 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
649 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
650 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
651 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
652 /**
653 * @}
654 */
655
656 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
657 * @{
658 */
659 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
660 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
661 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
662 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
663 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
664 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
665 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
666 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
667 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
668 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
669 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
670 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
671 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
672 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
673 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
674 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
675 /**
676 * @}
677 */
678
679 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
680 * @{
681 */
682 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
683 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
684 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
685 /**
686 * @}
687 */
688
689 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
690 * @{
691 */
692 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
693 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
694 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
695 /**
696 * @}
697 */
698
699 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
700 * @{
701 */
702 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
703 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
704 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
705 /**
706 * @}
707 */
708
709 /** @defgroup TIM_LL_EC_TRGO Trigger Output
710 * @{
711 */
712 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
713 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
714 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
715 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
716 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
717 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
718 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
719 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
720 /**
721 * @}
722 */
723
724
725 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
726 * @{
727 */
728 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
729 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
730 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
731 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
732 /**
733 * @}
734 */
735
736 /** @defgroup TIM_LL_EC_TS Trigger Selection
737 * @{
738 */
739 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
740 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
741 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
742 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
743 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
744 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
745 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
746 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
747 /**
748 * @}
749 */
750
751 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
752 * @{
753 */
754 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
755 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
756 /**
757 * @}
758 */
759
760 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
761 * @{
762 */
763 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
764 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
765 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
766 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
767 /**
768 * @}
769 */
770
771 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
772 * @{
773 */
774 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
775 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
776 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
777 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
778 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
779 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
780 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
781 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
782 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
783 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
784 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
785 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
786 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
787 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
788 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
789 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
790 /**
791 * @}
792 */
793
794
795 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
796 * @{
797 */
798 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
799 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
800 /**
801 * @}
802 */
803
804
805
806
807 /** @defgroup TIM_LL_EC_OSSI OSSI
808 * @{
809 */
810 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
811 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
812 /**
813 * @}
814 */
815
816 /** @defgroup TIM_LL_EC_OSSR OSSR
817 * @{
818 */
819 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
820 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
821 /**
822 * @}
823 */
824
825
826 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
827 * @{
828 */
829 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
830 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
831 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
832 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
833 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
834 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
835 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
836 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
837 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
838 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
839 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
840 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
841 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
842 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
843 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
844 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
845 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
846 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
847 /**
848 * @}
849 */
850
851 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
852 * @{
853 */
854 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
855 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
856 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
857 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
858 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
859 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
860 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
861 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
862 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
863 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
864 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
865 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
866 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
867 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
868 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
869 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
870 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
871 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
872 /**
873 * @}
874 */
875
876
877 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
878 * @{
879 */
880 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
881 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
882 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
883 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
884 /**
885 * @}
886 */
887
888 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
889 * @{
890 */
891 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
892 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
893 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
894 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
895 /**
896 * @}
897 */
898
899 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
900 * @{
901 */
902 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
903 #if defined(SPDIFRX)
904 #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
905 #else
906 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
907 #endif
908 #define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */
909 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */
910 /**
911 * @}
912 */
913
914 /**
915 * @}
916 */
917
918 /* Exported macro ------------------------------------------------------------*/
919 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
920 * @{
921 */
922
923 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
924 * @{
925 */
926 /**
927 * @brief Write a value in TIM register.
928 * @param __INSTANCE__ TIM Instance
929 * @param __REG__ Register to be written
930 * @param __VALUE__ Value to be written in the register
931 * @retval None
932 */
933 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
934
935 /**
936 * @brief Read a value in TIM register.
937 * @param __INSTANCE__ TIM Instance
938 * @param __REG__ Register to be read
939 * @retval Register value
940 */
941 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
942 /**
943 * @}
944 */
945
946 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
947 * @{
948 */
949
950 /**
951 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
952 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
953 * @param __TIMCLK__ timer input clock frequency (in Hz)
954 * @param __CKD__ This parameter can be one of the following values:
955 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
956 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
957 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
958 * @param __DT__ deadtime duration (in ns)
959 * @retval DTG[0:7]
960 */
961 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
962 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
963 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
964 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
965 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
966 0U)
967
968 /**
969 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
970 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
971 * @param __TIMCLK__ timer input clock frequency (in Hz)
972 * @param __CNTCLK__ counter clock frequency (in Hz)
973 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
974 */
975 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
976 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
977
978 /**
979 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
980 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
981 * @param __TIMCLK__ timer input clock frequency (in Hz)
982 * @param __PSC__ prescaler
983 * @param __FREQ__ output signal frequency (in Hz)
984 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
985 */
986 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
987 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
988
989 /**
990 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
991 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
992 * @param __TIMCLK__ timer input clock frequency (in Hz)
993 * @param __PSC__ prescaler
994 * @param __DELAY__ timer output compare active/inactive delay (in us)
995 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
996 */
997 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
998 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
999 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1000
1001 /**
1002 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1003 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1004 * @param __TIMCLK__ timer input clock frequency (in Hz)
1005 * @param __PSC__ prescaler
1006 * @param __DELAY__ timer output compare active/inactive delay (in us)
1007 * @param __PULSE__ pulse duration (in us)
1008 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1009 */
1010 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1011 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1012 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1013
1014 /**
1015 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1016 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1017 * @param __ICPSC__ This parameter can be one of the following values:
1018 * @arg @ref LL_TIM_ICPSC_DIV1
1019 * @arg @ref LL_TIM_ICPSC_DIV2
1020 * @arg @ref LL_TIM_ICPSC_DIV4
1021 * @arg @ref LL_TIM_ICPSC_DIV8
1022 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1023 */
1024 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1025 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1026
1027
1028 /**
1029 * @}
1030 */
1031
1032
1033 /**
1034 * @}
1035 */
1036
1037 /* Exported functions --------------------------------------------------------*/
1038 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1039 * @{
1040 */
1041
1042 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1043 * @{
1044 */
1045 /**
1046 * @brief Enable timer counter.
1047 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1048 * @param TIMx Timer instance
1049 * @retval None
1050 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1051 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1052 {
1053 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1054 }
1055
1056 /**
1057 * @brief Disable timer counter.
1058 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1059 * @param TIMx Timer instance
1060 * @retval None
1061 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1062 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1063 {
1064 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1065 }
1066
1067 /**
1068 * @brief Indicates whether the timer counter is enabled.
1069 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1070 * @param TIMx Timer instance
1071 * @retval State of bit (1 or 0).
1072 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)1073 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1074 {
1075 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1076 }
1077
1078 /**
1079 * @brief Enable update event generation.
1080 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1081 * @param TIMx Timer instance
1082 * @retval None
1083 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1084 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1085 {
1086 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1087 }
1088
1089 /**
1090 * @brief Disable update event generation.
1091 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1092 * @param TIMx Timer instance
1093 * @retval None
1094 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1095 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1096 {
1097 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1098 }
1099
1100 /**
1101 * @brief Indicates whether update event generation is enabled.
1102 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1103 * @param TIMx Timer instance
1104 * @retval Inverted state of bit (0 or 1).
1105 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)1106 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1107 {
1108 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1109 }
1110
1111 /**
1112 * @brief Set update event source
1113 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1114 * generate an update interrupt or DMA request if enabled:
1115 * - Counter overflow/underflow
1116 * - Setting the UG bit
1117 * - Update generation through the slave mode controller
1118 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1119 * overflow/underflow generates an update interrupt or DMA request if enabled.
1120 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1121 * @param TIMx Timer instance
1122 * @param UpdateSource This parameter can be one of the following values:
1123 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1124 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1125 * @retval None
1126 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1127 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1128 {
1129 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1130 }
1131
1132 /**
1133 * @brief Get actual event update source
1134 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1135 * @param TIMx Timer instance
1136 * @retval Returned value can be one of the following values:
1137 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1138 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1139 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)1140 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1141 {
1142 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1143 }
1144
1145 /**
1146 * @brief Set one pulse mode (one shot v.s. repetitive).
1147 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1148 * @param TIMx Timer instance
1149 * @param OnePulseMode This parameter can be one of the following values:
1150 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1151 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1152 * @retval None
1153 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1154 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1155 {
1156 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1157 }
1158
1159 /**
1160 * @brief Get actual one pulse mode.
1161 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1162 * @param TIMx Timer instance
1163 * @retval Returned value can be one of the following values:
1164 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1165 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1166 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1167 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1168 {
1169 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1170 }
1171
1172 /**
1173 * @brief Set the timer counter counting mode.
1174 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1175 * check whether or not the counter mode selection feature is supported
1176 * by a timer instance.
1177 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1178 * requires a timer reset to avoid unexpected direction
1179 * due to DIR bit readonly in center aligned mode.
1180 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1181 * CR1 CMS LL_TIM_SetCounterMode
1182 * @param TIMx Timer instance
1183 * @param CounterMode This parameter can be one of the following values:
1184 * @arg @ref LL_TIM_COUNTERMODE_UP
1185 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1186 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1187 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1188 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1189 * @retval None
1190 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1191 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1192 {
1193 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1194 }
1195
1196 /**
1197 * @brief Get actual counter mode.
1198 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1199 * check whether or not the counter mode selection feature is supported
1200 * by a timer instance.
1201 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1202 * CR1 CMS LL_TIM_GetCounterMode
1203 * @param TIMx Timer instance
1204 * @retval Returned value can be one of the following values:
1205 * @arg @ref LL_TIM_COUNTERMODE_UP
1206 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1207 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1208 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1209 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1210 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1211 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1212 {
1213 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1214 }
1215
1216 /**
1217 * @brief Enable auto-reload (ARR) preload.
1218 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1219 * @param TIMx Timer instance
1220 * @retval None
1221 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1222 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1223 {
1224 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1225 }
1226
1227 /**
1228 * @brief Disable auto-reload (ARR) preload.
1229 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1230 * @param TIMx Timer instance
1231 * @retval None
1232 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1233 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1234 {
1235 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1236 }
1237
1238 /**
1239 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1240 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1241 * @param TIMx Timer instance
1242 * @retval State of bit (1 or 0).
1243 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1244 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1245 {
1246 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1247 }
1248
1249 /**
1250 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1251 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1252 * whether or not the clock division feature is supported by the timer
1253 * instance.
1254 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1255 * @param TIMx Timer instance
1256 * @param ClockDivision This parameter can be one of the following values:
1257 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1258 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1259 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1260 * @retval None
1261 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1262 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1263 {
1264 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1265 }
1266
1267 /**
1268 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1269 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1270 * whether or not the clock division feature is supported by the timer
1271 * instance.
1272 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1273 * @param TIMx Timer instance
1274 * @retval Returned value can be one of the following values:
1275 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1276 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1277 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1278 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1279 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1280 {
1281 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1282 }
1283
1284 /**
1285 * @brief Set the counter value.
1286 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1287 * whether or not a timer instance supports a 32 bits counter.
1288 * @rmtoll CNT CNT LL_TIM_SetCounter
1289 * @param TIMx Timer instance
1290 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1291 * @retval None
1292 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1293 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1294 {
1295 WRITE_REG(TIMx->CNT, Counter);
1296 }
1297
1298 /**
1299 * @brief Get the counter value.
1300 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1301 * whether or not a timer instance supports a 32 bits counter.
1302 * @rmtoll CNT CNT LL_TIM_GetCounter
1303 * @param TIMx Timer instance
1304 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1305 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1306 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1307 {
1308 return (uint32_t)(READ_REG(TIMx->CNT));
1309 }
1310
1311 /**
1312 * @brief Get the current direction of the counter
1313 * @rmtoll CR1 DIR LL_TIM_GetDirection
1314 * @param TIMx Timer instance
1315 * @retval Returned value can be one of the following values:
1316 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1317 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1318 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1319 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1320 {
1321 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1322 }
1323
1324 /**
1325 * @brief Set the prescaler value.
1326 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1327 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1328 * prescaler ratio is taken into account at the next update event.
1329 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1330 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1331 * @param TIMx Timer instance
1332 * @param Prescaler between Min_Data=0 and Max_Data=65535
1333 * @retval None
1334 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1335 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1336 {
1337 WRITE_REG(TIMx->PSC, Prescaler);
1338 }
1339
1340 /**
1341 * @brief Get the prescaler value.
1342 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1343 * @param TIMx Timer instance
1344 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1345 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1346 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1347 {
1348 return (uint32_t)(READ_REG(TIMx->PSC));
1349 }
1350
1351 /**
1352 * @brief Set the auto-reload value.
1353 * @note The counter is blocked while the auto-reload value is null.
1354 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1355 * whether or not a timer instance supports a 32 bits counter.
1356 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1357 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1358 * @param TIMx Timer instance
1359 * @param AutoReload between Min_Data=0 and Max_Data=65535
1360 * @retval None
1361 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1362 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1363 {
1364 WRITE_REG(TIMx->ARR, AutoReload);
1365 }
1366
1367 /**
1368 * @brief Get the auto-reload value.
1369 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1370 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1371 * whether or not a timer instance supports a 32 bits counter.
1372 * @param TIMx Timer instance
1373 * @retval Auto-reload value
1374 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1375 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1376 {
1377 return (uint32_t)(READ_REG(TIMx->ARR));
1378 }
1379
1380 /**
1381 * @brief Set the repetition counter value.
1382 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1383 * whether or not a timer instance supports a repetition counter.
1384 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1385 * @param TIMx Timer instance
1386 * @param RepetitionCounter between Min_Data=0 and Max_Data=255
1387 * @retval None
1388 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1389 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1390 {
1391 WRITE_REG(TIMx->RCR, RepetitionCounter);
1392 }
1393
1394 /**
1395 * @brief Get the repetition counter value.
1396 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1397 * whether or not a timer instance supports a repetition counter.
1398 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1399 * @param TIMx Timer instance
1400 * @retval Repetition counter value
1401 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)1402 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1403 {
1404 return (uint32_t)(READ_REG(TIMx->RCR));
1405 }
1406
1407 /**
1408 * @}
1409 */
1410
1411 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1412 * @{
1413 */
1414 /**
1415 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1416 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1417 * they are updated only when a commutation event (COM) occurs.
1418 * @note Only on channels that have a complementary output.
1419 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1420 * whether or not a timer instance is able to generate a commutation event.
1421 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1422 * @param TIMx Timer instance
1423 * @retval None
1424 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1425 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1426 {
1427 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1428 }
1429
1430 /**
1431 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1432 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1433 * whether or not a timer instance is able to generate a commutation event.
1434 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1435 * @param TIMx Timer instance
1436 * @retval None
1437 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1438 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1439 {
1440 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1441 }
1442
1443 /**
1444 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1445 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1446 * whether or not a timer instance is able to generate a commutation event.
1447 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1448 * @param TIMx Timer instance
1449 * @param CCUpdateSource This parameter can be one of the following values:
1450 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1451 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1452 * @retval None
1453 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1454 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1455 {
1456 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1457 }
1458
1459 /**
1460 * @brief Set the trigger of the capture/compare DMA request.
1461 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1462 * @param TIMx Timer instance
1463 * @param DMAReqTrigger This parameter can be one of the following values:
1464 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1465 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1466 * @retval None
1467 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1468 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1469 {
1470 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1471 }
1472
1473 /**
1474 * @brief Get actual trigger of the capture/compare DMA request.
1475 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1476 * @param TIMx Timer instance
1477 * @retval Returned value can be one of the following values:
1478 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1479 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1480 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1481 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1482 {
1483 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1484 }
1485
1486 /**
1487 * @brief Set the lock level to freeze the
1488 * configuration of several capture/compare parameters.
1489 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1490 * the lock mechanism is supported by a timer instance.
1491 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1492 * @param TIMx Timer instance
1493 * @param LockLevel This parameter can be one of the following values:
1494 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1495 * @arg @ref LL_TIM_LOCKLEVEL_1
1496 * @arg @ref LL_TIM_LOCKLEVEL_2
1497 * @arg @ref LL_TIM_LOCKLEVEL_3
1498 * @retval None
1499 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1500 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1501 {
1502 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1503 }
1504
1505 /**
1506 * @brief Enable capture/compare channels.
1507 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1508 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1509 * CCER CC2E LL_TIM_CC_EnableChannel\n
1510 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1511 * CCER CC3E LL_TIM_CC_EnableChannel\n
1512 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1513 * CCER CC4E LL_TIM_CC_EnableChannel
1514 * @param TIMx Timer instance
1515 * @param Channels This parameter can be a combination of the following values:
1516 * @arg @ref LL_TIM_CHANNEL_CH1
1517 * @arg @ref LL_TIM_CHANNEL_CH1N
1518 * @arg @ref LL_TIM_CHANNEL_CH2
1519 * @arg @ref LL_TIM_CHANNEL_CH2N
1520 * @arg @ref LL_TIM_CHANNEL_CH3
1521 * @arg @ref LL_TIM_CHANNEL_CH3N
1522 * @arg @ref LL_TIM_CHANNEL_CH4
1523 * @retval None
1524 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1525 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1526 {
1527 SET_BIT(TIMx->CCER, Channels);
1528 }
1529
1530 /**
1531 * @brief Disable capture/compare channels.
1532 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1533 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1534 * CCER CC2E LL_TIM_CC_DisableChannel\n
1535 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1536 * CCER CC3E LL_TIM_CC_DisableChannel\n
1537 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1538 * CCER CC4E LL_TIM_CC_DisableChannel
1539 * @param TIMx Timer instance
1540 * @param Channels This parameter can be a combination of the following values:
1541 * @arg @ref LL_TIM_CHANNEL_CH1
1542 * @arg @ref LL_TIM_CHANNEL_CH1N
1543 * @arg @ref LL_TIM_CHANNEL_CH2
1544 * @arg @ref LL_TIM_CHANNEL_CH2N
1545 * @arg @ref LL_TIM_CHANNEL_CH3
1546 * @arg @ref LL_TIM_CHANNEL_CH3N
1547 * @arg @ref LL_TIM_CHANNEL_CH4
1548 * @retval None
1549 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1550 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1551 {
1552 CLEAR_BIT(TIMx->CCER, Channels);
1553 }
1554
1555 /**
1556 * @brief Indicate whether channel(s) is(are) enabled.
1557 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1558 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1559 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1560 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1561 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1562 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1563 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1564 * @param TIMx Timer instance
1565 * @param Channels This parameter can be a combination of the following values:
1566 * @arg @ref LL_TIM_CHANNEL_CH1
1567 * @arg @ref LL_TIM_CHANNEL_CH1N
1568 * @arg @ref LL_TIM_CHANNEL_CH2
1569 * @arg @ref LL_TIM_CHANNEL_CH2N
1570 * @arg @ref LL_TIM_CHANNEL_CH3
1571 * @arg @ref LL_TIM_CHANNEL_CH3N
1572 * @arg @ref LL_TIM_CHANNEL_CH4
1573 * @retval State of bit (1 or 0).
1574 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1575 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1576 {
1577 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1578 }
1579
1580 /**
1581 * @}
1582 */
1583
1584 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1585 * @{
1586 */
1587 /**
1588 * @brief Configure an output channel.
1589 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1590 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1591 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1592 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1593 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1594 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1595 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1596 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1597 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1598 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1599 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1600 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1601 * @param TIMx Timer instance
1602 * @param Channel This parameter can be one of the following values:
1603 * @arg @ref LL_TIM_CHANNEL_CH1
1604 * @arg @ref LL_TIM_CHANNEL_CH2
1605 * @arg @ref LL_TIM_CHANNEL_CH3
1606 * @arg @ref LL_TIM_CHANNEL_CH4
1607 * @param Configuration This parameter must be a combination of all the following values:
1608 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1609 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1610 * @retval None
1611 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1612 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1613 {
1614 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1615 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1616 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1617 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1618 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1619 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1620 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1621 }
1622
1623 /**
1624 * @brief Define the behavior of the output reference signal OCxREF from which
1625 * OCx and OCxN (when relevant) are derived.
1626 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1627 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1628 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1629 * CCMR2 OC4M LL_TIM_OC_SetMode
1630 * @param TIMx Timer instance
1631 * @param Channel This parameter can be one of the following values:
1632 * @arg @ref LL_TIM_CHANNEL_CH1
1633 * @arg @ref LL_TIM_CHANNEL_CH2
1634 * @arg @ref LL_TIM_CHANNEL_CH3
1635 * @arg @ref LL_TIM_CHANNEL_CH4
1636 * @param Mode This parameter can be one of the following values:
1637 * @arg @ref LL_TIM_OCMODE_FROZEN
1638 * @arg @ref LL_TIM_OCMODE_ACTIVE
1639 * @arg @ref LL_TIM_OCMODE_INACTIVE
1640 * @arg @ref LL_TIM_OCMODE_TOGGLE
1641 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1642 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1643 * @arg @ref LL_TIM_OCMODE_PWM1
1644 * @arg @ref LL_TIM_OCMODE_PWM2
1645 * @retval None
1646 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1647 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1648 {
1649 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1650 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1651 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1652 }
1653
1654 /**
1655 * @brief Get the output compare mode of an output channel.
1656 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1657 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1658 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1659 * CCMR2 OC4M LL_TIM_OC_GetMode
1660 * @param TIMx Timer instance
1661 * @param Channel This parameter can be one of the following values:
1662 * @arg @ref LL_TIM_CHANNEL_CH1
1663 * @arg @ref LL_TIM_CHANNEL_CH2
1664 * @arg @ref LL_TIM_CHANNEL_CH3
1665 * @arg @ref LL_TIM_CHANNEL_CH4
1666 * @retval Returned value can be one of the following values:
1667 * @arg @ref LL_TIM_OCMODE_FROZEN
1668 * @arg @ref LL_TIM_OCMODE_ACTIVE
1669 * @arg @ref LL_TIM_OCMODE_INACTIVE
1670 * @arg @ref LL_TIM_OCMODE_TOGGLE
1671 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1672 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1673 * @arg @ref LL_TIM_OCMODE_PWM1
1674 * @arg @ref LL_TIM_OCMODE_PWM2
1675 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)1676 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
1677 {
1678 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1679 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1680 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1681 }
1682
1683 /**
1684 * @brief Set the polarity of an output channel.
1685 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1686 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1687 * CCER CC2P LL_TIM_OC_SetPolarity\n
1688 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1689 * CCER CC3P LL_TIM_OC_SetPolarity\n
1690 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1691 * CCER CC4P LL_TIM_OC_SetPolarity
1692 * @param TIMx Timer instance
1693 * @param Channel This parameter can be one of the following values:
1694 * @arg @ref LL_TIM_CHANNEL_CH1
1695 * @arg @ref LL_TIM_CHANNEL_CH1N
1696 * @arg @ref LL_TIM_CHANNEL_CH2
1697 * @arg @ref LL_TIM_CHANNEL_CH2N
1698 * @arg @ref LL_TIM_CHANNEL_CH3
1699 * @arg @ref LL_TIM_CHANNEL_CH3N
1700 * @arg @ref LL_TIM_CHANNEL_CH4
1701 * @param Polarity This parameter can be one of the following values:
1702 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1703 * @arg @ref LL_TIM_OCPOLARITY_LOW
1704 * @retval None
1705 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1706 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1707 {
1708 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1709 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1710 }
1711
1712 /**
1713 * @brief Get the polarity of an output channel.
1714 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1715 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1716 * CCER CC2P LL_TIM_OC_GetPolarity\n
1717 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1718 * CCER CC3P LL_TIM_OC_GetPolarity\n
1719 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1720 * CCER CC4P LL_TIM_OC_GetPolarity
1721 * @param TIMx Timer instance
1722 * @param Channel This parameter can be one of the following values:
1723 * @arg @ref LL_TIM_CHANNEL_CH1
1724 * @arg @ref LL_TIM_CHANNEL_CH1N
1725 * @arg @ref LL_TIM_CHANNEL_CH2
1726 * @arg @ref LL_TIM_CHANNEL_CH2N
1727 * @arg @ref LL_TIM_CHANNEL_CH3
1728 * @arg @ref LL_TIM_CHANNEL_CH3N
1729 * @arg @ref LL_TIM_CHANNEL_CH4
1730 * @retval Returned value can be one of the following values:
1731 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1732 * @arg @ref LL_TIM_OCPOLARITY_LOW
1733 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)1734 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
1735 {
1736 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1737 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1738 }
1739
1740 /**
1741 * @brief Set the IDLE state of an output channel
1742 * @note This function is significant only for the timer instances
1743 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
1744 * can be used to check whether or not a timer instance provides
1745 * a break input.
1746 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1747 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1748 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1749 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1750 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1751 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1752 * CR2 OIS4 LL_TIM_OC_SetIdleState
1753 * @param TIMx Timer instance
1754 * @param Channel This parameter can be one of the following values:
1755 * @arg @ref LL_TIM_CHANNEL_CH1
1756 * @arg @ref LL_TIM_CHANNEL_CH1N
1757 * @arg @ref LL_TIM_CHANNEL_CH2
1758 * @arg @ref LL_TIM_CHANNEL_CH2N
1759 * @arg @ref LL_TIM_CHANNEL_CH3
1760 * @arg @ref LL_TIM_CHANNEL_CH3N
1761 * @arg @ref LL_TIM_CHANNEL_CH4
1762 * @param IdleState This parameter can be one of the following values:
1763 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1764 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1765 * @retval None
1766 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1767 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1768 {
1769 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1770 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1771 }
1772
1773 /**
1774 * @brief Get the IDLE state of an output channel
1775 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1776 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1777 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1778 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1779 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1780 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1781 * CR2 OIS4 LL_TIM_OC_GetIdleState
1782 * @param TIMx Timer instance
1783 * @param Channel This parameter can be one of the following values:
1784 * @arg @ref LL_TIM_CHANNEL_CH1
1785 * @arg @ref LL_TIM_CHANNEL_CH1N
1786 * @arg @ref LL_TIM_CHANNEL_CH2
1787 * @arg @ref LL_TIM_CHANNEL_CH2N
1788 * @arg @ref LL_TIM_CHANNEL_CH3
1789 * @arg @ref LL_TIM_CHANNEL_CH3N
1790 * @arg @ref LL_TIM_CHANNEL_CH4
1791 * @retval Returned value can be one of the following values:
1792 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1793 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1794 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)1795 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
1796 {
1797 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1798 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1799 }
1800
1801 /**
1802 * @brief Enable fast mode for the output channel.
1803 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1804 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1805 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1806 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1807 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1808 * @param TIMx Timer instance
1809 * @param Channel This parameter can be one of the following values:
1810 * @arg @ref LL_TIM_CHANNEL_CH1
1811 * @arg @ref LL_TIM_CHANNEL_CH2
1812 * @arg @ref LL_TIM_CHANNEL_CH3
1813 * @arg @ref LL_TIM_CHANNEL_CH4
1814 * @retval None
1815 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1816 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1817 {
1818 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1819 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1820 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1821
1822 }
1823
1824 /**
1825 * @brief Disable fast mode for the output channel.
1826 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1827 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1828 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1829 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1830 * @param TIMx Timer instance
1831 * @param Channel This parameter can be one of the following values:
1832 * @arg @ref LL_TIM_CHANNEL_CH1
1833 * @arg @ref LL_TIM_CHANNEL_CH2
1834 * @arg @ref LL_TIM_CHANNEL_CH3
1835 * @arg @ref LL_TIM_CHANNEL_CH4
1836 * @retval None
1837 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1838 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1839 {
1840 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1841 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1842 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1843
1844 }
1845
1846 /**
1847 * @brief Indicates whether fast mode is enabled for the output channel.
1848 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1849 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1850 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1851 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1852 * @param TIMx Timer instance
1853 * @param Channel This parameter can be one of the following values:
1854 * @arg @ref LL_TIM_CHANNEL_CH1
1855 * @arg @ref LL_TIM_CHANNEL_CH2
1856 * @arg @ref LL_TIM_CHANNEL_CH3
1857 * @arg @ref LL_TIM_CHANNEL_CH4
1858 * @retval State of bit (1 or 0).
1859 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)1860 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
1861 {
1862 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1863 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1864 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1865 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1866 }
1867
1868 /**
1869 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1870 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1871 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1872 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1873 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1874 * @param TIMx Timer instance
1875 * @param Channel This parameter can be one of the following values:
1876 * @arg @ref LL_TIM_CHANNEL_CH1
1877 * @arg @ref LL_TIM_CHANNEL_CH2
1878 * @arg @ref LL_TIM_CHANNEL_CH3
1879 * @arg @ref LL_TIM_CHANNEL_CH4
1880 * @retval None
1881 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1882 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1883 {
1884 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1885 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1886 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1887 }
1888
1889 /**
1890 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1891 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1892 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1893 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1894 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1895 * @param TIMx Timer instance
1896 * @param Channel This parameter can be one of the following values:
1897 * @arg @ref LL_TIM_CHANNEL_CH1
1898 * @arg @ref LL_TIM_CHANNEL_CH2
1899 * @arg @ref LL_TIM_CHANNEL_CH3
1900 * @arg @ref LL_TIM_CHANNEL_CH4
1901 * @retval None
1902 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1903 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1904 {
1905 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1906 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1907 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1908 }
1909
1910 /**
1911 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1912 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1913 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1914 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1915 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1916 * @param TIMx Timer instance
1917 * @param Channel This parameter can be one of the following values:
1918 * @arg @ref LL_TIM_CHANNEL_CH1
1919 * @arg @ref LL_TIM_CHANNEL_CH2
1920 * @arg @ref LL_TIM_CHANNEL_CH3
1921 * @arg @ref LL_TIM_CHANNEL_CH4
1922 * @retval State of bit (1 or 0).
1923 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)1924 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
1925 {
1926 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1927 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1928 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1929 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
1930 }
1931
1932 /**
1933 * @brief Enable clearing the output channel on an external event.
1934 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1935 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1936 * or not a timer instance can clear the OCxREF signal on an external event.
1937 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
1938 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
1939 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
1940 * CCMR2 OC4CE LL_TIM_OC_EnableClear
1941 * @param TIMx Timer instance
1942 * @param Channel This parameter can be one of the following values:
1943 * @arg @ref LL_TIM_CHANNEL_CH1
1944 * @arg @ref LL_TIM_CHANNEL_CH2
1945 * @arg @ref LL_TIM_CHANNEL_CH3
1946 * @arg @ref LL_TIM_CHANNEL_CH4
1947 * @retval None
1948 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)1949 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1950 {
1951 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1952 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1953 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1954 }
1955
1956 /**
1957 * @brief Disable clearing the output channel on an external event.
1958 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1959 * or not a timer instance can clear the OCxREF signal on an external event.
1960 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
1961 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
1962 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
1963 * CCMR2 OC4CE LL_TIM_OC_DisableClear
1964 * @param TIMx Timer instance
1965 * @param Channel This parameter can be one of the following values:
1966 * @arg @ref LL_TIM_CHANNEL_CH1
1967 * @arg @ref LL_TIM_CHANNEL_CH2
1968 * @arg @ref LL_TIM_CHANNEL_CH3
1969 * @arg @ref LL_TIM_CHANNEL_CH4
1970 * @retval None
1971 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)1972 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1973 {
1974 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1975 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1976 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1977 }
1978
1979 /**
1980 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
1981 * @note This function enables clearing the output channel on an external event.
1982 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1983 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1984 * or not a timer instance can clear the OCxREF signal on an external event.
1985 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
1986 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
1987 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
1988 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
1989 * @param TIMx Timer instance
1990 * @param Channel This parameter can be one of the following values:
1991 * @arg @ref LL_TIM_CHANNEL_CH1
1992 * @arg @ref LL_TIM_CHANNEL_CH2
1993 * @arg @ref LL_TIM_CHANNEL_CH3
1994 * @arg @ref LL_TIM_CHANNEL_CH4
1995 * @retval State of bit (1 or 0).
1996 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)1997 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
1998 {
1999 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2000 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2001 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2002 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2003 }
2004
2005 /**
2006 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2007 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2008 * dead-time insertion feature is supported by a timer instance.
2009 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2010 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2011 * @param TIMx Timer instance
2012 * @param DeadTime between Min_Data=0 and Max_Data=255
2013 * @retval None
2014 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2015 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2016 {
2017 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2018 }
2019
2020 /**
2021 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2022 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2023 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2024 * whether or not a timer instance supports a 32 bits counter.
2025 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2026 * output channel 1 is supported by a timer instance.
2027 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2028 * @param TIMx Timer instance
2029 * @param CompareValue between Min_Data=0 and Max_Data=65535
2030 * @retval None
2031 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2032 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2033 {
2034 WRITE_REG(TIMx->CCR1, CompareValue);
2035 }
2036
2037 /**
2038 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2039 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2040 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2041 * whether or not a timer instance supports a 32 bits counter.
2042 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2043 * output channel 2 is supported by a timer instance.
2044 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2045 * @param TIMx Timer instance
2046 * @param CompareValue between Min_Data=0 and Max_Data=65535
2047 * @retval None
2048 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2049 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2050 {
2051 WRITE_REG(TIMx->CCR2, CompareValue);
2052 }
2053
2054 /**
2055 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2056 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2057 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2058 * whether or not a timer instance supports a 32 bits counter.
2059 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2060 * output channel is supported by a timer instance.
2061 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2062 * @param TIMx Timer instance
2063 * @param CompareValue between Min_Data=0 and Max_Data=65535
2064 * @retval None
2065 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2066 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2067 {
2068 WRITE_REG(TIMx->CCR3, CompareValue);
2069 }
2070
2071 /**
2072 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2073 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2074 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2075 * whether or not a timer instance supports a 32 bits counter.
2076 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2077 * output channel 4 is supported by a timer instance.
2078 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2079 * @param TIMx Timer instance
2080 * @param CompareValue between Min_Data=0 and Max_Data=65535
2081 * @retval None
2082 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2083 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2084 {
2085 WRITE_REG(TIMx->CCR4, CompareValue);
2086 }
2087
2088 /**
2089 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2090 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2091 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2092 * whether or not a timer instance supports a 32 bits counter.
2093 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2094 * output channel 1 is supported by a timer instance.
2095 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2096 * @param TIMx Timer instance
2097 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2098 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)2099 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2100 {
2101 return (uint32_t)(READ_REG(TIMx->CCR1));
2102 }
2103
2104 /**
2105 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2106 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2107 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2108 * whether or not a timer instance supports a 32 bits counter.
2109 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2110 * output channel 2 is supported by a timer instance.
2111 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2112 * @param TIMx Timer instance
2113 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2114 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)2115 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2116 {
2117 return (uint32_t)(READ_REG(TIMx->CCR2));
2118 }
2119
2120 /**
2121 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2122 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2123 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2124 * whether or not a timer instance supports a 32 bits counter.
2125 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2126 * output channel 3 is supported by a timer instance.
2127 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2128 * @param TIMx Timer instance
2129 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2130 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)2131 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2132 {
2133 return (uint32_t)(READ_REG(TIMx->CCR3));
2134 }
2135
2136 /**
2137 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2138 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2139 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2140 * whether or not a timer instance supports a 32 bits counter.
2141 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2142 * output channel 4 is supported by a timer instance.
2143 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2144 * @param TIMx Timer instance
2145 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2146 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)2147 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2148 {
2149 return (uint32_t)(READ_REG(TIMx->CCR4));
2150 }
2151
2152 /**
2153 * @}
2154 */
2155
2156 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2157 * @{
2158 */
2159 /**
2160 * @brief Configure input channel.
2161 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2162 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2163 * CCMR1 IC1F LL_TIM_IC_Config\n
2164 * CCMR1 CC2S LL_TIM_IC_Config\n
2165 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2166 * CCMR1 IC2F LL_TIM_IC_Config\n
2167 * CCMR2 CC3S LL_TIM_IC_Config\n
2168 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2169 * CCMR2 IC3F LL_TIM_IC_Config\n
2170 * CCMR2 CC4S LL_TIM_IC_Config\n
2171 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2172 * CCMR2 IC4F LL_TIM_IC_Config\n
2173 * CCER CC1P LL_TIM_IC_Config\n
2174 * CCER CC1NP LL_TIM_IC_Config\n
2175 * CCER CC2P LL_TIM_IC_Config\n
2176 * CCER CC2NP LL_TIM_IC_Config\n
2177 * CCER CC3P LL_TIM_IC_Config\n
2178 * CCER CC3NP LL_TIM_IC_Config\n
2179 * CCER CC4P LL_TIM_IC_Config\n
2180 * CCER CC4NP LL_TIM_IC_Config
2181 * @param TIMx Timer instance
2182 * @param Channel This parameter can be one of the following values:
2183 * @arg @ref LL_TIM_CHANNEL_CH1
2184 * @arg @ref LL_TIM_CHANNEL_CH2
2185 * @arg @ref LL_TIM_CHANNEL_CH3
2186 * @arg @ref LL_TIM_CHANNEL_CH4
2187 * @param Configuration This parameter must be a combination of all the following values:
2188 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2189 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2190 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2191 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2192 * @retval None
2193 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2194 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2195 {
2196 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2197 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2198 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2199 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2200 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2201 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2202 }
2203
2204 /**
2205 * @brief Set the active input.
2206 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2207 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2208 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2209 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2210 * @param TIMx Timer instance
2211 * @param Channel This parameter can be one of the following values:
2212 * @arg @ref LL_TIM_CHANNEL_CH1
2213 * @arg @ref LL_TIM_CHANNEL_CH2
2214 * @arg @ref LL_TIM_CHANNEL_CH3
2215 * @arg @ref LL_TIM_CHANNEL_CH4
2216 * @param ICActiveInput This parameter can be one of the following values:
2217 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2218 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2219 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2220 * @retval None
2221 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2222 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2223 {
2224 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2225 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2226 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2227 }
2228
2229 /**
2230 * @brief Get the current active input.
2231 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2232 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2233 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2234 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2235 * @param TIMx Timer instance
2236 * @param Channel This parameter can be one of the following values:
2237 * @arg @ref LL_TIM_CHANNEL_CH1
2238 * @arg @ref LL_TIM_CHANNEL_CH2
2239 * @arg @ref LL_TIM_CHANNEL_CH3
2240 * @arg @ref LL_TIM_CHANNEL_CH4
2241 * @retval Returned value can be one of the following values:
2242 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2243 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2244 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2245 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)2246 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2247 {
2248 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2249 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2250 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2251 }
2252
2253 /**
2254 * @brief Set the prescaler of input channel.
2255 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2256 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2257 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2258 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2259 * @param TIMx Timer instance
2260 * @param Channel This parameter can be one of the following values:
2261 * @arg @ref LL_TIM_CHANNEL_CH1
2262 * @arg @ref LL_TIM_CHANNEL_CH2
2263 * @arg @ref LL_TIM_CHANNEL_CH3
2264 * @arg @ref LL_TIM_CHANNEL_CH4
2265 * @param ICPrescaler This parameter can be one of the following values:
2266 * @arg @ref LL_TIM_ICPSC_DIV1
2267 * @arg @ref LL_TIM_ICPSC_DIV2
2268 * @arg @ref LL_TIM_ICPSC_DIV4
2269 * @arg @ref LL_TIM_ICPSC_DIV8
2270 * @retval None
2271 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2272 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2273 {
2274 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2275 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2276 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2277 }
2278
2279 /**
2280 * @brief Get the current prescaler value acting on an input channel.
2281 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2282 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2283 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2284 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2285 * @param TIMx Timer instance
2286 * @param Channel This parameter can be one of the following values:
2287 * @arg @ref LL_TIM_CHANNEL_CH1
2288 * @arg @ref LL_TIM_CHANNEL_CH2
2289 * @arg @ref LL_TIM_CHANNEL_CH3
2290 * @arg @ref LL_TIM_CHANNEL_CH4
2291 * @retval Returned value can be one of the following values:
2292 * @arg @ref LL_TIM_ICPSC_DIV1
2293 * @arg @ref LL_TIM_ICPSC_DIV2
2294 * @arg @ref LL_TIM_ICPSC_DIV4
2295 * @arg @ref LL_TIM_ICPSC_DIV8
2296 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)2297 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2298 {
2299 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2300 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2301 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2302 }
2303
2304 /**
2305 * @brief Set the input filter duration.
2306 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2307 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2308 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2309 * CCMR2 IC4F LL_TIM_IC_SetFilter
2310 * @param TIMx Timer instance
2311 * @param Channel This parameter can be one of the following values:
2312 * @arg @ref LL_TIM_CHANNEL_CH1
2313 * @arg @ref LL_TIM_CHANNEL_CH2
2314 * @arg @ref LL_TIM_CHANNEL_CH3
2315 * @arg @ref LL_TIM_CHANNEL_CH4
2316 * @param ICFilter This parameter can be one of the following values:
2317 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2318 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2319 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2320 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2321 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2322 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2323 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2324 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2325 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2326 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2327 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2328 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2329 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2330 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2331 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2332 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2333 * @retval None
2334 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2335 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2336 {
2337 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2338 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2339 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2340 }
2341
2342 /**
2343 * @brief Get the input filter duration.
2344 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2345 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2346 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2347 * CCMR2 IC4F LL_TIM_IC_GetFilter
2348 * @param TIMx Timer instance
2349 * @param Channel This parameter can be one of the following values:
2350 * @arg @ref LL_TIM_CHANNEL_CH1
2351 * @arg @ref LL_TIM_CHANNEL_CH2
2352 * @arg @ref LL_TIM_CHANNEL_CH3
2353 * @arg @ref LL_TIM_CHANNEL_CH4
2354 * @retval Returned value can be one of the following values:
2355 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2356 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2357 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2358 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2359 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2360 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2361 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2362 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2363 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2364 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2365 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2366 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2367 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2368 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2369 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2370 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2371 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2372 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2373 {
2374 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2375 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2376 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2377 }
2378
2379 /**
2380 * @brief Set the input channel polarity.
2381 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2382 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2383 * CCER CC2P LL_TIM_IC_SetPolarity\n
2384 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2385 * CCER CC3P LL_TIM_IC_SetPolarity\n
2386 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2387 * CCER CC4P LL_TIM_IC_SetPolarity\n
2388 * CCER CC4NP LL_TIM_IC_SetPolarity
2389 * @param TIMx Timer instance
2390 * @param Channel This parameter can be one of the following values:
2391 * @arg @ref LL_TIM_CHANNEL_CH1
2392 * @arg @ref LL_TIM_CHANNEL_CH2
2393 * @arg @ref LL_TIM_CHANNEL_CH3
2394 * @arg @ref LL_TIM_CHANNEL_CH4
2395 * @param ICPolarity This parameter can be one of the following values:
2396 * @arg @ref LL_TIM_IC_POLARITY_RISING
2397 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2398 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2399 * @retval None
2400 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2401 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2402 {
2403 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2404 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2405 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2406 }
2407
2408 /**
2409 * @brief Get the current input channel polarity.
2410 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2411 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2412 * CCER CC2P LL_TIM_IC_GetPolarity\n
2413 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2414 * CCER CC3P LL_TIM_IC_GetPolarity\n
2415 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2416 * CCER CC4P LL_TIM_IC_GetPolarity\n
2417 * CCER CC4NP LL_TIM_IC_GetPolarity
2418 * @param TIMx Timer instance
2419 * @param Channel This parameter can be one of the following values:
2420 * @arg @ref LL_TIM_CHANNEL_CH1
2421 * @arg @ref LL_TIM_CHANNEL_CH2
2422 * @arg @ref LL_TIM_CHANNEL_CH3
2423 * @arg @ref LL_TIM_CHANNEL_CH4
2424 * @retval Returned value can be one of the following values:
2425 * @arg @ref LL_TIM_IC_POLARITY_RISING
2426 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2427 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2428 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2429 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2430 {
2431 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2432 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2433 SHIFT_TAB_CCxP[iChannel]);
2434 }
2435
2436 /**
2437 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2438 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2439 * a timer instance provides an XOR input.
2440 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2441 * @param TIMx Timer instance
2442 * @retval None
2443 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2444 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2445 {
2446 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2447 }
2448
2449 /**
2450 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2451 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2452 * a timer instance provides an XOR input.
2453 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2454 * @param TIMx Timer instance
2455 * @retval None
2456 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2457 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2458 {
2459 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2460 }
2461
2462 /**
2463 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2464 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2465 * a timer instance provides an XOR input.
2466 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2467 * @param TIMx Timer instance
2468 * @retval State of bit (1 or 0).
2469 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)2470 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2471 {
2472 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
2473 }
2474
2475 /**
2476 * @brief Get captured value for input channel 1.
2477 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2478 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2479 * whether or not a timer instance supports a 32 bits counter.
2480 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2481 * input channel 1 is supported by a timer instance.
2482 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2483 * @param TIMx Timer instance
2484 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2485 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)2486 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
2487 {
2488 return (uint32_t)(READ_REG(TIMx->CCR1));
2489 }
2490
2491 /**
2492 * @brief Get captured value for input channel 2.
2493 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2494 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2495 * whether or not a timer instance supports a 32 bits counter.
2496 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2497 * input channel 2 is supported by a timer instance.
2498 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2499 * @param TIMx Timer instance
2500 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2501 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)2502 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
2503 {
2504 return (uint32_t)(READ_REG(TIMx->CCR2));
2505 }
2506
2507 /**
2508 * @brief Get captured value for input channel 3.
2509 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2510 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2511 * whether or not a timer instance supports a 32 bits counter.
2512 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2513 * input channel 3 is supported by a timer instance.
2514 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2515 * @param TIMx Timer instance
2516 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2517 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)2518 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
2519 {
2520 return (uint32_t)(READ_REG(TIMx->CCR3));
2521 }
2522
2523 /**
2524 * @brief Get captured value for input channel 4.
2525 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2526 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2527 * whether or not a timer instance supports a 32 bits counter.
2528 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2529 * input channel 4 is supported by a timer instance.
2530 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2531 * @param TIMx Timer instance
2532 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2533 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)2534 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
2535 {
2536 return (uint32_t)(READ_REG(TIMx->CCR4));
2537 }
2538
2539 /**
2540 * @}
2541 */
2542
2543 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2544 * @{
2545 */
2546 /**
2547 * @brief Enable external clock mode 2.
2548 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2549 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2550 * whether or not a timer instance supports external clock mode2.
2551 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2552 * @param TIMx Timer instance
2553 * @retval None
2554 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2555 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2556 {
2557 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2558 }
2559
2560 /**
2561 * @brief Disable external clock mode 2.
2562 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2563 * whether or not a timer instance supports external clock mode2.
2564 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2565 * @param TIMx Timer instance
2566 * @retval None
2567 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2568 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2569 {
2570 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2571 }
2572
2573 /**
2574 * @brief Indicate whether external clock mode 2 is enabled.
2575 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2576 * whether or not a timer instance supports external clock mode2.
2577 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2578 * @param TIMx Timer instance
2579 * @retval State of bit (1 or 0).
2580 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)2581 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
2582 {
2583 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
2584 }
2585
2586 /**
2587 * @brief Set the clock source of the counter clock.
2588 * @note when selected clock source is external clock mode 1, the timer input
2589 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2590 * function. This timer input must be configured by calling
2591 * the @ref LL_TIM_IC_Config() function.
2592 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2593 * whether or not a timer instance supports external clock mode1.
2594 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2595 * whether or not a timer instance supports external clock mode2.
2596 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2597 * SMCR ECE LL_TIM_SetClockSource
2598 * @param TIMx Timer instance
2599 * @param ClockSource This parameter can be one of the following values:
2600 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2601 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2602 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2603 * @retval None
2604 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2605 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2606 {
2607 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2608 }
2609
2610 /**
2611 * @brief Set the encoder interface mode.
2612 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2613 * whether or not a timer instance supports the encoder mode.
2614 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2615 * @param TIMx Timer instance
2616 * @param EncoderMode This parameter can be one of the following values:
2617 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2618 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2619 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2620 * @retval None
2621 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2622 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2623 {
2624 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2625 }
2626
2627 /**
2628 * @}
2629 */
2630
2631 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2632 * @{
2633 */
2634 /**
2635 * @brief Set the trigger output (TRGO) used for timer synchronization .
2636 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2637 * whether or not a timer instance can operate as a master timer.
2638 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2639 * @param TIMx Timer instance
2640 * @param TimerSynchronization This parameter can be one of the following values:
2641 * @arg @ref LL_TIM_TRGO_RESET
2642 * @arg @ref LL_TIM_TRGO_ENABLE
2643 * @arg @ref LL_TIM_TRGO_UPDATE
2644 * @arg @ref LL_TIM_TRGO_CC1IF
2645 * @arg @ref LL_TIM_TRGO_OC1REF
2646 * @arg @ref LL_TIM_TRGO_OC2REF
2647 * @arg @ref LL_TIM_TRGO_OC3REF
2648 * @arg @ref LL_TIM_TRGO_OC4REF
2649 * @retval None
2650 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2651 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2652 {
2653 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2654 }
2655
2656 /**
2657 * @brief Set the synchronization mode of a slave timer.
2658 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2659 * a timer instance can operate as a slave timer.
2660 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2661 * @param TIMx Timer instance
2662 * @param SlaveMode This parameter can be one of the following values:
2663 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2664 * @arg @ref LL_TIM_SLAVEMODE_RESET
2665 * @arg @ref LL_TIM_SLAVEMODE_GATED
2666 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2667 * @retval None
2668 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2669 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2670 {
2671 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2672 }
2673
2674 /**
2675 * @brief Set the selects the trigger input to be used to synchronize the counter.
2676 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2677 * a timer instance can operate as a slave timer.
2678 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2679 * @param TIMx Timer instance
2680 * @param TriggerInput This parameter can be one of the following values:
2681 * @arg @ref LL_TIM_TS_ITR0
2682 * @arg @ref LL_TIM_TS_ITR1
2683 * @arg @ref LL_TIM_TS_ITR2
2684 * @arg @ref LL_TIM_TS_ITR3
2685 * @arg @ref LL_TIM_TS_TI1F_ED
2686 * @arg @ref LL_TIM_TS_TI1FP1
2687 * @arg @ref LL_TIM_TS_TI2FP2
2688 * @arg @ref LL_TIM_TS_ETRF
2689 * @retval None
2690 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2691 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2692 {
2693 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2694 }
2695
2696 /**
2697 * @brief Enable the Master/Slave mode.
2698 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2699 * a timer instance can operate as a slave timer.
2700 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2701 * @param TIMx Timer instance
2702 * @retval None
2703 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2704 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2705 {
2706 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2707 }
2708
2709 /**
2710 * @brief Disable the Master/Slave mode.
2711 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2712 * a timer instance can operate as a slave timer.
2713 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2714 * @param TIMx Timer instance
2715 * @retval None
2716 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2717 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2718 {
2719 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2720 }
2721
2722 /**
2723 * @brief Indicates whether the Master/Slave mode is enabled.
2724 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2725 * a timer instance can operate as a slave timer.
2726 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2727 * @param TIMx Timer instance
2728 * @retval State of bit (1 or 0).
2729 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)2730 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
2731 {
2732 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
2733 }
2734
2735 /**
2736 * @brief Configure the external trigger (ETR) input.
2737 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2738 * a timer instance provides an external trigger input.
2739 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2740 * SMCR ETPS LL_TIM_ConfigETR\n
2741 * SMCR ETF LL_TIM_ConfigETR
2742 * @param TIMx Timer instance
2743 * @param ETRPolarity This parameter can be one of the following values:
2744 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2745 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2746 * @param ETRPrescaler This parameter can be one of the following values:
2747 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2748 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2749 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2750 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2751 * @param ETRFilter This parameter can be one of the following values:
2752 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2753 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2754 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2755 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2756 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2757 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2758 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2759 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2760 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2761 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2762 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2763 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2764 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2765 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2766 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2767 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2768 * @retval None
2769 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2770 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2771 uint32_t ETRFilter)
2772 {
2773 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2774 }
2775
2776 /**
2777 * @}
2778 */
2779
2780 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2781 * @{
2782 */
2783 /**
2784 * @brief Enable the break function.
2785 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2786 * a timer instance provides a break input.
2787 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2788 * @param TIMx Timer instance
2789 * @retval None
2790 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2791 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2792 {
2793 __IO uint32_t tmpreg;
2794 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2795 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2796 tmpreg = READ_REG(TIMx->BDTR);
2797 (void)(tmpreg);
2798 }
2799
2800 /**
2801 * @brief Disable the break function.
2802 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2803 * @param TIMx Timer instance
2804 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2805 * a timer instance provides a break input.
2806 * @retval None
2807 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2808 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2809 {
2810 __IO uint32_t tmpreg;
2811 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2812 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2813 tmpreg = READ_REG(TIMx->BDTR);
2814 (void)(tmpreg);
2815 }
2816
2817 /**
2818 * @brief Configure the break input.
2819 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2820 * a timer instance provides a break input.
2821 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2822 * @param TIMx Timer instance
2823 * @param BreakPolarity This parameter can be one of the following values:
2824 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2825 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2826 * @retval None
2827 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2828 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2829 {
2830 __IO uint32_t tmpreg;
2831 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2832 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
2833 tmpreg = READ_REG(TIMx->BDTR);
2834 (void)(tmpreg);
2835 }
2836
2837 /**
2838 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2839 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2840 * a timer instance provides a break input.
2841 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2842 * BDTR OSSR LL_TIM_SetOffStates
2843 * @param TIMx Timer instance
2844 * @param OffStateIdle This parameter can be one of the following values:
2845 * @arg @ref LL_TIM_OSSI_DISABLE
2846 * @arg @ref LL_TIM_OSSI_ENABLE
2847 * @param OffStateRun This parameter can be one of the following values:
2848 * @arg @ref LL_TIM_OSSR_DISABLE
2849 * @arg @ref LL_TIM_OSSR_ENABLE
2850 * @retval None
2851 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2852 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2853 {
2854 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2855 }
2856
2857 /**
2858 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2859 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2860 * a timer instance provides a break input.
2861 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2862 * @param TIMx Timer instance
2863 * @retval None
2864 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2865 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2866 {
2867 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2868 }
2869
2870 /**
2871 * @brief Disable automatic output (MOE can be set only by software).
2872 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2873 * a timer instance provides a break input.
2874 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2875 * @param TIMx Timer instance
2876 * @retval None
2877 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2878 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2879 {
2880 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2881 }
2882
2883 /**
2884 * @brief Indicate whether automatic output is enabled.
2885 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2886 * a timer instance provides a break input.
2887 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2888 * @param TIMx Timer instance
2889 * @retval State of bit (1 or 0).
2890 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)2891 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
2892 {
2893 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
2894 }
2895
2896 /**
2897 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2898 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2899 * software and is reset in case of break or break2 event
2900 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2901 * a timer instance provides a break input.
2902 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2903 * @param TIMx Timer instance
2904 * @retval None
2905 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2906 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2907 {
2908 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2909 }
2910
2911 /**
2912 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
2913 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2914 * software and is reset in case of break or break2 event.
2915 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2916 * a timer instance provides a break input.
2917 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
2918 * @param TIMx Timer instance
2919 * @retval None
2920 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)2921 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
2922 {
2923 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2924 }
2925
2926 /**
2927 * @brief Indicates whether outputs are enabled.
2928 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2929 * a timer instance provides a break input.
2930 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
2931 * @param TIMx Timer instance
2932 * @retval State of bit (1 or 0).
2933 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)2934 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
2935 {
2936 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
2937 }
2938
2939 /**
2940 * @}
2941 */
2942
2943 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
2944 * @{
2945 */
2946 /**
2947 * @brief Configures the timer DMA burst feature.
2948 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2949 * not a timer instance supports the DMA burst mode.
2950 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
2951 * DCR DBA LL_TIM_ConfigDMABurst
2952 * @param TIMx Timer instance
2953 * @param DMABurstBaseAddress This parameter can be one of the following values:
2954 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
2955 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
2956 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
2957 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
2958 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
2959 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
2960 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
2961 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
2962 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
2963 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
2964 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
2965 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
2966 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
2967 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
2968 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
2969 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
2970 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
2971 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
2972 * @param DMABurstLength This parameter can be one of the following values:
2973 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
2974 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
2975 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
2976 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
2977 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
2978 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
2979 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
2980 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
2981 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
2982 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
2983 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
2984 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
2985 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
2986 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
2987 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
2988 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
2989 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
2990 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
2991 * @retval None
2992 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)2993 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
2994 {
2995 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
2996 }
2997
2998 /**
2999 * @}
3000 */
3001
3002 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3003 * @{
3004 */
3005 /**
3006 * @brief Remap TIM inputs (input channel, internal/external triggers).
3007 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3008 * a some timer inputs can be remapped.
3009 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3010 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3011 * TIM11_OR TI1_RMP LL_TIM_SetRemap
3012 * @param TIMx Timer instance
3013 * @param Remap Remap param depends on the TIMx. Description available only
3014 * in CHM version of the User Manual (not in .pdf).
3015 * Otherwise see Reference Manual description of OR registers.
3016 *
3017 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3018 *
3019 * TIM2: one of the following values
3020 *
3021 * ITR1_RMP can be one of the following values
3022 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3023 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3024 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3025 *
3026 * TIM5: one of the following values
3027 *
3028 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3029 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3030 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3031 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3032 *
3033 * TIM11: one of the following values
3034 *
3035 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3036 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*)
3037 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
3038 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
3039 * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*)
3040 *
3041 * (*) Value not defined in all devices. \n
3042 *
3043 * @retval None
3044 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3045 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3046 {
3047 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3048 }
3049
3050 /**
3051 * @}
3052 */
3053
3054 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3055 * @{
3056 */
3057 /**
3058 * @brief Clear the update interrupt flag (UIF).
3059 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3060 * @param TIMx Timer instance
3061 * @retval None
3062 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3063 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3064 {
3065 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3066 }
3067
3068 /**
3069 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3070 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3071 * @param TIMx Timer instance
3072 * @retval State of bit (1 or 0).
3073 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)3074 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3075 {
3076 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
3077 }
3078
3079 /**
3080 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3081 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3082 * @param TIMx Timer instance
3083 * @retval None
3084 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3085 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3086 {
3087 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3088 }
3089
3090 /**
3091 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3092 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3093 * @param TIMx Timer instance
3094 * @retval State of bit (1 or 0).
3095 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)3096 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3097 {
3098 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
3099 }
3100
3101 /**
3102 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3103 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3104 * @param TIMx Timer instance
3105 * @retval None
3106 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3107 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3108 {
3109 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3110 }
3111
3112 /**
3113 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3114 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3115 * @param TIMx Timer instance
3116 * @retval State of bit (1 or 0).
3117 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)3118 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3119 {
3120 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
3121 }
3122
3123 /**
3124 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3125 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3126 * @param TIMx Timer instance
3127 * @retval None
3128 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3129 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3130 {
3131 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3132 }
3133
3134 /**
3135 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3136 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3137 * @param TIMx Timer instance
3138 * @retval State of bit (1 or 0).
3139 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)3140 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
3141 {
3142 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
3143 }
3144
3145 /**
3146 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3147 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3148 * @param TIMx Timer instance
3149 * @retval None
3150 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3151 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3152 {
3153 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3154 }
3155
3156 /**
3157 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3158 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3159 * @param TIMx Timer instance
3160 * @retval State of bit (1 or 0).
3161 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)3162 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
3163 {
3164 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
3165 }
3166
3167 /**
3168 * @brief Clear the commutation interrupt flag (COMIF).
3169 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3170 * @param TIMx Timer instance
3171 * @retval None
3172 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3173 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3174 {
3175 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3176 }
3177
3178 /**
3179 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3180 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3181 * @param TIMx Timer instance
3182 * @retval State of bit (1 or 0).
3183 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)3184 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
3185 {
3186 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
3187 }
3188
3189 /**
3190 * @brief Clear the trigger interrupt flag (TIF).
3191 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3192 * @param TIMx Timer instance
3193 * @retval None
3194 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3195 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3196 {
3197 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3198 }
3199
3200 /**
3201 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3202 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3203 * @param TIMx Timer instance
3204 * @retval State of bit (1 or 0).
3205 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)3206 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
3207 {
3208 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
3209 }
3210
3211 /**
3212 * @brief Clear the break interrupt flag (BIF).
3213 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3214 * @param TIMx Timer instance
3215 * @retval None
3216 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3217 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3218 {
3219 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3220 }
3221
3222 /**
3223 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3224 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3225 * @param TIMx Timer instance
3226 * @retval State of bit (1 or 0).
3227 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)3228 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
3229 {
3230 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
3231 }
3232
3233 /**
3234 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3235 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3236 * @param TIMx Timer instance
3237 * @retval None
3238 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3239 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3240 {
3241 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3242 }
3243
3244 /**
3245 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
3246 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3247 * @param TIMx Timer instance
3248 * @retval State of bit (1 or 0).
3249 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)3250 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
3251 {
3252 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
3253 }
3254
3255 /**
3256 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3257 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3258 * @param TIMx Timer instance
3259 * @retval None
3260 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3261 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3262 {
3263 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3264 }
3265
3266 /**
3267 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
3268 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3269 * @param TIMx Timer instance
3270 * @retval State of bit (1 or 0).
3271 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)3272 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
3273 {
3274 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
3275 }
3276
3277 /**
3278 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3279 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3280 * @param TIMx Timer instance
3281 * @retval None
3282 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3283 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3284 {
3285 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3286 }
3287
3288 /**
3289 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
3290 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3291 * @param TIMx Timer instance
3292 * @retval State of bit (1 or 0).
3293 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)3294 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
3295 {
3296 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
3297 }
3298
3299 /**
3300 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3301 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3302 * @param TIMx Timer instance
3303 * @retval None
3304 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3305 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3306 {
3307 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3308 }
3309
3310 /**
3311 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
3312 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3313 * @param TIMx Timer instance
3314 * @retval State of bit (1 or 0).
3315 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)3316 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
3317 {
3318 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
3319 }
3320
3321 /**
3322 * @}
3323 */
3324
3325 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3326 * @{
3327 */
3328 /**
3329 * @brief Enable update interrupt (UIE).
3330 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3331 * @param TIMx Timer instance
3332 * @retval None
3333 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3334 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3335 {
3336 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3337 }
3338
3339 /**
3340 * @brief Disable update interrupt (UIE).
3341 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3342 * @param TIMx Timer instance
3343 * @retval None
3344 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3345 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3346 {
3347 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3348 }
3349
3350 /**
3351 * @brief Indicates whether the update interrupt (UIE) is enabled.
3352 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3353 * @param TIMx Timer instance
3354 * @retval State of bit (1 or 0).
3355 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)3356 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
3357 {
3358 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
3359 }
3360
3361 /**
3362 * @brief Enable capture/compare 1 interrupt (CC1IE).
3363 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3364 * @param TIMx Timer instance
3365 * @retval None
3366 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3367 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3368 {
3369 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3370 }
3371
3372 /**
3373 * @brief Disable capture/compare 1 interrupt (CC1IE).
3374 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3375 * @param TIMx Timer instance
3376 * @retval None
3377 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3378 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3379 {
3380 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3381 }
3382
3383 /**
3384 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3385 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3386 * @param TIMx Timer instance
3387 * @retval State of bit (1 or 0).
3388 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)3389 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
3390 {
3391 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
3392 }
3393
3394 /**
3395 * @brief Enable capture/compare 2 interrupt (CC2IE).
3396 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3397 * @param TIMx Timer instance
3398 * @retval None
3399 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3400 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3401 {
3402 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3403 }
3404
3405 /**
3406 * @brief Disable capture/compare 2 interrupt (CC2IE).
3407 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3408 * @param TIMx Timer instance
3409 * @retval None
3410 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3411 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3412 {
3413 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3414 }
3415
3416 /**
3417 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3418 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3419 * @param TIMx Timer instance
3420 * @retval State of bit (1 or 0).
3421 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)3422 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
3423 {
3424 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
3425 }
3426
3427 /**
3428 * @brief Enable capture/compare 3 interrupt (CC3IE).
3429 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3430 * @param TIMx Timer instance
3431 * @retval None
3432 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3433 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3434 {
3435 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3436 }
3437
3438 /**
3439 * @brief Disable capture/compare 3 interrupt (CC3IE).
3440 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3441 * @param TIMx Timer instance
3442 * @retval None
3443 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3444 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3445 {
3446 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3447 }
3448
3449 /**
3450 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3451 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3452 * @param TIMx Timer instance
3453 * @retval State of bit (1 or 0).
3454 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)3455 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
3456 {
3457 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
3458 }
3459
3460 /**
3461 * @brief Enable capture/compare 4 interrupt (CC4IE).
3462 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3463 * @param TIMx Timer instance
3464 * @retval None
3465 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3466 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3467 {
3468 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3469 }
3470
3471 /**
3472 * @brief Disable capture/compare 4 interrupt (CC4IE).
3473 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3474 * @param TIMx Timer instance
3475 * @retval None
3476 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3477 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3478 {
3479 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3480 }
3481
3482 /**
3483 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3484 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3485 * @param TIMx Timer instance
3486 * @retval State of bit (1 or 0).
3487 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)3488 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
3489 {
3490 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
3491 }
3492
3493 /**
3494 * @brief Enable commutation interrupt (COMIE).
3495 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3496 * @param TIMx Timer instance
3497 * @retval None
3498 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3499 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3500 {
3501 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3502 }
3503
3504 /**
3505 * @brief Disable commutation interrupt (COMIE).
3506 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3507 * @param TIMx Timer instance
3508 * @retval None
3509 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3510 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3511 {
3512 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3513 }
3514
3515 /**
3516 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3517 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3518 * @param TIMx Timer instance
3519 * @retval State of bit (1 or 0).
3520 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)3521 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
3522 {
3523 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
3524 }
3525
3526 /**
3527 * @brief Enable trigger interrupt (TIE).
3528 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3529 * @param TIMx Timer instance
3530 * @retval None
3531 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3532 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3533 {
3534 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3535 }
3536
3537 /**
3538 * @brief Disable trigger interrupt (TIE).
3539 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3540 * @param TIMx Timer instance
3541 * @retval None
3542 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3543 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3544 {
3545 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3546 }
3547
3548 /**
3549 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3550 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3551 * @param TIMx Timer instance
3552 * @retval State of bit (1 or 0).
3553 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)3554 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
3555 {
3556 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
3557 }
3558
3559 /**
3560 * @brief Enable break interrupt (BIE).
3561 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3562 * @param TIMx Timer instance
3563 * @retval None
3564 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3565 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3566 {
3567 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3568 }
3569
3570 /**
3571 * @brief Disable break interrupt (BIE).
3572 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3573 * @param TIMx Timer instance
3574 * @retval None
3575 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3576 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3577 {
3578 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3579 }
3580
3581 /**
3582 * @brief Indicates whether the break interrupt (BIE) is enabled.
3583 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3584 * @param TIMx Timer instance
3585 * @retval State of bit (1 or 0).
3586 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)3587 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
3588 {
3589 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
3590 }
3591
3592 /**
3593 * @}
3594 */
3595
3596 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
3597 * @{
3598 */
3599 /**
3600 * @brief Enable update DMA request (UDE).
3601 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3602 * @param TIMx Timer instance
3603 * @retval None
3604 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3605 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3606 {
3607 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3608 }
3609
3610 /**
3611 * @brief Disable update DMA request (UDE).
3612 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3613 * @param TIMx Timer instance
3614 * @retval None
3615 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3616 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3617 {
3618 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3619 }
3620
3621 /**
3622 * @brief Indicates whether the update DMA request (UDE) is enabled.
3623 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3624 * @param TIMx Timer instance
3625 * @retval State of bit (1 or 0).
3626 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)3627 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
3628 {
3629 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
3630 }
3631
3632 /**
3633 * @brief Enable capture/compare 1 DMA request (CC1DE).
3634 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3635 * @param TIMx Timer instance
3636 * @retval None
3637 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3638 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3639 {
3640 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3641 }
3642
3643 /**
3644 * @brief Disable capture/compare 1 DMA request (CC1DE).
3645 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3646 * @param TIMx Timer instance
3647 * @retval None
3648 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3649 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3650 {
3651 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3652 }
3653
3654 /**
3655 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3656 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3657 * @param TIMx Timer instance
3658 * @retval State of bit (1 or 0).
3659 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)3660 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
3661 {
3662 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
3663 }
3664
3665 /**
3666 * @brief Enable capture/compare 2 DMA request (CC2DE).
3667 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3668 * @param TIMx Timer instance
3669 * @retval None
3670 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3671 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3672 {
3673 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3674 }
3675
3676 /**
3677 * @brief Disable capture/compare 2 DMA request (CC2DE).
3678 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3679 * @param TIMx Timer instance
3680 * @retval None
3681 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3682 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3683 {
3684 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3685 }
3686
3687 /**
3688 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3689 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3690 * @param TIMx Timer instance
3691 * @retval State of bit (1 or 0).
3692 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)3693 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
3694 {
3695 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
3696 }
3697
3698 /**
3699 * @brief Enable capture/compare 3 DMA request (CC3DE).
3700 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3701 * @param TIMx Timer instance
3702 * @retval None
3703 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3704 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3705 {
3706 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3707 }
3708
3709 /**
3710 * @brief Disable capture/compare 3 DMA request (CC3DE).
3711 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3712 * @param TIMx Timer instance
3713 * @retval None
3714 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3715 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3716 {
3717 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3718 }
3719
3720 /**
3721 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3722 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3723 * @param TIMx Timer instance
3724 * @retval State of bit (1 or 0).
3725 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)3726 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
3727 {
3728 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
3729 }
3730
3731 /**
3732 * @brief Enable capture/compare 4 DMA request (CC4DE).
3733 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3734 * @param TIMx Timer instance
3735 * @retval None
3736 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3737 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3738 {
3739 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3740 }
3741
3742 /**
3743 * @brief Disable capture/compare 4 DMA request (CC4DE).
3744 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3745 * @param TIMx Timer instance
3746 * @retval None
3747 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3748 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3749 {
3750 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3751 }
3752
3753 /**
3754 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3755 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3756 * @param TIMx Timer instance
3757 * @retval State of bit (1 or 0).
3758 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)3759 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
3760 {
3761 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
3762 }
3763
3764 /**
3765 * @brief Enable commutation DMA request (COMDE).
3766 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3767 * @param TIMx Timer instance
3768 * @retval None
3769 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3770 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3771 {
3772 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3773 }
3774
3775 /**
3776 * @brief Disable commutation DMA request (COMDE).
3777 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3778 * @param TIMx Timer instance
3779 * @retval None
3780 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3781 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3782 {
3783 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3784 }
3785
3786 /**
3787 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3788 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3789 * @param TIMx Timer instance
3790 * @retval State of bit (1 or 0).
3791 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)3792 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
3793 {
3794 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
3795 }
3796
3797 /**
3798 * @brief Enable trigger interrupt (TDE).
3799 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3800 * @param TIMx Timer instance
3801 * @retval None
3802 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3803 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3804 {
3805 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3806 }
3807
3808 /**
3809 * @brief Disable trigger interrupt (TDE).
3810 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3811 * @param TIMx Timer instance
3812 * @retval None
3813 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3814 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3815 {
3816 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3817 }
3818
3819 /**
3820 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3821 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3822 * @param TIMx Timer instance
3823 * @retval State of bit (1 or 0).
3824 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)3825 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
3826 {
3827 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
3828 }
3829
3830 /**
3831 * @}
3832 */
3833
3834 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3835 * @{
3836 */
3837 /**
3838 * @brief Generate an update event.
3839 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3840 * @param TIMx Timer instance
3841 * @retval None
3842 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3843 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3844 {
3845 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3846 }
3847
3848 /**
3849 * @brief Generate Capture/Compare 1 event.
3850 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3851 * @param TIMx Timer instance
3852 * @retval None
3853 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3854 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3855 {
3856 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3857 }
3858
3859 /**
3860 * @brief Generate Capture/Compare 2 event.
3861 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3862 * @param TIMx Timer instance
3863 * @retval None
3864 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3865 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3866 {
3867 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3868 }
3869
3870 /**
3871 * @brief Generate Capture/Compare 3 event.
3872 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3873 * @param TIMx Timer instance
3874 * @retval None
3875 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3876 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3877 {
3878 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3879 }
3880
3881 /**
3882 * @brief Generate Capture/Compare 4 event.
3883 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3884 * @param TIMx Timer instance
3885 * @retval None
3886 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)3887 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3888 {
3889 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3890 }
3891
3892 /**
3893 * @brief Generate commutation event.
3894 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
3895 * @param TIMx Timer instance
3896 * @retval None
3897 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)3898 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
3899 {
3900 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
3901 }
3902
3903 /**
3904 * @brief Generate trigger event.
3905 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3906 * @param TIMx Timer instance
3907 * @retval None
3908 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)3909 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3910 {
3911 SET_BIT(TIMx->EGR, TIM_EGR_TG);
3912 }
3913
3914 /**
3915 * @brief Generate break event.
3916 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
3917 * @param TIMx Timer instance
3918 * @retval None
3919 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)3920 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
3921 {
3922 SET_BIT(TIMx->EGR, TIM_EGR_BG);
3923 }
3924
3925 /**
3926 * @}
3927 */
3928
3929 #if defined(USE_FULL_LL_DRIVER)
3930 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
3931 * @{
3932 */
3933
3934 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
3935 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
3936 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
3937 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3938 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3939 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
3940 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
3941 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3942 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3943 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3944 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3945 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3946 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3947 /**
3948 * @}
3949 */
3950 #endif /* USE_FULL_LL_DRIVER */
3951
3952 /**
3953 * @}
3954 */
3955
3956 /**
3957 * @}
3958 */
3959
3960 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
3961
3962 /**
3963 * @}
3964 */
3965
3966 #ifdef __cplusplus
3967 }
3968 #endif
3969
3970 #endif /* __STM32F4xx_LL_TIM_H */
3971 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3972