1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F4xx_LL_LPTIM_H
22 #define STM32F4xx_LL_LPTIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (LPTIM1)
36
37 /** @defgroup LPTIM_LL LPTIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47 #if defined(USE_FULL_LL_DRIVER)
48 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
49 * @{
50 */
51 /**
52 * @}
53 */
54 #endif /*USE_FULL_LL_DRIVER*/
55
56 /* Exported types ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
59 * @{
60 */
61
62 /**
63 * @brief LPTIM Init structure definition
64 */
65 typedef struct
66 {
67 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
68 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
69
70 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
76
77 uint32_t Waveform; /*!< Specifies the waveform shape.
78 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
79
80 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
81
82 uint32_t Polarity; /*!< Specifies waveform polarity.
83 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
84
85 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
86 } LL_LPTIM_InitTypeDef;
87
88 /**
89 * @}
90 */
91 #endif /* USE_FULL_LL_DRIVER */
92
93 /* Exported constants --------------------------------------------------------*/
94 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
95 * @{
96 */
97
98 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
99 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
100 * @{
101 */
102 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
103 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
104 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
105 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
106 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
107 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
108 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
109 /**
110 * @}
111 */
112
113 /** @defgroup LPTIM_LL_EC_IT IT Defines
114 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
115 * @{
116 */
117 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
118 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
119 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
120 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
121 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
122 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
123 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
124 /**
125 * @}
126 */
127
128 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
129 * @{
130 */
131 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
132 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
133 /**
134 * @}
135 */
136
137 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
138 * @{
139 */
140 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
141 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
142 /**
143 * @}
144 */
145
146 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
147 * @{
148 */
149 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
150 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
151 /**
152 * @}
153 */
154
155 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
156 * @{
157 */
158 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
159 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
160 /**
161 * @}
162 */
163
164 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
165 * @{
166 */
167 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
168 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
169 /**
170 * @}
171 */
172
173 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
174 * @{
175 */
176 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
177 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
178 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
179 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
180 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
181 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
182 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
183 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
184 /**
185 * @}
186 */
187
188 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
189 * @{
190 */
191 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
192 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
193 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
194 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
195 #define LL_LPTIM_TRIG_SOURCE_TIM1_TRGO LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to TIM1*/
196 #define LL_LPTIM_TRIG_SOURCE_TIM5_TRGO (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to TIM5*/
197 /**
198 * @}
199 */
200
201 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
202 * @{
203 */
204 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
205 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
206 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
207 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
208 /**
209 * @}
210 */
211
212 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
213 * @{
214 */
215 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
216 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
217 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
218 /**
219 * @}
220 */
221
222 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
223 * @{
224 */
225 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
226 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
227 /**
228 * @}
229 */
230
231 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
232 * @{
233 */
234 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
235 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
236 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
237 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
238 /**
239 * @}
240 */
241
242 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
243 * @{
244 */
245 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
246 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
247 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
248 /**
249 * @}
250 */
251
252 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
253 * @{
254 */
255 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
256 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
257 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
258 /**
259 * @}
260 */
261 #if defined(LPTIM_OR_OR)
262
263 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
264 * @{
265 */
266 #define LL_LPTIM_INPUT1_SRC_PAD_AF 0x00000000U
267 #define LL_LPTIM_INPUT1_SRC_PAD_PA4 LPTIM_OR_OR_0
268 #define LL_LPTIM_INPUT1_SRC_PAD_PB9 LPTIM_OR_OR_1
269 #define LL_LPTIM_INPUT1_SRC_TIM_DAC LPTIM_OR_OR
270 /**
271 * @}
272 */
273 #endif /* LPTIM_OR_OR */
274
275 /**
276 * @}
277 */
278
279 /* Exported macro ------------------------------------------------------------*/
280 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
281 * @{
282 */
283
284 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
285 * @{
286 */
287
288 /**
289 * @brief Write a value in LPTIM register
290 * @param __INSTANCE__ LPTIM Instance
291 * @param __REG__ Register to be written
292 * @param __VALUE__ Value to be written in the register
293 * @retval None
294 */
295 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
296
297 /**
298 * @brief Read a value in LPTIM register
299 * @param __INSTANCE__ LPTIM Instance
300 * @param __REG__ Register to be read
301 * @retval Register value
302 */
303 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
304 /**
305 * @}
306 */
307
308 /**
309 * @}
310 */
311
312 /* Exported functions --------------------------------------------------------*/
313 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
314 * @{
315 */
316
317 #if defined(USE_FULL_LL_DRIVER)
318 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
319 * @{
320 */
321
322 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
323 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
324 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
325 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
326 /**
327 * @}
328 */
329 #endif /* USE_FULL_LL_DRIVER */
330
331 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
332 * @{
333 */
334
335 /**
336 * @brief Enable the LPTIM instance
337 * @note After setting the ENABLE bit, a delay of two counter clock is needed
338 * before the LPTIM instance is actually enabled.
339 * @rmtoll CR ENABLE LL_LPTIM_Enable
340 * @param LPTIMx Low-Power Timer instance
341 * @retval None
342 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)343 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
344 {
345 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
346 }
347
348 /**
349 * @brief Indicates whether the LPTIM instance is enabled.
350 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
351 * @param LPTIMx Low-Power Timer instance
352 * @retval State of bit (1 or 0).
353 */
LL_LPTIM_IsEnabled(LPTIM_TypeDef * LPTIMx)354 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
355 {
356 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
357 }
358
359 /**
360 * @brief Starts the LPTIM counter in the desired mode.
361 * @note LPTIM instance must be enabled before starting the counter.
362 * @note It is possible to change on the fly from One Shot mode to
363 * Continuous mode.
364 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
365 * CR SNGSTRT LL_LPTIM_StartCounter
366 * @param LPTIMx Low-Power Timer instance
367 * @param OperatingMode This parameter can be one of the following values:
368 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
369 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
370 * @retval None
371 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)372 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
373 {
374 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
375 }
376
377 /**
378 * @brief Set the LPTIM registers update mode (enable/disable register preload)
379 * @note This function must be called when the LPTIM instance is disabled.
380 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
381 * @param LPTIMx Low-Power Timer instance
382 * @param UpdateMode This parameter can be one of the following values:
383 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
384 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
385 * @retval None
386 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)387 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
388 {
389 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
390 }
391
392 /**
393 * @brief Get the LPTIM registers update mode
394 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
395 * @param LPTIMx Low-Power Timer instance
396 * @retval Returned value can be one of the following values:
397 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
398 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
399 */
LL_LPTIM_GetUpdateMode(LPTIM_TypeDef * LPTIMx)400 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
401 {
402 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
403 }
404
405 /**
406 * @brief Set the auto reload value
407 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
408 * @note After a write to the LPTIMx_ARR register a new write operation to the
409 * same register can only be performed when the previous write operation
410 * is completed. Any successive write before the ARROK flag is set, will
411 * lead to unpredictable results.
412 * @note autoreload value be strictly greater than the compare value.
413 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
414 * @param LPTIMx Low-Power Timer instance
415 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
416 * @retval None
417 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)418 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
419 {
420 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
421 }
422
423 /**
424 * @brief Get actual auto reload value
425 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
426 * @param LPTIMx Low-Power Timer instance
427 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
428 */
LL_LPTIM_GetAutoReload(LPTIM_TypeDef * LPTIMx)429 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
430 {
431 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
432 }
433
434 /**
435 * @brief Set the compare value
436 * @note After a write to the LPTIMx_CMP register a new write operation to the
437 * same register can only be performed when the previous write operation
438 * is completed. Any successive write before the CMPOK flag is set, will
439 * lead to unpredictable results.
440 * @rmtoll CMP CMP LL_LPTIM_SetCompare
441 * @param LPTIMx Low-Power Timer instance
442 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
443 * @retval None
444 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)445 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
446 {
447 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
448 }
449
450 /**
451 * @brief Get actual compare value
452 * @rmtoll CMP CMP LL_LPTIM_GetCompare
453 * @param LPTIMx Low-Power Timer instance
454 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
455 */
LL_LPTIM_GetCompare(LPTIM_TypeDef * LPTIMx)456 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
457 {
458 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
459 }
460
461 /**
462 * @brief Get actual counter value
463 * @note When the LPTIM instance is running with an asynchronous clock, reading
464 * the LPTIMx_CNT register may return unreliable values. So in this case
465 * it is necessary to perform two consecutive read accesses and verify
466 * that the two returned values are identical.
467 * @rmtoll CNT CNT LL_LPTIM_GetCounter
468 * @param LPTIMx Low-Power Timer instance
469 * @retval Counter value
470 */
LL_LPTIM_GetCounter(LPTIM_TypeDef * LPTIMx)471 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
472 {
473 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
474 }
475
476 /**
477 * @brief Set the counter mode (selection of the LPTIM counter clock source).
478 * @note The counter mode can be set only when the LPTIM instance is disabled.
479 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
480 * @param LPTIMx Low-Power Timer instance
481 * @param CounterMode This parameter can be one of the following values:
482 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
483 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
484 * @retval None
485 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)486 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
487 {
488 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
489 }
490
491 /**
492 * @brief Get the counter mode
493 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
494 * @param LPTIMx Low-Power Timer instance
495 * @retval Returned value can be one of the following values:
496 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
497 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
498 */
LL_LPTIM_GetCounterMode(LPTIM_TypeDef * LPTIMx)499 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
500 {
501 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
502 }
503
504 /**
505 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
506 * @note This function must be called when the LPTIM instance is disabled.
507 * @note Regarding the LPTIM output polarity the change takes effect
508 * immediately, so the output default value will change immediately after
509 * the polarity is re-configured, even before the timer is enabled.
510 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
511 * CFGR WAVPOL LL_LPTIM_ConfigOutput
512 * @param LPTIMx Low-Power Timer instance
513 * @param Waveform This parameter can be one of the following values:
514 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
515 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
516 * @param Polarity This parameter can be one of the following values:
517 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
518 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
519 * @retval None
520 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)521 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
522 {
523 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
524 }
525
526 /**
527 * @brief Set waveform shape
528 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
529 * @param LPTIMx Low-Power Timer instance
530 * @param Waveform This parameter can be one of the following values:
531 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
532 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
533 * @retval None
534 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)535 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
536 {
537 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
538 }
539
540 /**
541 * @brief Get actual waveform shape
542 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
543 * @param LPTIMx Low-Power Timer instance
544 * @retval Returned value can be one of the following values:
545 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
546 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
547 */
LL_LPTIM_GetWaveform(LPTIM_TypeDef * LPTIMx)548 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
549 {
550 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
551 }
552
553 /**
554 * @brief Set output polarity
555 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
556 * @param LPTIMx Low-Power Timer instance
557 * @param Polarity This parameter can be one of the following values:
558 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
559 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
560 * @retval None
561 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)562 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
563 {
564 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
565 }
566
567 /**
568 * @brief Get actual output polarity
569 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
570 * @param LPTIMx Low-Power Timer instance
571 * @retval Returned value can be one of the following values:
572 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
573 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
574 */
LL_LPTIM_GetPolarity(LPTIM_TypeDef * LPTIMx)575 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
576 {
577 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
578 }
579
580 /**
581 * @brief Set actual prescaler division ratio.
582 * @note This function must be called when the LPTIM instance is disabled.
583 * @note When the LPTIM is configured to be clocked by an internal clock source
584 * and the LPTIM counter is configured to be updated by active edges
585 * detected on the LPTIM external Input1, the internal clock provided to
586 * the LPTIM must be not be prescaled.
587 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
588 * @param LPTIMx Low-Power Timer instance
589 * @param Prescaler This parameter can be one of the following values:
590 * @arg @ref LL_LPTIM_PRESCALER_DIV1
591 * @arg @ref LL_LPTIM_PRESCALER_DIV2
592 * @arg @ref LL_LPTIM_PRESCALER_DIV4
593 * @arg @ref LL_LPTIM_PRESCALER_DIV8
594 * @arg @ref LL_LPTIM_PRESCALER_DIV16
595 * @arg @ref LL_LPTIM_PRESCALER_DIV32
596 * @arg @ref LL_LPTIM_PRESCALER_DIV64
597 * @arg @ref LL_LPTIM_PRESCALER_DIV128
598 * @retval None
599 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)600 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
601 {
602 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
603 }
604
605 /**
606 * @brief Get actual prescaler division ratio.
607 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
608 * @param LPTIMx Low-Power Timer instance
609 * @retval Returned value can be one of the following values:
610 * @arg @ref LL_LPTIM_PRESCALER_DIV1
611 * @arg @ref LL_LPTIM_PRESCALER_DIV2
612 * @arg @ref LL_LPTIM_PRESCALER_DIV4
613 * @arg @ref LL_LPTIM_PRESCALER_DIV8
614 * @arg @ref LL_LPTIM_PRESCALER_DIV16
615 * @arg @ref LL_LPTIM_PRESCALER_DIV32
616 * @arg @ref LL_LPTIM_PRESCALER_DIV64
617 * @arg @ref LL_LPTIM_PRESCALER_DIV128
618 */
LL_LPTIM_GetPrescaler(LPTIM_TypeDef * LPTIMx)619 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
620 {
621 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
622 }
623 #if defined(LPTIM_OR_OR)
624
625 /**
626 * @brief Set LPTIM input 1 source (default GPIO).
627 * @rmtoll OR OR LL_LPTIM_SetInput1Src
628 * @param LPTIMx Low-Power Timer instance
629 * @param Src This parameter can be one of the following values:
630 * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_AF
631 * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PA4
632 * @arg @ref LL_LPTIM_INPUT1_SRC_PAD_PB9
633 * @arg @ref LL_LPTIM_INPUT1_SRC_TIM_DAC
634 * @retval None
635 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)636 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
637 {
638 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
639 }
640 #endif /* LPTIM_OR_OR */
641
642 /**
643 * @}
644 */
645
646 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
647 * @{
648 */
649
650 /**
651 * @brief Enable the timeout function
652 * @note This function must be called when the LPTIM instance is disabled.
653 * @note The first trigger event will start the timer, any successive trigger
654 * event will reset the counter and the timer will restart.
655 * @note The timeout value corresponds to the compare value; if no trigger
656 * occurs within the expected time frame, the MCU is waked-up by the
657 * compare match event.
658 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
659 * @param LPTIMx Low-Power Timer instance
660 * @retval None
661 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)662 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
663 {
664 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
665 }
666
667 /**
668 * @brief Disable the timeout function
669 * @note This function must be called when the LPTIM instance is disabled.
670 * @note A trigger event arriving when the timer is already started will be
671 * ignored.
672 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
673 * @param LPTIMx Low-Power Timer instance
674 * @retval None
675 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)676 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
677 {
678 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
679 }
680
681 /**
682 * @brief Indicate whether the timeout function is enabled.
683 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
684 * @param LPTIMx Low-Power Timer instance
685 * @retval State of bit (1 or 0).
686 */
LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef * LPTIMx)687 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
688 {
689 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
690 }
691
692 /**
693 * @brief Start the LPTIM counter
694 * @note This function must be called when the LPTIM instance is disabled.
695 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
696 * @param LPTIMx Low-Power Timer instance
697 * @retval None
698 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)699 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
700 {
701 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
702 }
703
704 /**
705 * @brief Configure the external trigger used as a trigger event for the LPTIM.
706 * @note This function must be called when the LPTIM instance is disabled.
707 * @note An internal clock source must be present when a digital filter is
708 * required for the trigger.
709 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
710 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
711 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
712 * @param LPTIMx Low-Power Timer instance
713 * @param Source This parameter can be one of the following values:
714 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
715 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
716 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
717 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
718 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO
719 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO
720 * @param Filter This parameter can be one of the following values:
721 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
722 * @arg @ref LL_LPTIM_TRIG_FILTER_2
723 * @arg @ref LL_LPTIM_TRIG_FILTER_4
724 * @arg @ref LL_LPTIM_TRIG_FILTER_8
725 * @param Polarity This parameter can be one of the following values:
726 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
727 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
728 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
729 * @retval None
730 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)731 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
732 {
733 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
734 }
735
736 /**
737 * @brief Get actual external trigger source.
738 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
739 * @param LPTIMx Low-Power Timer instance
740 * @retval Returned value can be one of the following values:
741 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
742 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
743 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
744 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
745 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO
746 * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO
747 */
LL_LPTIM_GetTriggerSource(LPTIM_TypeDef * LPTIMx)748 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
749 {
750 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
751 }
752
753 /**
754 * @brief Get actual external trigger filter.
755 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
756 * @param LPTIMx Low-Power Timer instance
757 * @retval Returned value can be one of the following values:
758 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
759 * @arg @ref LL_LPTIM_TRIG_FILTER_2
760 * @arg @ref LL_LPTIM_TRIG_FILTER_4
761 * @arg @ref LL_LPTIM_TRIG_FILTER_8
762 */
LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef * LPTIMx)763 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
764 {
765 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
766 }
767
768 /**
769 * @brief Get actual external trigger polarity.
770 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
771 * @param LPTIMx Low-Power Timer instance
772 * @retval Returned value can be one of the following values:
773 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
774 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
775 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
776 */
LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef * LPTIMx)777 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
778 {
779 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
780 }
781
782 /**
783 * @}
784 */
785
786 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
787 * @{
788 */
789
790 /**
791 * @brief Set the source of the clock used by the LPTIM instance.
792 * @note This function must be called when the LPTIM instance is disabled.
793 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
794 * @param LPTIMx Low-Power Timer instance
795 * @param ClockSource This parameter can be one of the following values:
796 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
797 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
798 * @retval None
799 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)800 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
801 {
802 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
803 }
804
805 /**
806 * @brief Get actual LPTIM instance clock source.
807 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
808 * @param LPTIMx Low-Power Timer instance
809 * @retval Returned value can be one of the following values:
810 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
811 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
812 */
LL_LPTIM_GetClockSource(LPTIM_TypeDef * LPTIMx)813 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
814 {
815 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
816 }
817
818 /**
819 * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
820 * @note This function must be called when the LPTIM instance is disabled.
821 * @note When both external clock signal edges are considered active ones,
822 * the LPTIM must also be clocked by an internal clock source with a
823 * frequency equal to at least four times the external clock frequency.
824 * @note An internal clock source must be present when a digital filter is
825 * required for external clock.
826 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
827 * CFGR CKPOL LL_LPTIM_ConfigClock
828 * @param LPTIMx Low-Power Timer instance
829 * @param ClockFilter This parameter can be one of the following values:
830 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
831 * @arg @ref LL_LPTIM_CLK_FILTER_2
832 * @arg @ref LL_LPTIM_CLK_FILTER_4
833 * @arg @ref LL_LPTIM_CLK_FILTER_8
834 * @param ClockPolarity This parameter can be one of the following values:
835 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
836 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
837 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
838 * @retval None
839 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)840 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
841 {
842 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
843 }
844
845 /**
846 * @brief Get actual clock polarity
847 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
848 * @param LPTIMx Low-Power Timer instance
849 * @retval Returned value can be one of the following values:
850 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
851 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
852 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
853 */
LL_LPTIM_GetClockPolarity(LPTIM_TypeDef * LPTIMx)854 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
855 {
856 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
857 }
858
859 /**
860 * @brief Get actual clock digital filter
861 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
862 * @param LPTIMx Low-Power Timer instance
863 * @retval Returned value can be one of the following values:
864 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
865 * @arg @ref LL_LPTIM_CLK_FILTER_2
866 * @arg @ref LL_LPTIM_CLK_FILTER_4
867 * @arg @ref LL_LPTIM_CLK_FILTER_8
868 */
LL_LPTIM_GetClockFilter(LPTIM_TypeDef * LPTIMx)869 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
870 {
871 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
872 }
873
874 /**
875 * @}
876 */
877
878 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
879 * @{
880 */
881
882 /**
883 * @brief Configure the encoder mode.
884 * @note This function must be called when the LPTIM instance is disabled.
885 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
886 * @param LPTIMx Low-Power Timer instance
887 * @param EncoderMode This parameter can be one of the following values:
888 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
889 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
890 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
891 * @retval None
892 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)893 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
894 {
895 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
896 }
897
898 /**
899 * @brief Get actual encoder mode.
900 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
901 * @param LPTIMx Low-Power Timer instance
902 * @retval Returned value can be one of the following values:
903 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
904 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
905 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
906 */
LL_LPTIM_GetEncoderMode(LPTIM_TypeDef * LPTIMx)907 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
908 {
909 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
910 }
911
912 /**
913 * @brief Enable the encoder mode
914 * @note This function must be called when the LPTIM instance is disabled.
915 * @note In this mode the LPTIM instance must be clocked by an internal clock
916 * source. Also, the prescaler division ratio must be equal to 1.
917 * @note LPTIM instance must be configured in continuous mode prior enabling
918 * the encoder mode.
919 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
920 * @param LPTIMx Low-Power Timer instance
921 * @retval None
922 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)923 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
924 {
925 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
926 }
927
928 /**
929 * @brief Disable the encoder mode
930 * @note This function must be called when the LPTIM instance is disabled.
931 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
932 * @param LPTIMx Low-Power Timer instance
933 * @retval None
934 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)935 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
936 {
937 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
938 }
939
940 /**
941 * @brief Indicates whether the LPTIM operates in encoder mode.
942 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
943 * @param LPTIMx Low-Power Timer instance
944 * @retval State of bit (1 or 0).
945 */
LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef * LPTIMx)946 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
947 {
948 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
949 }
950
951 /**
952 * @}
953 */
954
955 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
956 * @{
957 */
958
959 /**
960 * @brief Clear the compare match flag (CMPMCF)
961 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
962 * @param LPTIMx Low-Power Timer instance
963 * @retval None
964 */
LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef * LPTIMx)965 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
966 {
967 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
968 }
969
970 /**
971 * @brief Inform application whether a compare match interrupt has occurred.
972 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
973 * @param LPTIMx Low-Power Timer instance
974 * @retval State of bit (1 or 0).
975 */
LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef * LPTIMx)976 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
977 {
978 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
979 }
980
981 /**
982 * @brief Clear the autoreload match flag (ARRMCF)
983 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
984 * @param LPTIMx Low-Power Timer instance
985 * @retval None
986 */
LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef * LPTIMx)987 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
988 {
989 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
990 }
991
992 /**
993 * @brief Inform application whether a autoreload match interrupt has occurred.
994 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
995 * @param LPTIMx Low-Power Timer instance
996 * @retval State of bit (1 or 0).
997 */
LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef * LPTIMx)998 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
999 {
1000 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1001 }
1002
1003 /**
1004 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1005 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1006 * @param LPTIMx Low-Power Timer instance
1007 * @retval None
1008 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1009 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1010 {
1011 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1012 }
1013
1014 /**
1015 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1016 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1017 * @param LPTIMx Low-Power Timer instance
1018 * @retval State of bit (1 or 0).
1019 */
LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1020 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1021 {
1022 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1023 }
1024
1025 /**
1026 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1027 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1028 * @param LPTIMx Low-Power Timer instance
1029 * @retval None
1030 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1031 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1032 {
1033 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1034 }
1035
1036 /**
1037 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
1038 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1039 * @param LPTIMx Low-Power Timer instance
1040 * @retval State of bit (1 or 0).
1041 */
LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1042 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1043 {
1044 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1045 }
1046
1047 /**
1048 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1049 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1050 * @param LPTIMx Low-Power Timer instance
1051 * @retval None
1052 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1053 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1054 {
1055 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1056 }
1057
1058 /**
1059 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
1060 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1061 * @param LPTIMx Low-Power Timer instance
1062 * @retval State of bit (1 or 0).
1063 */
LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef * LPTIMx)1064 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1065 {
1066 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1067 }
1068
1069 /**
1070 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1071 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1072 * @param LPTIMx Low-Power Timer instance
1073 * @retval None
1074 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1075 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1076 {
1077 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1078 }
1079
1080 /**
1081 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
1082 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1083 * @param LPTIMx Low-Power Timer instance
1084 * @retval State of bit (1 or 0).
1085 */
LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef * LPTIMx)1086 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1087 {
1088 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1089 }
1090
1091 /**
1092 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1093 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1094 * @param LPTIMx Low-Power Timer instance
1095 * @retval None
1096 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1097 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1098 {
1099 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1100 }
1101
1102 /**
1103 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
1104 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1105 * @param LPTIMx Low-Power Timer instance
1106 * @retval State of bit (1 or 0).
1107 */
LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef * LPTIMx)1108 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1109 {
1110 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1111 }
1112
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1118 * @{
1119 */
1120
1121 /**
1122 * @brief Enable compare match interrupt (CMPMIE).
1123 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1124 * @param LPTIMx Low-Power Timer instance
1125 * @retval None
1126 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1127 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1128 {
1129 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1130 }
1131
1132 /**
1133 * @brief Disable compare match interrupt (CMPMIE).
1134 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1135 * @param LPTIMx Low-Power Timer instance
1136 * @retval None
1137 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1138 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1139 {
1140 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1141 }
1142
1143 /**
1144 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1145 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1146 * @param LPTIMx Low-Power Timer instance
1147 * @retval State of bit (1 or 0).
1148 */
LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef * LPTIMx)1149 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1150 {
1151 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1152 }
1153
1154 /**
1155 * @brief Enable autoreload match interrupt (ARRMIE).
1156 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1157 * @param LPTIMx Low-Power Timer instance
1158 * @retval None
1159 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1160 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1161 {
1162 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1163 }
1164
1165 /**
1166 * @brief Disable autoreload match interrupt (ARRMIE).
1167 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1168 * @param LPTIMx Low-Power Timer instance
1169 * @retval None
1170 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1171 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1172 {
1173 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1174 }
1175
1176 /**
1177 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1178 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1179 * @param LPTIMx Low-Power Timer instance
1180 * @retval State of bit (1 or 0).
1181 */
LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef * LPTIMx)1182 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1183 {
1184 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1185 }
1186
1187 /**
1188 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1189 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1190 * @param LPTIMx Low-Power Timer instance
1191 * @retval None
1192 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1193 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1194 {
1195 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1196 }
1197
1198 /**
1199 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1200 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1201 * @param LPTIMx Low-Power Timer instance
1202 * @retval None
1203 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1204 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1205 {
1206 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1207 }
1208
1209 /**
1210 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1211 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1212 * @param LPTIMx Low-Power Timer instance
1213 * @retval State of bit (1 or 0).
1214 */
LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1215 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1216 {
1217 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1218 }
1219
1220 /**
1221 * @brief Enable compare register write completed interrupt (CMPOKIE).
1222 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1223 * @param LPTIMx Low-Power Timer instance
1224 * @retval None
1225 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1226 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1227 {
1228 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1229 }
1230
1231 /**
1232 * @brief Disable compare register write completed interrupt (CMPOKIE).
1233 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1234 * @param LPTIMx Low-Power Timer instance
1235 * @retval None
1236 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1237 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1238 {
1239 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1240 }
1241
1242 /**
1243 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1244 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1245 * @param LPTIMx Low-Power Timer instance
1246 * @retval State of bit (1 or 0).
1247 */
LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef * LPTIMx)1248 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1249 {
1250 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1251 }
1252
1253 /**
1254 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1255 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1256 * @param LPTIMx Low-Power Timer instance
1257 * @retval None
1258 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1259 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1260 {
1261 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1262 }
1263
1264 /**
1265 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1266 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1267 * @param LPTIMx Low-Power Timer instance
1268 * @retval None
1269 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1270 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1271 {
1272 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1273 }
1274
1275 /**
1276 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1277 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1278 * @param LPTIMx Low-Power Timer instance
1279 * @retval State of bit(1 or 0).
1280 */
LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef * LPTIMx)1281 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1282 {
1283 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1284 }
1285
1286 /**
1287 * @brief Enable direction change to up interrupt (UPIE).
1288 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1289 * @param LPTIMx Low-Power Timer instance
1290 * @retval None
1291 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1292 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1293 {
1294 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1295 }
1296
1297 /**
1298 * @brief Disable direction change to up interrupt (UPIE).
1299 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1300 * @param LPTIMx Low-Power Timer instance
1301 * @retval None
1302 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1303 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1304 {
1305 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1306 }
1307
1308 /**
1309 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1310 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1311 * @param LPTIMx Low-Power Timer instance
1312 * @retval State of bit(1 or 0).
1313 */
LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef * LPTIMx)1314 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1315 {
1316 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1317 }
1318
1319 /**
1320 * @brief Enable direction change to down interrupt (DOWNIE).
1321 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1322 * @param LPTIMx Low-Power Timer instance
1323 * @retval None
1324 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1325 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1326 {
1327 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1328 }
1329
1330 /**
1331 * @brief Disable direction change to down interrupt (DOWNIE).
1332 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1333 * @param LPTIMx Low-Power Timer instance
1334 * @retval None
1335 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1336 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1337 {
1338 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1339 }
1340
1341 /**
1342 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1343 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1344 * @param LPTIMx Low-Power Timer instance
1345 * @retval State of bit(1 or 0).
1346 */
LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef * LPTIMx)1347 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1348 {
1349 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1350 }
1351
1352 /**
1353 * @}
1354 */
1355
1356 /**
1357 * @}
1358 */
1359
1360 /**
1361 * @}
1362 */
1363
1364 #endif /* LPTIM1 */
1365
1366 /**
1367 * @}
1368 */
1369
1370 #ifdef __cplusplus
1371 }
1372 #endif
1373
1374 #endif /* STM32F4xx_LL_LPTIM_H */
1375
1376 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1377