1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F4xx_LL_DMA2D_H
22 #define STM32F4xx_LL_DMA2D_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f4xx.h"
30
31 /** @addtogroup STM32F4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA2D)
36
37 /** @defgroup DMA2D_LL DMA2D
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
47 * @{
48 */
49
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
58 * @{
59 */
60
61 /**
62 * @brief LL DMA2D Init Structure Definition
63 */
64 typedef struct
65 {
66 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
67 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
68
69 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
75
76 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
77 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
78 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
79 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
80 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
81 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
82
83 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
84 function @ref LL_DMA2D_ConfigOutputColor(). */
85
86 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
87 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
88 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
89 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
90 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
91 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
92
93 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
94 function @ref LL_DMA2D_ConfigOutputColor(). */
95
96 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
97 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
98 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
99 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
100 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
101 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
102
103 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
104 function @ref LL_DMA2D_ConfigOutputColor(). */
105
106 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
107 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
108 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
109 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
110 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
111
112 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
113 function @ref LL_DMA2D_ConfigOutputColor(). */
114
115 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
116 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
117
118 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
119
120
121
122 uint32_t LineOffset; /*!< Specifies the output line offset value.
123 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
124
125 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
126
127 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
128 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
129
130 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
131
132 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
133 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
134
135 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
136
137
138 } LL_DMA2D_InitTypeDef;
139
140 /**
141 * @brief LL DMA2D Layer Configuration Structure Definition
142 */
143 typedef struct
144 {
145 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
146 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
147
148 This parameter can be modified afterwards using unitary functions
149 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
150 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
151
152 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
153 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
154
155 This parameter can be modified afterwards using unitary functions
156 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
157 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
158
159 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
160 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
161
162 This parameter can be modified afterwards using unitary functions
163 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
164 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
165
166 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
167 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
168
169 This parameter can be modified afterwards using unitary functions
170 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
171 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
172
173 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
174 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
175
176 This parameter can be modified afterwards using unitary functions
177 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
178 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
179
180 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
181 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
182
183 This parameter can be modified afterwards using unitary functions
184 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
185 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
186
187 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
188 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
189
190 This parameter can be modified afterwards using unitary functions
191 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
192 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
193
194 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
195 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
196
197 This parameter can be modified afterwards using unitary functions
198 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
199 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
200
201 uint32_t Green; /*!< Specifies the foreground or background Green color value.
202 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
203
204 This parameter can be modified afterwards using unitary functions
205 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
206 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
207
208 uint32_t Red; /*!< Specifies the foreground or background Red color value.
209 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
210
211 This parameter can be modified afterwards using unitary functions
212 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
213 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
214
215 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
216 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
217
218 This parameter can be modified afterwards using unitary functions
219 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
220 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
221
222
223
224 } LL_DMA2D_LayerCfgTypeDef;
225
226 /**
227 * @brief LL DMA2D Output Color Structure Definition
228 */
229 typedef struct
230 {
231 uint32_t ColorMode; /*!< Specifies the color format of the output image.
232 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
233
234 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
235
236 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
237 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
238 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
239 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
240 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
241 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
242
243 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
244 function @ref LL_DMA2D_ConfigOutputColor(). */
245
246 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
247 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
248 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
249 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
250 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
251 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
252
253 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
254 function @ref LL_DMA2D_ConfigOutputColor(). */
255
256 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
257 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
258 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
259 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
261 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
262
263 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
264 function @ref LL_DMA2D_ConfigOutputColor(). */
265
266 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
267 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
268 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
269 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
270 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
271
272 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
273 function @ref LL_DMA2D_ConfigOutputColor(). */
274
275 } LL_DMA2D_ColorTypeDef;
276
277 /**
278 * @}
279 */
280 #endif /* USE_FULL_LL_DRIVER */
281
282 /* Exported constants --------------------------------------------------------*/
283 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
284 * @{
285 */
286
287 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
288 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
289 * @{
290 */
291 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
292 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
293 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
294 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
295 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
296 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
297 /**
298 * @}
299 */
300
301 /** @defgroup DMA2D_LL_EC_IT IT Defines
302 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
303 * @{
304 */
305 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
306 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
307 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
308 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
309 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
310 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
311 /**
312 * @}
313 */
314
315 /** @defgroup DMA2D_LL_EC_MODE Mode
316 * @{
317 */
318 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
319 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
320 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
321 #define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
322 /**
323 * @}
324 */
325
326 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
327 * @{
328 */
329 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
330 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
331 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
332 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
333 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
334 /**
335 * @}
336 */
337
338 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
339 * @{
340 */
341 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
342 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
343 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
344 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
345 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
346 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
347 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
348 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
349 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
350 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
351 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
352 /**
353 * @}
354 */
355
356 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
357 * @{
358 */
359 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
360 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
361 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
362 with original alpha channel value */
363 /**
364 * @}
365 */
366
367
368
369
370 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
371 * @{
372 */
373 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
374 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
375 /**
376 * @}
377 */
378
379
380 /**
381 * @}
382 */
383
384 /* Exported macro ------------------------------------------------------------*/
385 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
386 * @{
387 */
388
389 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
390 * @{
391 */
392
393 /**
394 * @brief Write a value in DMA2D register.
395 * @param __INSTANCE__ DMA2D Instance
396 * @param __REG__ Register to be written
397 * @param __VALUE__ Value to be written in the register
398 * @retval None
399 */
400 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
401
402 /**
403 * @brief Read a value in DMA2D register.
404 * @param __INSTANCE__ DMA2D Instance
405 * @param __REG__ Register to be read
406 * @retval Register value
407 */
408 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
409 /**
410 * @}
411 */
412
413 /**
414 * @}
415 */
416
417 /* Exported functions --------------------------------------------------------*/
418 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
419 * @{
420 */
421
422 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
423 * @{
424 */
425
426 /**
427 * @brief Start a DMA2D transfer.
428 * @rmtoll CR START LL_DMA2D_Start
429 * @param DMA2Dx DMA2D Instance
430 * @retval None
431 */
LL_DMA2D_Start(DMA2D_TypeDef * DMA2Dx)432 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
433 {
434 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
435 }
436
437 /**
438 * @brief Indicate if a DMA2D transfer is ongoing.
439 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
440 * @param DMA2Dx DMA2D Instance
441 * @retval State of bit (1 or 0).
442 */
LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef * DMA2Dx)443 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
444 {
445 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
446 }
447
448 /**
449 * @brief Suspend DMA2D transfer.
450 * @note This API can be used to suspend automatic foreground or background CLUT loading.
451 * @rmtoll CR SUSP LL_DMA2D_Suspend
452 * @param DMA2Dx DMA2D Instance
453 * @retval None
454 */
LL_DMA2D_Suspend(DMA2D_TypeDef * DMA2Dx)455 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
456 {
457 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
458 }
459
460 /**
461 * @brief Resume DMA2D transfer.
462 * @note This API can be used to resume automatic foreground or background CLUT loading.
463 * @rmtoll CR SUSP LL_DMA2D_Resume
464 * @param DMA2Dx DMA2D Instance
465 * @retval None
466 */
LL_DMA2D_Resume(DMA2D_TypeDef * DMA2Dx)467 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
468 {
469 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
470 }
471
472 /**
473 * @brief Indicate if DMA2D transfer is suspended.
474 * @note This API can be used to indicate whether or not automatic foreground or
475 * background CLUT loading is suspended.
476 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
477 * @param DMA2Dx DMA2D Instance
478 * @retval State of bit (1 or 0).
479 */
LL_DMA2D_IsSuspended(DMA2D_TypeDef * DMA2Dx)480 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
481 {
482 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
483 }
484
485 /**
486 * @brief Abort DMA2D transfer.
487 * @note This API can be used to abort automatic foreground or background CLUT loading.
488 * @rmtoll CR ABORT LL_DMA2D_Abort
489 * @param DMA2Dx DMA2D Instance
490 * @retval None
491 */
LL_DMA2D_Abort(DMA2D_TypeDef * DMA2Dx)492 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
493 {
494 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
495 }
496
497 /**
498 * @brief Indicate if DMA2D transfer is aborted.
499 * @note This API can be used to indicate whether or not automatic foreground or
500 * background CLUT loading is aborted.
501 * @rmtoll CR ABORT LL_DMA2D_IsAborted
502 * @param DMA2Dx DMA2D Instance
503 * @retval State of bit (1 or 0).
504 */
LL_DMA2D_IsAborted(DMA2D_TypeDef * DMA2Dx)505 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
506 {
507 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
508 }
509
510 /**
511 * @brief Set DMA2D mode.
512 * @rmtoll CR MODE LL_DMA2D_SetMode
513 * @param DMA2Dx DMA2D Instance
514 * @param Mode This parameter can be one of the following values:
515 * @arg @ref LL_DMA2D_MODE_M2M
516 * @arg @ref LL_DMA2D_MODE_M2M_PFC
517 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
518 * @arg @ref LL_DMA2D_MODE_R2M
519 * @retval None
520 */
LL_DMA2D_SetMode(DMA2D_TypeDef * DMA2Dx,uint32_t Mode)521 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
522 {
523 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
524 }
525
526 /**
527 * @brief Return DMA2D mode
528 * @rmtoll CR MODE LL_DMA2D_GetMode
529 * @param DMA2Dx DMA2D Instance
530 * @retval Returned value can be one of the following values:
531 * @arg @ref LL_DMA2D_MODE_M2M
532 * @arg @ref LL_DMA2D_MODE_M2M_PFC
533 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
534 * @arg @ref LL_DMA2D_MODE_R2M
535 */
LL_DMA2D_GetMode(DMA2D_TypeDef * DMA2Dx)536 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
537 {
538 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
539 }
540
541 /**
542 * @brief Set DMA2D output color mode.
543 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
544 * @param DMA2Dx DMA2D Instance
545 * @param ColorMode This parameter can be one of the following values:
546 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
547 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
548 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
549 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
550 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
551 * @retval None
552 */
LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)553 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
554 {
555 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
556 }
557
558 /**
559 * @brief Return DMA2D output color mode.
560 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
561 * @param DMA2Dx DMA2D Instance
562 * @retval Returned value can be one of the following values:
563 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
564 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
565 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
566 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
567 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
568 */
LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef * DMA2Dx)569 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
570 {
571 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
572 }
573
574
575
576
577 /**
578 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
579 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
580 * @param DMA2Dx DMA2D Instance
581 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
582 * @retval None
583 */
LL_DMA2D_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)584 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
585 {
586 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
587 }
588
589 /**
590 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
591 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
592 * @param DMA2Dx DMA2D Instance
593 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
594 */
LL_DMA2D_GetLineOffset(DMA2D_TypeDef * DMA2Dx)595 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
596 {
597 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
598 }
599
600 /**
601 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
602 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
603 * @param DMA2Dx DMA2D Instance
604 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
605 * @retval None
606 */
LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfPixelsPerLines)607 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
608 {
609 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
610 }
611
612 /**
613 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
614 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
615 * @param DMA2Dx DMA2D Instance
616 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
617 */
LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx)618 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
619 {
620 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
621 }
622
623 /**
624 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
625 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
626 * @param DMA2Dx DMA2D Instance
627 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
628 * @retval None
629 */
LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfLines)630 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
631 {
632 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
633 }
634
635 /**
636 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
637 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
638 * @param DMA2Dx DMA2D Instance
639 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
640 */
LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef * DMA2Dx)641 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
642 {
643 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
644 }
645
646 /**
647 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
648 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
649 * @param DMA2Dx DMA2D Instance
650 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
651 * @retval None
652 */
LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t OutputMemoryAddress)653 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
654 {
655 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
656 }
657
658 /**
659 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
660 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
661 * @param DMA2Dx DMA2D Instance
662 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
663 */
LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef * DMA2Dx)664 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
665 {
666 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
667 }
668
669 /**
670 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
671 * @note Output color format depends on output color mode, ARGB8888, RGB888,
672 * RGB565, ARGB1555 or ARGB4444.
673 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
674 * with respect to color mode is not done by the user code.
675 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
676 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
677 * OCOLR RED LL_DMA2D_SetOutputColor\n
678 * OCOLR ALPHA LL_DMA2D_SetOutputColor
679 * @param DMA2Dx DMA2D Instance
680 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
681 * @retval None
682 */
LL_DMA2D_SetOutputColor(DMA2D_TypeDef * DMA2Dx,uint32_t OutputColor)683 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
684 {
685 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
686 OutputColor);
687 }
688
689 /**
690 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
691 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
692 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
693 * as set by @ref LL_DMA2D_SetOutputColorMode.
694 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
695 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
696 * OCOLR RED LL_DMA2D_GetOutputColor\n
697 * OCOLR ALPHA LL_DMA2D_GetOutputColor
698 * @param DMA2Dx DMA2D Instance
699 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
700 */
LL_DMA2D_GetOutputColor(DMA2D_TypeDef * DMA2Dx)701 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
702 {
703 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
704 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
705 }
706
707 /**
708 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
709 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
710 * @param DMA2Dx DMA2D Instance
711 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
712 * @retval None
713 */
LL_DMA2D_SetLineWatermark(DMA2D_TypeDef * DMA2Dx,uint32_t LineWatermark)714 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
715 {
716 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
717 }
718
719 /**
720 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
721 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
722 * @param DMA2Dx DMA2D Instance
723 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
724 */
LL_DMA2D_GetLineWatermark(DMA2D_TypeDef * DMA2Dx)725 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
726 {
727 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
728 }
729
730 /**
731 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
732 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
733 * @param DMA2Dx DMA2D Instance
734 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
735 * @retval None
736 */
LL_DMA2D_SetDeadTime(DMA2D_TypeDef * DMA2Dx,uint32_t DeadTime)737 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
738 {
739 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
740 }
741
742 /**
743 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
744 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
745 * @param DMA2Dx DMA2D Instance
746 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
747 */
LL_DMA2D_GetDeadTime(DMA2D_TypeDef * DMA2Dx)748 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
749 {
750 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
751 }
752
753 /**
754 * @brief Enable DMA2D dead time functionality.
755 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
756 * @param DMA2Dx DMA2D Instance
757 * @retval None
758 */
LL_DMA2D_EnableDeadTime(DMA2D_TypeDef * DMA2Dx)759 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
760 {
761 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
762 }
763
764 /**
765 * @brief Disable DMA2D dead time functionality.
766 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
767 * @param DMA2Dx DMA2D Instance
768 * @retval None
769 */
LL_DMA2D_DisableDeadTime(DMA2D_TypeDef * DMA2Dx)770 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
771 {
772 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
773 }
774
775 /**
776 * @brief Indicate if DMA2D dead time functionality is enabled.
777 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
778 * @param DMA2Dx DMA2D Instance
779 * @retval State of bit (1 or 0).
780 */
LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef * DMA2Dx)781 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
782 {
783 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
784 }
785
786 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
787 * @{
788 */
789
790 /**
791 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
792 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
793 * @param DMA2Dx DMA2D Instance
794 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
795 * @retval None
796 */
LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)797 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
798 {
799 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
800 }
801
802 /**
803 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
804 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
805 * @param DMA2Dx DMA2D Instance
806 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
807 */
LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)808 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
809 {
810 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
811 }
812
813 /**
814 * @brief Enable DMA2D foreground CLUT loading.
815 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
816 * @param DMA2Dx DMA2D Instance
817 * @retval None
818 */
LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)819 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
820 {
821 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
822 }
823
824 /**
825 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
826 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
827 * @param DMA2Dx DMA2D Instance
828 * @retval State of bit (1 or 0).
829 */
LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)830 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
831 {
832 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
833 }
834
835 /**
836 * @brief Set DMA2D foreground color mode.
837 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
838 * @param DMA2Dx DMA2D Instance
839 * @param ColorMode This parameter can be one of the following values:
840 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
841 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
842 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
843 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
844 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
845 * @arg @ref LL_DMA2D_INPUT_MODE_L8
846 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
847 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
848 * @arg @ref LL_DMA2D_INPUT_MODE_L4
849 * @arg @ref LL_DMA2D_INPUT_MODE_A8
850 * @arg @ref LL_DMA2D_INPUT_MODE_A4
851 * @retval None
852 */
LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)853 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
854 {
855 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
856 }
857
858 /**
859 * @brief Return DMA2D foreground color mode.
860 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
861 * @param DMA2Dx DMA2D Instance
862 * @retval Returned value can be one of the following values:
863 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
864 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
865 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
866 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
867 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
868 * @arg @ref LL_DMA2D_INPUT_MODE_L8
869 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
870 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
871 * @arg @ref LL_DMA2D_INPUT_MODE_L4
872 * @arg @ref LL_DMA2D_INPUT_MODE_A8
873 * @arg @ref LL_DMA2D_INPUT_MODE_A4
874 */
LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)875 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
876 {
877 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
878 }
879
880 /**
881 * @brief Set DMA2D foreground alpha mode.
882 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
883 * @param DMA2Dx DMA2D Instance
884 * @param AphaMode This parameter can be one of the following values:
885 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
886 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
887 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
888 * @retval None
889 */
LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)890 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
891 {
892 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
893 }
894
895 /**
896 * @brief Return DMA2D foreground alpha mode.
897 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
898 * @param DMA2Dx DMA2D Instance
899 * @retval Returned value can be one of the following values:
900 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
901 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
902 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
903 */
LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)904 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
905 {
906 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
907 }
908
909 /**
910 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
911 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
912 * @param DMA2Dx DMA2D Instance
913 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
914 * @retval None
915 */
LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)916 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
917 {
918 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
919 }
920
921 /**
922 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
923 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
924 * @param DMA2Dx DMA2D Instance
925 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
926 */
LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)927 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
928 {
929 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
930 }
931
932
933 /**
934 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
935 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
936 * @param DMA2Dx DMA2D Instance
937 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
938 * @retval None
939 */
LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)940 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
941 {
942 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
943 }
944
945 /**
946 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
947 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
948 * @param DMA2Dx DMA2D Instance
949 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
950 */
LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)951 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
952 {
953 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
954 }
955
956 /**
957 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
958 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
959 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
960 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
961 * @param DMA2Dx DMA2D Instance
962 * @param Red Value between Min_Data=0 and Max_Data=0xFF
963 * @param Green Value between Min_Data=0 and Max_Data=0xFF
964 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
965 * @retval None
966 */
LL_DMA2D_FGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)967 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
968 {
969 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
970 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
971 }
972
973 /**
974 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
975 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
976 * @param DMA2Dx DMA2D Instance
977 * @param Red Value between Min_Data=0 and Max_Data=0xFF
978 * @retval None
979 */
LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)980 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
981 {
982 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
983 }
984
985 /**
986 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
987 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
988 * @param DMA2Dx DMA2D Instance
989 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
990 */
LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)991 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
992 {
993 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
994 }
995
996 /**
997 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
998 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
999 * @param DMA2Dx DMA2D Instance
1000 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1001 * @retval None
1002 */
LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1003 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1004 {
1005 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1006 }
1007
1008 /**
1009 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1010 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1011 * @param DMA2Dx DMA2D Instance
1012 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1013 */
LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1014 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1015 {
1016 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1017 }
1018
1019 /**
1020 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1021 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1022 * @param DMA2Dx DMA2D Instance
1023 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1024 * @retval None
1025 */
LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1026 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1027 {
1028 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1029 }
1030
1031 /**
1032 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1033 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1034 * @param DMA2Dx DMA2D Instance
1035 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1036 */
LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1037 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1038 {
1039 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1040 }
1041
1042 /**
1043 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1044 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1045 * @param DMA2Dx DMA2D Instance
1046 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1047 * @retval None
1048 */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1049 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1050 {
1051 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1052 }
1053
1054 /**
1055 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1056 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1057 * @param DMA2Dx DMA2D Instance
1058 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1059 */
LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1060 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1061 {
1062 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1063 }
1064
1065 /**
1066 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1067 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1068 * @param DMA2Dx DMA2D Instance
1069 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1070 * @retval None
1071 */
LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1072 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1073 {
1074 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1075 }
1076
1077 /**
1078 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1079 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1080 * @param DMA2Dx DMA2D Instance
1081 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1082 */
LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1083 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1084 {
1085 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1086 }
1087
1088 /**
1089 * @brief Set DMA2D foreground CLUT color mode.
1090 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1091 * @param DMA2Dx DMA2D Instance
1092 * @param CLUTColorMode This parameter can be one of the following values:
1093 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1094 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1095 * @retval None
1096 */
LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1097 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1098 {
1099 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1100 }
1101
1102 /**
1103 * @brief Return DMA2D foreground CLUT color mode.
1104 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1105 * @param DMA2Dx DMA2D Instance
1106 * @retval Returned value can be one of the following values:
1107 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1108 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1109 */
LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1110 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1111 {
1112 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1113 }
1114
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1120 * @{
1121 */
1122
1123 /**
1124 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1125 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1126 * @param DMA2Dx DMA2D Instance
1127 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1128 * @retval None
1129 */
LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1130 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1131 {
1132 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1133 }
1134
1135 /**
1136 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1137 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1138 * @param DMA2Dx DMA2D Instance
1139 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1140 */
LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef * DMA2Dx)1141 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1142 {
1143 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1144 }
1145
1146 /**
1147 * @brief Enable DMA2D background CLUT loading.
1148 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1149 * @param DMA2Dx DMA2D Instance
1150 * @retval None
1151 */
LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1152 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1153 {
1154 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1155 }
1156
1157 /**
1158 * @brief Indicate if DMA2D background CLUT loading is enabled.
1159 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1160 * @param DMA2Dx DMA2D Instance
1161 * @retval State of bit (1 or 0).
1162 */
LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef * DMA2Dx)1163 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1164 {
1165 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1166 }
1167
1168 /**
1169 * @brief Set DMA2D background color mode.
1170 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1171 * @param DMA2Dx DMA2D Instance
1172 * @param ColorMode This parameter can be one of the following values:
1173 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1174 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1175 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1176 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1177 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1178 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1179 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1180 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1181 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1182 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1183 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1184 * @retval None
1185 */
LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1186 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1187 {
1188 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1189 }
1190
1191 /**
1192 * @brief Return DMA2D background color mode.
1193 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1194 * @param DMA2Dx DMA2D Instance
1195 * @retval Returned value can be one of the following values:
1196 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1197 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1198 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1199 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1200 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1201 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1202 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1203 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1204 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1205 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1206 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1207 */
LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef * DMA2Dx)1208 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1209 {
1210 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1211 }
1212
1213 /**
1214 * @brief Set DMA2D background alpha mode.
1215 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1216 * @param DMA2Dx DMA2D Instance
1217 * @param AphaMode This parameter can be one of the following values:
1218 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1219 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1220 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1221 * @retval None
1222 */
LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1223 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1224 {
1225 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1226 }
1227
1228 /**
1229 * @brief Return DMA2D background alpha mode.
1230 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1231 * @param DMA2Dx DMA2D Instance
1232 * @retval Returned value can be one of the following values:
1233 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1234 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1235 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1236 */
LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef * DMA2Dx)1237 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1238 {
1239 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1240 }
1241
1242 /**
1243 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1244 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1245 * @param DMA2Dx DMA2D Instance
1246 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1247 * @retval None
1248 */
LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1249 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1250 {
1251 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1252 }
1253
1254 /**
1255 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1256 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1257 * @param DMA2Dx DMA2D Instance
1258 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1259 */
LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef * DMA2Dx)1260 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1261 {
1262 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1263 }
1264
1265
1266 /**
1267 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1268 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1269 * @param DMA2Dx DMA2D Instance
1270 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1271 * @retval None
1272 */
LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1273 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1274 {
1275 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1276 }
1277
1278 /**
1279 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1280 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1281 * @param DMA2Dx DMA2D Instance
1282 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1283 */
LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef * DMA2Dx)1284 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1285 {
1286 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1287 }
1288
1289 /**
1290 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1291 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1292 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1293 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1294 * @param DMA2Dx DMA2D Instance
1295 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1296 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1297 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1298 * @retval None
1299 */
LL_DMA2D_BGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1300 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1301 {
1302 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1303 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1304 }
1305
1306 /**
1307 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1308 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1309 * @param DMA2Dx DMA2D Instance
1310 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1311 * @retval None
1312 */
LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1313 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1314 {
1315 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1316 }
1317
1318 /**
1319 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1320 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1321 * @param DMA2Dx DMA2D Instance
1322 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1323 */
LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef * DMA2Dx)1324 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1325 {
1326 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1327 }
1328
1329 /**
1330 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1331 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1332 * @param DMA2Dx DMA2D Instance
1333 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1334 * @retval None
1335 */
LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1336 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1337 {
1338 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1339 }
1340
1341 /**
1342 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1343 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1344 * @param DMA2Dx DMA2D Instance
1345 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1346 */
LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef * DMA2Dx)1347 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1348 {
1349 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1350 }
1351
1352 /**
1353 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1354 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1355 * @param DMA2Dx DMA2D Instance
1356 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1357 * @retval None
1358 */
LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1359 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1360 {
1361 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1362 }
1363
1364 /**
1365 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1366 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1367 * @param DMA2Dx DMA2D Instance
1368 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1369 */
LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef * DMA2Dx)1370 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1371 {
1372 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1373 }
1374
1375 /**
1376 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1377 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1378 * @param DMA2Dx DMA2D Instance
1379 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1380 * @retval None
1381 */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1382 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1383 {
1384 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1385 }
1386
1387 /**
1388 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1389 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1390 * @param DMA2Dx DMA2D Instance
1391 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1392 */
LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx)1393 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1394 {
1395 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1396 }
1397
1398 /**
1399 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1400 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1401 * @param DMA2Dx DMA2D Instance
1402 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1403 * @retval None
1404 */
LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1405 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1406 {
1407 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1408 }
1409
1410 /**
1411 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1412 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1413 * @param DMA2Dx DMA2D Instance
1414 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1415 */
LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef * DMA2Dx)1416 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1417 {
1418 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1419 }
1420
1421 /**
1422 * @brief Set DMA2D background CLUT color mode.
1423 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1424 * @param DMA2Dx DMA2D Instance
1425 * @param CLUTColorMode This parameter can be one of the following values:
1426 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1427 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1428 * @retval None
1429 */
LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1430 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1431 {
1432 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1433 }
1434
1435 /**
1436 * @brief Return DMA2D background CLUT color mode.
1437 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1438 * @param DMA2Dx DMA2D Instance
1439 * @retval Returned value can be one of the following values:
1440 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1441 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1442 */
LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef * DMA2Dx)1443 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1444 {
1445 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1446 }
1447
1448 /**
1449 * @}
1450 */
1451
1452 /**
1453 * @}
1454 */
1455
1456
1457 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1458 * @{
1459 */
1460
1461 /**
1462 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1463 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1464 * @param DMA2Dx DMA2D Instance
1465 * @retval State of bit (1 or 0).
1466 */
LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef * DMA2Dx)1467 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1468 {
1469 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1470 }
1471
1472 /**
1473 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1474 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1475 * @param DMA2Dx DMA2D Instance
1476 * @retval State of bit (1 or 0).
1477 */
LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef * DMA2Dx)1478 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1479 {
1480 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1481 }
1482
1483 /**
1484 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1485 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1486 * @param DMA2Dx DMA2D Instance
1487 * @retval State of bit (1 or 0).
1488 */
LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef * DMA2Dx)1489 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1490 {
1491 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1492 }
1493
1494 /**
1495 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1496 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1497 * @param DMA2Dx DMA2D Instance
1498 * @retval State of bit (1 or 0).
1499 */
LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef * DMA2Dx)1500 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1501 {
1502 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1503 }
1504
1505 /**
1506 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1507 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1508 * @param DMA2Dx DMA2D Instance
1509 * @retval State of bit (1 or 0).
1510 */
LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef * DMA2Dx)1511 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1512 {
1513 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1514 }
1515
1516 /**
1517 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1518 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1519 * @param DMA2Dx DMA2D Instance
1520 * @retval State of bit (1 or 0).
1521 */
LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef * DMA2Dx)1522 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1523 {
1524 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1525 }
1526
1527 /**
1528 * @brief Clear DMA2D Configuration Error Interrupt Flag
1529 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1530 * @param DMA2Dx DMA2D Instance
1531 * @retval None
1532 */
LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef * DMA2Dx)1533 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1534 {
1535 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1536 }
1537
1538 /**
1539 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1540 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1541 * @param DMA2Dx DMA2D Instance
1542 * @retval None
1543 */
LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef * DMA2Dx)1544 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1545 {
1546 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1547 }
1548
1549 /**
1550 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1551 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1552 * @param DMA2Dx DMA2D Instance
1553 * @retval None
1554 */
LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef * DMA2Dx)1555 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1556 {
1557 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1558 }
1559
1560 /**
1561 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1562 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1563 * @param DMA2Dx DMA2D Instance
1564 * @retval None
1565 */
LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef * DMA2Dx)1566 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1567 {
1568 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1569 }
1570
1571 /**
1572 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1573 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1574 * @param DMA2Dx DMA2D Instance
1575 * @retval None
1576 */
LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef * DMA2Dx)1577 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1578 {
1579 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1580 }
1581
1582 /**
1583 * @brief Clear DMA2D Transfer Error Interrupt Flag
1584 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1585 * @param DMA2Dx DMA2D Instance
1586 * @retval None
1587 */
LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef * DMA2Dx)1588 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1589 {
1590 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1591 }
1592
1593 /**
1594 * @}
1595 */
1596
1597 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1598 * @{
1599 */
1600
1601 /**
1602 * @brief Enable Configuration Error Interrupt
1603 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1604 * @param DMA2Dx DMA2D Instance
1605 * @retval None
1606 */
LL_DMA2D_EnableIT_CE(DMA2D_TypeDef * DMA2Dx)1607 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1608 {
1609 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1610 }
1611
1612 /**
1613 * @brief Enable CLUT Transfer Complete Interrupt
1614 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1615 * @param DMA2Dx DMA2D Instance
1616 * @retval None
1617 */
LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef * DMA2Dx)1618 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1619 {
1620 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1621 }
1622
1623 /**
1624 * @brief Enable CLUT Access Error Interrupt
1625 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1626 * @param DMA2Dx DMA2D Instance
1627 * @retval None
1628 */
LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef * DMA2Dx)1629 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1630 {
1631 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1632 }
1633
1634 /**
1635 * @brief Enable Transfer Watermark Interrupt
1636 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
1637 * @param DMA2Dx DMA2D Instance
1638 * @retval None
1639 */
LL_DMA2D_EnableIT_TW(DMA2D_TypeDef * DMA2Dx)1640 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1641 {
1642 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1643 }
1644
1645 /**
1646 * @brief Enable Transfer Complete Interrupt
1647 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
1648 * @param DMA2Dx DMA2D Instance
1649 * @retval None
1650 */
LL_DMA2D_EnableIT_TC(DMA2D_TypeDef * DMA2Dx)1651 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1652 {
1653 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1654 }
1655
1656 /**
1657 * @brief Enable Transfer Error Interrupt
1658 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
1659 * @param DMA2Dx DMA2D Instance
1660 * @retval None
1661 */
LL_DMA2D_EnableIT_TE(DMA2D_TypeDef * DMA2Dx)1662 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1663 {
1664 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1665 }
1666
1667 /**
1668 * @brief Disable Configuration Error Interrupt
1669 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
1670 * @param DMA2Dx DMA2D Instance
1671 * @retval None
1672 */
LL_DMA2D_DisableIT_CE(DMA2D_TypeDef * DMA2Dx)1673 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
1674 {
1675 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1676 }
1677
1678 /**
1679 * @brief Disable CLUT Transfer Complete Interrupt
1680 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
1681 * @param DMA2Dx DMA2D Instance
1682 * @retval None
1683 */
LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef * DMA2Dx)1684 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1685 {
1686 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1687 }
1688
1689 /**
1690 * @brief Disable CLUT Access Error Interrupt
1691 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
1692 * @param DMA2Dx DMA2D Instance
1693 * @retval None
1694 */
LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef * DMA2Dx)1695 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1696 {
1697 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1698 }
1699
1700 /**
1701 * @brief Disable Transfer Watermark Interrupt
1702 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
1703 * @param DMA2Dx DMA2D Instance
1704 * @retval None
1705 */
LL_DMA2D_DisableIT_TW(DMA2D_TypeDef * DMA2Dx)1706 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
1707 {
1708 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1709 }
1710
1711 /**
1712 * @brief Disable Transfer Complete Interrupt
1713 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
1714 * @param DMA2Dx DMA2D Instance
1715 * @retval None
1716 */
LL_DMA2D_DisableIT_TC(DMA2D_TypeDef * DMA2Dx)1717 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
1718 {
1719 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1720 }
1721
1722 /**
1723 * @brief Disable Transfer Error Interrupt
1724 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
1725 * @param DMA2Dx DMA2D Instance
1726 * @retval None
1727 */
LL_DMA2D_DisableIT_TE(DMA2D_TypeDef * DMA2Dx)1728 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
1729 {
1730 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1731 }
1732
1733 /**
1734 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
1735 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
1736 * @param DMA2Dx DMA2D Instance
1737 * @retval State of bit (1 or 0).
1738 */
LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef * DMA2Dx)1739 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
1740 {
1741 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
1742 }
1743
1744 /**
1745 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
1746 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
1747 * @param DMA2Dx DMA2D Instance
1748 * @retval State of bit (1 or 0).
1749 */
LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef * DMA2Dx)1750 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
1751 {
1752 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
1753 }
1754
1755 /**
1756 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
1757 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
1758 * @param DMA2Dx DMA2D Instance
1759 * @retval State of bit (1 or 0).
1760 */
LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef * DMA2Dx)1761 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
1762 {
1763 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
1764 }
1765
1766 /**
1767 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
1768 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
1769 * @param DMA2Dx DMA2D Instance
1770 * @retval State of bit (1 or 0).
1771 */
LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef * DMA2Dx)1772 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
1773 {
1774 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
1775 }
1776
1777 /**
1778 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
1779 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
1780 * @param DMA2Dx DMA2D Instance
1781 * @retval State of bit (1 or 0).
1782 */
LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef * DMA2Dx)1783 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
1784 {
1785 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
1786 }
1787
1788 /**
1789 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
1790 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
1791 * @param DMA2Dx DMA2D Instance
1792 * @retval State of bit (1 or 0).
1793 */
LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef * DMA2Dx)1794 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
1795 {
1796 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
1797 }
1798
1799
1800
1801 /**
1802 * @}
1803 */
1804
1805 #if defined(USE_FULL_LL_DRIVER)
1806 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
1807 * @{
1808 */
1809
1810 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
1811 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
1812 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
1813 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
1814 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
1815 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
1816 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1817 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1818 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1819 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
1820 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
1821
1822 /**
1823 * @}
1824 */
1825 #endif /* USE_FULL_LL_DRIVER */
1826
1827 /**
1828 * @}
1829 */
1830
1831 /**
1832 * @}
1833 */
1834
1835 #endif /* defined (DMA2D) */
1836
1837 /**
1838 * @}
1839 */
1840
1841 #ifdef __cplusplus
1842 }
1843 #endif
1844
1845 #endif /* STM32F4xx_LL_DMA2D_H */
1846
1847 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1848