1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F4xx_HAL_DMA2D_H 22 #define STM32F4xx_HAL_DMA2D_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /** @addtogroup STM32F4xx_HAL_Driver 32 * @{ 33 */ 34 35 #if defined (DMA2D) 36 37 /** @addtogroup DMA2D DMA2D 38 * @brief DMA2D HAL module driver 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 44 * @{ 45 */ 46 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 47 48 /** 49 * @brief DMA2D CLUT Structure definition 50 */ 51 typedef struct 52 { 53 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 54 55 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 56 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 57 58 uint32_t Size; /*!< Configures the DMA2D CLUT size. 59 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 60 } DMA2D_CLUTCfgTypeDef; 61 62 /** 63 * @brief DMA2D Init structure definition 64 */ 65 typedef struct 66 { 67 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 68 This parameter can be one value of @ref DMA2D_Mode. */ 69 70 uint32_t ColorMode; /*!< Configures the color format of the output image. 71 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 72 73 uint32_t OutputOffset; /*!< Specifies the Offset value. 74 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 76 77 78 79 } DMA2D_InitTypeDef; 80 81 82 /** 83 * @brief DMA2D Layer structure definition 84 */ 85 typedef struct 86 { 87 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 88 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 89 90 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 91 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 92 93 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 94 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 95 96 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. 97 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. 98 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between 99 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 100 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 101 - InputAlpha[16:23] is the red value RED[0:7] 102 - InputAlpha[8:15] is the green value GREEN[0:7] 103 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 104 105 106 } DMA2D_LayerCfgTypeDef; 107 108 /** 109 * @brief HAL DMA2D State structures definition 110 */ 111 typedef enum 112 { 113 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 114 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 115 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 116 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 117 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 118 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 119 }HAL_DMA2D_StateTypeDef; 120 121 /** 122 * @brief DMA2D handle Structure definition 123 */ 124 typedef struct __DMA2D_HandleTypeDef 125 { 126 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 127 128 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 129 130 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ 131 132 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ 133 134 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 135 void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ 136 137 void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ 138 139 void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ 140 141 void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ 142 143 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 144 145 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 146 147 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 148 149 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 150 151 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 152 } DMA2D_HandleTypeDef; 153 154 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 155 /** 156 * @brief HAL DMA2D Callback pointer definition 157 */ 158 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ 159 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 160 /** 161 * @} 162 */ 163 164 /* Exported constants --------------------------------------------------------*/ 165 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 166 * @{ 167 */ 168 169 /** @defgroup DMA2D_Error_Code DMA2D Error Code 170 * @{ 171 */ 172 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 173 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 174 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 175 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 176 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 177 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 178 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 179 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 180 181 /** 182 * @} 183 */ 184 185 /** @defgroup DMA2D_Mode DMA2D Mode 186 * @{ 187 */ 188 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 189 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 190 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 191 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ 192 /** 193 * @} 194 */ 195 196 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 197 * @{ 198 */ 199 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 200 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 201 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 202 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 203 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 209 * @{ 210 */ 211 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 212 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 213 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 214 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 215 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 216 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 217 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 218 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 219 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 220 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 221 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 227 * @{ 228 */ 229 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 230 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 231 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 232 with original alpha channel value */ 233 /** 234 * @} 235 */ 236 237 238 239 240 241 242 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 243 * @{ 244 */ 245 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 246 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 247 /** 248 * @} 249 */ 250 251 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 252 * @{ 253 */ 254 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 255 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 256 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 257 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 258 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 259 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup DMA2D_Flags DMA2D Flags 265 * @{ 266 */ 267 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 268 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 269 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 270 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 271 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 272 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup DMA2D_Aliases DMA2D API Aliases 278 * @{ 279 */ 280 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ 281 /** 282 * @} 283 */ 284 285 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 286 /** 287 * @brief HAL DMA2D common Callback ID enumeration definition 288 */ 289 typedef enum 290 { 291 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 292 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 293 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 294 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 295 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 296 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 297 }HAL_DMA2D_CallbackIDTypeDef; 298 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 299 300 301 /** 302 * @} 303 */ 304 /* Exported macros ------------------------------------------------------------*/ 305 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 306 * @{ 307 */ 308 309 /** @brief Reset DMA2D handle state 310 * @param __HANDLE__ specifies the DMA2D handle. 311 * @retval None 312 */ 313 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 314 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 315 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 316 (__HANDLE__)->MspInitCallback = NULL; \ 317 (__HANDLE__)->MspDeInitCallback = NULL; \ 318 }while(0) 319 #else 320 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 321 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 322 323 324 /** 325 * @brief Enable the DMA2D. 326 * @param __HANDLE__ DMA2D handle 327 * @retval None. 328 */ 329 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 330 331 332 /* Interrupt & Flag management */ 333 /** 334 * @brief Get the DMA2D pending flags. 335 * @param __HANDLE__ DMA2D handle 336 * @param __FLAG__ flag to check. 337 * This parameter can be any combination of the following values: 338 * @arg DMA2D_FLAG_CE: Configuration error flag 339 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 340 * @arg DMA2D_FLAG_CAE: CLUT access error flag 341 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 342 * @arg DMA2D_FLAG_TC: Transfer complete flag 343 * @arg DMA2D_FLAG_TE: Transfer error flag 344 * @retval The state of FLAG. 345 */ 346 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 347 348 /** 349 * @brief Clear the DMA2D pending flags. 350 * @param __HANDLE__ DMA2D handle 351 * @param __FLAG__ specifies the flag to clear. 352 * This parameter can be any combination of the following values: 353 * @arg DMA2D_FLAG_CE: Configuration error flag 354 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 355 * @arg DMA2D_FLAG_CAE: CLUT access error flag 356 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 357 * @arg DMA2D_FLAG_TC: Transfer complete flag 358 * @arg DMA2D_FLAG_TE: Transfer error flag 359 * @retval None 360 */ 361 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 362 363 /** 364 * @brief Enable the specified DMA2D interrupts. 365 * @param __HANDLE__ DMA2D handle 366 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 367 * This parameter can be any combination of the following values: 368 * @arg DMA2D_IT_CE: Configuration error interrupt mask 369 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 370 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 371 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 372 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 373 * @arg DMA2D_IT_TE: Transfer error interrupt mask 374 * @retval None 375 */ 376 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 377 378 /** 379 * @brief Disable the specified DMA2D interrupts. 380 * @param __HANDLE__ DMA2D handle 381 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 382 * This parameter can be any combination of the following values: 383 * @arg DMA2D_IT_CE: Configuration error interrupt mask 384 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 385 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 386 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 387 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 388 * @arg DMA2D_IT_TE: Transfer error interrupt mask 389 * @retval None 390 */ 391 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 392 393 /** 394 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 395 * @param __HANDLE__ DMA2D handle 396 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 397 * This parameter can be one of the following values: 398 * @arg DMA2D_IT_CE: Configuration error interrupt mask 399 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 400 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 401 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 402 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 403 * @arg DMA2D_IT_TE: Transfer error interrupt mask 404 * @retval The state of INTERRUPT source. 405 */ 406 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 407 408 /** 409 * @} 410 */ 411 412 /* Exported functions --------------------------------------------------------*/ 413 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 414 * @{ 415 */ 416 417 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 418 * @{ 419 */ 420 421 /* Initialization and de-initialization functions *******************************/ 422 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 423 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); 424 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); 425 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); 426 /* Callbacks Register/UnRegister functions ***********************************/ 427 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 428 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); 429 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 430 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 431 432 /** 433 * @} 434 */ 435 436 437 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 438 * @{ 439 */ 440 441 /* IO operation functions *******************************************************/ 442 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 443 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 444 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 445 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 446 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 447 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 448 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 449 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 450 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); 451 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); 452 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 453 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 454 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 455 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 456 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 457 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 458 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 459 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 460 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 461 462 /** 463 * @} 464 */ 465 466 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 467 * @{ 468 */ 469 470 /* Peripheral Control functions *************************************************/ 471 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 472 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 473 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 474 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 475 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 476 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 477 478 /** 479 * @} 480 */ 481 482 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 483 * @{ 484 */ 485 486 /* Peripheral State functions ***************************************************/ 487 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 488 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 489 490 /** 491 * @} 492 */ 493 494 /** 495 * @} 496 */ 497 498 /* Private constants ---------------------------------------------------------*/ 499 500 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 501 * @{ 502 */ 503 504 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 505 * @{ 506 */ 507 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 508 /** 509 * @} 510 */ 511 512 /** @defgroup DMA2D_Color_Value DMA2D Color Value 513 * @{ 514 */ 515 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 516 /** 517 * @} 518 */ 519 520 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 521 * @{ 522 */ 523 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup DMA2D_Layers DMA2D Layers 529 * @{ 530 */ 531 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 532 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 533 /** 534 * @} 535 */ 536 537 /** @defgroup DMA2D_Offset DMA2D Offset 538 * @{ 539 */ 540 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup DMA2D_Size DMA2D Size 546 * @{ 547 */ 548 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 549 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 555 * @{ 556 */ 557 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 558 /** 559 * @} 560 */ 561 562 /** 563 * @} 564 */ 565 566 567 /* Private macros ------------------------------------------------------------*/ 568 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 569 * @{ 570 */ 571 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 572 573 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 574 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 575 576 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 577 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 578 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 579 580 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 581 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 582 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 583 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 584 585 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 586 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 587 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ 588 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 589 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ 590 ((INPUT_CM) == DMA2D_INPUT_A4)) 591 592 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 593 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 594 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 595 596 597 598 599 600 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 601 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 602 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 603 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 604 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 605 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 606 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 607 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 608 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 609 /** 610 * @} 611 */ 612 613 /** 614 * @} 615 */ 616 617 #endif /* defined (DMA2D) */ 618 619 /** 620 * @} 621 */ 622 623 #ifdef __cplusplus 624 } 625 #endif 626 627 #endif /* STM32F4xx_HAL_DMA2D_H */ 628 629 630 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 631