1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @brief DMA2D HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the DMA2D peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 (#) Program the required configuration through the following parameters:
19 the transfer mode, the output color mode and the output offset using
20 HAL_DMA2D_Init() function.
21
22 (#) Program the required configuration through the following parameters:
23 the input color mode, the input color, the input alpha value, the alpha mode,
24 the red/blue swap mode, the inverted alpha mode and the input offset using
25 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
26
27 *** Polling mode IO operation ***
28 =================================
29 [..]
30 (#) Configure pdata parameter (explained hereafter), destination and data length
31 and enable the transfer using HAL_DMA2D_Start().
32 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
33 user can specify the value of timeout according to his end application.
34
35 *** Interrupt mode IO operation ***
36 ===================================
37 [..]
38 (#) Configure pdata parameter, destination and data length and enable
39 the transfer using HAL_DMA2D_Start_IT().
40 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
41 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
42 add his own function by customization of function pointer XferCpltCallback (member
43 of DMA2D handle structure).
44 (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
45 XferErrorCallback.
46
47 -@- In Register-to-Memory transfer mode, pdata parameter is the register
48 color, in Memory-to-memory or Memory-to-Memory with pixel format
49 conversion pdata is the source address.
50
51 -@- Configure the foreground source address, the background source address,
52 the destination and data length then Enable the transfer using
53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
54 in interrupt mode.
55
56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
57 are used if the memory to memory with blending transfer mode is selected.
58
59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
60 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
61
62 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
63
64 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
65 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
66 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
67 HAL_DMA2D_DisableDeadTime().
68
69 (#) The transfer can be suspended, resumed and aborted using the following
70 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
71
72 (#) The CLUT loading can be suspended, resumed and aborted using the following
73 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
74 HAL_DMA2D_CLUTLoading_Abort().
75
76 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
77
78 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
79
80 *** DMA2D HAL driver macros list ***
81 =============================================
82 [..]
83 Below the list of most used macros in DMA2D HAL driver :
84
85 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
86 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
87 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
88 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
89 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
90 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
91
92 *** Callback registration ***
93 ===================================
94 [..]
95 (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
96 allows the user to configure dynamically the driver callbacks.
97 Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
98
99 (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
100 (+) XferCpltCallback : callback for transfer complete.
101 (+) XferErrorCallback : callback for transfer error.
102 (+) LineEventCallback : callback for line event.
103 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
104 (+) MspInitCallback : DMA2D MspInit.
105 (+) MspDeInitCallback : DMA2D MspDeInit.
106 This function takes as parameters the HAL peripheral handle, the Callback ID
107 and a pointer to the user callback function.
108
109 (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
110 weak (surcharged) function.
111 @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
112 and the Callback ID.
113 This function allows to reset following callbacks:
114 (+) XferCpltCallback : callback for transfer complete.
115 (+) XferErrorCallback : callback for transfer error.
116 (+) LineEventCallback : callback for line event.
117 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
118 (+) MspInitCallback : DMA2D MspInit.
119 (+) MspDeInitCallback : DMA2D MspDeInit.
120
121 (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
122 all callbacks are reset to the corresponding legacy weak (surcharged) functions:
123 examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
124 Exception done for MspInit and MspDeInit callbacks that are respectively
125 reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
126 and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
127 If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
128 keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
129
130 Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
131 as weak (surcharged) functions. They must be defined by the user to be resorted to.
132
133 Callbacks can be registered/unregistered in READY state only.
134 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
135 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
136 during the Init/DeInit.
137 In that case first register the MspInit/MspDeInit user callbacks
138 using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
139 or @ref HAL_DMA2D_Init function.
140
141 When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
142 not defined, the callback registering feature is not available
143 and weak (surcharged) callbacks are used.
144
145 [..]
146 (@) You can refer to the DMA2D HAL driver header file for more useful macros
147
148 @endverbatim
149 ******************************************************************************
150 * @attention
151 *
152 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
153 * All rights reserved.</center></h2>
154 *
155 * This software component is licensed by ST under BSD 3-Clause license,
156 * the "License"; You may not use this file except in compliance with the
157 * License. You may obtain a copy of the License at:
158 * opensource.org/licenses/BSD-3-Clause
159 *
160 ******************************************************************************
161 */
162
163 /* Includes ------------------------------------------------------------------*/
164 #include "stm32f4xx_hal.h"
165
166 #ifdef HAL_DMA2D_MODULE_ENABLED
167 #if defined (DMA2D)
168
169 /** @addtogroup STM32F4xx_HAL_Driver
170 * @{
171 */
172
173 /** @defgroup DMA2D DMA2D
174 * @brief DMA2D HAL module driver
175 * @{
176 */
177
178 /* Private types -------------------------------------------------------------*/
179 /* Private define ------------------------------------------------------------*/
180 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
181 * @{
182 */
183
184 /** @defgroup DMA2D_TimeOut DMA2D Time Out
185 * @{
186 */
187 #define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
188 #define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
189 /**
190 * @}
191 */
192
193 /**
194 * @}
195 */
196
197 /* Private variables ---------------------------------------------------------*/
198 /* Private constants ---------------------------------------------------------*/
199 /* Private macro -------------------------------------------------------------*/
200 /* Private function prototypes -----------------------------------------------*/
201 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
202 * @{
203 */
204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
205 /**
206 * @}
207 */
208
209 /* Private functions ---------------------------------------------------------*/
210 /* Exported functions --------------------------------------------------------*/
211 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
212 * @{
213 */
214
215 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
216 * @brief Initialization and Configuration functions
217 *
218 @verbatim
219 ===============================================================================
220 ##### Initialization and Configuration functions #####
221 ===============================================================================
222 [..] This section provides functions allowing to:
223 (+) Initialize and configure the DMA2D
224 (+) De-initialize the DMA2D
225
226 @endverbatim
227 * @{
228 */
229
230 /**
231 * @brief Initialize the DMA2D according to the specified
232 * parameters in the DMA2D_InitTypeDef and create the associated handle.
233 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
234 * the configuration information for the DMA2D.
235 * @retval HAL status
236 */
HAL_DMA2D_Init(DMA2D_HandleTypeDef * hdma2d)237 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
238 {
239 /* Check the DMA2D peripheral state */
240 if(hdma2d == NULL)
241 {
242 return HAL_ERROR;
243 }
244
245 /* Check the parameters */
246 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
247 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
248 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
249 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
250
251 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
252 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
253 {
254 /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
255 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
256 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
257 if(hdma2d->MspInitCallback == NULL)
258 {
259 hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
260 }
261
262 /* Init the low level hardware */
263 hdma2d->MspInitCallback(hdma2d);
264 }
265 #else
266 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
267 {
268 /* Allocate lock resource and initialize it */
269 hdma2d->Lock = HAL_UNLOCKED;
270 /* Init the low level hardware */
271 HAL_DMA2D_MspInit(hdma2d);
272 }
273 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
274
275 /* Change DMA2D peripheral state */
276 hdma2d->State = HAL_DMA2D_STATE_BUSY;
277
278 /* DMA2D CR register configuration -------------------------------------------*/
279 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
280
281 /* DMA2D OPFCCR register configuration ---------------------------------------*/
282 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
283
284 /* DMA2D OOR register configuration ------------------------------------------*/
285 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
286
287
288 /* Update error code */
289 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
290
291 /* Initialize the DMA2D state*/
292 hdma2d->State = HAL_DMA2D_STATE_READY;
293
294 return HAL_OK;
295 }
296
297 /**
298 * @brief Deinitializes the DMA2D peripheral registers to their default reset
299 * values.
300 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
301 * the configuration information for the DMA2D.
302 * @retval None
303 */
304
HAL_DMA2D_DeInit(DMA2D_HandleTypeDef * hdma2d)305 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
306 {
307
308 /* Check the DMA2D peripheral state */
309 if(hdma2d == NULL)
310 {
311 return HAL_ERROR;
312 }
313
314 /* Before aborting any DMA2D transfer or CLUT loading, check
315 first whether or not DMA2D clock is enabled */
316 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
317 {
318 /* Abort DMA2D transfer if any */
319 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
320 {
321 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
322 {
323 /* Issue when aborting DMA2D transfer */
324 return HAL_ERROR;
325 }
326 }
327 else
328 {
329 /* Abort background CLUT loading if any */
330 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
331 {
332 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
333 {
334 /* Issue when aborting background CLUT loading */
335 return HAL_ERROR;
336 }
337 }
338 else
339 {
340 /* Abort foreground CLUT loading if any */
341 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
342 {
343 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
344 {
345 /* Issue when aborting foreground CLUT loading */
346 return HAL_ERROR;
347 }
348 }
349 }
350 }
351 }
352
353 /* Reset DMA2D control registers*/
354 hdma2d->Instance->CR = 0U;
355 hdma2d->Instance->IFCR = 0x3FU;
356 hdma2d->Instance->FGOR = 0U;
357 hdma2d->Instance->BGOR = 0U;
358 hdma2d->Instance->FGPFCCR = 0U;
359 hdma2d->Instance->BGPFCCR = 0U;
360 hdma2d->Instance->OPFCCR = 0U;
361
362 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
363
364 if(hdma2d->MspDeInitCallback == NULL)
365 {
366 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
367 }
368
369 /* DeInit the low level hardware */
370 hdma2d->MspDeInitCallback(hdma2d);
371
372 #else
373 /* Carry on with de-initialization of low level hardware */
374 HAL_DMA2D_MspDeInit(hdma2d);
375 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
376
377 /* Update error code */
378 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
379
380 /* Initialize the DMA2D state*/
381 hdma2d->State = HAL_DMA2D_STATE_RESET;
382
383 /* Release Lock */
384 __HAL_UNLOCK(hdma2d);
385
386 return HAL_OK;
387 }
388
389 /**
390 * @brief Initializes the DMA2D MSP.
391 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
392 * the configuration information for the DMA2D.
393 * @retval None
394 */
HAL_DMA2D_MspInit(DMA2D_HandleTypeDef * hdma2d)395 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
396 {
397 /* Prevent unused argument(s) compilation warning */
398 UNUSED(hdma2d);
399
400 /* NOTE : This function should not be modified; when the callback is needed,
401 the HAL_DMA2D_MspInit can be implemented in the user file.
402 */
403 }
404
405 /**
406 * @brief DeInitializes the DMA2D MSP.
407 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
408 * the configuration information for the DMA2D.
409 * @retval None
410 */
HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef * hdma2d)411 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
412 {
413 /* Prevent unused argument(s) compilation warning */
414 UNUSED(hdma2d);
415
416 /* NOTE : This function should not be modified; when the callback is needed,
417 the HAL_DMA2D_MspDeInit can be implemented in the user file.
418 */
419 }
420
421 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
422 /**
423 * @brief Register a User DMA2D Callback
424 * To be used instead of the weak (surcharged) predefined callback
425 * @param hdma2d DMA2D handle
426 * @param CallbackID ID of the callback to be registered
427 * This parameter can be one of the following values:
428 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
429 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
430 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
431 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
432 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
433 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
434 * @param pCallback pointer to the Callback function
435 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
436 * @retval status
437 */
HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID,pDMA2D_CallbackTypeDef pCallback)438 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
439 {
440 HAL_StatusTypeDef status = HAL_OK;
441
442 if(pCallback == NULL)
443 {
444 /* Update the error code */
445 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
446 return HAL_ERROR;
447 }
448 /* Process locked */
449 __HAL_LOCK(hdma2d);
450
451 if(HAL_DMA2D_STATE_READY == hdma2d->State)
452 {
453 switch (CallbackID)
454 {
455 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
456 hdma2d->XferCpltCallback = pCallback;
457 break;
458
459 case HAL_DMA2D_TRANSFERERROR_CB_ID :
460 hdma2d->XferErrorCallback = pCallback;
461 break;
462
463 case HAL_DMA2D_LINEEVENT_CB_ID :
464 hdma2d->LineEventCallback = pCallback;
465 break;
466
467 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
468 hdma2d->CLUTLoadingCpltCallback = pCallback;
469 break;
470
471 case HAL_DMA2D_MSPINIT_CB_ID :
472 hdma2d->MspInitCallback = pCallback;
473 break;
474
475 case HAL_DMA2D_MSPDEINIT_CB_ID :
476 hdma2d->MspDeInitCallback = pCallback;
477 break;
478
479 default :
480 /* Update the error code */
481 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
482 /* update return status */
483 status = HAL_ERROR;
484 break;
485 }
486 }
487 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
488 {
489 switch (CallbackID)
490 {
491 case HAL_DMA2D_MSPINIT_CB_ID :
492 hdma2d->MspInitCallback = pCallback;
493 break;
494
495 case HAL_DMA2D_MSPDEINIT_CB_ID :
496 hdma2d->MspDeInitCallback = pCallback;
497 break;
498
499 default :
500 /* Update the error code */
501 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
502 /* update return status */
503 status = HAL_ERROR;
504 break;
505 }
506 }
507 else
508 {
509 /* Update the error code */
510 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
511 /* update return status */
512 status = HAL_ERROR;
513 }
514
515 /* Release Lock */
516 __HAL_UNLOCK(hdma2d);
517 return status;
518 }
519
520 /**
521 * @brief Unregister a DMA2D Callback
522 * DMA2D Callback is redirected to the weak (surcharged) predefined callback
523 * @param hdma2d DMA2D handle
524 * @param CallbackID ID of the callback to be unregistered
525 * This parameter can be one of the following values:
526 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
527 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
528 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
529 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
530 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
531 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
532 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
533 * @retval status
534 */
HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID)535 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
536 {
537 HAL_StatusTypeDef status = HAL_OK;
538
539 /* Process locked */
540 __HAL_LOCK(hdma2d);
541
542 if(HAL_DMA2D_STATE_READY == hdma2d->State)
543 {
544 switch (CallbackID)
545 {
546 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
547 hdma2d->XferCpltCallback = NULL;
548 break;
549
550 case HAL_DMA2D_TRANSFERERROR_CB_ID :
551 hdma2d->XferErrorCallback = NULL;
552 break;
553
554 case HAL_DMA2D_LINEEVENT_CB_ID :
555 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
556 break;
557
558 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
559 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
560 break;
561
562 case HAL_DMA2D_MSPINIT_CB_ID :
563 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
564 break;
565
566 case HAL_DMA2D_MSPDEINIT_CB_ID :
567 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
568 break;
569
570 default :
571 /* Update the error code */
572 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
573 /* update return status */
574 status = HAL_ERROR;
575 break;
576 }
577 }
578 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
579 {
580 switch (CallbackID)
581 {
582 case HAL_DMA2D_MSPINIT_CB_ID :
583 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
584 break;
585
586 case HAL_DMA2D_MSPDEINIT_CB_ID :
587 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
588 break;
589
590 default :
591 /* Update the error code */
592 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
593 /* update return status */
594 status = HAL_ERROR;
595 break;
596 }
597 }
598 else
599 {
600 /* Update the error code */
601 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
602 /* update return status */
603 status = HAL_ERROR;
604 }
605
606 /* Release Lock */
607 __HAL_UNLOCK(hdma2d);
608 return status;
609 }
610 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
611
612 /**
613 * @}
614 */
615
616
617 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
618 * @brief IO operation functions
619 *
620 @verbatim
621 ===============================================================================
622 ##### IO operation functions #####
623 ===============================================================================
624 [..] This section provides functions allowing to:
625 (+) Configure the pdata, destination address and data size then
626 start the DMA2D transfer.
627 (+) Configure the source for foreground and background, destination address
628 and data size then start a MultiBuffer DMA2D transfer.
629 (+) Configure the pdata, destination address and data size then
630 start the DMA2D transfer with interrupt.
631 (+) Configure the source for foreground and background, destination address
632 and data size then start a MultiBuffer DMA2D transfer with interrupt.
633 (+) Abort DMA2D transfer.
634 (+) Suspend DMA2D transfer.
635 (+) Resume DMA2D transfer.
636 (+) Enable CLUT transfer.
637 (+) Configure CLUT loading then start transfer in polling mode.
638 (+) Configure CLUT loading then start transfer in interrupt mode.
639 (+) Abort DMA2D CLUT loading.
640 (+) Suspend DMA2D CLUT loading.
641 (+) Resume DMA2D CLUT loading.
642 (+) Poll for transfer complete.
643 (+) handle DMA2D interrupt request.
644 (+) Transfer watermark callback.
645 (+) CLUT Transfer Complete callback.
646
647
648 @endverbatim
649 * @{
650 */
651
652 /**
653 * @brief Start the DMA2D Transfer.
654 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
655 * the configuration information for the DMA2D.
656 * @param pdata Configure the source memory Buffer address if
657 * Memory-to-Memory or Memory-to-Memory with pixel format
658 * conversion mode is selected, or configure
659 * the color value if Register-to-Memory mode is selected.
660 * @param DstAddress The destination memory Buffer address.
661 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
662 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
663 * @retval HAL status
664 */
HAL_DMA2D_Start(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)665 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
666 {
667 /* Check the parameters */
668 assert_param(IS_DMA2D_LINE(Height));
669 assert_param(IS_DMA2D_PIXEL(Width));
670
671 /* Process locked */
672 __HAL_LOCK(hdma2d);
673
674 /* Change DMA2D peripheral state */
675 hdma2d->State = HAL_DMA2D_STATE_BUSY;
676
677 /* Configure the source, destination address and the data size */
678 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
679
680 /* Enable the Peripheral */
681 __HAL_DMA2D_ENABLE(hdma2d);
682
683 return HAL_OK;
684 }
685
686 /**
687 * @brief Start the DMA2D Transfer with interrupt enabled.
688 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
689 * the configuration information for the DMA2D.
690 * @param pdata Configure the source memory Buffer address if
691 * the Memory-to-Memory or Memory-to-Memory with pixel format
692 * conversion mode is selected, or configure
693 * the color value if Register-to-Memory mode is selected.
694 * @param DstAddress The destination memory Buffer address.
695 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
696 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
697 * @retval HAL status
698 */
HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)699 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
700 {
701 /* Check the parameters */
702 assert_param(IS_DMA2D_LINE(Height));
703 assert_param(IS_DMA2D_PIXEL(Width));
704
705 /* Process locked */
706 __HAL_LOCK(hdma2d);
707
708 /* Change DMA2D peripheral state */
709 hdma2d->State = HAL_DMA2D_STATE_BUSY;
710
711 /* Configure the source, destination address and the data size */
712 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
713
714 /* Enable the transfer complete, transfer error and configuration error interrupts */
715 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
716
717 /* Enable the Peripheral */
718 __HAL_DMA2D_ENABLE(hdma2d);
719
720 return HAL_OK;
721 }
722
723 /**
724 * @brief Start the multi-source DMA2D Transfer.
725 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
726 * the configuration information for the DMA2D.
727 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
728 * @param SrcAddress2 The source memory Buffer address for the background layer.
729 * @param DstAddress The destination memory Buffer address.
730 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
731 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
732 * @retval HAL status
733 */
HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)734 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
735 {
736 /* Check the parameters */
737 assert_param(IS_DMA2D_LINE(Height));
738 assert_param(IS_DMA2D_PIXEL(Width));
739
740 /* Process locked */
741 __HAL_LOCK(hdma2d);
742
743 /* Change DMA2D peripheral state */
744 hdma2d->State = HAL_DMA2D_STATE_BUSY;
745
746 /* Configure DMA2D Stream source2 address */
747 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
748
749 /* Configure the source, destination address and the data size */
750 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
751
752 /* Enable the Peripheral */
753 __HAL_DMA2D_ENABLE(hdma2d);
754
755 return HAL_OK;
756 }
757
758 /**
759 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
760 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
761 * the configuration information for the DMA2D.
762 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
763 * @param SrcAddress2 The source memory Buffer address for the background layer.
764 * @param DstAddress The destination memory Buffer address.
765 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
766 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
767 * @retval HAL status
768 */
HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)769 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
770 {
771 /* Check the parameters */
772 assert_param(IS_DMA2D_LINE(Height));
773 assert_param(IS_DMA2D_PIXEL(Width));
774
775 /* Process locked */
776 __HAL_LOCK(hdma2d);
777
778 /* Change DMA2D peripheral state */
779 hdma2d->State = HAL_DMA2D_STATE_BUSY;
780
781 /* Configure DMA2D Stream source2 address */
782 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
783
784 /* Configure the source, destination address and the data size */
785 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
786
787 /* Enable the transfer complete, transfer error and configuration error interrupts */
788 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
789
790 /* Enable the Peripheral */
791 __HAL_DMA2D_ENABLE(hdma2d);
792
793 return HAL_OK;
794 }
795
796 /**
797 * @brief Abort the DMA2D Transfer.
798 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
799 * the configuration information for the DMA2D.
800 * @retval HAL status
801 */
HAL_DMA2D_Abort(DMA2D_HandleTypeDef * hdma2d)802 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
803 {
804 uint32_t tickstart;
805
806 /* Abort the DMA2D transfer */
807 /* START bit is reset to make sure not to set it again, in the event the HW clears it
808 between the register read and the register write by the CPU (writing 0 has no
809 effect on START bitvalue) */
810 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
811
812 /* Get tick */
813 tickstart = HAL_GetTick();
814
815 /* Check if the DMA2D is effectively disabled */
816 while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
817 {
818 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
819 {
820 /* Update error code */
821 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
822
823 /* Change the DMA2D state */
824 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
825
826 /* Process Unlocked */
827 __HAL_UNLOCK(hdma2d);
828
829 return HAL_TIMEOUT;
830 }
831 }
832
833 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
834 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
835
836 /* Change the DMA2D state*/
837 hdma2d->State = HAL_DMA2D_STATE_READY;
838
839 /* Process Unlocked */
840 __HAL_UNLOCK(hdma2d);
841
842 return HAL_OK;
843 }
844
845 /**
846 * @brief Suspend the DMA2D Transfer.
847 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
848 * the configuration information for the DMA2D.
849 * @retval HAL status
850 */
HAL_DMA2D_Suspend(DMA2D_HandleTypeDef * hdma2d)851 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
852 {
853 uint32_t tickstart;
854
855 /* Suspend the DMA2D transfer */
856 /* START bit is reset to make sure not to set it again, in the event the HW clears it
857 between the register read and the register write by the CPU (writing 0 has no
858 effect on START bitvalue). */
859 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
860
861 /* Get tick */
862 tickstart = HAL_GetTick();
863
864 /* Check if the DMA2D is effectively suspended */
865 while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
866 {
867 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
868 {
869 /* Update error code */
870 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
871
872 /* Change the DMA2D state */
873 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
874
875 return HAL_TIMEOUT;
876 }
877 }
878
879 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
880 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
881 {
882 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
883 }
884 else
885 {
886 /* Make sure SUSP bit is cleared since it is meaningless
887 when no tranfer is on-going */
888 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
889 }
890
891 return HAL_OK;
892 }
893
894 /**
895 * @brief Resume the DMA2D Transfer.
896 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
897 * the configuration information for the DMA2D.
898 * @retval HAL status
899 */
HAL_DMA2D_Resume(DMA2D_HandleTypeDef * hdma2d)900 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
901 {
902 /* Check the SUSP and START bits */
903 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
904 {
905 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
906 hdma2d->State = HAL_DMA2D_STATE_BUSY;
907 }
908
909 /* Resume the DMA2D transfer */
910 /* START bit is reset to make sure not to set it again, in the event the HW clears it
911 between the register read and the register write by the CPU (writing 0 has no
912 effect on START bitvalue). */
913 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
914
915 return HAL_OK;
916 }
917
918
919 /**
920 * @brief Enable the DMA2D CLUT Transfer.
921 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
922 * the configuration information for the DMA2D.
923 * @param LayerIdx DMA2D Layer index.
924 * This parameter can be one of the following values:
925 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
926 * @retval HAL status
927 */
HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)928 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
929 {
930 /* Check the parameters */
931 assert_param(IS_DMA2D_LAYER(LayerIdx));
932
933 /* Process locked */
934 __HAL_LOCK(hdma2d);
935
936 /* Change DMA2D peripheral state */
937 hdma2d->State = HAL_DMA2D_STATE_BUSY;
938
939 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
940 {
941 /* Enable the background CLUT loading */
942 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
943 }
944 else
945 {
946 /* Enable the foreground CLUT loading */
947 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
948 }
949
950 return HAL_OK;
951 }
952
953 /**
954 * @brief Start DMA2D CLUT Loading.
955 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
956 * the configuration information for the DMA2D.
957 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
958 * the configuration information for the color look up table.
959 * @param LayerIdx DMA2D Layer index.
960 * This parameter can be one of the following values:
961 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
962 * @retval HAL status
963 */
HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)964 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
965 {
966 /* Check the parameters */
967 assert_param(IS_DMA2D_LAYER(LayerIdx));
968 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
969 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
970
971 /* Process locked */
972 __HAL_LOCK(hdma2d);
973
974 /* Change DMA2D peripheral state */
975 hdma2d->State = HAL_DMA2D_STATE_BUSY;
976
977 /* Configure the CLUT of the background DMA2D layer */
978 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
979 {
980 /* Write background CLUT memory address */
981 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
982
983 /* Write background CLUT size and CLUT color mode */
984 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
985 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
986
987 /* Enable the CLUT loading for the background */
988 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
989 }
990 /* Configure the CLUT of the foreground DMA2D layer */
991 else
992 {
993 /* Write foreground CLUT memory address */
994 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
995
996 /* Write foreground CLUT size and CLUT color mode */
997 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
998 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
999
1000 /* Enable the CLUT loading for the foreground */
1001 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1002 }
1003
1004 return HAL_OK;
1005 }
1006
1007 /**
1008 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1009 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1010 * the configuration information for the DMA2D.
1011 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1012 * the configuration information for the color look up table.
1013 * @param LayerIdx DMA2D Layer index.
1014 * This parameter can be one of the following values:
1015 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1016 * @retval HAL status
1017 */
HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)1018 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
1019 {
1020 /* Check the parameters */
1021 assert_param(IS_DMA2D_LAYER(LayerIdx));
1022 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1023 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1024
1025 /* Process locked */
1026 __HAL_LOCK(hdma2d);
1027
1028 /* Change DMA2D peripheral state */
1029 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1030
1031 /* Configure the CLUT of the background DMA2D layer */
1032 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1033 {
1034 /* Write background CLUT memory address */
1035 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1036
1037 /* Write background CLUT size and CLUT color mode */
1038 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1039 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1040
1041 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1042 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1043
1044 /* Enable the CLUT loading for the background */
1045 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1046 }
1047 /* Configure the CLUT of the foreground DMA2D layer */
1048 else
1049 {
1050 /* Write foreground CLUT memory address */
1051 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1052
1053 /* Write foreground CLUT size and CLUT color mode */
1054 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1055 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1056
1057 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1058 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1059
1060 /* Enable the CLUT loading for the foreground */
1061 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1062 }
1063
1064 return HAL_OK;
1065 }
1066
1067 /**
1068 * @brief Start DMA2D CLUT Loading.
1069 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1070 * the configuration information for the DMA2D.
1071 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1072 * the configuration information for the color look up table.
1073 * @param LayerIdx DMA2D Layer index.
1074 * This parameter can be one of the following values:
1075 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1076 * @note API obsolete and maintained for compatibility with legacy. User is
1077 * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
1078 * code compactness, code size and improved heap usage.
1079 * @retval HAL status
1080 */
HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1081 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1082 {
1083 /* Check the parameters */
1084 assert_param(IS_DMA2D_LAYER(LayerIdx));
1085 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1086 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1087
1088 /* Process locked */
1089 __HAL_LOCK(hdma2d);
1090
1091 /* Change DMA2D peripheral state */
1092 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1093
1094 /* Configure the CLUT of the background DMA2D layer */
1095 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1096 {
1097 /* Write background CLUT memory address */
1098 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1099
1100 /* Write background CLUT size and CLUT color mode */
1101 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1102 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1103
1104 /* Enable the CLUT loading for the background */
1105 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1106 }
1107 /* Configure the CLUT of the foreground DMA2D layer */
1108 else
1109 {
1110 /* Write foreground CLUT memory address */
1111 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1112
1113 /* Write foreground CLUT size and CLUT color mode */
1114 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1115 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1116
1117 /* Enable the CLUT loading for the foreground */
1118 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1119 }
1120
1121 return HAL_OK;
1122 }
1123
1124 /**
1125 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1126 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1127 * the configuration information for the DMA2D.
1128 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1129 * the configuration information for the color look up table.
1130 * @param LayerIdx DMA2D Layer index.
1131 * This parameter can be one of the following values:
1132 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1133 * @note API obsolete and maintained for compatibility with legacy. User is
1134 * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
1135 * from code compactness, code size and improved heap usage.
1136 * @retval HAL status
1137 */
HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1138 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1139 {
1140 /* Check the parameters */
1141 assert_param(IS_DMA2D_LAYER(LayerIdx));
1142 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1143 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1144
1145 /* Process locked */
1146 __HAL_LOCK(hdma2d);
1147
1148 /* Change DMA2D peripheral state */
1149 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1150
1151 /* Configure the CLUT of the background DMA2D layer */
1152 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1153 {
1154 /* Write background CLUT memory address */
1155 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1156
1157 /* Write background CLUT size and CLUT color mode */
1158 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1159 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1160
1161 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1162 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1163
1164 /* Enable the CLUT loading for the background */
1165 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1166 }
1167 /* Configure the CLUT of the foreground DMA2D layer */
1168 else
1169 {
1170 /* Write foreground CLUT memory address */
1171 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1172
1173 /* Write foreground CLUT size and CLUT color mode */
1174 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1175 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1176
1177 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1178 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1179
1180 /* Enable the CLUT loading for the foreground */
1181 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1182 }
1183
1184 return HAL_OK;
1185 }
1186
1187 /**
1188 * @brief Abort the DMA2D CLUT loading.
1189 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1190 * the configuration information for the DMA2D.
1191 * @param LayerIdx DMA2D Layer index.
1192 * This parameter can be one of the following values:
1193 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1194 * @retval HAL status
1195 */
HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1196 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1197 {
1198 uint32_t tickstart;
1199 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1200
1201 /* Abort the CLUT loading */
1202 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1203
1204 /* If foreground CLUT loading is considered, update local variables */
1205 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1206 {
1207 reg = &(hdma2d->Instance->FGPFCCR);
1208 }
1209
1210
1211 /* Get tick */
1212 tickstart = HAL_GetTick();
1213
1214 /* Check if the CLUT loading is aborted */
1215 while((*reg & DMA2D_BGPFCCR_START) != 0U)
1216 {
1217 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
1218 {
1219 /* Update error code */
1220 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1221
1222 /* Change the DMA2D state */
1223 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1224
1225 /* Process Unlocked */
1226 __HAL_UNLOCK(hdma2d);
1227
1228 return HAL_TIMEOUT;
1229 }
1230 }
1231
1232 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1233 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1234
1235 /* Change the DMA2D state*/
1236 hdma2d->State = HAL_DMA2D_STATE_READY;
1237
1238 /* Process Unlocked */
1239 __HAL_UNLOCK(hdma2d);
1240
1241 return HAL_OK;
1242 }
1243
1244 /**
1245 * @brief Suspend the DMA2D CLUT loading.
1246 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1247 * the configuration information for the DMA2D.
1248 * @param LayerIdx DMA2D Layer index.
1249 * This parameter can be one of the following values:
1250 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1251 * @retval HAL status
1252 */
HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1253 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1254 {
1255 uint32_t tickstart;
1256 uint32_t loadsuspended;
1257 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1258
1259 /* Suspend the CLUT loading */
1260 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1261
1262 /* If foreground CLUT loading is considered, update local variables */
1263 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1264 {
1265 reg = &(hdma2d->Instance->FGPFCCR);
1266 }
1267
1268 /* Get tick */
1269 tickstart = HAL_GetTick();
1270
1271 /* Check if the CLUT loading is suspended */
1272 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1273 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1274 while (loadsuspended == 0UL)
1275 {
1276 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
1277 {
1278 /* Update error code */
1279 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1280
1281 /* Change the DMA2D state */
1282 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1283
1284 return HAL_TIMEOUT;
1285 }
1286 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1287 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1288 }
1289
1290 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1291 if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1292 {
1293 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1294 }
1295 else
1296 {
1297 /* Make sure SUSP bit is cleared since it is meaningless
1298 when no tranfer is on-going */
1299 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1300 }
1301
1302 return HAL_OK;
1303 }
1304
1305 /**
1306 * @brief Resume the DMA2D CLUT loading.
1307 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1308 * the configuration information for the DMA2D.
1309 * @param LayerIdx DMA2D Layer index.
1310 * This parameter can be one of the following values:
1311 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1312 * @retval HAL status
1313 */
HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1314 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1315 {
1316 /* Check the SUSP and START bits for background or foreground CLUT loading */
1317 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1318 {
1319 /* Background CLUT loading suspension check */
1320 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1321 {
1322 if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1323 {
1324 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1325 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1326 }
1327 }
1328 }
1329 else
1330 {
1331 /* Foreground CLUT loading suspension check */
1332 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1333 {
1334 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1335 {
1336 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1337 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1338 }
1339 }
1340 }
1341
1342 /* Resume the CLUT loading */
1343 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1344
1345 return HAL_OK;
1346 }
1347
1348
1349 /**
1350
1351 * @brief Polling for transfer complete or CLUT loading.
1352 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1353 * the configuration information for the DMA2D.
1354 * @param Timeout Timeout duration
1355 * @retval HAL status
1356 */
HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef * hdma2d,uint32_t Timeout)1357 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1358 {
1359 uint32_t tickstart;
1360 uint32_t layer_start;
1361 __IO uint32_t isrflags = 0x0U;
1362
1363 /* Polling for DMA2D transfer */
1364 if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1365 {
1366 /* Get tick */
1367 tickstart = HAL_GetTick();
1368
1369 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1370 {
1371 isrflags = READ_REG(hdma2d->Instance->ISR);
1372 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1373 {
1374 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1375 {
1376 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1377 }
1378 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1379 {
1380 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1381 }
1382 /* Clear the transfer and configuration error flags */
1383 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1384
1385 /* Change DMA2D state */
1386 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1387
1388 /* Process unlocked */
1389 __HAL_UNLOCK(hdma2d);
1390
1391 return HAL_ERROR;
1392 }
1393 /* Check for the Timeout */
1394 if(Timeout != HAL_MAX_DELAY)
1395 {
1396 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1397 {
1398 /* Update error code */
1399 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1400
1401 /* Change the DMA2D state */
1402 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1403
1404 /* Process unlocked */
1405 __HAL_UNLOCK(hdma2d);
1406
1407 return HAL_TIMEOUT;
1408 }
1409 }
1410 }
1411 }
1412 /* Polling for CLUT loading (foreground or background) */
1413 layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1414 layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1415 if (layer_start != 0U)
1416 {
1417 /* Get tick */
1418 tickstart = HAL_GetTick();
1419
1420 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1421 {
1422 isrflags = READ_REG(hdma2d->Instance->ISR);
1423 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1424 {
1425 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1426 {
1427 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1428 }
1429 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1430 {
1431 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1432 }
1433 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1434 {
1435 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1436 }
1437 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1438 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1439
1440 /* Change DMA2D state */
1441 hdma2d->State= HAL_DMA2D_STATE_ERROR;
1442
1443 /* Process unlocked */
1444 __HAL_UNLOCK(hdma2d);
1445
1446 return HAL_ERROR;
1447 }
1448 /* Check for the Timeout */
1449 if(Timeout != HAL_MAX_DELAY)
1450 {
1451 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1452 {
1453 /* Update error code */
1454 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1455
1456 /* Change the DMA2D state */
1457 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1458
1459 /* Process unlocked */
1460 __HAL_UNLOCK(hdma2d);
1461
1462 return HAL_TIMEOUT;
1463 }
1464 }
1465 }
1466 }
1467
1468 /* Clear the transfer complete and CLUT loading flags */
1469 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1470
1471 /* Change DMA2D state */
1472 hdma2d->State = HAL_DMA2D_STATE_READY;
1473
1474 /* Process unlocked */
1475 __HAL_UNLOCK(hdma2d);
1476
1477 return HAL_OK;
1478 }
1479 /**
1480 * @brief Handle DMA2D interrupt request.
1481 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1482 * the configuration information for the DMA2D.
1483 * @retval HAL status
1484 */
HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef * hdma2d)1485 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1486 {
1487 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1488 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1489
1490 /* Transfer Error Interrupt management ***************************************/
1491 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1492 {
1493 if ((crflags & DMA2D_IT_TE) != 0U)
1494 {
1495 /* Disable the transfer Error interrupt */
1496 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1497
1498 /* Update error code */
1499 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1500
1501 /* Clear the transfer error flag */
1502 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1503
1504 /* Change DMA2D state */
1505 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1506
1507 /* Process Unlocked */
1508 __HAL_UNLOCK(hdma2d);
1509
1510 if(hdma2d->XferErrorCallback != NULL)
1511 {
1512 /* Transfer error Callback */
1513 hdma2d->XferErrorCallback(hdma2d);
1514 }
1515 }
1516 }
1517 /* Configuration Error Interrupt management **********************************/
1518 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1519 {
1520 if ((crflags & DMA2D_IT_CE) != 0U)
1521 {
1522 /* Disable the Configuration Error interrupt */
1523 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1524
1525 /* Clear the Configuration error flag */
1526 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1527
1528 /* Update error code */
1529 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1530
1531 /* Change DMA2D state */
1532 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1533
1534 /* Process Unlocked */
1535 __HAL_UNLOCK(hdma2d);
1536
1537 if(hdma2d->XferErrorCallback != NULL)
1538 {
1539 /* Transfer error Callback */
1540 hdma2d->XferErrorCallback(hdma2d);
1541 }
1542 }
1543 }
1544 /* CLUT access Error Interrupt management ***********************************/
1545 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1546 {
1547 if ((crflags & DMA2D_IT_CAE) != 0U)
1548 {
1549 /* Disable the CLUT access error interrupt */
1550 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1551
1552 /* Clear the CLUT access error flag */
1553 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1554
1555 /* Update error code */
1556 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1557
1558 /* Change DMA2D state */
1559 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1560
1561 /* Process Unlocked */
1562 __HAL_UNLOCK(hdma2d);
1563
1564 if(hdma2d->XferErrorCallback != NULL)
1565 {
1566 /* Transfer error Callback */
1567 hdma2d->XferErrorCallback(hdma2d);
1568 }
1569 }
1570 }
1571 /* Transfer watermark Interrupt management **********************************/
1572 if ((isrflags & DMA2D_FLAG_TW) != 0U)
1573 {
1574 if ((crflags & DMA2D_IT_TW) != 0U)
1575 {
1576 /* Disable the transfer watermark interrupt */
1577 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1578
1579 /* Clear the transfer watermark flag */
1580 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1581
1582 /* Transfer watermark Callback */
1583 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1584 hdma2d->LineEventCallback(hdma2d);
1585 #else
1586 HAL_DMA2D_LineEventCallback(hdma2d);
1587 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1588
1589 }
1590 }
1591 /* Transfer Complete Interrupt management ************************************/
1592 if ((isrflags & DMA2D_FLAG_TC) != 0U)
1593 {
1594 if ((crflags & DMA2D_IT_TC) != 0U)
1595 {
1596 /* Disable the transfer complete interrupt */
1597 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1598
1599 /* Clear the transfer complete flag */
1600 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1601
1602 /* Update error code */
1603 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1604
1605 /* Change DMA2D state */
1606 hdma2d->State = HAL_DMA2D_STATE_READY;
1607
1608 /* Process Unlocked */
1609 __HAL_UNLOCK(hdma2d);
1610
1611 if(hdma2d->XferCpltCallback != NULL)
1612 {
1613 /* Transfer complete Callback */
1614 hdma2d->XferCpltCallback(hdma2d);
1615 }
1616 }
1617 }
1618 /* CLUT Transfer Complete Interrupt management ******************************/
1619 if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1620 {
1621 if ((crflags & DMA2D_IT_CTC) != 0U)
1622 {
1623 /* Disable the CLUT transfer complete interrupt */
1624 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1625
1626 /* Clear the CLUT transfer complete flag */
1627 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1628
1629 /* Update error code */
1630 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1631
1632 /* Change DMA2D state */
1633 hdma2d->State = HAL_DMA2D_STATE_READY;
1634
1635 /* Process Unlocked */
1636 __HAL_UNLOCK(hdma2d);
1637
1638 /* CLUT Transfer complete Callback */
1639 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1640 hdma2d->CLUTLoadingCpltCallback(hdma2d);
1641 #else
1642 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1643 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1644 }
1645 }
1646
1647 }
1648
1649 /**
1650 * @brief Transfer watermark callback.
1651 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1652 * the configuration information for the DMA2D.
1653 * @retval None
1654 */
HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef * hdma2d)1655 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1656 {
1657 /* Prevent unused argument(s) compilation warning */
1658 UNUSED(hdma2d);
1659
1660 /* NOTE : This function should not be modified; when the callback is needed,
1661 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1662 */
1663 }
1664
1665 /**
1666 * @brief CLUT Transfer Complete callback.
1667 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1668 * the configuration information for the DMA2D.
1669 * @retval None
1670 */
HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef * hdma2d)1671 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1672 {
1673 /* Prevent unused argument(s) compilation warning */
1674 UNUSED(hdma2d);
1675
1676 /* NOTE : This function should not be modified; when the callback is needed,
1677 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1678 */
1679 }
1680
1681 /**
1682 * @}
1683 */
1684
1685 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1686 * @brief Peripheral Control functions
1687 *
1688 @verbatim
1689 ===============================================================================
1690 ##### Peripheral Control functions #####
1691 ===============================================================================
1692 [..] This section provides functions allowing to:
1693 (+) Configure the DMA2D foreground or background layer parameters.
1694 (+) Configure the DMA2D CLUT transfer.
1695 (+) Configure the line watermark
1696 (+) Configure the dead time value.
1697 (+) Enable or disable the dead time value functionality.
1698
1699
1700 @endverbatim
1701 * @{
1702 */
1703
1704 /**
1705 * @brief Configure the DMA2D Layer according to the specified
1706 * parameters in the DMA2D_HandleTypeDef.
1707 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1708 * the configuration information for the DMA2D.
1709 * @param LayerIdx DMA2D Layer index.
1710 * This parameter can be one of the following values:
1711 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1712 * @retval HAL status
1713 */
HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1714 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1715 {
1716 DMA2D_LayerCfgTypeDef *pLayerCfg;
1717 uint32_t regMask, regValue;
1718
1719 /* Check the parameters */
1720 assert_param(IS_DMA2D_LAYER(LayerIdx));
1721 assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1722 if(hdma2d->Init.Mode != DMA2D_R2M)
1723 {
1724 assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1725 if(hdma2d->Init.Mode != DMA2D_M2M)
1726 {
1727 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1728 }
1729 }
1730
1731 /* Process locked */
1732 __HAL_LOCK(hdma2d);
1733
1734 /* Change DMA2D peripheral state */
1735 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1736
1737 pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1738
1739 /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1740 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
1741 regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
1742
1743
1744 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1745 {
1746 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1747 }
1748 else
1749 {
1750 regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1751 }
1752
1753 /* Configure the background DMA2D layer */
1754 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1755 {
1756 /* Write DMA2D BGPFCCR register */
1757 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1758
1759 /* DMA2D BGOR register configuration -------------------------------------*/
1760 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1761
1762 /* DMA2D BGCOLR register configuration -------------------------------------*/
1763 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1764 {
1765 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1766 }
1767 }
1768 /* Configure the foreground DMA2D layer */
1769 else
1770 {
1771
1772
1773 /* Write DMA2D FGPFCCR register */
1774 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1775
1776 /* DMA2D FGOR register configuration -------------------------------------*/
1777 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1778
1779 /* DMA2D FGCOLR register configuration -------------------------------------*/
1780 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1781 {
1782 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1783 }
1784 }
1785 /* Initialize the DMA2D state*/
1786 hdma2d->State = HAL_DMA2D_STATE_READY;
1787
1788 /* Process unlocked */
1789 __HAL_UNLOCK(hdma2d);
1790
1791 return HAL_OK;
1792 }
1793
1794 /**
1795 * @brief Configure the DMA2D CLUT Transfer.
1796 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1797 * the configuration information for the DMA2D.
1798 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1799 * the configuration information for the color look up table.
1800 * @param LayerIdx DMA2D Layer index.
1801 * This parameter can be one of the following values:
1802 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1803 * @note API obsolete and maintained for compatibility with legacy. User is invited
1804 * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
1805 * code size and improved heap usage.
1806 * @retval HAL status
1807 */
HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1808 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1809 {
1810 /* Check the parameters */
1811 assert_param(IS_DMA2D_LAYER(LayerIdx));
1812 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1813 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1814
1815 /* Process locked */
1816 __HAL_LOCK(hdma2d);
1817
1818 /* Change DMA2D peripheral state */
1819 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1820
1821 /* Configure the CLUT of the background DMA2D layer */
1822 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1823 {
1824 /* Write background CLUT memory address */
1825 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1826
1827 /* Write background CLUT size and CLUT color mode */
1828 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1829 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1830 }
1831 /* Configure the CLUT of the foreground DMA2D layer */
1832 else
1833 {
1834 /* Write foreground CLUT memory address */
1835 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1836
1837 /* Write foreground CLUT size and CLUT color mode */
1838 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1839 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1840 }
1841
1842 /* Set the DMA2D state to Ready*/
1843 hdma2d->State = HAL_DMA2D_STATE_READY;
1844
1845 /* Process unlocked */
1846 __HAL_UNLOCK(hdma2d);
1847
1848 return HAL_OK;
1849 }
1850
1851
1852 /**
1853 * @brief Configure the line watermark.
1854 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1855 * the configuration information for the DMA2D.
1856 * @param Line Line Watermark configuration (maximum 16-bit long value expected).
1857 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1858 * @note The transfer watermark interrupt is disabled once it has occurred.
1859 * @retval HAL status
1860 */
1861
HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef * hdma2d,uint32_t Line)1862 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1863 {
1864 /* Check the parameters */
1865 assert_param(IS_DMA2D_LINEWATERMARK(Line));
1866
1867 if (Line > DMA2D_LWR_LW)
1868 {
1869 return HAL_ERROR;
1870 }
1871 else
1872 {
1873 /* Process locked */
1874 __HAL_LOCK(hdma2d);
1875
1876 /* Change DMA2D peripheral state */
1877 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1878
1879 /* Sets the Line watermark configuration */
1880 WRITE_REG(hdma2d->Instance->LWR, Line);
1881
1882 /* Enable the Line interrupt */
1883 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1884
1885 /* Initialize the DMA2D state*/
1886 hdma2d->State = HAL_DMA2D_STATE_READY;
1887
1888 /* Process unlocked */
1889 __HAL_UNLOCK(hdma2d);
1890
1891 return HAL_OK;
1892 }
1893 }
1894
1895 /**
1896 * @brief Enable DMA2D dead time feature.
1897 * @param hdma2d DMA2D handle.
1898 * @retval HAL status
1899 */
HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef * hdma2d)1900 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1901 {
1902 /* Process Locked */
1903 __HAL_LOCK(hdma2d);
1904
1905 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1906
1907 /* Set DMA2D_AMTCR EN bit */
1908 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1909
1910 hdma2d->State = HAL_DMA2D_STATE_READY;
1911
1912 /* Process Unlocked */
1913 __HAL_UNLOCK(hdma2d);
1914
1915 return HAL_OK;
1916 }
1917
1918 /**
1919 * @brief Disable DMA2D dead time feature.
1920 * @param hdma2d DMA2D handle.
1921 * @retval HAL status
1922 */
HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef * hdma2d)1923 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1924 {
1925 /* Process Locked */
1926 __HAL_LOCK(hdma2d);
1927
1928 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1929
1930 /* Clear DMA2D_AMTCR EN bit */
1931 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1932
1933 hdma2d->State = HAL_DMA2D_STATE_READY;
1934
1935 /* Process Unlocked */
1936 __HAL_UNLOCK(hdma2d);
1937
1938 return HAL_OK;
1939 }
1940
1941 /**
1942 * @brief Configure dead time.
1943 * @note The dead time value represents the guaranteed minimum number of cycles between
1944 * two consecutive transactions on the AHB bus.
1945 * @param hdma2d DMA2D handle.
1946 * @param DeadTime dead time value.
1947 * @retval HAL status
1948 */
HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef * hdma2d,uint8_t DeadTime)1949 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
1950 {
1951 /* Process Locked */
1952 __HAL_LOCK(hdma2d);
1953
1954 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1955
1956 /* Set DMA2D_AMTCR DT field */
1957 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
1958
1959 hdma2d->State = HAL_DMA2D_STATE_READY;
1960
1961 /* Process Unlocked */
1962 __HAL_UNLOCK(hdma2d);
1963
1964 return HAL_OK;
1965 }
1966
1967 /**
1968 * @}
1969 */
1970
1971
1972 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
1973 * @brief Peripheral State functions
1974 *
1975 @verbatim
1976 ===============================================================================
1977 ##### Peripheral State and Errors functions #####
1978 ===============================================================================
1979 [..]
1980 This subsection provides functions allowing to:
1981 (+) Get the DMA2D state
1982 (+) Get the DMA2D error code
1983
1984 @endverbatim
1985 * @{
1986 */
1987
1988 /**
1989 * @brief Return the DMA2D state
1990 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1991 * the configuration information for the DMA2D.
1992 * @retval HAL state
1993 */
HAL_DMA2D_GetState(DMA2D_HandleTypeDef * hdma2d)1994 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
1995 {
1996 return hdma2d->State;
1997 }
1998
1999 /**
2000 * @brief Return the DMA2D error code
2001 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2002 * the configuration information for DMA2D.
2003 * @retval DMA2D Error Code
2004 */
HAL_DMA2D_GetError(DMA2D_HandleTypeDef * hdma2d)2005 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
2006 {
2007 return hdma2d->ErrorCode;
2008 }
2009
2010 /**
2011 * @}
2012 */
2013
2014 /**
2015 * @}
2016 */
2017
2018
2019 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
2020 * @{
2021 */
2022
2023 /**
2024 * @brief Set the DMA2D transfer parameters.
2025 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
2026 * the configuration information for the specified DMA2D.
2027 * @param pdata The source memory Buffer address
2028 * @param DstAddress The destination memory Buffer address
2029 * @param Width The width of data to be transferred from source to destination.
2030 * @param Height The height of data to be transferred from source to destination.
2031 * @retval HAL status
2032 */
DMA2D_SetConfig(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)2033 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
2034 {
2035 uint32_t tmp;
2036 uint32_t tmp1;
2037 uint32_t tmp2;
2038 uint32_t tmp3;
2039 uint32_t tmp4;
2040
2041 /* Configure DMA2D data size */
2042 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
2043
2044 /* Configure DMA2D destination address */
2045 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
2046
2047 /* Register to memory DMA2D mode selected */
2048 if (hdma2d->Init.Mode == DMA2D_R2M)
2049 {
2050 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
2051 tmp2 = pdata & DMA2D_OCOLR_RED_1;
2052 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
2053 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
2054
2055 /* Prepare the value to be written to the OCOLR register according to the color mode */
2056 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
2057 {
2058 tmp = (tmp3 | tmp2 | tmp1| tmp4);
2059 }
2060 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
2061 {
2062 tmp = (tmp3 | tmp2 | tmp4);
2063 }
2064 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
2065 {
2066 tmp2 = (tmp2 >> 19U);
2067 tmp3 = (tmp3 >> 10U);
2068 tmp4 = (tmp4 >> 3U );
2069 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
2070 }
2071 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
2072 {
2073 tmp1 = (tmp1 >> 31U);
2074 tmp2 = (tmp2 >> 19U);
2075 tmp3 = (tmp3 >> 11U);
2076 tmp4 = (tmp4 >> 3U );
2077 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
2078 }
2079 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
2080 {
2081 tmp1 = (tmp1 >> 28U);
2082 tmp2 = (tmp2 >> 20U);
2083 tmp3 = (tmp3 >> 12U);
2084 tmp4 = (tmp4 >> 4U );
2085 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
2086 }
2087 /* Write to DMA2D OCOLR register */
2088 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
2089 }
2090 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
2091 {
2092 /* Configure DMA2D source address */
2093 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
2094 }
2095 }
2096
2097 /**
2098 * @}
2099 */
2100
2101 /**
2102 * @}
2103 */
2104
2105 /**
2106 * @}
2107 */
2108 #endif /* DMA2D */
2109 #endif /* HAL_DMA2D_MODULE_ENABLED */
2110
2111 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2112