xref: /btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h (revision a8f7f3fcbcd51f8d2e92aca076b6a9f812db358c) 
1 /**
2   ******************************************************************************
3   * @file    stm32f439xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32F439xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - peripherals registers declarations and bits definition
10   *           - Macros to access peripheral’s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.</center></h2>
17   *
18   * This software component is licensed by ST under BSD 3-Clause license,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/BSD-3-Clause
22   *
23   ******************************************************************************
24   */
25 
26 /** @addtogroup CMSIS_Device
27   * @{
28   */
29 
30 /** @addtogroup stm32f439xx
31   * @{
32   */
33 
34 #ifndef __STM32F439xx_H
35 #define __STM32F439xx_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 
45 /**
46   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47   */
48 #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
49 #define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
50 #define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
52 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32F4XX Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 typedef enum
67 {
68 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77 /******  STM32 specific Interrupt Numbers **********************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
80   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
90   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
91   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
92   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
93   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
94   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
95   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
96   ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
97   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
98   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
99   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
100   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
101   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
102   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
103   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
104   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
106   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
107   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
108   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
111   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
112   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
113   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
114   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
117   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
118   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
119   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
120   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
121   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
122   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
123   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
125   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
126   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
127   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
128   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
129   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
130   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
131   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
132   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
133   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
134   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
135   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
136   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
137   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
138   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
139   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
140   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
141   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
142   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
143   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
144   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
145   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
146   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
147   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
148   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
149   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
150   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
151   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
152   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
153   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
154   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
155   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
156   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
157   CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
158   HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
159   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
160   UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
161   UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
162   SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
163   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
164   SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
165   SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
166   LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */
167   LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */
168   DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
169 } IRQn_Type;
170 
171 /**
172   * @}
173   */
174 
175 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
176 #include "system_stm32f4xx.h"
177 #include <stdint.h>
178 
179 /** @addtogroup Peripheral_registers_structures
180   * @{
181   */
182 
183 /**
184   * @brief Analog to Digital Converter
185   */
186 
187 typedef struct
188 {
189   __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
190   __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
191   __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
192   __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
193   __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
194   __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
195   __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
196   __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
197   __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
198   __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
199   __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
200   __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
201   __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
202   __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
203   __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
204   __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
205   __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
206   __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
207   __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
208   __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
209 } ADC_TypeDef;
210 
211 typedef struct
212 {
213   __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
214   __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
215   __IO uint32_t CDR;    /*!< ADC common regular data register for dual
216                              AND triple modes,                            Address offset: ADC1 base address + 0x308 */
217 } ADC_Common_TypeDef;
218 
219 
220 /**
221   * @brief Controller Area Network TxMailBox
222   */
223 
224 typedef struct
225 {
226   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
227   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
228   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
229   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
230 } CAN_TxMailBox_TypeDef;
231 
232 /**
233   * @brief Controller Area Network FIFOMailBox
234   */
235 
236 typedef struct
237 {
238   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
239   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
240   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
241   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
242 } CAN_FIFOMailBox_TypeDef;
243 
244 /**
245   * @brief Controller Area Network FilterRegister
246   */
247 
248 typedef struct
249 {
250   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
251   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
252 } CAN_FilterRegister_TypeDef;
253 
254 /**
255   * @brief Controller Area Network
256   */
257 
258 typedef struct
259 {
260   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
261   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
262   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
263   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
264   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
265   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
266   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
267   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
268   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
269   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
270   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
271   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
272   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
273   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
274   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
275   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
276   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
277   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
278   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
279   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
280   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
281   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
282 } CAN_TypeDef;
283 
284 /**
285   * @brief CRC calculation unit
286   */
287 
288 typedef struct
289 {
290   __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
291   __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
292   uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
293   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
294   __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
295 } CRC_TypeDef;
296 
297 /**
298   * @brief Digital to Analog Converter
299   */
300 
301 typedef struct
302 {
303   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
304   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
305   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
306   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
307   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
308   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
309   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
310   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
311   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
312   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
313   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
314   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
315   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
316   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
317 } DAC_TypeDef;
318 
319 /**
320   * @brief Debug MCU
321   */
322 
323 typedef struct
324 {
325   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
326   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
327   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
328   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
329 }DBGMCU_TypeDef;
330 
331 /**
332   * @brief DCMI
333   */
334 
335 typedef struct
336 {
337   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
338   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
339   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
340   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
341   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
342   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
343   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
344   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
345   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
346   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
347   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
348 } DCMI_TypeDef;
349 
350 /**
351   * @brief DMA Controller
352   */
353 
354 typedef struct
355 {
356   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
357   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
358   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
359   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
360   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
361   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
362 } DMA_Stream_TypeDef;
363 
364 typedef struct
365 {
366   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
367   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
368   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
369   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
370 } DMA_TypeDef;
371 
372 /**
373   * @brief DMA2D Controller
374   */
375 
376 typedef struct
377 {
378   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
379   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
380   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
381   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
382   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
383   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
384   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
385   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
386   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
387   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
388   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
389   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
390   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
391   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
392   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
393   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
394   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
395   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
396   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
397   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
398   uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
399   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
400   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
401 } DMA2D_TypeDef;
402 
403 /**
404   * @brief Ethernet MAC
405   */
406 
407 typedef struct
408 {
409   __IO uint32_t MACCR;
410   __IO uint32_t MACFFR;
411   __IO uint32_t MACHTHR;
412   __IO uint32_t MACHTLR;
413   __IO uint32_t MACMIIAR;
414   __IO uint32_t MACMIIDR;
415   __IO uint32_t MACFCR;
416   __IO uint32_t MACVLANTR;             /*    8 */
417   uint32_t      RESERVED0[2];
418   __IO uint32_t MACRWUFFR;             /*   11 */
419   __IO uint32_t MACPMTCSR;
420   uint32_t      RESERVED1;
421   __IO uint32_t MACDBGR;
422   __IO uint32_t MACSR;                 /*   15 */
423   __IO uint32_t MACIMR;
424   __IO uint32_t MACA0HR;
425   __IO uint32_t MACA0LR;
426   __IO uint32_t MACA1HR;
427   __IO uint32_t MACA1LR;
428   __IO uint32_t MACA2HR;
429   __IO uint32_t MACA2LR;
430   __IO uint32_t MACA3HR;
431   __IO uint32_t MACA3LR;               /*   24 */
432   uint32_t      RESERVED2[40];
433   __IO uint32_t MMCCR;                 /*   65 */
434   __IO uint32_t MMCRIR;
435   __IO uint32_t MMCTIR;
436   __IO uint32_t MMCRIMR;
437   __IO uint32_t MMCTIMR;               /*   69 */
438   uint32_t      RESERVED3[14];
439   __IO uint32_t MMCTGFSCCR;            /*   84 */
440   __IO uint32_t MMCTGFMSCCR;
441   uint32_t      RESERVED4[5];
442   __IO uint32_t MMCTGFCR;
443   uint32_t      RESERVED5[10];
444   __IO uint32_t MMCRFCECR;
445   __IO uint32_t MMCRFAECR;
446   uint32_t      RESERVED6[10];
447   __IO uint32_t MMCRGUFCR;
448   uint32_t      RESERVED7[334];
449   __IO uint32_t PTPTSCR;
450   __IO uint32_t PTPSSIR;
451   __IO uint32_t PTPTSHR;
452   __IO uint32_t PTPTSLR;
453   __IO uint32_t PTPTSHUR;
454   __IO uint32_t PTPTSLUR;
455   __IO uint32_t PTPTSAR;
456   __IO uint32_t PTPTTHR;
457   __IO uint32_t PTPTTLR;
458   __IO uint32_t RESERVED8;
459   __IO uint32_t PTPTSSR;
460   uint32_t      RESERVED9[565];
461   __IO uint32_t DMABMR;
462   __IO uint32_t DMATPDR;
463   __IO uint32_t DMARPDR;
464   __IO uint32_t DMARDLAR;
465   __IO uint32_t DMATDLAR;
466   __IO uint32_t DMASR;
467   __IO uint32_t DMAOMR;
468   __IO uint32_t DMAIER;
469   __IO uint32_t DMAMFBOCR;
470   __IO uint32_t DMARSWTR;
471   uint32_t      RESERVED10[8];
472   __IO uint32_t DMACHTDR;
473   __IO uint32_t DMACHRDR;
474   __IO uint32_t DMACHTBAR;
475   __IO uint32_t DMACHRBAR;
476 } ETH_TypeDef;
477 
478 /**
479   * @brief External Interrupt/Event Controller
480   */
481 
482 typedef struct
483 {
484   __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
485   __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
486   __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
487   __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
488   __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
489   __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
490 } EXTI_TypeDef;
491 
492 /**
493   * @brief FLASH Registers
494   */
495 
496 typedef struct
497 {
498   __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
499   __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
500   __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
501   __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
502   __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
503   __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
504   __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
505 } FLASH_TypeDef;
506 
507 /**
508   * @brief Flexible Memory Controller
509   */
510 
511 typedef struct
512 {
513   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
514 } FMC_Bank1_TypeDef;
515 
516 /**
517   * @brief Flexible Memory Controller Bank1E
518   */
519 
520 typedef struct
521 {
522   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
523 } FMC_Bank1E_TypeDef;
524 /**
525   * @brief Flexible Memory Controller Bank2
526   */
527 
528 typedef struct
529 {
530   __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
531   __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
532   __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
533   __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
534   uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
535   __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
536   uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
537   uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
538   __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
539   __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
540   __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
541   __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
542   uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
543   __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
544 } FMC_Bank2_3_TypeDef;
545 
546 /**
547   * @brief Flexible Memory Controller Bank4
548   */
549 
550 typedef struct
551 {
552   __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
553   __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
554   __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
555   __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
556   __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
557 } FMC_Bank4_TypeDef;
558 
559 /**
560   * @brief Flexible Memory Controller Bank5_6
561   */
562 
563 typedef struct
564 {
565   __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
566   __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
567   __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */
568   __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */
569   __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */
570 } FMC_Bank5_6_TypeDef;
571 
572 /**
573   * @brief General Purpose I/O
574   */
575 
576 typedef struct
577 {
578   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
579   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
580   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
581   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
582   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
583   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
584   __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
585   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
586   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
587 } GPIO_TypeDef;
588 
589 /**
590   * @brief System configuration controller
591   */
592 
593 typedef struct
594 {
595   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
596   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
597   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
598   uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
599   __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
600 } SYSCFG_TypeDef;
601 
602 /**
603   * @brief Inter-integrated Circuit Interface
604   */
605 
606 typedef struct
607 {
608   __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
609   __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
610   __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
611   __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
612   __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
613   __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
614   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
615   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
616   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
617   __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
618 } I2C_TypeDef;
619 
620 /**
621   * @brief Independent WATCHDOG
622   */
623 
624 typedef struct
625 {
626   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
627   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
628   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
629   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
630 } IWDG_TypeDef;
631 
632 /**
633   * @brief LCD-TFT Display Controller
634   */
635 
636 typedef struct
637 {
638   uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
639   __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
640   __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
641   __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
642   __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
643   __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
644   uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
645   __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
646   uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
647   __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
648   uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
649   __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
650   __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
651   __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
652   __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
653   __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
654   __IO uint32_t CDSR;          /*!< LTDC Current Display Status Register,                Address offset: 0x48 */
655 } LTDC_TypeDef;
656 
657 /**
658   * @brief LCD-TFT Display layer x Controller
659   */
660 
661 typedef struct
662 {
663   __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
664   __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
665   __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
666   __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
667   __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
668   __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
669   __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
670   __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
671   uint32_t      RESERVED0[2];  /*!< Reserved                                                                           */
672   __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
673   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
674   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
675   uint32_t      RESERVED1[3];  /*!< Reserved                                                                           */
676   __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144*/
677 } LTDC_Layer_TypeDef;
678 
679 /**
680   * @brief Power Control
681   */
682 
683 typedef struct
684 {
685   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
686   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
687 } PWR_TypeDef;
688 
689 /**
690   * @brief Reset and Clock Control
691   */
692 
693 typedef struct
694 {
695   __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
696   __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
697   __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
698   __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
699   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
700   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
701   __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
702   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
703   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
704   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
705   uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
706   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
707   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
708   __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
709   uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
710   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
711   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
712   uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
713   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
714   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
715   __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
716   uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
717   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
718   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
719   uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
720   __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
721   __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
722   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
723   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
724   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
725   __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
726   __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
727 } RCC_TypeDef;
728 
729 /**
730   * @brief Real-Time Clock
731   */
732 
733 typedef struct
734 {
735   __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
736   __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
737   __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
738   __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
739   __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
740   __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
741   __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
742   __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
743   __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
744   __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
745   __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
746   __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
747   __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
748   __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
749   __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
750   __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
751   __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
752   __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
753   __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
754   uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
755   __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
756   __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
757   __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
758   __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
759   __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
760   __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
761   __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
762   __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
763   __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
764   __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
765   __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
766   __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
767   __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
768   __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
769   __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
770   __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
771   __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
772   __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
773   __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
774   __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
775 } RTC_TypeDef;
776 
777 /**
778   * @brief Serial Audio Interface
779   */
780 
781 typedef struct
782 {
783   __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
784 } SAI_TypeDef;
785 
786 typedef struct
787 {
788   __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
789   __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
790   __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
791   __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
792   __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
793   __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
794   __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
795   __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
796 } SAI_Block_TypeDef;
797 
798 /**
799   * @brief SD host Interface
800   */
801 
802 typedef struct
803 {
804   __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
805   __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
806   __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
807   __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
808   __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
809   __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
810   __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
811   __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
812   __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
813   __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
814   __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
815   __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
816   __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
817   __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
818   __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
819   __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
820   uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
821   __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
822   uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
823   __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
824 } SDIO_TypeDef;
825 
826 /**
827   * @brief Serial Peripheral Interface
828   */
829 
830 typedef struct
831 {
832   __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
833   __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
834   __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
835   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
836   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
837   __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
838   __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
839   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
840   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
841 } SPI_TypeDef;
842 
843 
844 /**
845   * @brief TIM
846   */
847 
848 typedef struct
849 {
850   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
851   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
852   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
853   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
854   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
855   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
856   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
857   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
858   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
859   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
860   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
861   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
862   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
863   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
864   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
865   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
866   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
867   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
868   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
869   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
870   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
871 } TIM_TypeDef;
872 
873 /**
874   * @brief Universal Synchronous Asynchronous Receiver Transmitter
875   */
876 
877 typedef struct
878 {
879   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
880   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
881   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
882   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
883   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
884   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
885   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
886 } USART_TypeDef;
887 
888 /**
889   * @brief Window WATCHDOG
890   */
891 
892 typedef struct
893 {
894   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
895   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
896   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
897 } WWDG_TypeDef;
898 
899 /**
900   * @brief Crypto Processor
901   */
902 
903 typedef struct
904 {
905   __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
906   __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
907   __IO uint32_t DIN;         /*!< CRYP data input register,                                 Address offset: 0x08 */
908   __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
909   __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
910   __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
911   __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
912   __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
913   __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
914   __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
915   __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
916   __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
917   __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
918   __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
919   __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
920   __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
921   __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
922   __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
923   __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
924   __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
925   __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
926   __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
927   __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
928   __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
929   __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
930   __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
931   __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
932   __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
933   __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
934   __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
935   __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
936   __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
937   __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
938   __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
939   __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
940   __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
941 } CRYP_TypeDef;
942 
943 /**
944   * @brief HASH
945   */
946 
947 typedef struct
948 {
949   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
950   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
951   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
952   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
953   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
954   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
955        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
956   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
957 } HASH_TypeDef;
958 
959 /**
960   * @brief HASH_DIGEST
961   */
962 
963 typedef struct
964 {
965   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
966 } HASH_DIGEST_TypeDef;
967 
968 /**
969   * @brief RNG
970   */
971 
972 typedef struct
973 {
974   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
975   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
976   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
977 } RNG_TypeDef;
978 
979 /**
980   * @brief USB_OTG_Core_Registers
981   */
982 typedef struct
983 {
984   __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
985   __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
986   __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
987   __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
988   __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
989   __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
990   __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
991   __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
992   __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
993   __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
994   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
995   __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
996   uint32_t Reserved30[2];             /*!< Reserved                                     030h */
997   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
998   __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
999   uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */
1000   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
1001   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
1002 } USB_OTG_GlobalTypeDef;
1003 
1004 /**
1005   * @brief USB_OTG_device_Registers
1006   */
1007 typedef struct
1008 {
1009   __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
1010   __IO uint32_t DCTL;            /*!< dev Control Register         804h */
1011   __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
1012   uint32_t Reserved0C;           /*!< Reserved                     80Ch */
1013   __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
1014   __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
1015   __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
1016   __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
1017   uint32_t  Reserved20;          /*!< Reserved                     820h */
1018   uint32_t Reserved9;            /*!< Reserved                     824h */
1019   __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
1020   __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
1021   __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
1022   __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
1023   __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
1024   __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
1025   uint32_t Reserved40;           /*!< dedicated EP mask            840h */
1026   __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
1027   uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
1028   __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
1029 } USB_OTG_DeviceTypeDef;
1030 
1031 /**
1032   * @brief USB_OTG_IN_Endpoint-Specific_Register
1033   */
1034 typedef struct
1035 {
1036   __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
1037   uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
1038   __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
1039   uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
1040   __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
1041   __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
1042   __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1043   uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1044 } USB_OTG_INEndpointTypeDef;
1045 
1046 /**
1047   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1048   */
1049 typedef struct
1050 {
1051   __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
1052   uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
1053   __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
1054   uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
1055   __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
1056   __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
1057   uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1058 } USB_OTG_OUTEndpointTypeDef;
1059 
1060 /**
1061   * @brief USB_OTG_Host_Mode_Register_Structures
1062   */
1063 typedef struct
1064 {
1065   __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
1066   __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
1067   __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
1068   uint32_t Reserved40C;           /*!< Reserved                             40Ch */
1069   __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
1070   __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
1071   __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
1072 } USB_OTG_HostTypeDef;
1073 
1074 /**
1075   * @brief USB_OTG_Host_Channel_Specific_Registers
1076   */
1077 typedef struct
1078 {
1079   __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
1080   __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
1081   __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
1082   __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
1083   __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
1084   __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
1085   uint32_t Reserved[2];           /*!< Reserved                                      */
1086 } USB_OTG_HostChannelTypeDef;
1087 
1088 /**
1089   * @}
1090   */
1091 
1092 /** @addtogroup Peripheral_memory_map
1093   * @{
1094   */
1095 #define FLASH_BASE            0x08000000UL /*!< FLASH(up to 2 MB) base address in the alias region                         */
1096 #define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
1097 #define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */
1098 #define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
1099 #define SRAM3_BASE            0x20020000UL /*!< SRAM3(64 KB) base address in the alias region                              */
1100 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
1101 #define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
1102 #define FMC_R_BASE            0xA0000000UL /*!< FMC registers base address                                                 */
1103 #define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
1104 #define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
1105 #define SRAM3_BB_BASE         0x22400000UL /*!< SRAM3(64 KB) base address in the bit-band region                           */
1106 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
1107 #define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
1108 #define FLASH_END             0x081FFFFFUL /*!< FLASH end address                                                          */
1109 #define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
1110 #define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
1111 #define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */
1112 
1113 /* Legacy defines */
1114 #define SRAM_BASE             SRAM1_BASE
1115 #define SRAM_BB_BASE          SRAM1_BB_BASE
1116 
1117 /*!< Peripheral memory map */
1118 #define APB1PERIPH_BASE       PERIPH_BASE
1119 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1120 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1121 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
1122 
1123 /*!< APB1 peripherals */
1124 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1125 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1126 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1127 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
1128 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1129 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1130 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
1131 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
1132 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
1133 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1134 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1135 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1136 #define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
1137 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1138 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1139 #define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
1140 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1141 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1142 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1143 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1144 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1145 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1146 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
1147 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
1148 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
1149 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1150 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
1151 #define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)
1152 #define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)
1153 
1154 /*!< APB2 peripherals */
1155 #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
1156 #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
1157 #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
1158 #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
1159 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
1160 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
1161 #define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
1162 #define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
1163 /* Legacy define */
1164 #define ADC_BASE               ADC123_COMMON_BASE
1165 #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1166 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1167 #define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)
1168 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
1169 #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1170 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
1171 #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
1172 #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
1173 #define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
1174 #define SPI6_BASE             (APB2PERIPH_BASE + 0x5400UL)
1175 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)
1176 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
1177 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
1178 #define LTDC_BASE             (APB2PERIPH_BASE + 0x6800UL)
1179 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
1180 #define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
1181 
1182 /*!< AHB1 peripherals */
1183 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
1184 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
1185 #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
1186 #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
1187 #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
1188 #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
1189 #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
1190 #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
1191 #define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
1192 #define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400UL)
1193 #define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800UL)
1194 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1195 #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
1196 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
1197 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
1198 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
1199 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
1200 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
1201 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
1202 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
1203 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
1204 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
1205 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
1206 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
1207 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
1208 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
1209 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
1210 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
1211 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
1212 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
1213 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
1214 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
1215 #define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
1216 #define ETH_MAC_BASE          (ETH_BASE)
1217 #define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
1218 #define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
1219 #define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
1220 #define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000UL)
1221 
1222 /*!< AHB2 peripherals */
1223 #define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
1224 #define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000UL)
1225 #define HASH_BASE             (AHB2PERIPH_BASE + 0x60400UL)
1226 #define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710UL)
1227 #define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
1228 
1229 /*!< FMC Bankx registers base address */
1230 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
1231 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
1232 #define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060UL)
1233 #define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0UL)
1234 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
1235 
1236 
1237 /*!< Debug MCU registers base address */
1238 #define DBGMCU_BASE           0xE0042000UL
1239 /*!< USB registers base address */
1240 #define USB_OTG_HS_PERIPH_BASE               0x40040000UL
1241 #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
1242 
1243 #define USB_OTG_GLOBAL_BASE                  0x000UL
1244 #define USB_OTG_DEVICE_BASE                  0x800UL
1245 #define USB_OTG_IN_ENDPOINT_BASE             0x900UL
1246 #define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
1247 #define USB_OTG_EP_REG_SIZE                  0x20UL
1248 #define USB_OTG_HOST_BASE                    0x400UL
1249 #define USB_OTG_HOST_PORT_BASE               0x440UL
1250 #define USB_OTG_HOST_CHANNEL_BASE            0x500UL
1251 #define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
1252 #define USB_OTG_PCGCCTL_BASE                 0xE00UL
1253 #define USB_OTG_FIFO_BASE                    0x1000UL
1254 #define USB_OTG_FIFO_SIZE                    0x1000UL
1255 
1256 #define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
1257 #define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
1258 #define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
1259 /**
1260   * @}
1261   */
1262 
1263 /** @addtogroup Peripheral_declaration
1264   * @{
1265   */
1266 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1267 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1268 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1269 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1270 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1271 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1272 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1273 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1274 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1275 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1276 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1277 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1278 #define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
1279 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1280 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1281 #define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
1282 #define USART2              ((USART_TypeDef *) USART2_BASE)
1283 #define USART3              ((USART_TypeDef *) USART3_BASE)
1284 #define UART4               ((USART_TypeDef *) UART4_BASE)
1285 #define UART5               ((USART_TypeDef *) UART5_BASE)
1286 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1287 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1288 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1289 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1290 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1291 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1292 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
1293 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1294 #define UART7               ((USART_TypeDef *) UART7_BASE)
1295 #define UART8               ((USART_TypeDef *) UART8_BASE)
1296 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1297 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1298 #define USART1              ((USART_TypeDef *) USART1_BASE)
1299 #define USART6              ((USART_TypeDef *) USART6_BASE)
1300 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1301 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1302 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1303 #define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1304 /* Legacy define */
1305 #define ADC                  ADC123_COMMON
1306 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
1307 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1308 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
1309 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1310 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1311 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1312 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1313 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1314 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
1315 #define SPI6                ((SPI_TypeDef *) SPI6_BASE)
1316 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1317 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1318 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1319 #define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
1320 #define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1321 #define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1322 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1323 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1324 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1325 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1326 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1327 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1328 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1329 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1330 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
1331 #define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
1332 #define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
1333 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1334 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1335 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1336 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1337 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1338 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1339 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1340 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1341 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1342 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1343 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1344 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1345 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1346 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1347 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1348 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1349 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1350 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1351 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1352 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1353 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1354 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
1355 #define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
1356 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1357 #define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
1358 #define HASH                ((HASH_TypeDef *) HASH_BASE)
1359 #define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1360 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1361 #define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1362 #define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1363 #define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1364 #define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1365 #define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1366 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1367 #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1368 #define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1369 
1370 /**
1371   * @}
1372   */
1373 
1374 /** @addtogroup Exported_constants
1375   * @{
1376   */
1377 
1378   /** @addtogroup Peripheral_Registers_Bits_Definition
1379   * @{
1380   */
1381 
1382 /******************************************************************************/
1383 /*                         Peripheral Registers_Bits_Definition               */
1384 /******************************************************************************/
1385 
1386 /******************************************************************************/
1387 /*                                                                            */
1388 /*                        Analog to Digital Converter                         */
1389 /*                                                                            */
1390 /******************************************************************************/
1391 /*
1392  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1393  */
1394 #define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */
1395 
1396 /********************  Bit definition for ADC_SR register  ********************/
1397 #define ADC_SR_AWD_Pos            (0U)
1398 #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
1399 #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
1400 #define ADC_SR_EOC_Pos            (1U)
1401 #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
1402 #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
1403 #define ADC_SR_JEOC_Pos           (2U)
1404 #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
1405 #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
1406 #define ADC_SR_JSTRT_Pos          (3U)
1407 #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
1408 #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
1409 #define ADC_SR_STRT_Pos           (4U)
1410 #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
1411 #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
1412 #define ADC_SR_OVR_Pos            (5U)
1413 #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
1414 #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
1415 
1416 /*******************  Bit definition for ADC_CR1 register  ********************/
1417 #define ADC_CR1_AWDCH_Pos         (0U)
1418 #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
1419 #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1420 #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
1421 #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
1422 #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
1423 #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
1424 #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
1425 #define ADC_CR1_EOCIE_Pos         (5U)
1426 #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
1427 #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
1428 #define ADC_CR1_AWDIE_Pos         (6U)
1429 #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
1430 #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
1431 #define ADC_CR1_JEOCIE_Pos        (7U)
1432 #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
1433 #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
1434 #define ADC_CR1_SCAN_Pos          (8U)
1435 #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
1436 #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
1437 #define ADC_CR1_AWDSGL_Pos        (9U)
1438 #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
1439 #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
1440 #define ADC_CR1_JAUTO_Pos         (10U)
1441 #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
1442 #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
1443 #define ADC_CR1_DISCEN_Pos        (11U)
1444 #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
1445 #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
1446 #define ADC_CR1_JDISCEN_Pos       (12U)
1447 #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
1448 #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
1449 #define ADC_CR1_DISCNUM_Pos       (13U)
1450 #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
1451 #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1452 #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
1453 #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
1454 #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
1455 #define ADC_CR1_JAWDEN_Pos        (22U)
1456 #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
1457 #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
1458 #define ADC_CR1_AWDEN_Pos         (23U)
1459 #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
1460 #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
1461 #define ADC_CR1_RES_Pos           (24U)
1462 #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
1463 #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
1464 #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
1465 #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
1466 #define ADC_CR1_OVRIE_Pos         (26U)
1467 #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
1468 #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
1469 
1470 /*******************  Bit definition for ADC_CR2 register  ********************/
1471 #define ADC_CR2_ADON_Pos          (0U)
1472 #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
1473 #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
1474 #define ADC_CR2_CONT_Pos          (1U)
1475 #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
1476 #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
1477 #define ADC_CR2_DMA_Pos           (8U)
1478 #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
1479 #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
1480 #define ADC_CR2_DDS_Pos           (9U)
1481 #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
1482 #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
1483 #define ADC_CR2_EOCS_Pos          (10U)
1484 #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
1485 #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
1486 #define ADC_CR2_ALIGN_Pos         (11U)
1487 #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
1488 #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
1489 #define ADC_CR2_JEXTSEL_Pos       (16U)
1490 #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
1491 #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1492 #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
1493 #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
1494 #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
1495 #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
1496 #define ADC_CR2_JEXTEN_Pos        (20U)
1497 #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
1498 #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1499 #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
1500 #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
1501 #define ADC_CR2_JSWSTART_Pos      (22U)
1502 #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
1503 #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
1504 #define ADC_CR2_EXTSEL_Pos        (24U)
1505 #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
1506 #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1507 #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
1508 #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
1509 #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
1510 #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
1511 #define ADC_CR2_EXTEN_Pos         (28U)
1512 #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
1513 #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1514 #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
1515 #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
1516 #define ADC_CR2_SWSTART_Pos       (30U)
1517 #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
1518 #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
1519 
1520 /******************  Bit definition for ADC_SMPR1 register  *******************/
1521 #define ADC_SMPR1_SMP10_Pos       (0U)
1522 #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
1523 #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1524 #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
1525 #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
1526 #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
1527 #define ADC_SMPR1_SMP11_Pos       (3U)
1528 #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
1529 #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1530 #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
1531 #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
1532 #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
1533 #define ADC_SMPR1_SMP12_Pos       (6U)
1534 #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
1535 #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1536 #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
1537 #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
1538 #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
1539 #define ADC_SMPR1_SMP13_Pos       (9U)
1540 #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
1541 #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1542 #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
1543 #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
1544 #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
1545 #define ADC_SMPR1_SMP14_Pos       (12U)
1546 #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
1547 #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1548 #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
1549 #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
1550 #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
1551 #define ADC_SMPR1_SMP15_Pos       (15U)
1552 #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
1553 #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1554 #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
1555 #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
1556 #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
1557 #define ADC_SMPR1_SMP16_Pos       (18U)
1558 #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
1559 #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1560 #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
1561 #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
1562 #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
1563 #define ADC_SMPR1_SMP17_Pos       (21U)
1564 #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
1565 #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1566 #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
1567 #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
1568 #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
1569 #define ADC_SMPR1_SMP18_Pos       (24U)
1570 #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
1571 #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1572 #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
1573 #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
1574 #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
1575 
1576 /******************  Bit definition for ADC_SMPR2 register  *******************/
1577 #define ADC_SMPR2_SMP0_Pos        (0U)
1578 #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
1579 #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1580 #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
1581 #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
1582 #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
1583 #define ADC_SMPR2_SMP1_Pos        (3U)
1584 #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
1585 #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1586 #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
1587 #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
1588 #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
1589 #define ADC_SMPR2_SMP2_Pos        (6U)
1590 #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
1591 #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1592 #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
1593 #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
1594 #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
1595 #define ADC_SMPR2_SMP3_Pos        (9U)
1596 #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
1597 #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1598 #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
1599 #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
1600 #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
1601 #define ADC_SMPR2_SMP4_Pos        (12U)
1602 #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
1603 #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1604 #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
1605 #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
1606 #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
1607 #define ADC_SMPR2_SMP5_Pos        (15U)
1608 #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
1609 #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1610 #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
1611 #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
1612 #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
1613 #define ADC_SMPR2_SMP6_Pos        (18U)
1614 #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
1615 #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1616 #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
1617 #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
1618 #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
1619 #define ADC_SMPR2_SMP7_Pos        (21U)
1620 #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
1621 #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1622 #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
1623 #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
1624 #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
1625 #define ADC_SMPR2_SMP8_Pos        (24U)
1626 #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
1627 #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1628 #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
1629 #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
1630 #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
1631 #define ADC_SMPR2_SMP9_Pos        (27U)
1632 #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
1633 #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1634 #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
1635 #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
1636 #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
1637 
1638 /******************  Bit definition for ADC_JOFR1 register  *******************/
1639 #define ADC_JOFR1_JOFFSET1_Pos    (0U)
1640 #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
1641 #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
1642 
1643 /******************  Bit definition for ADC_JOFR2 register  *******************/
1644 #define ADC_JOFR2_JOFFSET2_Pos    (0U)
1645 #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
1646 #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
1647 
1648 /******************  Bit definition for ADC_JOFR3 register  *******************/
1649 #define ADC_JOFR3_JOFFSET3_Pos    (0U)
1650 #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
1651 #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
1652 
1653 /******************  Bit definition for ADC_JOFR4 register  *******************/
1654 #define ADC_JOFR4_JOFFSET4_Pos    (0U)
1655 #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
1656 #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
1657 
1658 /*******************  Bit definition for ADC_HTR register  ********************/
1659 #define ADC_HTR_HT_Pos            (0U)
1660 #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1661 #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1662 
1663 /*******************  Bit definition for ADC_LTR register  ********************/
1664 #define ADC_LTR_LT_Pos            (0U)
1665 #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1666 #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1667 
1668 /*******************  Bit definition for ADC_SQR1 register  *******************/
1669 #define ADC_SQR1_SQ13_Pos         (0U)
1670 #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1671 #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1672 #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1673 #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1674 #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1675 #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1676 #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1677 #define ADC_SQR1_SQ14_Pos         (5U)
1678 #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1679 #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1680 #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1681 #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1682 #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1683 #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1684 #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1685 #define ADC_SQR1_SQ15_Pos         (10U)
1686 #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1687 #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1688 #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1689 #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1690 #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1691 #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1692 #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1693 #define ADC_SQR1_SQ16_Pos         (15U)
1694 #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1695 #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1696 #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1697 #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1698 #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1699 #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1700 #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1701 #define ADC_SQR1_L_Pos            (20U)
1702 #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1703 #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1704 #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1705 #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1706 #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1707 #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1708 
1709 /*******************  Bit definition for ADC_SQR2 register  *******************/
1710 #define ADC_SQR2_SQ7_Pos          (0U)
1711 #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1712 #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1713 #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1714 #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1715 #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1716 #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1717 #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1718 #define ADC_SQR2_SQ8_Pos          (5U)
1719 #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1720 #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1721 #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1722 #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1723 #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1724 #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1725 #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1726 #define ADC_SQR2_SQ9_Pos          (10U)
1727 #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1728 #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1729 #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1730 #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1731 #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1732 #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1733 #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1734 #define ADC_SQR2_SQ10_Pos         (15U)
1735 #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1736 #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1737 #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1738 #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1739 #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1740 #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1741 #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1742 #define ADC_SQR2_SQ11_Pos         (20U)
1743 #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1744 #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1745 #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1746 #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1747 #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1748 #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1749 #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1750 #define ADC_SQR2_SQ12_Pos         (25U)
1751 #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1752 #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1753 #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1754 #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1755 #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1756 #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1757 #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1758 
1759 /*******************  Bit definition for ADC_SQR3 register  *******************/
1760 #define ADC_SQR3_SQ1_Pos          (0U)
1761 #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1762 #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1763 #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1764 #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1765 #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1766 #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1767 #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1768 #define ADC_SQR3_SQ2_Pos          (5U)
1769 #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1770 #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1771 #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1772 #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1773 #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1774 #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1775 #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1776 #define ADC_SQR3_SQ3_Pos          (10U)
1777 #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1778 #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1779 #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1780 #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1781 #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1782 #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1783 #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1784 #define ADC_SQR3_SQ4_Pos          (15U)
1785 #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1786 #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1787 #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1788 #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1789 #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1790 #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1791 #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1792 #define ADC_SQR3_SQ5_Pos          (20U)
1793 #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1794 #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1795 #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1796 #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1797 #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1798 #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1799 #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1800 #define ADC_SQR3_SQ6_Pos          (25U)
1801 #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1802 #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1803 #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1804 #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1805 #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1806 #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1807 #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1808 
1809 /*******************  Bit definition for ADC_JSQR register  *******************/
1810 #define ADC_JSQR_JSQ1_Pos         (0U)
1811 #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1812 #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1813 #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1814 #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1815 #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1816 #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1817 #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1818 #define ADC_JSQR_JSQ2_Pos         (5U)
1819 #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1820 #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1821 #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1822 #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1823 #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1824 #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1825 #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1826 #define ADC_JSQR_JSQ3_Pos         (10U)
1827 #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1828 #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1829 #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1830 #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1831 #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1832 #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1833 #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1834 #define ADC_JSQR_JSQ4_Pos         (15U)
1835 #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1836 #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1837 #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1838 #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1839 #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1840 #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1841 #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1842 #define ADC_JSQR_JL_Pos           (20U)
1843 #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1844 #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1845 #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1846 #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1847 
1848 /*******************  Bit definition for ADC_JDR1 register  *******************/
1849 #define ADC_JDR1_JDATA_Pos        (0U)
1850 #define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
1851 #define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
1852 
1853 /*******************  Bit definition for ADC_JDR2 register  *******************/
1854 #define ADC_JDR2_JDATA_Pos        (0U)
1855 #define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
1856 #define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
1857 
1858 /*******************  Bit definition for ADC_JDR3 register  *******************/
1859 #define ADC_JDR3_JDATA_Pos        (0U)
1860 #define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
1861 #define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
1862 
1863 /*******************  Bit definition for ADC_JDR4 register  *******************/
1864 #define ADC_JDR4_JDATA_Pos        (0U)
1865 #define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
1866 #define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
1867 
1868 /********************  Bit definition for ADC_DR register  ********************/
1869 #define ADC_DR_DATA_Pos           (0U)
1870 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1871 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1872 #define ADC_DR_ADC2DATA_Pos       (16U)
1873 #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1874 #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1875 
1876 /*******************  Bit definition for ADC_CSR register  ********************/
1877 #define ADC_CSR_AWD1_Pos          (0U)
1878 #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1879 #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
1880 #define ADC_CSR_EOC1_Pos          (1U)
1881 #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1882 #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
1883 #define ADC_CSR_JEOC1_Pos         (2U)
1884 #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1885 #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1886 #define ADC_CSR_JSTRT1_Pos        (3U)
1887 #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1888 #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
1889 #define ADC_CSR_STRT1_Pos         (4U)
1890 #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1891 #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
1892 #define ADC_CSR_OVR1_Pos          (5U)
1893 #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1894 #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
1895 #define ADC_CSR_AWD2_Pos          (8U)
1896 #define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
1897 #define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
1898 #define ADC_CSR_EOC2_Pos          (9U)
1899 #define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
1900 #define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
1901 #define ADC_CSR_JEOC2_Pos         (10U)
1902 #define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
1903 #define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
1904 #define ADC_CSR_JSTRT2_Pos        (11U)
1905 #define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
1906 #define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
1907 #define ADC_CSR_STRT2_Pos         (12U)
1908 #define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
1909 #define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
1910 #define ADC_CSR_OVR2_Pos          (13U)
1911 #define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
1912 #define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
1913 #define ADC_CSR_AWD3_Pos          (16U)
1914 #define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
1915 #define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
1916 #define ADC_CSR_EOC3_Pos          (17U)
1917 #define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
1918 #define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
1919 #define ADC_CSR_JEOC3_Pos         (18U)
1920 #define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
1921 #define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
1922 #define ADC_CSR_JSTRT3_Pos        (19U)
1923 #define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
1924 #define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
1925 #define ADC_CSR_STRT3_Pos         (20U)
1926 #define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
1927 #define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
1928 #define ADC_CSR_OVR3_Pos          (21U)
1929 #define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
1930 #define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
1931 
1932 /* Legacy defines */
1933 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
1934 #define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
1935 #define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
1936 
1937 /*******************  Bit definition for ADC_CCR register  ********************/
1938 #define ADC_CCR_MULTI_Pos         (0U)
1939 #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
1940 #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1941 #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
1942 #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
1943 #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
1944 #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
1945 #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
1946 #define ADC_CCR_DELAY_Pos         (8U)
1947 #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
1948 #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1949 #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
1950 #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
1951 #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
1952 #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
1953 #define ADC_CCR_DDS_Pos           (13U)
1954 #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
1955 #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
1956 #define ADC_CCR_DMA_Pos           (14U)
1957 #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
1958 #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1959 #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
1960 #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
1961 #define ADC_CCR_ADCPRE_Pos        (16U)
1962 #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
1963 #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
1964 #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
1965 #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
1966 #define ADC_CCR_VBATE_Pos         (22U)
1967 #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
1968 #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
1969 #define ADC_CCR_TSVREFE_Pos       (23U)
1970 #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
1971 #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
1972 
1973 /*******************  Bit definition for ADC_CDR register  ********************/
1974 #define ADC_CDR_DATA1_Pos         (0U)
1975 #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
1976 #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
1977 #define ADC_CDR_DATA2_Pos         (16U)
1978 #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
1979 #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
1980 
1981 /* Legacy defines */
1982 #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
1983 #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
1984 
1985 /******************************************************************************/
1986 /*                                                                            */
1987 /*                         Controller Area Network                            */
1988 /*                                                                            */
1989 /******************************************************************************/
1990 /*!<CAN control and status registers */
1991 /*******************  Bit definition for CAN_MCR register  ********************/
1992 #define CAN_MCR_INRQ_Pos       (0U)
1993 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
1994 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
1995 #define CAN_MCR_SLEEP_Pos      (1U)
1996 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
1997 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
1998 #define CAN_MCR_TXFP_Pos       (2U)
1999 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
2000 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
2001 #define CAN_MCR_RFLM_Pos       (3U)
2002 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
2003 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
2004 #define CAN_MCR_NART_Pos       (4U)
2005 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
2006 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
2007 #define CAN_MCR_AWUM_Pos       (5U)
2008 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
2009 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
2010 #define CAN_MCR_ABOM_Pos       (6U)
2011 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
2012 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
2013 #define CAN_MCR_TTCM_Pos       (7U)
2014 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
2015 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
2016 #define CAN_MCR_RESET_Pos      (15U)
2017 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
2018 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
2019 #define CAN_MCR_DBF_Pos        (16U)
2020 #define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
2021 #define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
2022 /*******************  Bit definition for CAN_MSR register  ********************/
2023 #define CAN_MSR_INAK_Pos       (0U)
2024 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
2025 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
2026 #define CAN_MSR_SLAK_Pos       (1U)
2027 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
2028 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
2029 #define CAN_MSR_ERRI_Pos       (2U)
2030 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
2031 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
2032 #define CAN_MSR_WKUI_Pos       (3U)
2033 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
2034 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
2035 #define CAN_MSR_SLAKI_Pos      (4U)
2036 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
2037 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
2038 #define CAN_MSR_TXM_Pos        (8U)
2039 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
2040 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
2041 #define CAN_MSR_RXM_Pos        (9U)
2042 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
2043 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
2044 #define CAN_MSR_SAMP_Pos       (10U)
2045 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
2046 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
2047 #define CAN_MSR_RX_Pos         (11U)
2048 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
2049 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
2050 
2051 /*******************  Bit definition for CAN_TSR register  ********************/
2052 #define CAN_TSR_RQCP0_Pos      (0U)
2053 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
2054 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
2055 #define CAN_TSR_TXOK0_Pos      (1U)
2056 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
2057 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
2058 #define CAN_TSR_ALST0_Pos      (2U)
2059 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
2060 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
2061 #define CAN_TSR_TERR0_Pos      (3U)
2062 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
2063 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
2064 #define CAN_TSR_ABRQ0_Pos      (7U)
2065 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
2066 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
2067 #define CAN_TSR_RQCP1_Pos      (8U)
2068 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
2069 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
2070 #define CAN_TSR_TXOK1_Pos      (9U)
2071 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
2072 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
2073 #define CAN_TSR_ALST1_Pos      (10U)
2074 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
2075 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
2076 #define CAN_TSR_TERR1_Pos      (11U)
2077 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
2078 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
2079 #define CAN_TSR_ABRQ1_Pos      (15U)
2080 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
2081 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
2082 #define CAN_TSR_RQCP2_Pos      (16U)
2083 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
2084 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
2085 #define CAN_TSR_TXOK2_Pos      (17U)
2086 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
2087 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
2088 #define CAN_TSR_ALST2_Pos      (18U)
2089 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
2090 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
2091 #define CAN_TSR_TERR2_Pos      (19U)
2092 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
2093 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
2094 #define CAN_TSR_ABRQ2_Pos      (23U)
2095 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
2096 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
2097 #define CAN_TSR_CODE_Pos       (24U)
2098 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
2099 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
2100 
2101 #define CAN_TSR_TME_Pos        (26U)
2102 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
2103 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
2104 #define CAN_TSR_TME0_Pos       (26U)
2105 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
2106 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
2107 #define CAN_TSR_TME1_Pos       (27U)
2108 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
2109 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
2110 #define CAN_TSR_TME2_Pos       (28U)
2111 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
2112 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
2113 
2114 #define CAN_TSR_LOW_Pos        (29U)
2115 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
2116 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
2117 #define CAN_TSR_LOW0_Pos       (29U)
2118 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
2119 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
2120 #define CAN_TSR_LOW1_Pos       (30U)
2121 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
2122 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
2123 #define CAN_TSR_LOW2_Pos       (31U)
2124 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
2125 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
2126 
2127 /*******************  Bit definition for CAN_RF0R register  *******************/
2128 #define CAN_RF0R_FMP0_Pos      (0U)
2129 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
2130 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
2131 #define CAN_RF0R_FULL0_Pos     (3U)
2132 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
2133 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
2134 #define CAN_RF0R_FOVR0_Pos     (4U)
2135 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
2136 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
2137 #define CAN_RF0R_RFOM0_Pos     (5U)
2138 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
2139 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
2140 
2141 /*******************  Bit definition for CAN_RF1R register  *******************/
2142 #define CAN_RF1R_FMP1_Pos      (0U)
2143 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
2144 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
2145 #define CAN_RF1R_FULL1_Pos     (3U)
2146 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
2147 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
2148 #define CAN_RF1R_FOVR1_Pos     (4U)
2149 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
2150 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
2151 #define CAN_RF1R_RFOM1_Pos     (5U)
2152 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
2153 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
2154 
2155 /********************  Bit definition for CAN_IER register  *******************/
2156 #define CAN_IER_TMEIE_Pos      (0U)
2157 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
2158 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
2159 #define CAN_IER_FMPIE0_Pos     (1U)
2160 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
2161 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2162 #define CAN_IER_FFIE0_Pos      (2U)
2163 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
2164 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
2165 #define CAN_IER_FOVIE0_Pos     (3U)
2166 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
2167 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
2168 #define CAN_IER_FMPIE1_Pos     (4U)
2169 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
2170 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2171 #define CAN_IER_FFIE1_Pos      (5U)
2172 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
2173 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
2174 #define CAN_IER_FOVIE1_Pos     (6U)
2175 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
2176 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
2177 #define CAN_IER_EWGIE_Pos      (8U)
2178 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
2179 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
2180 #define CAN_IER_EPVIE_Pos      (9U)
2181 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
2182 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
2183 #define CAN_IER_BOFIE_Pos      (10U)
2184 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
2185 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
2186 #define CAN_IER_LECIE_Pos      (11U)
2187 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
2188 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
2189 #define CAN_IER_ERRIE_Pos      (15U)
2190 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
2191 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
2192 #define CAN_IER_WKUIE_Pos      (16U)
2193 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
2194 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
2195 #define CAN_IER_SLKIE_Pos      (17U)
2196 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
2197 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
2198 #define CAN_IER_EWGIE_Pos      (8U)
2199 
2200 /********************  Bit definition for CAN_ESR register  *******************/
2201 #define CAN_ESR_EWGF_Pos       (0U)
2202 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
2203 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
2204 #define CAN_ESR_EPVF_Pos       (1U)
2205 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
2206 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
2207 #define CAN_ESR_BOFF_Pos       (2U)
2208 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
2209 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2210 
2211 #define CAN_ESR_LEC_Pos        (4U)
2212 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
2213 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2214 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
2215 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
2216 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
2217 
2218 #define CAN_ESR_TEC_Pos        (16U)
2219 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2220 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2221 #define CAN_ESR_REC_Pos        (24U)
2222 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2223 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2224 
2225 /*******************  Bit definition for CAN_BTR register  ********************/
2226 #define CAN_BTR_BRP_Pos        (0U)
2227 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2228 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2229 #define CAN_BTR_TS1_Pos        (16U)
2230 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2231 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2232 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2233 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2234 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2235 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2236 #define CAN_BTR_TS2_Pos        (20U)
2237 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2238 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2239 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2240 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2241 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2242 #define CAN_BTR_SJW_Pos        (24U)
2243 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2244 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2245 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2246 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2247 #define CAN_BTR_LBKM_Pos       (30U)
2248 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2249 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2250 #define CAN_BTR_SILM_Pos       (31U)
2251 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2252 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2253 
2254 
2255 /*!<Mailbox registers */
2256 /******************  Bit definition for CAN_TI0R register  ********************/
2257 #define CAN_TI0R_TXRQ_Pos      (0U)
2258 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2259 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2260 #define CAN_TI0R_RTR_Pos       (1U)
2261 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2262 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2263 #define CAN_TI0R_IDE_Pos       (2U)
2264 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2265 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2266 #define CAN_TI0R_EXID_Pos      (3U)
2267 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2268 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2269 #define CAN_TI0R_STID_Pos      (21U)
2270 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2271 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2272 
2273 /******************  Bit definition for CAN_TDT0R register  *******************/
2274 #define CAN_TDT0R_DLC_Pos      (0U)
2275 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2276 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2277 #define CAN_TDT0R_TGT_Pos      (8U)
2278 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2279 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2280 #define CAN_TDT0R_TIME_Pos     (16U)
2281 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2282 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2283 
2284 /******************  Bit definition for CAN_TDL0R register  *******************/
2285 #define CAN_TDL0R_DATA0_Pos    (0U)
2286 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2287 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2288 #define CAN_TDL0R_DATA1_Pos    (8U)
2289 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2290 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2291 #define CAN_TDL0R_DATA2_Pos    (16U)
2292 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2293 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2294 #define CAN_TDL0R_DATA3_Pos    (24U)
2295 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2296 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2297 
2298 /******************  Bit definition for CAN_TDH0R register  *******************/
2299 #define CAN_TDH0R_DATA4_Pos    (0U)
2300 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2301 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2302 #define CAN_TDH0R_DATA5_Pos    (8U)
2303 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2304 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2305 #define CAN_TDH0R_DATA6_Pos    (16U)
2306 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2307 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2308 #define CAN_TDH0R_DATA7_Pos    (24U)
2309 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2310 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2311 
2312 /*******************  Bit definition for CAN_TI1R register  *******************/
2313 #define CAN_TI1R_TXRQ_Pos      (0U)
2314 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2315 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2316 #define CAN_TI1R_RTR_Pos       (1U)
2317 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2318 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2319 #define CAN_TI1R_IDE_Pos       (2U)
2320 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2321 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2322 #define CAN_TI1R_EXID_Pos      (3U)
2323 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2324 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2325 #define CAN_TI1R_STID_Pos      (21U)
2326 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2327 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2328 
2329 /*******************  Bit definition for CAN_TDT1R register  ******************/
2330 #define CAN_TDT1R_DLC_Pos      (0U)
2331 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2332 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2333 #define CAN_TDT1R_TGT_Pos      (8U)
2334 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2335 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2336 #define CAN_TDT1R_TIME_Pos     (16U)
2337 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2338 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2339 
2340 /*******************  Bit definition for CAN_TDL1R register  ******************/
2341 #define CAN_TDL1R_DATA0_Pos    (0U)
2342 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2343 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2344 #define CAN_TDL1R_DATA1_Pos    (8U)
2345 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2346 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2347 #define CAN_TDL1R_DATA2_Pos    (16U)
2348 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2349 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2350 #define CAN_TDL1R_DATA3_Pos    (24U)
2351 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2352 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2353 
2354 /*******************  Bit definition for CAN_TDH1R register  ******************/
2355 #define CAN_TDH1R_DATA4_Pos    (0U)
2356 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2357 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2358 #define CAN_TDH1R_DATA5_Pos    (8U)
2359 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2360 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2361 #define CAN_TDH1R_DATA6_Pos    (16U)
2362 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2363 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2364 #define CAN_TDH1R_DATA7_Pos    (24U)
2365 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2366 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2367 
2368 /*******************  Bit definition for CAN_TI2R register  *******************/
2369 #define CAN_TI2R_TXRQ_Pos      (0U)
2370 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2371 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2372 #define CAN_TI2R_RTR_Pos       (1U)
2373 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2374 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2375 #define CAN_TI2R_IDE_Pos       (2U)
2376 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2377 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2378 #define CAN_TI2R_EXID_Pos      (3U)
2379 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2380 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2381 #define CAN_TI2R_STID_Pos      (21U)
2382 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2383 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2384 
2385 /*******************  Bit definition for CAN_TDT2R register  ******************/
2386 #define CAN_TDT2R_DLC_Pos      (0U)
2387 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2388 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2389 #define CAN_TDT2R_TGT_Pos      (8U)
2390 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2391 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2392 #define CAN_TDT2R_TIME_Pos     (16U)
2393 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2394 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2395 
2396 /*******************  Bit definition for CAN_TDL2R register  ******************/
2397 #define CAN_TDL2R_DATA0_Pos    (0U)
2398 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2399 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2400 #define CAN_TDL2R_DATA1_Pos    (8U)
2401 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2402 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2403 #define CAN_TDL2R_DATA2_Pos    (16U)
2404 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2405 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2406 #define CAN_TDL2R_DATA3_Pos    (24U)
2407 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2408 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2409 
2410 /*******************  Bit definition for CAN_TDH2R register  ******************/
2411 #define CAN_TDH2R_DATA4_Pos    (0U)
2412 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2413 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2414 #define CAN_TDH2R_DATA5_Pos    (8U)
2415 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2416 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2417 #define CAN_TDH2R_DATA6_Pos    (16U)
2418 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2419 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2420 #define CAN_TDH2R_DATA7_Pos    (24U)
2421 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2422 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2423 
2424 /*******************  Bit definition for CAN_RI0R register  *******************/
2425 #define CAN_RI0R_RTR_Pos       (1U)
2426 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2427 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2428 #define CAN_RI0R_IDE_Pos       (2U)
2429 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2430 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2431 #define CAN_RI0R_EXID_Pos      (3U)
2432 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2433 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2434 #define CAN_RI0R_STID_Pos      (21U)
2435 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2436 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2437 
2438 /*******************  Bit definition for CAN_RDT0R register  ******************/
2439 #define CAN_RDT0R_DLC_Pos      (0U)
2440 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
2441 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2442 #define CAN_RDT0R_FMI_Pos      (8U)
2443 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
2444 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2445 #define CAN_RDT0R_TIME_Pos     (16U)
2446 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2447 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2448 
2449 /*******************  Bit definition for CAN_RDL0R register  ******************/
2450 #define CAN_RDL0R_DATA0_Pos    (0U)
2451 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2452 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2453 #define CAN_RDL0R_DATA1_Pos    (8U)
2454 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2455 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2456 #define CAN_RDL0R_DATA2_Pos    (16U)
2457 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2458 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2459 #define CAN_RDL0R_DATA3_Pos    (24U)
2460 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2461 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2462 
2463 /*******************  Bit definition for CAN_RDH0R register  ******************/
2464 #define CAN_RDH0R_DATA4_Pos    (0U)
2465 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2466 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2467 #define CAN_RDH0R_DATA5_Pos    (8U)
2468 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2469 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2470 #define CAN_RDH0R_DATA6_Pos    (16U)
2471 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2472 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2473 #define CAN_RDH0R_DATA7_Pos    (24U)
2474 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2475 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2476 
2477 /*******************  Bit definition for CAN_RI1R register  *******************/
2478 #define CAN_RI1R_RTR_Pos       (1U)
2479 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
2480 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
2481 #define CAN_RI1R_IDE_Pos       (2U)
2482 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
2483 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
2484 #define CAN_RI1R_EXID_Pos      (3U)
2485 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2486 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
2487 #define CAN_RI1R_STID_Pos      (21U)
2488 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
2489 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2490 
2491 /*******************  Bit definition for CAN_RDT1R register  ******************/
2492 #define CAN_RDT1R_DLC_Pos      (0U)
2493 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
2494 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
2495 #define CAN_RDT1R_FMI_Pos      (8U)
2496 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
2497 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2498 #define CAN_RDT1R_TIME_Pos     (16U)
2499 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2500 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2501 
2502 /*******************  Bit definition for CAN_RDL1R register  ******************/
2503 #define CAN_RDL1R_DATA0_Pos    (0U)
2504 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2505 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2506 #define CAN_RDL1R_DATA1_Pos    (8U)
2507 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2508 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2509 #define CAN_RDL1R_DATA2_Pos    (16U)
2510 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2511 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2512 #define CAN_RDL1R_DATA3_Pos    (24U)
2513 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2514 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2515 
2516 /*******************  Bit definition for CAN_RDH1R register  ******************/
2517 #define CAN_RDH1R_DATA4_Pos    (0U)
2518 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2519 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2520 #define CAN_RDH1R_DATA5_Pos    (8U)
2521 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2522 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2523 #define CAN_RDH1R_DATA6_Pos    (16U)
2524 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2525 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2526 #define CAN_RDH1R_DATA7_Pos    (24U)
2527 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2528 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2529 
2530 /*!<CAN filter registers */
2531 /*******************  Bit definition for CAN_FMR register  ********************/
2532 #define CAN_FMR_FINIT_Pos      (0U)
2533 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
2534 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
2535 #define CAN_FMR_CAN2SB_Pos     (8U)
2536 #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
2537 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
2538 
2539 /*******************  Bit definition for CAN_FM1R register  *******************/
2540 #define CAN_FM1R_FBM_Pos       (0U)
2541 #define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
2542 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2543 #define CAN_FM1R_FBM0_Pos      (0U)
2544 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
2545 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
2546 #define CAN_FM1R_FBM1_Pos      (1U)
2547 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
2548 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
2549 #define CAN_FM1R_FBM2_Pos      (2U)
2550 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
2551 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
2552 #define CAN_FM1R_FBM3_Pos      (3U)
2553 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
2554 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
2555 #define CAN_FM1R_FBM4_Pos      (4U)
2556 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
2557 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
2558 #define CAN_FM1R_FBM5_Pos      (5U)
2559 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
2560 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
2561 #define CAN_FM1R_FBM6_Pos      (6U)
2562 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
2563 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
2564 #define CAN_FM1R_FBM7_Pos      (7U)
2565 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
2566 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
2567 #define CAN_FM1R_FBM8_Pos      (8U)
2568 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
2569 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
2570 #define CAN_FM1R_FBM9_Pos      (9U)
2571 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
2572 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
2573 #define CAN_FM1R_FBM10_Pos     (10U)
2574 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
2575 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2576 #define CAN_FM1R_FBM11_Pos     (11U)
2577 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
2578 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2579 #define CAN_FM1R_FBM12_Pos     (12U)
2580 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
2581 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2582 #define CAN_FM1R_FBM13_Pos     (13U)
2583 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
2584 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2585 #define CAN_FM1R_FBM14_Pos     (14U)
2586 #define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
2587 #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
2588 #define CAN_FM1R_FBM15_Pos     (15U)
2589 #define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
2590 #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
2591 #define CAN_FM1R_FBM16_Pos     (16U)
2592 #define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
2593 #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
2594 #define CAN_FM1R_FBM17_Pos     (17U)
2595 #define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
2596 #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
2597 #define CAN_FM1R_FBM18_Pos     (18U)
2598 #define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
2599 #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
2600 #define CAN_FM1R_FBM19_Pos     (19U)
2601 #define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
2602 #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
2603 #define CAN_FM1R_FBM20_Pos     (20U)
2604 #define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
2605 #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
2606 #define CAN_FM1R_FBM21_Pos     (21U)
2607 #define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
2608 #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
2609 #define CAN_FM1R_FBM22_Pos     (22U)
2610 #define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
2611 #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
2612 #define CAN_FM1R_FBM23_Pos     (23U)
2613 #define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
2614 #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
2615 #define CAN_FM1R_FBM24_Pos     (24U)
2616 #define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
2617 #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
2618 #define CAN_FM1R_FBM25_Pos     (25U)
2619 #define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
2620 #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
2621 #define CAN_FM1R_FBM26_Pos     (26U)
2622 #define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
2623 #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
2624 #define CAN_FM1R_FBM27_Pos     (27U)
2625 #define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
2626 #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
2627 
2628 /*******************  Bit definition for CAN_FS1R register  *******************/
2629 #define CAN_FS1R_FSC_Pos       (0U)
2630 #define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
2631 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
2632 #define CAN_FS1R_FSC0_Pos      (0U)
2633 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
2634 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
2635 #define CAN_FS1R_FSC1_Pos      (1U)
2636 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
2637 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
2638 #define CAN_FS1R_FSC2_Pos      (2U)
2639 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
2640 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
2641 #define CAN_FS1R_FSC3_Pos      (3U)
2642 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
2643 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
2644 #define CAN_FS1R_FSC4_Pos      (4U)
2645 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
2646 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
2647 #define CAN_FS1R_FSC5_Pos      (5U)
2648 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
2649 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
2650 #define CAN_FS1R_FSC6_Pos      (6U)
2651 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
2652 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
2653 #define CAN_FS1R_FSC7_Pos      (7U)
2654 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
2655 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
2656 #define CAN_FS1R_FSC8_Pos      (8U)
2657 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
2658 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
2659 #define CAN_FS1R_FSC9_Pos      (9U)
2660 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
2661 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
2662 #define CAN_FS1R_FSC10_Pos     (10U)
2663 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
2664 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2665 #define CAN_FS1R_FSC11_Pos     (11U)
2666 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
2667 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2668 #define CAN_FS1R_FSC12_Pos     (12U)
2669 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
2670 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2671 #define CAN_FS1R_FSC13_Pos     (13U)
2672 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
2673 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2674 #define CAN_FS1R_FSC14_Pos     (14U)
2675 #define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
2676 #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
2677 #define CAN_FS1R_FSC15_Pos     (15U)
2678 #define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
2679 #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
2680 #define CAN_FS1R_FSC16_Pos     (16U)
2681 #define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
2682 #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
2683 #define CAN_FS1R_FSC17_Pos     (17U)
2684 #define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
2685 #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
2686 #define CAN_FS1R_FSC18_Pos     (18U)
2687 #define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
2688 #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
2689 #define CAN_FS1R_FSC19_Pos     (19U)
2690 #define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
2691 #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
2692 #define CAN_FS1R_FSC20_Pos     (20U)
2693 #define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
2694 #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
2695 #define CAN_FS1R_FSC21_Pos     (21U)
2696 #define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
2697 #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
2698 #define CAN_FS1R_FSC22_Pos     (22U)
2699 #define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
2700 #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
2701 #define CAN_FS1R_FSC23_Pos     (23U)
2702 #define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
2703 #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
2704 #define CAN_FS1R_FSC24_Pos     (24U)
2705 #define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
2706 #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
2707 #define CAN_FS1R_FSC25_Pos     (25U)
2708 #define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
2709 #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
2710 #define CAN_FS1R_FSC26_Pos     (26U)
2711 #define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
2712 #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
2713 #define CAN_FS1R_FSC27_Pos     (27U)
2714 #define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
2715 #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
2716 
2717 /******************  Bit definition for CAN_FFA1R register  *******************/
2718 #define CAN_FFA1R_FFA_Pos      (0U)
2719 #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
2720 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2721 #define CAN_FFA1R_FFA0_Pos     (0U)
2722 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
2723 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
2724 #define CAN_FFA1R_FFA1_Pos     (1U)
2725 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
2726 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
2727 #define CAN_FFA1R_FFA2_Pos     (2U)
2728 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
2729 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
2730 #define CAN_FFA1R_FFA3_Pos     (3U)
2731 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
2732 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
2733 #define CAN_FFA1R_FFA4_Pos     (4U)
2734 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
2735 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
2736 #define CAN_FFA1R_FFA5_Pos     (5U)
2737 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
2738 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
2739 #define CAN_FFA1R_FFA6_Pos     (6U)
2740 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
2741 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
2742 #define CAN_FFA1R_FFA7_Pos     (7U)
2743 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
2744 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
2745 #define CAN_FFA1R_FFA8_Pos     (8U)
2746 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
2747 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
2748 #define CAN_FFA1R_FFA9_Pos     (9U)
2749 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
2750 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
2751 #define CAN_FFA1R_FFA10_Pos    (10U)
2752 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
2753 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
2754 #define CAN_FFA1R_FFA11_Pos    (11U)
2755 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
2756 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
2757 #define CAN_FFA1R_FFA12_Pos    (12U)
2758 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
2759 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
2760 #define CAN_FFA1R_FFA13_Pos    (13U)
2761 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
2762 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
2763 #define CAN_FFA1R_FFA14_Pos    (14U)
2764 #define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
2765 #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
2766 #define CAN_FFA1R_FFA15_Pos    (15U)
2767 #define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
2768 #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
2769 #define CAN_FFA1R_FFA16_Pos    (16U)
2770 #define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
2771 #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
2772 #define CAN_FFA1R_FFA17_Pos    (17U)
2773 #define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
2774 #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
2775 #define CAN_FFA1R_FFA18_Pos    (18U)
2776 #define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
2777 #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
2778 #define CAN_FFA1R_FFA19_Pos    (19U)
2779 #define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
2780 #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
2781 #define CAN_FFA1R_FFA20_Pos    (20U)
2782 #define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
2783 #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
2784 #define CAN_FFA1R_FFA21_Pos    (21U)
2785 #define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
2786 #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
2787 #define CAN_FFA1R_FFA22_Pos    (22U)
2788 #define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
2789 #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
2790 #define CAN_FFA1R_FFA23_Pos    (23U)
2791 #define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
2792 #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
2793 #define CAN_FFA1R_FFA24_Pos    (24U)
2794 #define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
2795 #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
2796 #define CAN_FFA1R_FFA25_Pos    (25U)
2797 #define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
2798 #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
2799 #define CAN_FFA1R_FFA26_Pos    (26U)
2800 #define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
2801 #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
2802 #define CAN_FFA1R_FFA27_Pos    (27U)
2803 #define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
2804 #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
2805 
2806 /*******************  Bit definition for CAN_FA1R register  *******************/
2807 #define CAN_FA1R_FACT_Pos      (0U)
2808 #define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
2809 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
2810 #define CAN_FA1R_FACT0_Pos     (0U)
2811 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
2812 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
2813 #define CAN_FA1R_FACT1_Pos     (1U)
2814 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
2815 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
2816 #define CAN_FA1R_FACT2_Pos     (2U)
2817 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
2818 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
2819 #define CAN_FA1R_FACT3_Pos     (3U)
2820 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
2821 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
2822 #define CAN_FA1R_FACT4_Pos     (4U)
2823 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
2824 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
2825 #define CAN_FA1R_FACT5_Pos     (5U)
2826 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
2827 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
2828 #define CAN_FA1R_FACT6_Pos     (6U)
2829 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
2830 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
2831 #define CAN_FA1R_FACT7_Pos     (7U)
2832 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
2833 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
2834 #define CAN_FA1R_FACT8_Pos     (8U)
2835 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
2836 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
2837 #define CAN_FA1R_FACT9_Pos     (9U)
2838 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
2839 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
2840 #define CAN_FA1R_FACT10_Pos    (10U)
2841 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
2842 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
2843 #define CAN_FA1R_FACT11_Pos    (11U)
2844 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
2845 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
2846 #define CAN_FA1R_FACT12_Pos    (12U)
2847 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
2848 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
2849 #define CAN_FA1R_FACT13_Pos    (13U)
2850 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
2851 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
2852 #define CAN_FA1R_FACT14_Pos    (14U)
2853 #define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
2854 #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
2855 #define CAN_FA1R_FACT15_Pos    (15U)
2856 #define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
2857 #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
2858 #define CAN_FA1R_FACT16_Pos    (16U)
2859 #define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
2860 #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
2861 #define CAN_FA1R_FACT17_Pos    (17U)
2862 #define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
2863 #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
2864 #define CAN_FA1R_FACT18_Pos    (18U)
2865 #define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
2866 #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
2867 #define CAN_FA1R_FACT19_Pos    (19U)
2868 #define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
2869 #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
2870 #define CAN_FA1R_FACT20_Pos    (20U)
2871 #define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
2872 #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
2873 #define CAN_FA1R_FACT21_Pos    (21U)
2874 #define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
2875 #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
2876 #define CAN_FA1R_FACT22_Pos    (22U)
2877 #define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
2878 #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
2879 #define CAN_FA1R_FACT23_Pos    (23U)
2880 #define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
2881 #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
2882 #define CAN_FA1R_FACT24_Pos    (24U)
2883 #define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
2884 #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
2885 #define CAN_FA1R_FACT25_Pos    (25U)
2886 #define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
2887 #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
2888 #define CAN_FA1R_FACT26_Pos    (26U)
2889 #define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
2890 #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
2891 #define CAN_FA1R_FACT27_Pos    (27U)
2892 #define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
2893 #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
2894 
2895 
2896 /*******************  Bit definition for CAN_F0R1 register  *******************/
2897 #define CAN_F0R1_FB0_Pos       (0U)
2898 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
2899 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2900 #define CAN_F0R1_FB1_Pos       (1U)
2901 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
2902 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2903 #define CAN_F0R1_FB2_Pos       (2U)
2904 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
2905 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2906 #define CAN_F0R1_FB3_Pos       (3U)
2907 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
2908 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2909 #define CAN_F0R1_FB4_Pos       (4U)
2910 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
2911 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2912 #define CAN_F0R1_FB5_Pos       (5U)
2913 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
2914 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2915 #define CAN_F0R1_FB6_Pos       (6U)
2916 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
2917 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2918 #define CAN_F0R1_FB7_Pos       (7U)
2919 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
2920 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2921 #define CAN_F0R1_FB8_Pos       (8U)
2922 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
2923 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2924 #define CAN_F0R1_FB9_Pos       (9U)
2925 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
2926 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2927 #define CAN_F0R1_FB10_Pos      (10U)
2928 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
2929 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2930 #define CAN_F0R1_FB11_Pos      (11U)
2931 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
2932 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2933 #define CAN_F0R1_FB12_Pos      (12U)
2934 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
2935 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2936 #define CAN_F0R1_FB13_Pos      (13U)
2937 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
2938 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2939 #define CAN_F0R1_FB14_Pos      (14U)
2940 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
2941 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2942 #define CAN_F0R1_FB15_Pos      (15U)
2943 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
2944 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2945 #define CAN_F0R1_FB16_Pos      (16U)
2946 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2947 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2948 #define CAN_F0R1_FB17_Pos      (17U)
2949 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2950 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2951 #define CAN_F0R1_FB18_Pos      (18U)
2952 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2953 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2954 #define CAN_F0R1_FB19_Pos      (19U)
2955 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2956 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2957 #define CAN_F0R1_FB20_Pos      (20U)
2958 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2959 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2960 #define CAN_F0R1_FB21_Pos      (21U)
2961 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2962 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2963 #define CAN_F0R1_FB22_Pos      (22U)
2964 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2965 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2966 #define CAN_F0R1_FB23_Pos      (23U)
2967 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2968 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2969 #define CAN_F0R1_FB24_Pos      (24U)
2970 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2971 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2972 #define CAN_F0R1_FB25_Pos      (25U)
2973 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2974 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2975 #define CAN_F0R1_FB26_Pos      (26U)
2976 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2977 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2978 #define CAN_F0R1_FB27_Pos      (27U)
2979 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2980 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2981 #define CAN_F0R1_FB28_Pos      (28U)
2982 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2983 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2984 #define CAN_F0R1_FB29_Pos      (29U)
2985 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
2986 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
2987 #define CAN_F0R1_FB30_Pos      (30U)
2988 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
2989 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
2990 #define CAN_F0R1_FB31_Pos      (31U)
2991 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
2992 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
2993 
2994 /*******************  Bit definition for CAN_F1R1 register  *******************/
2995 #define CAN_F1R1_FB0_Pos       (0U)
2996 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
2997 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
2998 #define CAN_F1R1_FB1_Pos       (1U)
2999 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
3000 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
3001 #define CAN_F1R1_FB2_Pos       (2U)
3002 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
3003 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
3004 #define CAN_F1R1_FB3_Pos       (3U)
3005 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
3006 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
3007 #define CAN_F1R1_FB4_Pos       (4U)
3008 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
3009 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
3010 #define CAN_F1R1_FB5_Pos       (5U)
3011 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
3012 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
3013 #define CAN_F1R1_FB6_Pos       (6U)
3014 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
3015 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
3016 #define CAN_F1R1_FB7_Pos       (7U)
3017 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
3018 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
3019 #define CAN_F1R1_FB8_Pos       (8U)
3020 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
3021 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
3022 #define CAN_F1R1_FB9_Pos       (9U)
3023 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
3024 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
3025 #define CAN_F1R1_FB10_Pos      (10U)
3026 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
3027 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
3028 #define CAN_F1R1_FB11_Pos      (11U)
3029 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
3030 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
3031 #define CAN_F1R1_FB12_Pos      (12U)
3032 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
3033 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
3034 #define CAN_F1R1_FB13_Pos      (13U)
3035 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
3036 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
3037 #define CAN_F1R1_FB14_Pos      (14U)
3038 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
3039 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
3040 #define CAN_F1R1_FB15_Pos      (15U)
3041 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
3042 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
3043 #define CAN_F1R1_FB16_Pos      (16U)
3044 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
3045 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
3046 #define CAN_F1R1_FB17_Pos      (17U)
3047 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
3048 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
3049 #define CAN_F1R1_FB18_Pos      (18U)
3050 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
3051 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
3052 #define CAN_F1R1_FB19_Pos      (19U)
3053 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
3054 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
3055 #define CAN_F1R1_FB20_Pos      (20U)
3056 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
3057 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
3058 #define CAN_F1R1_FB21_Pos      (21U)
3059 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
3060 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
3061 #define CAN_F1R1_FB22_Pos      (22U)
3062 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
3063 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
3064 #define CAN_F1R1_FB23_Pos      (23U)
3065 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
3066 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
3067 #define CAN_F1R1_FB24_Pos      (24U)
3068 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
3069 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
3070 #define CAN_F1R1_FB25_Pos      (25U)
3071 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
3072 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
3073 #define CAN_F1R1_FB26_Pos      (26U)
3074 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
3075 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
3076 #define CAN_F1R1_FB27_Pos      (27U)
3077 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
3078 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
3079 #define CAN_F1R1_FB28_Pos      (28U)
3080 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
3081 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
3082 #define CAN_F1R1_FB29_Pos      (29U)
3083 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
3084 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
3085 #define CAN_F1R1_FB30_Pos      (30U)
3086 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
3087 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
3088 #define CAN_F1R1_FB31_Pos      (31U)
3089 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
3090 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
3091 
3092 /*******************  Bit definition for CAN_F2R1 register  *******************/
3093 #define CAN_F2R1_FB0_Pos       (0U)
3094 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
3095 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
3096 #define CAN_F2R1_FB1_Pos       (1U)
3097 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
3098 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
3099 #define CAN_F2R1_FB2_Pos       (2U)
3100 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
3101 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
3102 #define CAN_F2R1_FB3_Pos       (3U)
3103 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
3104 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
3105 #define CAN_F2R1_FB4_Pos       (4U)
3106 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
3107 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
3108 #define CAN_F2R1_FB5_Pos       (5U)
3109 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
3110 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
3111 #define CAN_F2R1_FB6_Pos       (6U)
3112 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
3113 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
3114 #define CAN_F2R1_FB7_Pos       (7U)
3115 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
3116 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
3117 #define CAN_F2R1_FB8_Pos       (8U)
3118 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
3119 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
3120 #define CAN_F2R1_FB9_Pos       (9U)
3121 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
3122 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
3123 #define CAN_F2R1_FB10_Pos      (10U)
3124 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
3125 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
3126 #define CAN_F2R1_FB11_Pos      (11U)
3127 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
3128 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
3129 #define CAN_F2R1_FB12_Pos      (12U)
3130 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
3131 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3132 #define CAN_F2R1_FB13_Pos      (13U)
3133 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
3134 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
3135 #define CAN_F2R1_FB14_Pos      (14U)
3136 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
3137 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
3138 #define CAN_F2R1_FB15_Pos      (15U)
3139 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
3140 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
3141 #define CAN_F2R1_FB16_Pos      (16U)
3142 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
3143 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
3144 #define CAN_F2R1_FB17_Pos      (17U)
3145 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
3146 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
3147 #define CAN_F2R1_FB18_Pos      (18U)
3148 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
3149 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
3150 #define CAN_F2R1_FB19_Pos      (19U)
3151 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
3152 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
3153 #define CAN_F2R1_FB20_Pos      (20U)
3154 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
3155 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
3156 #define CAN_F2R1_FB21_Pos      (21U)
3157 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
3158 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
3159 #define CAN_F2R1_FB22_Pos      (22U)
3160 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
3161 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
3162 #define CAN_F2R1_FB23_Pos      (23U)
3163 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
3164 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
3165 #define CAN_F2R1_FB24_Pos      (24U)
3166 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
3167 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3168 #define CAN_F2R1_FB25_Pos      (25U)
3169 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
3170 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3171 #define CAN_F2R1_FB26_Pos      (26U)
3172 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
3173 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3174 #define CAN_F2R1_FB27_Pos      (27U)
3175 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
3176 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3177 #define CAN_F2R1_FB28_Pos      (28U)
3178 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
3179 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3180 #define CAN_F2R1_FB29_Pos      (29U)
3181 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
3182 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3183 #define CAN_F2R1_FB30_Pos      (30U)
3184 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
3185 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3186 #define CAN_F2R1_FB31_Pos      (31U)
3187 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
3188 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3189 
3190 /*******************  Bit definition for CAN_F3R1 register  *******************/
3191 #define CAN_F3R1_FB0_Pos       (0U)
3192 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
3193 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3194 #define CAN_F3R1_FB1_Pos       (1U)
3195 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
3196 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3197 #define CAN_F3R1_FB2_Pos       (2U)
3198 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
3199 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3200 #define CAN_F3R1_FB3_Pos       (3U)
3201 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
3202 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3203 #define CAN_F3R1_FB4_Pos       (4U)
3204 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
3205 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3206 #define CAN_F3R1_FB5_Pos       (5U)
3207 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
3208 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3209 #define CAN_F3R1_FB6_Pos       (6U)
3210 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3211 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3212 #define CAN_F3R1_FB7_Pos       (7U)
3213 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3214 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3215 #define CAN_F3R1_FB8_Pos       (8U)
3216 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3217 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3218 #define CAN_F3R1_FB9_Pos       (9U)
3219 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3220 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3221 #define CAN_F3R1_FB10_Pos      (10U)
3222 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3223 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3224 #define CAN_F3R1_FB11_Pos      (11U)
3225 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3226 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3227 #define CAN_F3R1_FB12_Pos      (12U)
3228 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3229 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3230 #define CAN_F3R1_FB13_Pos      (13U)
3231 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3232 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3233 #define CAN_F3R1_FB14_Pos      (14U)
3234 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3235 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3236 #define CAN_F3R1_FB15_Pos      (15U)
3237 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3238 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3239 #define CAN_F3R1_FB16_Pos      (16U)
3240 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3241 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3242 #define CAN_F3R1_FB17_Pos      (17U)
3243 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3244 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3245 #define CAN_F3R1_FB18_Pos      (18U)
3246 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3247 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3248 #define CAN_F3R1_FB19_Pos      (19U)
3249 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3250 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3251 #define CAN_F3R1_FB20_Pos      (20U)
3252 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3253 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3254 #define CAN_F3R1_FB21_Pos      (21U)
3255 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3256 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3257 #define CAN_F3R1_FB22_Pos      (22U)
3258 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3259 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3260 #define CAN_F3R1_FB23_Pos      (23U)
3261 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3262 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3263 #define CAN_F3R1_FB24_Pos      (24U)
3264 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3265 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3266 #define CAN_F3R1_FB25_Pos      (25U)
3267 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3268 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3269 #define CAN_F3R1_FB26_Pos      (26U)
3270 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3271 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3272 #define CAN_F3R1_FB27_Pos      (27U)
3273 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3274 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3275 #define CAN_F3R1_FB28_Pos      (28U)
3276 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3277 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3278 #define CAN_F3R1_FB29_Pos      (29U)
3279 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3280 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3281 #define CAN_F3R1_FB30_Pos      (30U)
3282 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3283 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3284 #define CAN_F3R1_FB31_Pos      (31U)
3285 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3286 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3287 
3288 /*******************  Bit definition for CAN_F4R1 register  *******************/
3289 #define CAN_F4R1_FB0_Pos       (0U)
3290 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3291 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3292 #define CAN_F4R1_FB1_Pos       (1U)
3293 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3294 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3295 #define CAN_F4R1_FB2_Pos       (2U)
3296 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3297 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3298 #define CAN_F4R1_FB3_Pos       (3U)
3299 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3300 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3301 #define CAN_F4R1_FB4_Pos       (4U)
3302 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3303 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3304 #define CAN_F4R1_FB5_Pos       (5U)
3305 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3306 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3307 #define CAN_F4R1_FB6_Pos       (6U)
3308 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3309 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3310 #define CAN_F4R1_FB7_Pos       (7U)
3311 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3312 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3313 #define CAN_F4R1_FB8_Pos       (8U)
3314 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3315 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3316 #define CAN_F4R1_FB9_Pos       (9U)
3317 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3318 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3319 #define CAN_F4R1_FB10_Pos      (10U)
3320 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3321 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3322 #define CAN_F4R1_FB11_Pos      (11U)
3323 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3324 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3325 #define CAN_F4R1_FB12_Pos      (12U)
3326 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3327 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3328 #define CAN_F4R1_FB13_Pos      (13U)
3329 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3330 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3331 #define CAN_F4R1_FB14_Pos      (14U)
3332 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3333 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3334 #define CAN_F4R1_FB15_Pos      (15U)
3335 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3336 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3337 #define CAN_F4R1_FB16_Pos      (16U)
3338 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3339 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3340 #define CAN_F4R1_FB17_Pos      (17U)
3341 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3342 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3343 #define CAN_F4R1_FB18_Pos      (18U)
3344 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3345 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3346 #define CAN_F4R1_FB19_Pos      (19U)
3347 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3348 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3349 #define CAN_F4R1_FB20_Pos      (20U)
3350 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3351 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3352 #define CAN_F4R1_FB21_Pos      (21U)
3353 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3354 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3355 #define CAN_F4R1_FB22_Pos      (22U)
3356 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3357 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3358 #define CAN_F4R1_FB23_Pos      (23U)
3359 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3360 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3361 #define CAN_F4R1_FB24_Pos      (24U)
3362 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3363 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3364 #define CAN_F4R1_FB25_Pos      (25U)
3365 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3366 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3367 #define CAN_F4R1_FB26_Pos      (26U)
3368 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3369 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3370 #define CAN_F4R1_FB27_Pos      (27U)
3371 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3372 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3373 #define CAN_F4R1_FB28_Pos      (28U)
3374 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3375 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3376 #define CAN_F4R1_FB29_Pos      (29U)
3377 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3378 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3379 #define CAN_F4R1_FB30_Pos      (30U)
3380 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3381 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3382 #define CAN_F4R1_FB31_Pos      (31U)
3383 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3384 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3385 
3386 /*******************  Bit definition for CAN_F5R1 register  *******************/
3387 #define CAN_F5R1_FB0_Pos       (0U)
3388 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3389 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3390 #define CAN_F5R1_FB1_Pos       (1U)
3391 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3392 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3393 #define CAN_F5R1_FB2_Pos       (2U)
3394 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3395 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3396 #define CAN_F5R1_FB3_Pos       (3U)
3397 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3398 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3399 #define CAN_F5R1_FB4_Pos       (4U)
3400 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3401 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3402 #define CAN_F5R1_FB5_Pos       (5U)
3403 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3404 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3405 #define CAN_F5R1_FB6_Pos       (6U)
3406 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3407 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3408 #define CAN_F5R1_FB7_Pos       (7U)
3409 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3410 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3411 #define CAN_F5R1_FB8_Pos       (8U)
3412 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3413 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3414 #define CAN_F5R1_FB9_Pos       (9U)
3415 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3416 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3417 #define CAN_F5R1_FB10_Pos      (10U)
3418 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3419 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3420 #define CAN_F5R1_FB11_Pos      (11U)
3421 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3422 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3423 #define CAN_F5R1_FB12_Pos      (12U)
3424 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3425 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3426 #define CAN_F5R1_FB13_Pos      (13U)
3427 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3428 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3429 #define CAN_F5R1_FB14_Pos      (14U)
3430 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3431 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3432 #define CAN_F5R1_FB15_Pos      (15U)
3433 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3434 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3435 #define CAN_F5R1_FB16_Pos      (16U)
3436 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3437 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3438 #define CAN_F5R1_FB17_Pos      (17U)
3439 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3440 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3441 #define CAN_F5R1_FB18_Pos      (18U)
3442 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3443 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3444 #define CAN_F5R1_FB19_Pos      (19U)
3445 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3446 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3447 #define CAN_F5R1_FB20_Pos      (20U)
3448 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3449 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3450 #define CAN_F5R1_FB21_Pos      (21U)
3451 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3452 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3453 #define CAN_F5R1_FB22_Pos      (22U)
3454 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3455 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3456 #define CAN_F5R1_FB23_Pos      (23U)
3457 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3458 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3459 #define CAN_F5R1_FB24_Pos      (24U)
3460 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3461 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3462 #define CAN_F5R1_FB25_Pos      (25U)
3463 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3464 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3465 #define CAN_F5R1_FB26_Pos      (26U)
3466 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3467 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3468 #define CAN_F5R1_FB27_Pos      (27U)
3469 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3470 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3471 #define CAN_F5R1_FB28_Pos      (28U)
3472 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3473 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3474 #define CAN_F5R1_FB29_Pos      (29U)
3475 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3476 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3477 #define CAN_F5R1_FB30_Pos      (30U)
3478 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3479 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3480 #define CAN_F5R1_FB31_Pos      (31U)
3481 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3482 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3483 
3484 /*******************  Bit definition for CAN_F6R1 register  *******************/
3485 #define CAN_F6R1_FB0_Pos       (0U)
3486 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3487 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3488 #define CAN_F6R1_FB1_Pos       (1U)
3489 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3490 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3491 #define CAN_F6R1_FB2_Pos       (2U)
3492 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3493 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3494 #define CAN_F6R1_FB3_Pos       (3U)
3495 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3496 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3497 #define CAN_F6R1_FB4_Pos       (4U)
3498 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3499 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3500 #define CAN_F6R1_FB5_Pos       (5U)
3501 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3502 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3503 #define CAN_F6R1_FB6_Pos       (6U)
3504 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3505 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3506 #define CAN_F6R1_FB7_Pos       (7U)
3507 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3508 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3509 #define CAN_F6R1_FB8_Pos       (8U)
3510 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3511 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3512 #define CAN_F6R1_FB9_Pos       (9U)
3513 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3514 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3515 #define CAN_F6R1_FB10_Pos      (10U)
3516 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3517 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3518 #define CAN_F6R1_FB11_Pos      (11U)
3519 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3520 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3521 #define CAN_F6R1_FB12_Pos      (12U)
3522 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3523 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3524 #define CAN_F6R1_FB13_Pos      (13U)
3525 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3526 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3527 #define CAN_F6R1_FB14_Pos      (14U)
3528 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3529 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3530 #define CAN_F6R1_FB15_Pos      (15U)
3531 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3532 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3533 #define CAN_F6R1_FB16_Pos      (16U)
3534 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3535 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3536 #define CAN_F6R1_FB17_Pos      (17U)
3537 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3538 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3539 #define CAN_F6R1_FB18_Pos      (18U)
3540 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3541 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3542 #define CAN_F6R1_FB19_Pos      (19U)
3543 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3544 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3545 #define CAN_F6R1_FB20_Pos      (20U)
3546 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3547 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3548 #define CAN_F6R1_FB21_Pos      (21U)
3549 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3550 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3551 #define CAN_F6R1_FB22_Pos      (22U)
3552 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3553 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3554 #define CAN_F6R1_FB23_Pos      (23U)
3555 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3556 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3557 #define CAN_F6R1_FB24_Pos      (24U)
3558 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3559 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3560 #define CAN_F6R1_FB25_Pos      (25U)
3561 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3562 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3563 #define CAN_F6R1_FB26_Pos      (26U)
3564 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3565 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3566 #define CAN_F6R1_FB27_Pos      (27U)
3567 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3568 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3569 #define CAN_F6R1_FB28_Pos      (28U)
3570 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3571 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3572 #define CAN_F6R1_FB29_Pos      (29U)
3573 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3574 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3575 #define CAN_F6R1_FB30_Pos      (30U)
3576 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3577 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3578 #define CAN_F6R1_FB31_Pos      (31U)
3579 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3580 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3581 
3582 /*******************  Bit definition for CAN_F7R1 register  *******************/
3583 #define CAN_F7R1_FB0_Pos       (0U)
3584 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3585 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3586 #define CAN_F7R1_FB1_Pos       (1U)
3587 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3588 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3589 #define CAN_F7R1_FB2_Pos       (2U)
3590 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3591 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3592 #define CAN_F7R1_FB3_Pos       (3U)
3593 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3594 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3595 #define CAN_F7R1_FB4_Pos       (4U)
3596 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3597 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3598 #define CAN_F7R1_FB5_Pos       (5U)
3599 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3600 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3601 #define CAN_F7R1_FB6_Pos       (6U)
3602 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3603 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3604 #define CAN_F7R1_FB7_Pos       (7U)
3605 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3606 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3607 #define CAN_F7R1_FB8_Pos       (8U)
3608 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3609 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3610 #define CAN_F7R1_FB9_Pos       (9U)
3611 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
3612 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3613 #define CAN_F7R1_FB10_Pos      (10U)
3614 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
3615 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3616 #define CAN_F7R1_FB11_Pos      (11U)
3617 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
3618 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3619 #define CAN_F7R1_FB12_Pos      (12U)
3620 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
3621 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3622 #define CAN_F7R1_FB13_Pos      (13U)
3623 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
3624 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3625 #define CAN_F7R1_FB14_Pos      (14U)
3626 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
3627 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3628 #define CAN_F7R1_FB15_Pos      (15U)
3629 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
3630 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3631 #define CAN_F7R1_FB16_Pos      (16U)
3632 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
3633 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3634 #define CAN_F7R1_FB17_Pos      (17U)
3635 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
3636 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3637 #define CAN_F7R1_FB18_Pos      (18U)
3638 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
3639 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3640 #define CAN_F7R1_FB19_Pos      (19U)
3641 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
3642 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3643 #define CAN_F7R1_FB20_Pos      (20U)
3644 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
3645 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3646 #define CAN_F7R1_FB21_Pos      (21U)
3647 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
3648 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3649 #define CAN_F7R1_FB22_Pos      (22U)
3650 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
3651 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3652 #define CAN_F7R1_FB23_Pos      (23U)
3653 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
3654 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3655 #define CAN_F7R1_FB24_Pos      (24U)
3656 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
3657 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3658 #define CAN_F7R1_FB25_Pos      (25U)
3659 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
3660 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3661 #define CAN_F7R1_FB26_Pos      (26U)
3662 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
3663 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3664 #define CAN_F7R1_FB27_Pos      (27U)
3665 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
3666 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3667 #define CAN_F7R1_FB28_Pos      (28U)
3668 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
3669 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3670 #define CAN_F7R1_FB29_Pos      (29U)
3671 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
3672 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3673 #define CAN_F7R1_FB30_Pos      (30U)
3674 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
3675 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3676 #define CAN_F7R1_FB31_Pos      (31U)
3677 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
3678 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3679 
3680 /*******************  Bit definition for CAN_F8R1 register  *******************/
3681 #define CAN_F8R1_FB0_Pos       (0U)
3682 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
3683 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3684 #define CAN_F8R1_FB1_Pos       (1U)
3685 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
3686 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3687 #define CAN_F8R1_FB2_Pos       (2U)
3688 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
3689 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3690 #define CAN_F8R1_FB3_Pos       (3U)
3691 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
3692 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3693 #define CAN_F8R1_FB4_Pos       (4U)
3694 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
3695 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3696 #define CAN_F8R1_FB5_Pos       (5U)
3697 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
3698 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3699 #define CAN_F8R1_FB6_Pos       (6U)
3700 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
3701 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3702 #define CAN_F8R1_FB7_Pos       (7U)
3703 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
3704 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3705 #define CAN_F8R1_FB8_Pos       (8U)
3706 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
3707 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3708 #define CAN_F8R1_FB9_Pos       (9U)
3709 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
3710 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3711 #define CAN_F8R1_FB10_Pos      (10U)
3712 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
3713 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3714 #define CAN_F8R1_FB11_Pos      (11U)
3715 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
3716 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3717 #define CAN_F8R1_FB12_Pos      (12U)
3718 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
3719 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3720 #define CAN_F8R1_FB13_Pos      (13U)
3721 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
3722 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3723 #define CAN_F8R1_FB14_Pos      (14U)
3724 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
3725 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3726 #define CAN_F8R1_FB15_Pos      (15U)
3727 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
3728 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3729 #define CAN_F8R1_FB16_Pos      (16U)
3730 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
3731 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3732 #define CAN_F8R1_FB17_Pos      (17U)
3733 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
3734 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3735 #define CAN_F8R1_FB18_Pos      (18U)
3736 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
3737 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3738 #define CAN_F8R1_FB19_Pos      (19U)
3739 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
3740 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3741 #define CAN_F8R1_FB20_Pos      (20U)
3742 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
3743 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3744 #define CAN_F8R1_FB21_Pos      (21U)
3745 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
3746 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3747 #define CAN_F8R1_FB22_Pos      (22U)
3748 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
3749 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3750 #define CAN_F8R1_FB23_Pos      (23U)
3751 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
3752 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3753 #define CAN_F8R1_FB24_Pos      (24U)
3754 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
3755 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3756 #define CAN_F8R1_FB25_Pos      (25U)
3757 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
3758 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3759 #define CAN_F8R1_FB26_Pos      (26U)
3760 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
3761 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3762 #define CAN_F8R1_FB27_Pos      (27U)
3763 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
3764 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3765 #define CAN_F8R1_FB28_Pos      (28U)
3766 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
3767 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3768 #define CAN_F8R1_FB29_Pos      (29U)
3769 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
3770 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3771 #define CAN_F8R1_FB30_Pos      (30U)
3772 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
3773 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3774 #define CAN_F8R1_FB31_Pos      (31U)
3775 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
3776 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3777 
3778 /*******************  Bit definition for CAN_F9R1 register  *******************/
3779 #define CAN_F9R1_FB0_Pos       (0U)
3780 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
3781 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3782 #define CAN_F9R1_FB1_Pos       (1U)
3783 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
3784 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3785 #define CAN_F9R1_FB2_Pos       (2U)
3786 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
3787 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3788 #define CAN_F9R1_FB3_Pos       (3U)
3789 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
3790 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3791 #define CAN_F9R1_FB4_Pos       (4U)
3792 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
3793 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3794 #define CAN_F9R1_FB5_Pos       (5U)
3795 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
3796 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3797 #define CAN_F9R1_FB6_Pos       (6U)
3798 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
3799 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3800 #define CAN_F9R1_FB7_Pos       (7U)
3801 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
3802 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3803 #define CAN_F9R1_FB8_Pos       (8U)
3804 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
3805 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3806 #define CAN_F9R1_FB9_Pos       (9U)
3807 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
3808 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3809 #define CAN_F9R1_FB10_Pos      (10U)
3810 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
3811 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3812 #define CAN_F9R1_FB11_Pos      (11U)
3813 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
3814 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3815 #define CAN_F9R1_FB12_Pos      (12U)
3816 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
3817 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3818 #define CAN_F9R1_FB13_Pos      (13U)
3819 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
3820 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3821 #define CAN_F9R1_FB14_Pos      (14U)
3822 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
3823 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3824 #define CAN_F9R1_FB15_Pos      (15U)
3825 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
3826 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3827 #define CAN_F9R1_FB16_Pos      (16U)
3828 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
3829 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3830 #define CAN_F9R1_FB17_Pos      (17U)
3831 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
3832 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3833 #define CAN_F9R1_FB18_Pos      (18U)
3834 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
3835 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3836 #define CAN_F9R1_FB19_Pos      (19U)
3837 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
3838 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3839 #define CAN_F9R1_FB20_Pos      (20U)
3840 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
3841 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3842 #define CAN_F9R1_FB21_Pos      (21U)
3843 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
3844 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3845 #define CAN_F9R1_FB22_Pos      (22U)
3846 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
3847 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3848 #define CAN_F9R1_FB23_Pos      (23U)
3849 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
3850 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3851 #define CAN_F9R1_FB24_Pos      (24U)
3852 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
3853 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3854 #define CAN_F9R1_FB25_Pos      (25U)
3855 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
3856 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3857 #define CAN_F9R1_FB26_Pos      (26U)
3858 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
3859 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3860 #define CAN_F9R1_FB27_Pos      (27U)
3861 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
3862 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3863 #define CAN_F9R1_FB28_Pos      (28U)
3864 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
3865 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3866 #define CAN_F9R1_FB29_Pos      (29U)
3867 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
3868 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3869 #define CAN_F9R1_FB30_Pos      (30U)
3870 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
3871 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3872 #define CAN_F9R1_FB31_Pos      (31U)
3873 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
3874 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3875 
3876 /*******************  Bit definition for CAN_F10R1 register  ******************/
3877 #define CAN_F10R1_FB0_Pos      (0U)
3878 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
3879 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3880 #define CAN_F10R1_FB1_Pos      (1U)
3881 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
3882 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3883 #define CAN_F10R1_FB2_Pos      (2U)
3884 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
3885 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3886 #define CAN_F10R1_FB3_Pos      (3U)
3887 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
3888 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3889 #define CAN_F10R1_FB4_Pos      (4U)
3890 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
3891 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3892 #define CAN_F10R1_FB5_Pos      (5U)
3893 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
3894 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3895 #define CAN_F10R1_FB6_Pos      (6U)
3896 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
3897 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3898 #define CAN_F10R1_FB7_Pos      (7U)
3899 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
3900 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3901 #define CAN_F10R1_FB8_Pos      (8U)
3902 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
3903 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3904 #define CAN_F10R1_FB9_Pos      (9U)
3905 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
3906 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3907 #define CAN_F10R1_FB10_Pos     (10U)
3908 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
3909 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3910 #define CAN_F10R1_FB11_Pos     (11U)
3911 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
3912 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3913 #define CAN_F10R1_FB12_Pos     (12U)
3914 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
3915 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3916 #define CAN_F10R1_FB13_Pos     (13U)
3917 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
3918 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3919 #define CAN_F10R1_FB14_Pos     (14U)
3920 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
3921 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3922 #define CAN_F10R1_FB15_Pos     (15U)
3923 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
3924 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3925 #define CAN_F10R1_FB16_Pos     (16U)
3926 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
3927 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3928 #define CAN_F10R1_FB17_Pos     (17U)
3929 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
3930 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3931 #define CAN_F10R1_FB18_Pos     (18U)
3932 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
3933 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3934 #define CAN_F10R1_FB19_Pos     (19U)
3935 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
3936 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3937 #define CAN_F10R1_FB20_Pos     (20U)
3938 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
3939 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3940 #define CAN_F10R1_FB21_Pos     (21U)
3941 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
3942 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3943 #define CAN_F10R1_FB22_Pos     (22U)
3944 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
3945 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3946 #define CAN_F10R1_FB23_Pos     (23U)
3947 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3948 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3949 #define CAN_F10R1_FB24_Pos     (24U)
3950 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3951 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3952 #define CAN_F10R1_FB25_Pos     (25U)
3953 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3954 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3955 #define CAN_F10R1_FB26_Pos     (26U)
3956 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3957 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3958 #define CAN_F10R1_FB27_Pos     (27U)
3959 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3960 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3961 #define CAN_F10R1_FB28_Pos     (28U)
3962 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3963 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3964 #define CAN_F10R1_FB29_Pos     (29U)
3965 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3966 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3967 #define CAN_F10R1_FB30_Pos     (30U)
3968 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3969 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3970 #define CAN_F10R1_FB31_Pos     (31U)
3971 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3972 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3973 
3974 /*******************  Bit definition for CAN_F11R1 register  ******************/
3975 #define CAN_F11R1_FB0_Pos      (0U)
3976 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3977 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3978 #define CAN_F11R1_FB1_Pos      (1U)
3979 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3980 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3981 #define CAN_F11R1_FB2_Pos      (2U)
3982 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3983 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3984 #define CAN_F11R1_FB3_Pos      (3U)
3985 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
3986 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
3987 #define CAN_F11R1_FB4_Pos      (4U)
3988 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
3989 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
3990 #define CAN_F11R1_FB5_Pos      (5U)
3991 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
3992 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
3993 #define CAN_F11R1_FB6_Pos      (6U)
3994 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
3995 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
3996 #define CAN_F11R1_FB7_Pos      (7U)
3997 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
3998 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
3999 #define CAN_F11R1_FB8_Pos      (8U)
4000 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
4001 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
4002 #define CAN_F11R1_FB9_Pos      (9U)
4003 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
4004 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
4005 #define CAN_F11R1_FB10_Pos     (10U)
4006 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
4007 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
4008 #define CAN_F11R1_FB11_Pos     (11U)
4009 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
4010 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
4011 #define CAN_F11R1_FB12_Pos     (12U)
4012 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
4013 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
4014 #define CAN_F11R1_FB13_Pos     (13U)
4015 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
4016 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
4017 #define CAN_F11R1_FB14_Pos     (14U)
4018 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
4019 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
4020 #define CAN_F11R1_FB15_Pos     (15U)
4021 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
4022 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
4023 #define CAN_F11R1_FB16_Pos     (16U)
4024 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
4025 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
4026 #define CAN_F11R1_FB17_Pos     (17U)
4027 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
4028 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
4029 #define CAN_F11R1_FB18_Pos     (18U)
4030 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
4031 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
4032 #define CAN_F11R1_FB19_Pos     (19U)
4033 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
4034 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
4035 #define CAN_F11R1_FB20_Pos     (20U)
4036 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
4037 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
4038 #define CAN_F11R1_FB21_Pos     (21U)
4039 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
4040 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
4041 #define CAN_F11R1_FB22_Pos     (22U)
4042 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
4043 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
4044 #define CAN_F11R1_FB23_Pos     (23U)
4045 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
4046 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
4047 #define CAN_F11R1_FB24_Pos     (24U)
4048 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
4049 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
4050 #define CAN_F11R1_FB25_Pos     (25U)
4051 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
4052 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
4053 #define CAN_F11R1_FB26_Pos     (26U)
4054 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
4055 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
4056 #define CAN_F11R1_FB27_Pos     (27U)
4057 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
4058 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
4059 #define CAN_F11R1_FB28_Pos     (28U)
4060 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
4061 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
4062 #define CAN_F11R1_FB29_Pos     (29U)
4063 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
4064 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
4065 #define CAN_F11R1_FB30_Pos     (30U)
4066 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
4067 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
4068 #define CAN_F11R1_FB31_Pos     (31U)
4069 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
4070 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
4071 
4072 /*******************  Bit definition for CAN_F12R1 register  ******************/
4073 #define CAN_F12R1_FB0_Pos      (0U)
4074 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
4075 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
4076 #define CAN_F12R1_FB1_Pos      (1U)
4077 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
4078 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
4079 #define CAN_F12R1_FB2_Pos      (2U)
4080 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
4081 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
4082 #define CAN_F12R1_FB3_Pos      (3U)
4083 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
4084 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
4085 #define CAN_F12R1_FB4_Pos      (4U)
4086 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
4087 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
4088 #define CAN_F12R1_FB5_Pos      (5U)
4089 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
4090 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
4091 #define CAN_F12R1_FB6_Pos      (6U)
4092 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
4093 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
4094 #define CAN_F12R1_FB7_Pos      (7U)
4095 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
4096 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
4097 #define CAN_F12R1_FB8_Pos      (8U)
4098 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
4099 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
4100 #define CAN_F12R1_FB9_Pos      (9U)
4101 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
4102 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
4103 #define CAN_F12R1_FB10_Pos     (10U)
4104 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
4105 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
4106 #define CAN_F12R1_FB11_Pos     (11U)
4107 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
4108 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
4109 #define CAN_F12R1_FB12_Pos     (12U)
4110 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
4111 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
4112 #define CAN_F12R1_FB13_Pos     (13U)
4113 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
4114 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
4115 #define CAN_F12R1_FB14_Pos     (14U)
4116 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
4117 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
4118 #define CAN_F12R1_FB15_Pos     (15U)
4119 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
4120 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
4121 #define CAN_F12R1_FB16_Pos     (16U)
4122 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
4123 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
4124 #define CAN_F12R1_FB17_Pos     (17U)
4125 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
4126 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
4127 #define CAN_F12R1_FB18_Pos     (18U)
4128 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
4129 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
4130 #define CAN_F12R1_FB19_Pos     (19U)
4131 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
4132 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4133 #define CAN_F12R1_FB20_Pos     (20U)
4134 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
4135 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
4136 #define CAN_F12R1_FB21_Pos     (21U)
4137 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
4138 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
4139 #define CAN_F12R1_FB22_Pos     (22U)
4140 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
4141 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
4142 #define CAN_F12R1_FB23_Pos     (23U)
4143 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
4144 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
4145 #define CAN_F12R1_FB24_Pos     (24U)
4146 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
4147 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
4148 #define CAN_F12R1_FB25_Pos     (25U)
4149 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
4150 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
4151 #define CAN_F12R1_FB26_Pos     (26U)
4152 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
4153 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
4154 #define CAN_F12R1_FB27_Pos     (27U)
4155 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
4156 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
4157 #define CAN_F12R1_FB28_Pos     (28U)
4158 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
4159 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
4160 #define CAN_F12R1_FB29_Pos     (29U)
4161 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
4162 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
4163 #define CAN_F12R1_FB30_Pos     (30U)
4164 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
4165 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
4166 #define CAN_F12R1_FB31_Pos     (31U)
4167 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
4168 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4169 
4170 /*******************  Bit definition for CAN_F13R1 register  ******************/
4171 #define CAN_F13R1_FB0_Pos      (0U)
4172 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
4173 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4174 #define CAN_F13R1_FB1_Pos      (1U)
4175 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
4176 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4177 #define CAN_F13R1_FB2_Pos      (2U)
4178 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
4179 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4180 #define CAN_F13R1_FB3_Pos      (3U)
4181 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
4182 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4183 #define CAN_F13R1_FB4_Pos      (4U)
4184 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
4185 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4186 #define CAN_F13R1_FB5_Pos      (5U)
4187 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
4188 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4189 #define CAN_F13R1_FB6_Pos      (6U)
4190 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
4191 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4192 #define CAN_F13R1_FB7_Pos      (7U)
4193 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
4194 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4195 #define CAN_F13R1_FB8_Pos      (8U)
4196 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
4197 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4198 #define CAN_F13R1_FB9_Pos      (9U)
4199 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
4200 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4201 #define CAN_F13R1_FB10_Pos     (10U)
4202 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
4203 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4204 #define CAN_F13R1_FB11_Pos     (11U)
4205 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
4206 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4207 #define CAN_F13R1_FB12_Pos     (12U)
4208 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4209 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4210 #define CAN_F13R1_FB13_Pos     (13U)
4211 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4212 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4213 #define CAN_F13R1_FB14_Pos     (14U)
4214 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4215 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4216 #define CAN_F13R1_FB15_Pos     (15U)
4217 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4218 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4219 #define CAN_F13R1_FB16_Pos     (16U)
4220 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4221 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4222 #define CAN_F13R1_FB17_Pos     (17U)
4223 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4224 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4225 #define CAN_F13R1_FB18_Pos     (18U)
4226 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4227 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4228 #define CAN_F13R1_FB19_Pos     (19U)
4229 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4230 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4231 #define CAN_F13R1_FB20_Pos     (20U)
4232 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4233 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4234 #define CAN_F13R1_FB21_Pos     (21U)
4235 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4236 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4237 #define CAN_F13R1_FB22_Pos     (22U)
4238 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4239 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4240 #define CAN_F13R1_FB23_Pos     (23U)
4241 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4242 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4243 #define CAN_F13R1_FB24_Pos     (24U)
4244 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4245 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4246 #define CAN_F13R1_FB25_Pos     (25U)
4247 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4248 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4249 #define CAN_F13R1_FB26_Pos     (26U)
4250 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4251 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4252 #define CAN_F13R1_FB27_Pos     (27U)
4253 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4254 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4255 #define CAN_F13R1_FB28_Pos     (28U)
4256 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4257 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4258 #define CAN_F13R1_FB29_Pos     (29U)
4259 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4260 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4261 #define CAN_F13R1_FB30_Pos     (30U)
4262 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4263 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4264 #define CAN_F13R1_FB31_Pos     (31U)
4265 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4266 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4267 
4268 /*******************  Bit definition for CAN_F0R2 register  *******************/
4269 #define CAN_F0R2_FB0_Pos       (0U)
4270 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4271 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4272 #define CAN_F0R2_FB1_Pos       (1U)
4273 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4274 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4275 #define CAN_F0R2_FB2_Pos       (2U)
4276 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4277 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4278 #define CAN_F0R2_FB3_Pos       (3U)
4279 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4280 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4281 #define CAN_F0R2_FB4_Pos       (4U)
4282 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4283 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4284 #define CAN_F0R2_FB5_Pos       (5U)
4285 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4286 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4287 #define CAN_F0R2_FB6_Pos       (6U)
4288 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4289 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4290 #define CAN_F0R2_FB7_Pos       (7U)
4291 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4292 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4293 #define CAN_F0R2_FB8_Pos       (8U)
4294 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4295 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4296 #define CAN_F0R2_FB9_Pos       (9U)
4297 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4298 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4299 #define CAN_F0R2_FB10_Pos      (10U)
4300 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4301 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4302 #define CAN_F0R2_FB11_Pos      (11U)
4303 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4304 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4305 #define CAN_F0R2_FB12_Pos      (12U)
4306 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4307 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4308 #define CAN_F0R2_FB13_Pos      (13U)
4309 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4310 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4311 #define CAN_F0R2_FB14_Pos      (14U)
4312 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4313 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4314 #define CAN_F0R2_FB15_Pos      (15U)
4315 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4316 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4317 #define CAN_F0R2_FB16_Pos      (16U)
4318 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4319 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4320 #define CAN_F0R2_FB17_Pos      (17U)
4321 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4322 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4323 #define CAN_F0R2_FB18_Pos      (18U)
4324 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4325 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4326 #define CAN_F0R2_FB19_Pos      (19U)
4327 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4328 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4329 #define CAN_F0R2_FB20_Pos      (20U)
4330 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4331 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4332 #define CAN_F0R2_FB21_Pos      (21U)
4333 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4334 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4335 #define CAN_F0R2_FB22_Pos      (22U)
4336 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4337 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4338 #define CAN_F0R2_FB23_Pos      (23U)
4339 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4340 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4341 #define CAN_F0R2_FB24_Pos      (24U)
4342 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4343 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4344 #define CAN_F0R2_FB25_Pos      (25U)
4345 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4346 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4347 #define CAN_F0R2_FB26_Pos      (26U)
4348 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4349 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4350 #define CAN_F0R2_FB27_Pos      (27U)
4351 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4352 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4353 #define CAN_F0R2_FB28_Pos      (28U)
4354 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4355 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4356 #define CAN_F0R2_FB29_Pos      (29U)
4357 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4358 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4359 #define CAN_F0R2_FB30_Pos      (30U)
4360 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4361 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4362 #define CAN_F0R2_FB31_Pos      (31U)
4363 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4364 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4365 
4366 /*******************  Bit definition for CAN_F1R2 register  *******************/
4367 #define CAN_F1R2_FB0_Pos       (0U)
4368 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4369 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4370 #define CAN_F1R2_FB1_Pos       (1U)
4371 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4372 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4373 #define CAN_F1R2_FB2_Pos       (2U)
4374 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4375 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4376 #define CAN_F1R2_FB3_Pos       (3U)
4377 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4378 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4379 #define CAN_F1R2_FB4_Pos       (4U)
4380 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4381 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4382 #define CAN_F1R2_FB5_Pos       (5U)
4383 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4384 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4385 #define CAN_F1R2_FB6_Pos       (6U)
4386 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4387 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4388 #define CAN_F1R2_FB7_Pos       (7U)
4389 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4390 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4391 #define CAN_F1R2_FB8_Pos       (8U)
4392 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4393 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4394 #define CAN_F1R2_FB9_Pos       (9U)
4395 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4396 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4397 #define CAN_F1R2_FB10_Pos      (10U)
4398 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4399 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4400 #define CAN_F1R2_FB11_Pos      (11U)
4401 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4402 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4403 #define CAN_F1R2_FB12_Pos      (12U)
4404 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4405 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4406 #define CAN_F1R2_FB13_Pos      (13U)
4407 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4408 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4409 #define CAN_F1R2_FB14_Pos      (14U)
4410 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4411 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4412 #define CAN_F1R2_FB15_Pos      (15U)
4413 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4414 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4415 #define CAN_F1R2_FB16_Pos      (16U)
4416 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4417 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4418 #define CAN_F1R2_FB17_Pos      (17U)
4419 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4420 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4421 #define CAN_F1R2_FB18_Pos      (18U)
4422 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4423 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4424 #define CAN_F1R2_FB19_Pos      (19U)
4425 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4426 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4427 #define CAN_F1R2_FB20_Pos      (20U)
4428 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4429 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4430 #define CAN_F1R2_FB21_Pos      (21U)
4431 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4432 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4433 #define CAN_F1R2_FB22_Pos      (22U)
4434 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4435 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4436 #define CAN_F1R2_FB23_Pos      (23U)
4437 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4438 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4439 #define CAN_F1R2_FB24_Pos      (24U)
4440 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4441 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4442 #define CAN_F1R2_FB25_Pos      (25U)
4443 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4444 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4445 #define CAN_F1R2_FB26_Pos      (26U)
4446 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4447 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4448 #define CAN_F1R2_FB27_Pos      (27U)
4449 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4450 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4451 #define CAN_F1R2_FB28_Pos      (28U)
4452 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4453 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4454 #define CAN_F1R2_FB29_Pos      (29U)
4455 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4456 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4457 #define CAN_F1R2_FB30_Pos      (30U)
4458 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4459 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4460 #define CAN_F1R2_FB31_Pos      (31U)
4461 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4462 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4463 
4464 /*******************  Bit definition for CAN_F2R2 register  *******************/
4465 #define CAN_F2R2_FB0_Pos       (0U)
4466 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4467 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4468 #define CAN_F2R2_FB1_Pos       (1U)
4469 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4470 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4471 #define CAN_F2R2_FB2_Pos       (2U)
4472 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4473 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4474 #define CAN_F2R2_FB3_Pos       (3U)
4475 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4476 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4477 #define CAN_F2R2_FB4_Pos       (4U)
4478 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4479 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4480 #define CAN_F2R2_FB5_Pos       (5U)
4481 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4482 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4483 #define CAN_F2R2_FB6_Pos       (6U)
4484 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4485 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4486 #define CAN_F2R2_FB7_Pos       (7U)
4487 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4488 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4489 #define CAN_F2R2_FB8_Pos       (8U)
4490 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4491 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4492 #define CAN_F2R2_FB9_Pos       (9U)
4493 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4494 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4495 #define CAN_F2R2_FB10_Pos      (10U)
4496 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4497 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4498 #define CAN_F2R2_FB11_Pos      (11U)
4499 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4500 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4501 #define CAN_F2R2_FB12_Pos      (12U)
4502 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4503 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4504 #define CAN_F2R2_FB13_Pos      (13U)
4505 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4506 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4507 #define CAN_F2R2_FB14_Pos      (14U)
4508 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4509 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4510 #define CAN_F2R2_FB15_Pos      (15U)
4511 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4512 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4513 #define CAN_F2R2_FB16_Pos      (16U)
4514 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4515 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4516 #define CAN_F2R2_FB17_Pos      (17U)
4517 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4518 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4519 #define CAN_F2R2_FB18_Pos      (18U)
4520 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4521 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4522 #define CAN_F2R2_FB19_Pos      (19U)
4523 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4524 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4525 #define CAN_F2R2_FB20_Pos      (20U)
4526 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4527 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4528 #define CAN_F2R2_FB21_Pos      (21U)
4529 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4530 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4531 #define CAN_F2R2_FB22_Pos      (22U)
4532 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4533 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4534 #define CAN_F2R2_FB23_Pos      (23U)
4535 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4536 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4537 #define CAN_F2R2_FB24_Pos      (24U)
4538 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4539 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4540 #define CAN_F2R2_FB25_Pos      (25U)
4541 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4542 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4543 #define CAN_F2R2_FB26_Pos      (26U)
4544 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4545 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4546 #define CAN_F2R2_FB27_Pos      (27U)
4547 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4548 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4549 #define CAN_F2R2_FB28_Pos      (28U)
4550 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4551 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4552 #define CAN_F2R2_FB29_Pos      (29U)
4553 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4554 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4555 #define CAN_F2R2_FB30_Pos      (30U)
4556 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4557 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4558 #define CAN_F2R2_FB31_Pos      (31U)
4559 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4560 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4561 
4562 /*******************  Bit definition for CAN_F3R2 register  *******************/
4563 #define CAN_F3R2_FB0_Pos       (0U)
4564 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4565 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4566 #define CAN_F3R2_FB1_Pos       (1U)
4567 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4568 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4569 #define CAN_F3R2_FB2_Pos       (2U)
4570 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4571 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4572 #define CAN_F3R2_FB3_Pos       (3U)
4573 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4574 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4575 #define CAN_F3R2_FB4_Pos       (4U)
4576 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4577 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4578 #define CAN_F3R2_FB5_Pos       (5U)
4579 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4580 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4581 #define CAN_F3R2_FB6_Pos       (6U)
4582 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4583 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4584 #define CAN_F3R2_FB7_Pos       (7U)
4585 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4586 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4587 #define CAN_F3R2_FB8_Pos       (8U)
4588 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4589 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4590 #define CAN_F3R2_FB9_Pos       (9U)
4591 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4592 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4593 #define CAN_F3R2_FB10_Pos      (10U)
4594 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4595 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4596 #define CAN_F3R2_FB11_Pos      (11U)
4597 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4598 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4599 #define CAN_F3R2_FB12_Pos      (12U)
4600 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4601 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4602 #define CAN_F3R2_FB13_Pos      (13U)
4603 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4604 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4605 #define CAN_F3R2_FB14_Pos      (14U)
4606 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4607 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4608 #define CAN_F3R2_FB15_Pos      (15U)
4609 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4610 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4611 #define CAN_F3R2_FB16_Pos      (16U)
4612 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
4613 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4614 #define CAN_F3R2_FB17_Pos      (17U)
4615 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
4616 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4617 #define CAN_F3R2_FB18_Pos      (18U)
4618 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
4619 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4620 #define CAN_F3R2_FB19_Pos      (19U)
4621 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
4622 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4623 #define CAN_F3R2_FB20_Pos      (20U)
4624 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
4625 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4626 #define CAN_F3R2_FB21_Pos      (21U)
4627 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
4628 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4629 #define CAN_F3R2_FB22_Pos      (22U)
4630 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
4631 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4632 #define CAN_F3R2_FB23_Pos      (23U)
4633 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
4634 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4635 #define CAN_F3R2_FB24_Pos      (24U)
4636 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
4637 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4638 #define CAN_F3R2_FB25_Pos      (25U)
4639 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
4640 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4641 #define CAN_F3R2_FB26_Pos      (26U)
4642 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
4643 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4644 #define CAN_F3R2_FB27_Pos      (27U)
4645 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
4646 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4647 #define CAN_F3R2_FB28_Pos      (28U)
4648 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
4649 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4650 #define CAN_F3R2_FB29_Pos      (29U)
4651 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
4652 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4653 #define CAN_F3R2_FB30_Pos      (30U)
4654 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
4655 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4656 #define CAN_F3R2_FB31_Pos      (31U)
4657 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
4658 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4659 
4660 /*******************  Bit definition for CAN_F4R2 register  *******************/
4661 #define CAN_F4R2_FB0_Pos       (0U)
4662 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
4663 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4664 #define CAN_F4R2_FB1_Pos       (1U)
4665 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
4666 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4667 #define CAN_F4R2_FB2_Pos       (2U)
4668 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
4669 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4670 #define CAN_F4R2_FB3_Pos       (3U)
4671 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
4672 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4673 #define CAN_F4R2_FB4_Pos       (4U)
4674 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
4675 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4676 #define CAN_F4R2_FB5_Pos       (5U)
4677 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
4678 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4679 #define CAN_F4R2_FB6_Pos       (6U)
4680 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
4681 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4682 #define CAN_F4R2_FB7_Pos       (7U)
4683 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
4684 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4685 #define CAN_F4R2_FB8_Pos       (8U)
4686 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
4687 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4688 #define CAN_F4R2_FB9_Pos       (9U)
4689 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
4690 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4691 #define CAN_F4R2_FB10_Pos      (10U)
4692 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
4693 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4694 #define CAN_F4R2_FB11_Pos      (11U)
4695 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
4696 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4697 #define CAN_F4R2_FB12_Pos      (12U)
4698 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
4699 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4700 #define CAN_F4R2_FB13_Pos      (13U)
4701 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
4702 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4703 #define CAN_F4R2_FB14_Pos      (14U)
4704 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
4705 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4706 #define CAN_F4R2_FB15_Pos      (15U)
4707 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
4708 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4709 #define CAN_F4R2_FB16_Pos      (16U)
4710 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
4711 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4712 #define CAN_F4R2_FB17_Pos      (17U)
4713 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
4714 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4715 #define CAN_F4R2_FB18_Pos      (18U)
4716 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
4717 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4718 #define CAN_F4R2_FB19_Pos      (19U)
4719 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
4720 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4721 #define CAN_F4R2_FB20_Pos      (20U)
4722 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
4723 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4724 #define CAN_F4R2_FB21_Pos      (21U)
4725 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
4726 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4727 #define CAN_F4R2_FB22_Pos      (22U)
4728 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
4729 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4730 #define CAN_F4R2_FB23_Pos      (23U)
4731 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
4732 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4733 #define CAN_F4R2_FB24_Pos      (24U)
4734 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
4735 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4736 #define CAN_F4R2_FB25_Pos      (25U)
4737 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
4738 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4739 #define CAN_F4R2_FB26_Pos      (26U)
4740 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
4741 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4742 #define CAN_F4R2_FB27_Pos      (27U)
4743 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
4744 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4745 #define CAN_F4R2_FB28_Pos      (28U)
4746 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
4747 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4748 #define CAN_F4R2_FB29_Pos      (29U)
4749 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
4750 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4751 #define CAN_F4R2_FB30_Pos      (30U)
4752 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
4753 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4754 #define CAN_F4R2_FB31_Pos      (31U)
4755 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
4756 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4757 
4758 /*******************  Bit definition for CAN_F5R2 register  *******************/
4759 #define CAN_F5R2_FB0_Pos       (0U)
4760 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
4761 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4762 #define CAN_F5R2_FB1_Pos       (1U)
4763 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
4764 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4765 #define CAN_F5R2_FB2_Pos       (2U)
4766 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
4767 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4768 #define CAN_F5R2_FB3_Pos       (3U)
4769 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
4770 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4771 #define CAN_F5R2_FB4_Pos       (4U)
4772 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
4773 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4774 #define CAN_F5R2_FB5_Pos       (5U)
4775 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
4776 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4777 #define CAN_F5R2_FB6_Pos       (6U)
4778 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
4779 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4780 #define CAN_F5R2_FB7_Pos       (7U)
4781 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
4782 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4783 #define CAN_F5R2_FB8_Pos       (8U)
4784 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
4785 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4786 #define CAN_F5R2_FB9_Pos       (9U)
4787 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
4788 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4789 #define CAN_F5R2_FB10_Pos      (10U)
4790 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
4791 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4792 #define CAN_F5R2_FB11_Pos      (11U)
4793 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
4794 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4795 #define CAN_F5R2_FB12_Pos      (12U)
4796 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
4797 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4798 #define CAN_F5R2_FB13_Pos      (13U)
4799 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
4800 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4801 #define CAN_F5R2_FB14_Pos      (14U)
4802 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
4803 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4804 #define CAN_F5R2_FB15_Pos      (15U)
4805 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
4806 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4807 #define CAN_F5R2_FB16_Pos      (16U)
4808 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
4809 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4810 #define CAN_F5R2_FB17_Pos      (17U)
4811 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
4812 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4813 #define CAN_F5R2_FB18_Pos      (18U)
4814 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
4815 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4816 #define CAN_F5R2_FB19_Pos      (19U)
4817 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
4818 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4819 #define CAN_F5R2_FB20_Pos      (20U)
4820 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
4821 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4822 #define CAN_F5R2_FB21_Pos      (21U)
4823 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
4824 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4825 #define CAN_F5R2_FB22_Pos      (22U)
4826 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
4827 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4828 #define CAN_F5R2_FB23_Pos      (23U)
4829 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
4830 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4831 #define CAN_F5R2_FB24_Pos      (24U)
4832 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
4833 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4834 #define CAN_F5R2_FB25_Pos      (25U)
4835 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
4836 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4837 #define CAN_F5R2_FB26_Pos      (26U)
4838 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
4839 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4840 #define CAN_F5R2_FB27_Pos      (27U)
4841 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
4842 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4843 #define CAN_F5R2_FB28_Pos      (28U)
4844 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
4845 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4846 #define CAN_F5R2_FB29_Pos      (29U)
4847 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
4848 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4849 #define CAN_F5R2_FB30_Pos      (30U)
4850 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
4851 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4852 #define CAN_F5R2_FB31_Pos      (31U)
4853 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
4854 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4855 
4856 /*******************  Bit definition for CAN_F6R2 register  *******************/
4857 #define CAN_F6R2_FB0_Pos       (0U)
4858 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
4859 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4860 #define CAN_F6R2_FB1_Pos       (1U)
4861 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
4862 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4863 #define CAN_F6R2_FB2_Pos       (2U)
4864 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
4865 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4866 #define CAN_F6R2_FB3_Pos       (3U)
4867 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
4868 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4869 #define CAN_F6R2_FB4_Pos       (4U)
4870 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
4871 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4872 #define CAN_F6R2_FB5_Pos       (5U)
4873 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
4874 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4875 #define CAN_F6R2_FB6_Pos       (6U)
4876 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
4877 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4878 #define CAN_F6R2_FB7_Pos       (7U)
4879 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
4880 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4881 #define CAN_F6R2_FB8_Pos       (8U)
4882 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
4883 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4884 #define CAN_F6R2_FB9_Pos       (9U)
4885 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
4886 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4887 #define CAN_F6R2_FB10_Pos      (10U)
4888 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
4889 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4890 #define CAN_F6R2_FB11_Pos      (11U)
4891 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
4892 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4893 #define CAN_F6R2_FB12_Pos      (12U)
4894 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
4895 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4896 #define CAN_F6R2_FB13_Pos      (13U)
4897 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
4898 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4899 #define CAN_F6R2_FB14_Pos      (14U)
4900 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
4901 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4902 #define CAN_F6R2_FB15_Pos      (15U)
4903 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
4904 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4905 #define CAN_F6R2_FB16_Pos      (16U)
4906 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
4907 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4908 #define CAN_F6R2_FB17_Pos      (17U)
4909 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
4910 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4911 #define CAN_F6R2_FB18_Pos      (18U)
4912 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
4913 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4914 #define CAN_F6R2_FB19_Pos      (19U)
4915 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
4916 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4917 #define CAN_F6R2_FB20_Pos      (20U)
4918 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
4919 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4920 #define CAN_F6R2_FB21_Pos      (21U)
4921 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
4922 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4923 #define CAN_F6R2_FB22_Pos      (22U)
4924 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
4925 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4926 #define CAN_F6R2_FB23_Pos      (23U)
4927 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
4928 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4929 #define CAN_F6R2_FB24_Pos      (24U)
4930 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
4931 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4932 #define CAN_F6R2_FB25_Pos      (25U)
4933 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
4934 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4935 #define CAN_F6R2_FB26_Pos      (26U)
4936 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
4937 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4938 #define CAN_F6R2_FB27_Pos      (27U)
4939 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
4940 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4941 #define CAN_F6R2_FB28_Pos      (28U)
4942 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
4943 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4944 #define CAN_F6R2_FB29_Pos      (29U)
4945 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4946 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4947 #define CAN_F6R2_FB30_Pos      (30U)
4948 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4949 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4950 #define CAN_F6R2_FB31_Pos      (31U)
4951 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4952 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4953 
4954 /*******************  Bit definition for CAN_F7R2 register  *******************/
4955 #define CAN_F7R2_FB0_Pos       (0U)
4956 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4957 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4958 #define CAN_F7R2_FB1_Pos       (1U)
4959 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4960 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4961 #define CAN_F7R2_FB2_Pos       (2U)
4962 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4963 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4964 #define CAN_F7R2_FB3_Pos       (3U)
4965 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4966 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4967 #define CAN_F7R2_FB4_Pos       (4U)
4968 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4969 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4970 #define CAN_F7R2_FB5_Pos       (5U)
4971 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4972 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4973 #define CAN_F7R2_FB6_Pos       (6U)
4974 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4975 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4976 #define CAN_F7R2_FB7_Pos       (7U)
4977 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4978 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4979 #define CAN_F7R2_FB8_Pos       (8U)
4980 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4981 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4982 #define CAN_F7R2_FB9_Pos       (9U)
4983 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4984 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4985 #define CAN_F7R2_FB10_Pos      (10U)
4986 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
4987 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
4988 #define CAN_F7R2_FB11_Pos      (11U)
4989 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
4990 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
4991 #define CAN_F7R2_FB12_Pos      (12U)
4992 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
4993 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
4994 #define CAN_F7R2_FB13_Pos      (13U)
4995 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
4996 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
4997 #define CAN_F7R2_FB14_Pos      (14U)
4998 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
4999 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
5000 #define CAN_F7R2_FB15_Pos      (15U)
5001 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
5002 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
5003 #define CAN_F7R2_FB16_Pos      (16U)
5004 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
5005 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
5006 #define CAN_F7R2_FB17_Pos      (17U)
5007 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
5008 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
5009 #define CAN_F7R2_FB18_Pos      (18U)
5010 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
5011 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
5012 #define CAN_F7R2_FB19_Pos      (19U)
5013 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
5014 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
5015 #define CAN_F7R2_FB20_Pos      (20U)
5016 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
5017 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
5018 #define CAN_F7R2_FB21_Pos      (21U)
5019 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
5020 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
5021 #define CAN_F7R2_FB22_Pos      (22U)
5022 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
5023 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
5024 #define CAN_F7R2_FB23_Pos      (23U)
5025 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
5026 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
5027 #define CAN_F7R2_FB24_Pos      (24U)
5028 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
5029 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
5030 #define CAN_F7R2_FB25_Pos      (25U)
5031 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
5032 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
5033 #define CAN_F7R2_FB26_Pos      (26U)
5034 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
5035 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
5036 #define CAN_F7R2_FB27_Pos      (27U)
5037 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
5038 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
5039 #define CAN_F7R2_FB28_Pos      (28U)
5040 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
5041 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
5042 #define CAN_F7R2_FB29_Pos      (29U)
5043 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
5044 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
5045 #define CAN_F7R2_FB30_Pos      (30U)
5046 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
5047 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
5048 #define CAN_F7R2_FB31_Pos      (31U)
5049 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
5050 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
5051 
5052 /*******************  Bit definition for CAN_F8R2 register  *******************/
5053 #define CAN_F8R2_FB0_Pos       (0U)
5054 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
5055 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
5056 #define CAN_F8R2_FB1_Pos       (1U)
5057 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
5058 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
5059 #define CAN_F8R2_FB2_Pos       (2U)
5060 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
5061 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
5062 #define CAN_F8R2_FB3_Pos       (3U)
5063 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
5064 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
5065 #define CAN_F8R2_FB4_Pos       (4U)
5066 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
5067 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
5068 #define CAN_F8R2_FB5_Pos       (5U)
5069 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
5070 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
5071 #define CAN_F8R2_FB6_Pos       (6U)
5072 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
5073 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
5074 #define CAN_F8R2_FB7_Pos       (7U)
5075 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
5076 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
5077 #define CAN_F8R2_FB8_Pos       (8U)
5078 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
5079 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
5080 #define CAN_F8R2_FB9_Pos       (9U)
5081 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
5082 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
5083 #define CAN_F8R2_FB10_Pos      (10U)
5084 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
5085 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
5086 #define CAN_F8R2_FB11_Pos      (11U)
5087 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
5088 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
5089 #define CAN_F8R2_FB12_Pos      (12U)
5090 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
5091 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
5092 #define CAN_F8R2_FB13_Pos      (13U)
5093 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
5094 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
5095 #define CAN_F8R2_FB14_Pos      (14U)
5096 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
5097 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
5098 #define CAN_F8R2_FB15_Pos      (15U)
5099 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
5100 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
5101 #define CAN_F8R2_FB16_Pos      (16U)
5102 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
5103 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
5104 #define CAN_F8R2_FB17_Pos      (17U)
5105 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
5106 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
5107 #define CAN_F8R2_FB18_Pos      (18U)
5108 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
5109 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
5110 #define CAN_F8R2_FB19_Pos      (19U)
5111 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
5112 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
5113 #define CAN_F8R2_FB20_Pos      (20U)
5114 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
5115 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
5116 #define CAN_F8R2_FB21_Pos      (21U)
5117 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
5118 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
5119 #define CAN_F8R2_FB22_Pos      (22U)
5120 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
5121 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
5122 #define CAN_F8R2_FB23_Pos      (23U)
5123 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
5124 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
5125 #define CAN_F8R2_FB24_Pos      (24U)
5126 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
5127 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
5128 #define CAN_F8R2_FB25_Pos      (25U)
5129 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
5130 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
5131 #define CAN_F8R2_FB26_Pos      (26U)
5132 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
5133 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
5134 #define CAN_F8R2_FB27_Pos      (27U)
5135 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
5136 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
5137 #define CAN_F8R2_FB28_Pos      (28U)
5138 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
5139 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
5140 #define CAN_F8R2_FB29_Pos      (29U)
5141 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
5142 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
5143 #define CAN_F8R2_FB30_Pos      (30U)
5144 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
5145 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
5146 #define CAN_F8R2_FB31_Pos      (31U)
5147 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
5148 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
5149 
5150 /*******************  Bit definition for CAN_F9R2 register  *******************/
5151 #define CAN_F9R2_FB0_Pos       (0U)
5152 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
5153 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
5154 #define CAN_F9R2_FB1_Pos       (1U)
5155 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
5156 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
5157 #define CAN_F9R2_FB2_Pos       (2U)
5158 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
5159 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
5160 #define CAN_F9R2_FB3_Pos       (3U)
5161 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
5162 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
5163 #define CAN_F9R2_FB4_Pos       (4U)
5164 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
5165 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
5166 #define CAN_F9R2_FB5_Pos       (5U)
5167 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
5168 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5169 #define CAN_F9R2_FB6_Pos       (6U)
5170 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
5171 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5172 #define CAN_F9R2_FB7_Pos       (7U)
5173 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
5174 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5175 #define CAN_F9R2_FB8_Pos       (8U)
5176 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
5177 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5178 #define CAN_F9R2_FB9_Pos       (9U)
5179 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
5180 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5181 #define CAN_F9R2_FB10_Pos      (10U)
5182 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
5183 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5184 #define CAN_F9R2_FB11_Pos      (11U)
5185 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
5186 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5187 #define CAN_F9R2_FB12_Pos      (12U)
5188 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
5189 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5190 #define CAN_F9R2_FB13_Pos      (13U)
5191 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
5192 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5193 #define CAN_F9R2_FB14_Pos      (14U)
5194 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
5195 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5196 #define CAN_F9R2_FB15_Pos      (15U)
5197 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
5198 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5199 #define CAN_F9R2_FB16_Pos      (16U)
5200 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
5201 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5202 #define CAN_F9R2_FB17_Pos      (17U)
5203 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
5204 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5205 #define CAN_F9R2_FB18_Pos      (18U)
5206 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
5207 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5208 #define CAN_F9R2_FB19_Pos      (19U)
5209 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5210 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5211 #define CAN_F9R2_FB20_Pos      (20U)
5212 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5213 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5214 #define CAN_F9R2_FB21_Pos      (21U)
5215 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5216 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5217 #define CAN_F9R2_FB22_Pos      (22U)
5218 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5219 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5220 #define CAN_F9R2_FB23_Pos      (23U)
5221 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5222 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5223 #define CAN_F9R2_FB24_Pos      (24U)
5224 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5225 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5226 #define CAN_F9R2_FB25_Pos      (25U)
5227 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5228 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5229 #define CAN_F9R2_FB26_Pos      (26U)
5230 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5231 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5232 #define CAN_F9R2_FB27_Pos      (27U)
5233 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5234 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5235 #define CAN_F9R2_FB28_Pos      (28U)
5236 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5237 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5238 #define CAN_F9R2_FB29_Pos      (29U)
5239 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5240 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5241 #define CAN_F9R2_FB30_Pos      (30U)
5242 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5243 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5244 #define CAN_F9R2_FB31_Pos      (31U)
5245 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5246 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5247 
5248 /*******************  Bit definition for CAN_F10R2 register  ******************/
5249 #define CAN_F10R2_FB0_Pos      (0U)
5250 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5251 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5252 #define CAN_F10R2_FB1_Pos      (1U)
5253 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5254 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5255 #define CAN_F10R2_FB2_Pos      (2U)
5256 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5257 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5258 #define CAN_F10R2_FB3_Pos      (3U)
5259 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5260 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5261 #define CAN_F10R2_FB4_Pos      (4U)
5262 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5263 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5264 #define CAN_F10R2_FB5_Pos      (5U)
5265 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5266 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5267 #define CAN_F10R2_FB6_Pos      (6U)
5268 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5269 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5270 #define CAN_F10R2_FB7_Pos      (7U)
5271 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5272 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5273 #define CAN_F10R2_FB8_Pos      (8U)
5274 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5275 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5276 #define CAN_F10R2_FB9_Pos      (9U)
5277 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5278 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5279 #define CAN_F10R2_FB10_Pos     (10U)
5280 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5281 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5282 #define CAN_F10R2_FB11_Pos     (11U)
5283 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5284 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5285 #define CAN_F10R2_FB12_Pos     (12U)
5286 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5287 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5288 #define CAN_F10R2_FB13_Pos     (13U)
5289 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5290 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5291 #define CAN_F10R2_FB14_Pos     (14U)
5292 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5293 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5294 #define CAN_F10R2_FB15_Pos     (15U)
5295 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5296 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5297 #define CAN_F10R2_FB16_Pos     (16U)
5298 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5299 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5300 #define CAN_F10R2_FB17_Pos     (17U)
5301 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5302 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5303 #define CAN_F10R2_FB18_Pos     (18U)
5304 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5305 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5306 #define CAN_F10R2_FB19_Pos     (19U)
5307 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5308 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5309 #define CAN_F10R2_FB20_Pos     (20U)
5310 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5311 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5312 #define CAN_F10R2_FB21_Pos     (21U)
5313 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5314 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5315 #define CAN_F10R2_FB22_Pos     (22U)
5316 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5317 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5318 #define CAN_F10R2_FB23_Pos     (23U)
5319 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5320 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5321 #define CAN_F10R2_FB24_Pos     (24U)
5322 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5323 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5324 #define CAN_F10R2_FB25_Pos     (25U)
5325 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5326 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5327 #define CAN_F10R2_FB26_Pos     (26U)
5328 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5329 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5330 #define CAN_F10R2_FB27_Pos     (27U)
5331 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5332 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5333 #define CAN_F10R2_FB28_Pos     (28U)
5334 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5335 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5336 #define CAN_F10R2_FB29_Pos     (29U)
5337 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5338 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5339 #define CAN_F10R2_FB30_Pos     (30U)
5340 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5341 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5342 #define CAN_F10R2_FB31_Pos     (31U)
5343 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5344 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5345 
5346 /*******************  Bit definition for CAN_F11R2 register  ******************/
5347 #define CAN_F11R2_FB0_Pos      (0U)
5348 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5349 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5350 #define CAN_F11R2_FB1_Pos      (1U)
5351 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5352 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5353 #define CAN_F11R2_FB2_Pos      (2U)
5354 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5355 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5356 #define CAN_F11R2_FB3_Pos      (3U)
5357 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5358 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5359 #define CAN_F11R2_FB4_Pos      (4U)
5360 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5361 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5362 #define CAN_F11R2_FB5_Pos      (5U)
5363 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5364 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5365 #define CAN_F11R2_FB6_Pos      (6U)
5366 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5367 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5368 #define CAN_F11R2_FB7_Pos      (7U)
5369 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5370 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5371 #define CAN_F11R2_FB8_Pos      (8U)
5372 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5373 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5374 #define CAN_F11R2_FB9_Pos      (9U)
5375 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5376 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5377 #define CAN_F11R2_FB10_Pos     (10U)
5378 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5379 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5380 #define CAN_F11R2_FB11_Pos     (11U)
5381 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5382 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5383 #define CAN_F11R2_FB12_Pos     (12U)
5384 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5385 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5386 #define CAN_F11R2_FB13_Pos     (13U)
5387 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5388 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5389 #define CAN_F11R2_FB14_Pos     (14U)
5390 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5391 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5392 #define CAN_F11R2_FB15_Pos     (15U)
5393 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5394 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5395 #define CAN_F11R2_FB16_Pos     (16U)
5396 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5397 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5398 #define CAN_F11R2_FB17_Pos     (17U)
5399 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5400 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5401 #define CAN_F11R2_FB18_Pos     (18U)
5402 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5403 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5404 #define CAN_F11R2_FB19_Pos     (19U)
5405 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5406 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5407 #define CAN_F11R2_FB20_Pos     (20U)
5408 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5409 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5410 #define CAN_F11R2_FB21_Pos     (21U)
5411 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5412 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5413 #define CAN_F11R2_FB22_Pos     (22U)
5414 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5415 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5416 #define CAN_F11R2_FB23_Pos     (23U)
5417 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5418 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5419 #define CAN_F11R2_FB24_Pos     (24U)
5420 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5421 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5422 #define CAN_F11R2_FB25_Pos     (25U)
5423 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5424 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5425 #define CAN_F11R2_FB26_Pos     (26U)
5426 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5427 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5428 #define CAN_F11R2_FB27_Pos     (27U)
5429 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5430 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5431 #define CAN_F11R2_FB28_Pos     (28U)
5432 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5433 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5434 #define CAN_F11R2_FB29_Pos     (29U)
5435 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5436 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5437 #define CAN_F11R2_FB30_Pos     (30U)
5438 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5439 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5440 #define CAN_F11R2_FB31_Pos     (31U)
5441 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5442 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5443 
5444 /*******************  Bit definition for CAN_F12R2 register  ******************/
5445 #define CAN_F12R2_FB0_Pos      (0U)
5446 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5447 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5448 #define CAN_F12R2_FB1_Pos      (1U)
5449 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5450 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5451 #define CAN_F12R2_FB2_Pos      (2U)
5452 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5453 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5454 #define CAN_F12R2_FB3_Pos      (3U)
5455 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5456 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5457 #define CAN_F12R2_FB4_Pos      (4U)
5458 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5459 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5460 #define CAN_F12R2_FB5_Pos      (5U)
5461 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5462 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5463 #define CAN_F12R2_FB6_Pos      (6U)
5464 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5465 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5466 #define CAN_F12R2_FB7_Pos      (7U)
5467 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5468 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5469 #define CAN_F12R2_FB8_Pos      (8U)
5470 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5471 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5472 #define CAN_F12R2_FB9_Pos      (9U)
5473 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5474 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5475 #define CAN_F12R2_FB10_Pos     (10U)
5476 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5477 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5478 #define CAN_F12R2_FB11_Pos     (11U)
5479 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5480 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5481 #define CAN_F12R2_FB12_Pos     (12U)
5482 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5483 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5484 #define CAN_F12R2_FB13_Pos     (13U)
5485 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5486 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5487 #define CAN_F12R2_FB14_Pos     (14U)
5488 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5489 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5490 #define CAN_F12R2_FB15_Pos     (15U)
5491 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5492 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5493 #define CAN_F12R2_FB16_Pos     (16U)
5494 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5495 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5496 #define CAN_F12R2_FB17_Pos     (17U)
5497 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5498 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5499 #define CAN_F12R2_FB18_Pos     (18U)
5500 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5501 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5502 #define CAN_F12R2_FB19_Pos     (19U)
5503 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5504 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5505 #define CAN_F12R2_FB20_Pos     (20U)
5506 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5507 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5508 #define CAN_F12R2_FB21_Pos     (21U)
5509 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5510 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5511 #define CAN_F12R2_FB22_Pos     (22U)
5512 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5513 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5514 #define CAN_F12R2_FB23_Pos     (23U)
5515 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5516 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5517 #define CAN_F12R2_FB24_Pos     (24U)
5518 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5519 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5520 #define CAN_F12R2_FB25_Pos     (25U)
5521 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5522 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5523 #define CAN_F12R2_FB26_Pos     (26U)
5524 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5525 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5526 #define CAN_F12R2_FB27_Pos     (27U)
5527 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5528 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5529 #define CAN_F12R2_FB28_Pos     (28U)
5530 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5531 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5532 #define CAN_F12R2_FB29_Pos     (29U)
5533 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5534 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5535 #define CAN_F12R2_FB30_Pos     (30U)
5536 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5537 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5538 #define CAN_F12R2_FB31_Pos     (31U)
5539 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5540 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5541 
5542 /*******************  Bit definition for CAN_F13R2 register  ******************/
5543 #define CAN_F13R2_FB0_Pos      (0U)
5544 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5545 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5546 #define CAN_F13R2_FB1_Pos      (1U)
5547 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5548 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5549 #define CAN_F13R2_FB2_Pos      (2U)
5550 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5551 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5552 #define CAN_F13R2_FB3_Pos      (3U)
5553 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5554 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5555 #define CAN_F13R2_FB4_Pos      (4U)
5556 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5557 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5558 #define CAN_F13R2_FB5_Pos      (5U)
5559 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5560 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5561 #define CAN_F13R2_FB6_Pos      (6U)
5562 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5563 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5564 #define CAN_F13R2_FB7_Pos      (7U)
5565 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5566 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5567 #define CAN_F13R2_FB8_Pos      (8U)
5568 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5569 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5570 #define CAN_F13R2_FB9_Pos      (9U)
5571 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5572 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5573 #define CAN_F13R2_FB10_Pos     (10U)
5574 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5575 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5576 #define CAN_F13R2_FB11_Pos     (11U)
5577 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5578 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5579 #define CAN_F13R2_FB12_Pos     (12U)
5580 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5581 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5582 #define CAN_F13R2_FB13_Pos     (13U)
5583 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5584 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5585 #define CAN_F13R2_FB14_Pos     (14U)
5586 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5587 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5588 #define CAN_F13R2_FB15_Pos     (15U)
5589 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5590 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5591 #define CAN_F13R2_FB16_Pos     (16U)
5592 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5593 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5594 #define CAN_F13R2_FB17_Pos     (17U)
5595 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5596 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5597 #define CAN_F13R2_FB18_Pos     (18U)
5598 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5599 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5600 #define CAN_F13R2_FB19_Pos     (19U)
5601 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5602 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5603 #define CAN_F13R2_FB20_Pos     (20U)
5604 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5605 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5606 #define CAN_F13R2_FB21_Pos     (21U)
5607 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5608 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5609 #define CAN_F13R2_FB22_Pos     (22U)
5610 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5611 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5612 #define CAN_F13R2_FB23_Pos     (23U)
5613 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
5614 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5615 #define CAN_F13R2_FB24_Pos     (24U)
5616 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
5617 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5618 #define CAN_F13R2_FB25_Pos     (25U)
5619 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
5620 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5621 #define CAN_F13R2_FB26_Pos     (26U)
5622 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
5623 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5624 #define CAN_F13R2_FB27_Pos     (27U)
5625 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
5626 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5627 #define CAN_F13R2_FB28_Pos     (28U)
5628 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
5629 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5630 #define CAN_F13R2_FB29_Pos     (29U)
5631 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
5632 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5633 #define CAN_F13R2_FB30_Pos     (30U)
5634 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
5635 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5636 #define CAN_F13R2_FB31_Pos     (31U)
5637 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
5638 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5639 
5640 /******************************************************************************/
5641 /*                                                                            */
5642 /*                          CRC calculation unit                              */
5643 /*                                                                            */
5644 /******************************************************************************/
5645 /*******************  Bit definition for CRC_DR register  *********************/
5646 #define CRC_DR_DR_Pos       (0U)
5647 #define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
5648 #define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
5649 
5650 
5651 /*******************  Bit definition for CRC_IDR register  ********************/
5652 #define CRC_IDR_IDR_Pos     (0U)
5653 #define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
5654 #define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
5655 
5656 
5657 /********************  Bit definition for CRC_CR register  ********************/
5658 #define CRC_CR_RESET_Pos    (0U)
5659 #define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
5660 #define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
5661 
5662 /******************************************************************************/
5663 /*                                                                            */
5664 /*                            Crypto Processor                                */
5665 /*                                                                            */
5666 /******************************************************************************/
5667 /******************* Bits definition for CRYP_CR register  ********************/
5668 #define CRYP_CR_ALGODIR_Pos              (2U)
5669 #define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)         /*!< 0x00000004 */
5670 #define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk
5671 
5672 #define CRYP_CR_ALGOMODE_Pos             (3U)
5673 #define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00080038 */
5674 #define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk
5675 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
5676 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
5677 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
5678 #define CRYP_CR_ALGOMODE_TDES_ECB        0x00000000U
5679 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
5680 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5681 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
5682 #define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)
5683 #define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5684 #define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk
5685 #define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)
5686 #define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5687 #define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk
5688 #define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
5689 #define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5690 #define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
5691 #define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
5692 #define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5693 #define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
5694 #define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
5695 #define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5696 #define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
5697 #define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
5698 #define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5699 #define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
5700 #define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)
5701 #define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
5702 #define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk
5703 #define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)
5704 #define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
5705 #define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk
5706 
5707 #define CRYP_CR_DATATYPE_Pos             (6U)
5708 #define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x000000C0 */
5709 #define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk
5710 #define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */
5711 #define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */
5712 #define CRYP_CR_KEYSIZE_Pos              (8U)
5713 #define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000300 */
5714 #define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk
5715 #define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */
5716 #define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */
5717 #define CRYP_CR_FFLUSH_Pos               (14U)
5718 #define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)          /*!< 0x00004000 */
5719 #define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk
5720 #define CRYP_CR_CRYPEN_Pos               (15U)
5721 #define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)          /*!< 0x00008000 */
5722 #define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk
5723 
5724 #define CRYP_CR_GCM_CCMPH_Pos            (16U)
5725 #define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00030000 */
5726 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
5727 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
5728 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
5729 #define CRYP_CR_ALGOMODE_3               0x00080000U
5730 
5731 /****************** Bits definition for CRYP_SR register  *********************/
5732 #define CRYP_SR_IFEM_Pos                 (0U)
5733 #define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)            /*!< 0x00000001 */
5734 #define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk
5735 #define CRYP_SR_IFNF_Pos                 (1U)
5736 #define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)            /*!< 0x00000002 */
5737 #define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk
5738 #define CRYP_SR_OFNE_Pos                 (2U)
5739 #define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)            /*!< 0x00000004 */
5740 #define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk
5741 #define CRYP_SR_OFFU_Pos                 (3U)
5742 #define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)            /*!< 0x00000008 */
5743 #define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk
5744 #define CRYP_SR_BUSY_Pos                 (4U)
5745 #define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)            /*!< 0x00000010 */
5746 #define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk
5747 /****************** Bits definition for CRYP_DMACR register  ******************/
5748 #define CRYP_DMACR_DIEN_Pos              (0U)
5749 #define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)         /*!< 0x00000001 */
5750 #define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk
5751 #define CRYP_DMACR_DOEN_Pos              (1U)
5752 #define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)         /*!< 0x00000002 */
5753 #define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk
5754 /*****************  Bits definition for CRYP_IMSCR register  ******************/
5755 #define CRYP_IMSCR_INIM_Pos              (0U)
5756 #define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)         /*!< 0x00000001 */
5757 #define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk
5758 #define CRYP_IMSCR_OUTIM_Pos             (1U)
5759 #define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)        /*!< 0x00000002 */
5760 #define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk
5761 /****************** Bits definition for CRYP_RISR register  *******************/
5762 #define CRYP_RISR_OUTRIS_Pos             (0U)
5763 #define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)        /*!< 0x00000001 */
5764 #define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk
5765 #define CRYP_RISR_INRIS_Pos              (1U)
5766 #define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)         /*!< 0x00000002 */
5767 #define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk
5768 /****************** Bits definition for CRYP_MISR register  *******************/
5769 #define CRYP_MISR_INMIS_Pos              (0U)
5770 #define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)         /*!< 0x00000001 */
5771 #define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk
5772 #define CRYP_MISR_OUTMIS_Pos             (1U)
5773 #define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)        /*!< 0x00000002 */
5774 #define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk
5775 
5776 /******************************************************************************/
5777 /*                                                                            */
5778 /*                      Digital to Analog Converter                           */
5779 /*                                                                            */
5780 /******************************************************************************/
5781 /*
5782  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5783  */
5784 #define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5785 /********************  Bit definition for DAC_CR register  ********************/
5786 #define DAC_CR_EN1_Pos              (0U)
5787 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5788 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5789 #define DAC_CR_BOFF1_Pos            (1U)
5790 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5791 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
5792 #define DAC_CR_TEN1_Pos             (2U)
5793 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5794 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5795 
5796 #define DAC_CR_TSEL1_Pos            (3U)
5797 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5798 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5799 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5800 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5801 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5802 
5803 #define DAC_CR_WAVE1_Pos            (6U)
5804 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5805 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5806 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5807 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5808 
5809 #define DAC_CR_MAMP1_Pos            (8U)
5810 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5811 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5812 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5813 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5814 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5815 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5816 
5817 #define DAC_CR_DMAEN1_Pos           (12U)
5818 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5819 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5820 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5821 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5822 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
5823 #define DAC_CR_EN2_Pos              (16U)
5824 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5825 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5826 #define DAC_CR_BOFF2_Pos            (17U)
5827 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5828 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
5829 #define DAC_CR_TEN2_Pos             (18U)
5830 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5831 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5832 
5833 #define DAC_CR_TSEL2_Pos            (19U)
5834 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5835 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5836 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5837 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5838 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5839 
5840 #define DAC_CR_WAVE2_Pos            (22U)
5841 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5842 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5843 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5844 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5845 
5846 #define DAC_CR_MAMP2_Pos            (24U)
5847 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5848 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5849 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5850 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5851 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5852 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5853 
5854 #define DAC_CR_DMAEN2_Pos           (28U)
5855 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5856 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5857 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5858 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5859 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
5860 
5861 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5862 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5863 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5864 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5865 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5866 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5867 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5868 
5869 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5870 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5871 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5872 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5873 
5874 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5875 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5876 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5877 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5878 
5879 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5880 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5881 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5882 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5883 
5884 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5885 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5886 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5887 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5888 
5889 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5890 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5891 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5892 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5893 
5894 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5895 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5896 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5897 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5898 
5899 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5900 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5901 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5902 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5903 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5904 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5905 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5906 
5907 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5908 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5909 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5910 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5911 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5912 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5913 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5914 
5915 /******************  Bit definition for DAC_DHR8RD register  ******************/
5916 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5917 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5918 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5919 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5920 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5921 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5922 
5923 /*******************  Bit definition for DAC_DOR1 register  *******************/
5924 #define DAC_DOR1_DACC1DOR_Pos       (0U)
5925 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
5926 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
5927 
5928 /*******************  Bit definition for DAC_DOR2 register  *******************/
5929 #define DAC_DOR2_DACC2DOR_Pos       (0U)
5930 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
5931 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
5932 
5933 /********************  Bit definition for DAC_SR register  ********************/
5934 #define DAC_SR_DMAUDR1_Pos          (13U)
5935 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
5936 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
5937 #define DAC_SR_DMAUDR2_Pos          (29U)
5938 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
5939 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
5940 
5941 /******************************************************************************/
5942 /*                                                                            */
5943 /*                                    DCMI                                    */
5944 /*                                                                            */
5945 /******************************************************************************/
5946 /********************  Bits definition for DCMI_CR register  ******************/
5947 #define DCMI_CR_CAPTURE_Pos        (0U)
5948 #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
5949 #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
5950 #define DCMI_CR_CM_Pos             (1U)
5951 #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
5952 #define DCMI_CR_CM                 DCMI_CR_CM_Msk
5953 #define DCMI_CR_CROP_Pos           (2U)
5954 #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
5955 #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
5956 #define DCMI_CR_JPEG_Pos           (3U)
5957 #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
5958 #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
5959 #define DCMI_CR_ESS_Pos            (4U)
5960 #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
5961 #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
5962 #define DCMI_CR_PCKPOL_Pos         (5U)
5963 #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
5964 #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
5965 #define DCMI_CR_HSPOL_Pos          (6U)
5966 #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
5967 #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
5968 #define DCMI_CR_VSPOL_Pos          (7U)
5969 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
5970 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
5971 #define DCMI_CR_FCRC_0             0x00000100U
5972 #define DCMI_CR_FCRC_1             0x00000200U
5973 #define DCMI_CR_EDM_0              0x00000400U
5974 #define DCMI_CR_EDM_1              0x00000800U
5975 #define DCMI_CR_ENABLE_Pos         (14U)
5976 #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
5977 #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
5978 
5979 /********************  Bits definition for DCMI_SR register  ******************/
5980 #define DCMI_SR_HSYNC_Pos          (0U)
5981 #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
5982 #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
5983 #define DCMI_SR_VSYNC_Pos          (1U)
5984 #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
5985 #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
5986 #define DCMI_SR_FNE_Pos            (2U)
5987 #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
5988 #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
5989 
5990 /********************  Bits definition for DCMI_RIS register  *****************/
5991 #define DCMI_RIS_FRAME_RIS_Pos     (0U)
5992 #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
5993 #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
5994 #define DCMI_RIS_OVR_RIS_Pos       (1U)
5995 #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
5996 #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
5997 #define DCMI_RIS_ERR_RIS_Pos       (2U)
5998 #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
5999 #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
6000 #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
6001 #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
6002 #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
6003 #define DCMI_RIS_LINE_RIS_Pos      (4U)
6004 #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
6005 #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
6006 /* Legacy defines */
6007 #define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
6008 #define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
6009 #define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
6010 #define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
6011 #define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
6012 #define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
6013 
6014 /********************  Bits definition for DCMI_IER register  *****************/
6015 #define DCMI_IER_FRAME_IE_Pos      (0U)
6016 #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
6017 #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
6018 #define DCMI_IER_OVR_IE_Pos        (1U)
6019 #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
6020 #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
6021 #define DCMI_IER_ERR_IE_Pos        (2U)
6022 #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
6023 #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
6024 #define DCMI_IER_VSYNC_IE_Pos      (3U)
6025 #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
6026 #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
6027 #define DCMI_IER_LINE_IE_Pos       (4U)
6028 #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
6029 #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
6030 /* Legacy defines */
6031 #define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
6032 
6033 /********************  Bits definition for DCMI_MIS register  *****************/
6034 #define DCMI_MIS_FRAME_MIS_Pos     (0U)
6035 #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
6036 #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
6037 #define DCMI_MIS_OVR_MIS_Pos       (1U)
6038 #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
6039 #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
6040 #define DCMI_MIS_ERR_MIS_Pos       (2U)
6041 #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
6042 #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
6043 #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
6044 #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
6045 #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
6046 #define DCMI_MIS_LINE_MIS_Pos      (4U)
6047 #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
6048 #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
6049 
6050 /* Legacy defines */
6051 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
6052 #define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
6053 #define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
6054 #define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
6055 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
6056 
6057 /********************  Bits definition for DCMI_ICR register  *****************/
6058 #define DCMI_ICR_FRAME_ISC_Pos     (0U)
6059 #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
6060 #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
6061 #define DCMI_ICR_OVR_ISC_Pos       (1U)
6062 #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
6063 #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
6064 #define DCMI_ICR_ERR_ISC_Pos       (2U)
6065 #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
6066 #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
6067 #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
6068 #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
6069 #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
6070 #define DCMI_ICR_LINE_ISC_Pos      (4U)
6071 #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
6072 #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
6073 
6074 /* Legacy defines */
6075 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
6076 
6077 /********************  Bits definition for DCMI_ESCR register  ******************/
6078 #define DCMI_ESCR_FSC_Pos          (0U)
6079 #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
6080 #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
6081 #define DCMI_ESCR_LSC_Pos          (8U)
6082 #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
6083 #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
6084 #define DCMI_ESCR_LEC_Pos          (16U)
6085 #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
6086 #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
6087 #define DCMI_ESCR_FEC_Pos          (24U)
6088 #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
6089 #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
6090 
6091 /********************  Bits definition for DCMI_ESUR register  ******************/
6092 #define DCMI_ESUR_FSU_Pos          (0U)
6093 #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
6094 #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
6095 #define DCMI_ESUR_LSU_Pos          (8U)
6096 #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
6097 #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
6098 #define DCMI_ESUR_LEU_Pos          (16U)
6099 #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
6100 #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
6101 #define DCMI_ESUR_FEU_Pos          (24U)
6102 #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
6103 #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
6104 
6105 /********************  Bits definition for DCMI_CWSTRT register  ******************/
6106 #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
6107 #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
6108 #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
6109 #define DCMI_CWSTRT_VST_Pos        (16U)
6110 #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
6111 #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
6112 
6113 /********************  Bits definition for DCMI_CWSIZE register  ******************/
6114 #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
6115 #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
6116 #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
6117 #define DCMI_CWSIZE_VLINE_Pos      (16U)
6118 #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
6119 #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
6120 
6121 /********************  Bits definition for DCMI_DR register  *********************/
6122 #define DCMI_DR_BYTE0_Pos          (0U)
6123 #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
6124 #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
6125 #define DCMI_DR_BYTE1_Pos          (8U)
6126 #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
6127 #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
6128 #define DCMI_DR_BYTE2_Pos          (16U)
6129 #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
6130 #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
6131 #define DCMI_DR_BYTE3_Pos          (24U)
6132 #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
6133 #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
6134 
6135 /******************************************************************************/
6136 /*                                                                            */
6137 /*                             DMA Controller                                 */
6138 /*                                                                            */
6139 /******************************************************************************/
6140 /********************  Bits definition for DMA_SxCR register  *****************/
6141 #define DMA_SxCR_CHSEL_Pos       (25U)
6142 #define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
6143 #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
6144 #define DMA_SxCR_CHSEL_0         0x02000000U
6145 #define DMA_SxCR_CHSEL_1         0x04000000U
6146 #define DMA_SxCR_CHSEL_2         0x08000000U
6147 #define DMA_SxCR_MBURST_Pos      (23U)
6148 #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
6149 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
6150 #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
6151 #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
6152 #define DMA_SxCR_PBURST_Pos      (21U)
6153 #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
6154 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
6155 #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
6156 #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
6157 #define DMA_SxCR_CT_Pos          (19U)
6158 #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
6159 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
6160 #define DMA_SxCR_DBM_Pos         (18U)
6161 #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
6162 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
6163 #define DMA_SxCR_PL_Pos          (16U)
6164 #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
6165 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
6166 #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
6167 #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
6168 #define DMA_SxCR_PINCOS_Pos      (15U)
6169 #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
6170 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
6171 #define DMA_SxCR_MSIZE_Pos       (13U)
6172 #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
6173 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
6174 #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
6175 #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
6176 #define DMA_SxCR_PSIZE_Pos       (11U)
6177 #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
6178 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
6179 #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
6180 #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
6181 #define DMA_SxCR_MINC_Pos        (10U)
6182 #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
6183 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
6184 #define DMA_SxCR_PINC_Pos        (9U)
6185 #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
6186 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
6187 #define DMA_SxCR_CIRC_Pos        (8U)
6188 #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
6189 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
6190 #define DMA_SxCR_DIR_Pos         (6U)
6191 #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
6192 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
6193 #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
6194 #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
6195 #define DMA_SxCR_PFCTRL_Pos      (5U)
6196 #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
6197 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
6198 #define DMA_SxCR_TCIE_Pos        (4U)
6199 #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
6200 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
6201 #define DMA_SxCR_HTIE_Pos        (3U)
6202 #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
6203 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
6204 #define DMA_SxCR_TEIE_Pos        (2U)
6205 #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
6206 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
6207 #define DMA_SxCR_DMEIE_Pos       (1U)
6208 #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
6209 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
6210 #define DMA_SxCR_EN_Pos          (0U)
6211 #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
6212 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
6213 
6214 /* Legacy defines */
6215 #define DMA_SxCR_ACK_Pos         (20U)
6216 #define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
6217 #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
6218 
6219 /********************  Bits definition for DMA_SxCNDTR register  **************/
6220 #define DMA_SxNDT_Pos            (0U)
6221 #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
6222 #define DMA_SxNDT                DMA_SxNDT_Msk
6223 #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
6224 #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
6225 #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
6226 #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
6227 #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
6228 #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
6229 #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
6230 #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
6231 #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
6232 #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
6233 #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
6234 #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
6235 #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
6236 #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
6237 #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
6238 #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
6239 
6240 /********************  Bits definition for DMA_SxFCR register  ****************/
6241 #define DMA_SxFCR_FEIE_Pos       (7U)
6242 #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
6243 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
6244 #define DMA_SxFCR_FS_Pos         (3U)
6245 #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
6246 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
6247 #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6248 #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6249 #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6250 #define DMA_SxFCR_DMDIS_Pos      (2U)
6251 #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
6252 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
6253 #define DMA_SxFCR_FTH_Pos        (0U)
6254 #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
6255 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
6256 #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6257 #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6258 
6259 /********************  Bits definition for DMA_LISR register  *****************/
6260 #define DMA_LISR_TCIF3_Pos       (27U)
6261 #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
6262 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
6263 #define DMA_LISR_HTIF3_Pos       (26U)
6264 #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
6265 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
6266 #define DMA_LISR_TEIF3_Pos       (25U)
6267 #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
6268 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
6269 #define DMA_LISR_DMEIF3_Pos      (24U)
6270 #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
6271 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
6272 #define DMA_LISR_FEIF3_Pos       (22U)
6273 #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
6274 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
6275 #define DMA_LISR_TCIF2_Pos       (21U)
6276 #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
6277 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
6278 #define DMA_LISR_HTIF2_Pos       (20U)
6279 #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
6280 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
6281 #define DMA_LISR_TEIF2_Pos       (19U)
6282 #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
6283 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
6284 #define DMA_LISR_DMEIF2_Pos      (18U)
6285 #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
6286 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
6287 #define DMA_LISR_FEIF2_Pos       (16U)
6288 #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
6289 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
6290 #define DMA_LISR_TCIF1_Pos       (11U)
6291 #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
6292 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
6293 #define DMA_LISR_HTIF1_Pos       (10U)
6294 #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
6295 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
6296 #define DMA_LISR_TEIF1_Pos       (9U)
6297 #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
6298 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
6299 #define DMA_LISR_DMEIF1_Pos      (8U)
6300 #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
6301 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
6302 #define DMA_LISR_FEIF1_Pos       (6U)
6303 #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
6304 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
6305 #define DMA_LISR_TCIF0_Pos       (5U)
6306 #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
6307 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
6308 #define DMA_LISR_HTIF0_Pos       (4U)
6309 #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
6310 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
6311 #define DMA_LISR_TEIF0_Pos       (3U)
6312 #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
6313 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
6314 #define DMA_LISR_DMEIF0_Pos      (2U)
6315 #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
6316 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
6317 #define DMA_LISR_FEIF0_Pos       (0U)
6318 #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
6319 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
6320 
6321 /********************  Bits definition for DMA_HISR register  *****************/
6322 #define DMA_HISR_TCIF7_Pos       (27U)
6323 #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
6324 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
6325 #define DMA_HISR_HTIF7_Pos       (26U)
6326 #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
6327 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
6328 #define DMA_HISR_TEIF7_Pos       (25U)
6329 #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
6330 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
6331 #define DMA_HISR_DMEIF7_Pos      (24U)
6332 #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
6333 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
6334 #define DMA_HISR_FEIF7_Pos       (22U)
6335 #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
6336 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
6337 #define DMA_HISR_TCIF6_Pos       (21U)
6338 #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
6339 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
6340 #define DMA_HISR_HTIF6_Pos       (20U)
6341 #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
6342 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
6343 #define DMA_HISR_TEIF6_Pos       (19U)
6344 #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
6345 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
6346 #define DMA_HISR_DMEIF6_Pos      (18U)
6347 #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
6348 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
6349 #define DMA_HISR_FEIF6_Pos       (16U)
6350 #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
6351 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
6352 #define DMA_HISR_TCIF5_Pos       (11U)
6353 #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
6354 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
6355 #define DMA_HISR_HTIF5_Pos       (10U)
6356 #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
6357 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
6358 #define DMA_HISR_TEIF5_Pos       (9U)
6359 #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
6360 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
6361 #define DMA_HISR_DMEIF5_Pos      (8U)
6362 #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
6363 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
6364 #define DMA_HISR_FEIF5_Pos       (6U)
6365 #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
6366 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
6367 #define DMA_HISR_TCIF4_Pos       (5U)
6368 #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
6369 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
6370 #define DMA_HISR_HTIF4_Pos       (4U)
6371 #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
6372 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
6373 #define DMA_HISR_TEIF4_Pos       (3U)
6374 #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
6375 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
6376 #define DMA_HISR_DMEIF4_Pos      (2U)
6377 #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
6378 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
6379 #define DMA_HISR_FEIF4_Pos       (0U)
6380 #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
6381 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
6382 
6383 /********************  Bits definition for DMA_LIFCR register  ****************/
6384 #define DMA_LIFCR_CTCIF3_Pos     (27U)
6385 #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
6386 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
6387 #define DMA_LIFCR_CHTIF3_Pos     (26U)
6388 #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
6389 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
6390 #define DMA_LIFCR_CTEIF3_Pos     (25U)
6391 #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
6392 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
6393 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
6394 #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
6395 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
6396 #define DMA_LIFCR_CFEIF3_Pos     (22U)
6397 #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
6398 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
6399 #define DMA_LIFCR_CTCIF2_Pos     (21U)
6400 #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
6401 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
6402 #define DMA_LIFCR_CHTIF2_Pos     (20U)
6403 #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
6404 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
6405 #define DMA_LIFCR_CTEIF2_Pos     (19U)
6406 #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
6407 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
6408 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
6409 #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
6410 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
6411 #define DMA_LIFCR_CFEIF2_Pos     (16U)
6412 #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
6413 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
6414 #define DMA_LIFCR_CTCIF1_Pos     (11U)
6415 #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
6416 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
6417 #define DMA_LIFCR_CHTIF1_Pos     (10U)
6418 #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
6419 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
6420 #define DMA_LIFCR_CTEIF1_Pos     (9U)
6421 #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
6422 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
6423 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
6424 #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
6425 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
6426 #define DMA_LIFCR_CFEIF1_Pos     (6U)
6427 #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
6428 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
6429 #define DMA_LIFCR_CTCIF0_Pos     (5U)
6430 #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
6431 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
6432 #define DMA_LIFCR_CHTIF0_Pos     (4U)
6433 #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
6434 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
6435 #define DMA_LIFCR_CTEIF0_Pos     (3U)
6436 #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6437 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
6438 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
6439 #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
6440 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
6441 #define DMA_LIFCR_CFEIF0_Pos     (0U)
6442 #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
6443 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
6444 
6445 /********************  Bits definition for DMA_HIFCR  register  ****************/
6446 #define DMA_HIFCR_CTCIF7_Pos     (27U)
6447 #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
6448 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
6449 #define DMA_HIFCR_CHTIF7_Pos     (26U)
6450 #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
6451 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
6452 #define DMA_HIFCR_CTEIF7_Pos     (25U)
6453 #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
6454 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
6455 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
6456 #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
6457 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
6458 #define DMA_HIFCR_CFEIF7_Pos     (22U)
6459 #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
6460 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
6461 #define DMA_HIFCR_CTCIF6_Pos     (21U)
6462 #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
6463 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
6464 #define DMA_HIFCR_CHTIF6_Pos     (20U)
6465 #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
6466 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
6467 #define DMA_HIFCR_CTEIF6_Pos     (19U)
6468 #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
6469 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
6470 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
6471 #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
6472 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
6473 #define DMA_HIFCR_CFEIF6_Pos     (16U)
6474 #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
6475 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
6476 #define DMA_HIFCR_CTCIF5_Pos     (11U)
6477 #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
6478 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
6479 #define DMA_HIFCR_CHTIF5_Pos     (10U)
6480 #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
6481 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
6482 #define DMA_HIFCR_CTEIF5_Pos     (9U)
6483 #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
6484 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
6485 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
6486 #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
6487 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
6488 #define DMA_HIFCR_CFEIF5_Pos     (6U)
6489 #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
6490 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
6491 #define DMA_HIFCR_CTCIF4_Pos     (5U)
6492 #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
6493 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
6494 #define DMA_HIFCR_CHTIF4_Pos     (4U)
6495 #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
6496 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
6497 #define DMA_HIFCR_CTEIF4_Pos     (3U)
6498 #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
6499 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
6500 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
6501 #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
6502 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
6503 #define DMA_HIFCR_CFEIF4_Pos     (0U)
6504 #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
6505 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
6506 
6507 /******************  Bit definition for DMA_SxPAR register  ********************/
6508 #define DMA_SxPAR_PA_Pos         (0U)
6509 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6510 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
6511 
6512 /******************  Bit definition for DMA_SxM0AR register  ********************/
6513 #define DMA_SxM0AR_M0A_Pos       (0U)
6514 #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
6515 #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
6516 
6517 /******************  Bit definition for DMA_SxM1AR register  ********************/
6518 #define DMA_SxM1AR_M1A_Pos       (0U)
6519 #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
6520 #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
6521 
6522 
6523 /******************************************************************************/
6524 /*                                                                            */
6525 /*                         AHB Master DMA2D Controller (DMA2D)                */
6526 /*                                                                            */
6527 /******************************************************************************/
6528 
6529 /********************  Bit definition for DMA2D_CR register  ******************/
6530 
6531 #define DMA2D_CR_START_Pos         (0U)
6532 #define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
6533 #define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
6534 #define DMA2D_CR_SUSP_Pos          (1U)
6535 #define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
6536 #define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
6537 #define DMA2D_CR_ABORT_Pos         (2U)
6538 #define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
6539 #define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
6540 #define DMA2D_CR_TEIE_Pos          (8U)
6541 #define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
6542 #define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
6543 #define DMA2D_CR_TCIE_Pos          (9U)
6544 #define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
6545 #define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
6546 #define DMA2D_CR_TWIE_Pos          (10U)
6547 #define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
6548 #define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
6549 #define DMA2D_CR_CAEIE_Pos         (11U)
6550 #define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
6551 #define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
6552 #define DMA2D_CR_CTCIE_Pos         (12U)
6553 #define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
6554 #define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
6555 #define DMA2D_CR_CEIE_Pos          (13U)
6556 #define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
6557 #define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
6558 #define DMA2D_CR_MODE_Pos          (16U)
6559 #define DMA2D_CR_MODE_Msk          (0x3UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
6560 #define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */
6561 #define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
6562 #define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
6563 
6564 /********************  Bit definition for DMA2D_ISR register  *****************/
6565 
6566 #define DMA2D_ISR_TEIF_Pos         (0U)
6567 #define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
6568 #define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
6569 #define DMA2D_ISR_TCIF_Pos         (1U)
6570 #define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
6571 #define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
6572 #define DMA2D_ISR_TWIF_Pos         (2U)
6573 #define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
6574 #define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
6575 #define DMA2D_ISR_CAEIF_Pos        (3U)
6576 #define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
6577 #define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
6578 #define DMA2D_ISR_CTCIF_Pos        (4U)
6579 #define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
6580 #define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
6581 #define DMA2D_ISR_CEIF_Pos         (5U)
6582 #define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
6583 #define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
6584 
6585 /********************  Bit definition for DMA2D_IFCR register  ****************/
6586 
6587 #define DMA2D_IFCR_CTEIF_Pos       (0U)
6588 #define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
6589 #define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
6590 #define DMA2D_IFCR_CTCIF_Pos       (1U)
6591 #define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
6592 #define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
6593 #define DMA2D_IFCR_CTWIF_Pos       (2U)
6594 #define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
6595 #define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
6596 #define DMA2D_IFCR_CAECIF_Pos      (3U)
6597 #define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
6598 #define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
6599 #define DMA2D_IFCR_CCTCIF_Pos      (4U)
6600 #define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
6601 #define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
6602 #define DMA2D_IFCR_CCEIF_Pos       (5U)
6603 #define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
6604 #define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
6605 
6606 /* Legacy defines */
6607 #define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
6608 #define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
6609 #define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
6610 #define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
6611 #define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
6612 #define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
6613 
6614 /********************  Bit definition for DMA2D_FGMAR register  ***************/
6615 
6616 #define DMA2D_FGMAR_MA_Pos         (0U)
6617 #define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6618 #define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
6619 
6620 /********************  Bit definition for DMA2D_FGOR register  ****************/
6621 
6622 #define DMA2D_FGOR_LO_Pos          (0U)
6623 #define DMA2D_FGOR_LO_Msk          (0x3FFFUL << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
6624 #define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
6625 
6626 /********************  Bit definition for DMA2D_BGMAR register  ***************/
6627 
6628 #define DMA2D_BGMAR_MA_Pos         (0U)
6629 #define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
6630 #define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
6631 
6632 /********************  Bit definition for DMA2D_BGOR register  ****************/
6633 
6634 #define DMA2D_BGOR_LO_Pos          (0U)
6635 #define DMA2D_BGOR_LO_Msk          (0x3FFFUL << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
6636 #define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
6637 
6638 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
6639 
6640 #define DMA2D_FGPFCCR_CM_Pos       (0U)
6641 #define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
6642 #define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6643 #define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
6644 #define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
6645 #define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
6646 #define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
6647 #define DMA2D_FGPFCCR_CCM_Pos      (4U)
6648 #define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6649 #define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6650 #define DMA2D_FGPFCCR_START_Pos    (5U)
6651 #define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
6652 #define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
6653 #define DMA2D_FGPFCCR_CS_Pos       (8U)
6654 #define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6655 #define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
6656 #define DMA2D_FGPFCCR_AM_Pos       (16U)
6657 #define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
6658 #define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6659 #define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
6660 #define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
6661 #define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
6662 #define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6663 #define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
6664 
6665 /********************  Bit definition for DMA2D_FGCOLR register  **************/
6666 
6667 #define DMA2D_FGCOLR_BLUE_Pos      (0U)
6668 #define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6669 #define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
6670 #define DMA2D_FGCOLR_GREEN_Pos     (8U)
6671 #define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6672 #define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
6673 #define DMA2D_FGCOLR_RED_Pos       (16U)
6674 #define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6675 #define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
6676 
6677 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
6678 
6679 #define DMA2D_BGPFCCR_CM_Pos       (0U)
6680 #define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
6681 #define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
6682 #define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
6683 #define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
6684 #define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
6685 #define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */
6686 #define DMA2D_BGPFCCR_CCM_Pos      (4U)
6687 #define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
6688 #define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
6689 #define DMA2D_BGPFCCR_START_Pos    (5U)
6690 #define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
6691 #define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
6692 #define DMA2D_BGPFCCR_CS_Pos       (8U)
6693 #define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
6694 #define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
6695 #define DMA2D_BGPFCCR_AM_Pos       (16U)
6696 #define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
6697 #define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
6698 #define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
6699 #define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
6700 #define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
6701 #define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
6702 #define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
6703 
6704 /********************  Bit definition for DMA2D_BGCOLR register  **************/
6705 
6706 #define DMA2D_BGCOLR_BLUE_Pos      (0U)
6707 #define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
6708 #define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
6709 #define DMA2D_BGCOLR_GREEN_Pos     (8U)
6710 #define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
6711 #define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
6712 #define DMA2D_BGCOLR_RED_Pos       (16U)
6713 #define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
6714 #define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
6715 
6716 /********************  Bit definition for DMA2D_FGCMAR register  **************/
6717 
6718 #define DMA2D_FGCMAR_MA_Pos        (0U)
6719 #define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6720 #define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
6721 
6722 /********************  Bit definition for DMA2D_BGCMAR register  **************/
6723 
6724 #define DMA2D_BGCMAR_MA_Pos        (0U)
6725 #define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
6726 #define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
6727 
6728 /********************  Bit definition for DMA2D_OPFCCR register  **************/
6729 
6730 #define DMA2D_OPFCCR_CM_Pos        (0U)
6731 #define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
6732 #define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
6733 #define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
6734 #define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
6735 #define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
6736 
6737 /********************  Bit definition for DMA2D_OCOLR register  ***************/
6738 
6739 /*!<Mode_ARGB8888/RGB888 */
6740 
6741 #define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */
6742 #define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */
6743 #define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */
6744 #define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */
6745 
6746 /*!<Mode_RGB565 */
6747 #define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */
6748 #define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */
6749 #define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */
6750 
6751 /*!<Mode_ARGB1555 */
6752 #define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */
6753 #define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */
6754 #define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */
6755 #define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */
6756 
6757 /*!<Mode_ARGB4444 */
6758 #define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */
6759 #define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */
6760 #define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */
6761 #define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */
6762 
6763 /********************  Bit definition for DMA2D_OMAR register  ****************/
6764 
6765 #define DMA2D_OMAR_MA_Pos          (0U)
6766 #define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
6767 #define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
6768 
6769 /********************  Bit definition for DMA2D_OOR register  *****************/
6770 
6771 #define DMA2D_OOR_LO_Pos           (0U)
6772 #define DMA2D_OOR_LO_Msk           (0x3FFFUL << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
6773 #define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
6774 
6775 /********************  Bit definition for DMA2D_NLR register  *****************/
6776 
6777 #define DMA2D_NLR_NL_Pos           (0U)
6778 #define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
6779 #define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
6780 #define DMA2D_NLR_PL_Pos           (16U)
6781 #define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
6782 #define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
6783 
6784 /********************  Bit definition for DMA2D_LWR register  *****************/
6785 
6786 #define DMA2D_LWR_LW_Pos           (0U)
6787 #define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
6788 #define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
6789 
6790 /********************  Bit definition for DMA2D_AMTCR register  ***************/
6791 
6792 #define DMA2D_AMTCR_EN_Pos         (0U)
6793 #define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
6794 #define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
6795 #define DMA2D_AMTCR_DT_Pos         (8U)
6796 #define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
6797 #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
6798 
6799 /********************  Bit definition for DMA2D_FGCLUT register  **************/
6800 
6801 /********************  Bit definition for DMA2D_BGCLUT register  **************/
6802 
6803 
6804 /******************************************************************************/
6805 /*                                                                            */
6806 /*                    External Interrupt/Event Controller                     */
6807 /*                                                                            */
6808 /******************************************************************************/
6809 /*******************  Bit definition for EXTI_IMR register  *******************/
6810 #define EXTI_IMR_MR0_Pos          (0U)
6811 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
6812 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
6813 #define EXTI_IMR_MR1_Pos          (1U)
6814 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
6815 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
6816 #define EXTI_IMR_MR2_Pos          (2U)
6817 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
6818 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
6819 #define EXTI_IMR_MR3_Pos          (3U)
6820 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
6821 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
6822 #define EXTI_IMR_MR4_Pos          (4U)
6823 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
6824 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
6825 #define EXTI_IMR_MR5_Pos          (5U)
6826 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
6827 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
6828 #define EXTI_IMR_MR6_Pos          (6U)
6829 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
6830 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
6831 #define EXTI_IMR_MR7_Pos          (7U)
6832 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
6833 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
6834 #define EXTI_IMR_MR8_Pos          (8U)
6835 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
6836 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
6837 #define EXTI_IMR_MR9_Pos          (9U)
6838 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
6839 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
6840 #define EXTI_IMR_MR10_Pos         (10U)
6841 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
6842 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
6843 #define EXTI_IMR_MR11_Pos         (11U)
6844 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
6845 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
6846 #define EXTI_IMR_MR12_Pos         (12U)
6847 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
6848 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
6849 #define EXTI_IMR_MR13_Pos         (13U)
6850 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
6851 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
6852 #define EXTI_IMR_MR14_Pos         (14U)
6853 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
6854 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
6855 #define EXTI_IMR_MR15_Pos         (15U)
6856 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
6857 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
6858 #define EXTI_IMR_MR16_Pos         (16U)
6859 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
6860 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
6861 #define EXTI_IMR_MR17_Pos         (17U)
6862 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
6863 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
6864 #define EXTI_IMR_MR18_Pos         (18U)
6865 #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
6866 #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
6867 #define EXTI_IMR_MR19_Pos         (19U)
6868 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
6869 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
6870 #define EXTI_IMR_MR20_Pos         (20U)
6871 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
6872 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
6873 #define EXTI_IMR_MR21_Pos         (21U)
6874 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
6875 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
6876 #define EXTI_IMR_MR22_Pos         (22U)
6877 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
6878 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
6879 
6880 /* Reference Defines */
6881 #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
6882 #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
6883 #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
6884 #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
6885 #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
6886 #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
6887 #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
6888 #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
6889 #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
6890 #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
6891 #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
6892 #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
6893 #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
6894 #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
6895 #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
6896 #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
6897 #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
6898 #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
6899 #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
6900 #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
6901 #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
6902 #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
6903 #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
6904 #define EXTI_IMR_IM_Pos           (0U)
6905 #define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
6906 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
6907 
6908 /*******************  Bit definition for EXTI_EMR register  *******************/
6909 #define EXTI_EMR_MR0_Pos          (0U)
6910 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
6911 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
6912 #define EXTI_EMR_MR1_Pos          (1U)
6913 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
6914 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
6915 #define EXTI_EMR_MR2_Pos          (2U)
6916 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
6917 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
6918 #define EXTI_EMR_MR3_Pos          (3U)
6919 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
6920 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
6921 #define EXTI_EMR_MR4_Pos          (4U)
6922 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
6923 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
6924 #define EXTI_EMR_MR5_Pos          (5U)
6925 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
6926 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
6927 #define EXTI_EMR_MR6_Pos          (6U)
6928 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
6929 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
6930 #define EXTI_EMR_MR7_Pos          (7U)
6931 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
6932 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
6933 #define EXTI_EMR_MR8_Pos          (8U)
6934 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
6935 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
6936 #define EXTI_EMR_MR9_Pos          (9U)
6937 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
6938 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
6939 #define EXTI_EMR_MR10_Pos         (10U)
6940 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
6941 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
6942 #define EXTI_EMR_MR11_Pos         (11U)
6943 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
6944 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
6945 #define EXTI_EMR_MR12_Pos         (12U)
6946 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
6947 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
6948 #define EXTI_EMR_MR13_Pos         (13U)
6949 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
6950 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
6951 #define EXTI_EMR_MR14_Pos         (14U)
6952 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
6953 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
6954 #define EXTI_EMR_MR15_Pos         (15U)
6955 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
6956 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
6957 #define EXTI_EMR_MR16_Pos         (16U)
6958 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
6959 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
6960 #define EXTI_EMR_MR17_Pos         (17U)
6961 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
6962 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
6963 #define EXTI_EMR_MR18_Pos         (18U)
6964 #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
6965 #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
6966 #define EXTI_EMR_MR19_Pos         (19U)
6967 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
6968 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
6969 #define EXTI_EMR_MR20_Pos         (20U)
6970 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
6971 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
6972 #define EXTI_EMR_MR21_Pos         (21U)
6973 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
6974 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
6975 #define EXTI_EMR_MR22_Pos         (22U)
6976 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
6977 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
6978 
6979 /* Reference Defines */
6980 #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
6981 #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
6982 #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
6983 #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
6984 #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
6985 #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
6986 #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
6987 #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
6988 #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
6989 #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
6990 #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
6991 #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
6992 #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
6993 #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
6994 #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
6995 #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
6996 #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
6997 #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
6998 #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
6999 #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
7000 #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
7001 #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
7002 #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
7003 
7004 /******************  Bit definition for EXTI_RTSR register  *******************/
7005 #define EXTI_RTSR_TR0_Pos         (0U)
7006 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
7007 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
7008 #define EXTI_RTSR_TR1_Pos         (1U)
7009 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
7010 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
7011 #define EXTI_RTSR_TR2_Pos         (2U)
7012 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
7013 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
7014 #define EXTI_RTSR_TR3_Pos         (3U)
7015 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
7016 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
7017 #define EXTI_RTSR_TR4_Pos         (4U)
7018 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
7019 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
7020 #define EXTI_RTSR_TR5_Pos         (5U)
7021 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
7022 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
7023 #define EXTI_RTSR_TR6_Pos         (6U)
7024 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
7025 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
7026 #define EXTI_RTSR_TR7_Pos         (7U)
7027 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
7028 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
7029 #define EXTI_RTSR_TR8_Pos         (8U)
7030 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
7031 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
7032 #define EXTI_RTSR_TR9_Pos         (9U)
7033 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
7034 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
7035 #define EXTI_RTSR_TR10_Pos        (10U)
7036 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
7037 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
7038 #define EXTI_RTSR_TR11_Pos        (11U)
7039 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
7040 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
7041 #define EXTI_RTSR_TR12_Pos        (12U)
7042 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
7043 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
7044 #define EXTI_RTSR_TR13_Pos        (13U)
7045 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
7046 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
7047 #define EXTI_RTSR_TR14_Pos        (14U)
7048 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
7049 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
7050 #define EXTI_RTSR_TR15_Pos        (15U)
7051 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
7052 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
7053 #define EXTI_RTSR_TR16_Pos        (16U)
7054 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
7055 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
7056 #define EXTI_RTSR_TR17_Pos        (17U)
7057 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
7058 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
7059 #define EXTI_RTSR_TR18_Pos        (18U)
7060 #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
7061 #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
7062 #define EXTI_RTSR_TR19_Pos        (19U)
7063 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
7064 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
7065 #define EXTI_RTSR_TR20_Pos        (20U)
7066 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
7067 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
7068 #define EXTI_RTSR_TR21_Pos        (21U)
7069 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
7070 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
7071 #define EXTI_RTSR_TR22_Pos        (22U)
7072 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
7073 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
7074 
7075 /******************  Bit definition for EXTI_FTSR register  *******************/
7076 #define EXTI_FTSR_TR0_Pos         (0U)
7077 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
7078 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
7079 #define EXTI_FTSR_TR1_Pos         (1U)
7080 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
7081 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
7082 #define EXTI_FTSR_TR2_Pos         (2U)
7083 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
7084 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
7085 #define EXTI_FTSR_TR3_Pos         (3U)
7086 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
7087 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
7088 #define EXTI_FTSR_TR4_Pos         (4U)
7089 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
7090 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
7091 #define EXTI_FTSR_TR5_Pos         (5U)
7092 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
7093 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
7094 #define EXTI_FTSR_TR6_Pos         (6U)
7095 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
7096 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
7097 #define EXTI_FTSR_TR7_Pos         (7U)
7098 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
7099 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
7100 #define EXTI_FTSR_TR8_Pos         (8U)
7101 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
7102 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
7103 #define EXTI_FTSR_TR9_Pos         (9U)
7104 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
7105 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
7106 #define EXTI_FTSR_TR10_Pos        (10U)
7107 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
7108 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
7109 #define EXTI_FTSR_TR11_Pos        (11U)
7110 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
7111 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
7112 #define EXTI_FTSR_TR12_Pos        (12U)
7113 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
7114 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
7115 #define EXTI_FTSR_TR13_Pos        (13U)
7116 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
7117 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
7118 #define EXTI_FTSR_TR14_Pos        (14U)
7119 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
7120 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
7121 #define EXTI_FTSR_TR15_Pos        (15U)
7122 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
7123 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
7124 #define EXTI_FTSR_TR16_Pos        (16U)
7125 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
7126 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
7127 #define EXTI_FTSR_TR17_Pos        (17U)
7128 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
7129 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
7130 #define EXTI_FTSR_TR18_Pos        (18U)
7131 #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
7132 #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
7133 #define EXTI_FTSR_TR19_Pos        (19U)
7134 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
7135 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
7136 #define EXTI_FTSR_TR20_Pos        (20U)
7137 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
7138 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
7139 #define EXTI_FTSR_TR21_Pos        (21U)
7140 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
7141 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
7142 #define EXTI_FTSR_TR22_Pos        (22U)
7143 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
7144 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
7145 
7146 /******************  Bit definition for EXTI_SWIER register  ******************/
7147 #define EXTI_SWIER_SWIER0_Pos     (0U)
7148 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
7149 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
7150 #define EXTI_SWIER_SWIER1_Pos     (1U)
7151 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
7152 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
7153 #define EXTI_SWIER_SWIER2_Pos     (2U)
7154 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
7155 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
7156 #define EXTI_SWIER_SWIER3_Pos     (3U)
7157 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
7158 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
7159 #define EXTI_SWIER_SWIER4_Pos     (4U)
7160 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
7161 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
7162 #define EXTI_SWIER_SWIER5_Pos     (5U)
7163 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
7164 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
7165 #define EXTI_SWIER_SWIER6_Pos     (6U)
7166 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
7167 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
7168 #define EXTI_SWIER_SWIER7_Pos     (7U)
7169 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
7170 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
7171 #define EXTI_SWIER_SWIER8_Pos     (8U)
7172 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
7173 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
7174 #define EXTI_SWIER_SWIER9_Pos     (9U)
7175 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
7176 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
7177 #define EXTI_SWIER_SWIER10_Pos    (10U)
7178 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
7179 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
7180 #define EXTI_SWIER_SWIER11_Pos    (11U)
7181 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
7182 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
7183 #define EXTI_SWIER_SWIER12_Pos    (12U)
7184 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
7185 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
7186 #define EXTI_SWIER_SWIER13_Pos    (13U)
7187 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
7188 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
7189 #define EXTI_SWIER_SWIER14_Pos    (14U)
7190 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
7191 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
7192 #define EXTI_SWIER_SWIER15_Pos    (15U)
7193 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
7194 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
7195 #define EXTI_SWIER_SWIER16_Pos    (16U)
7196 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
7197 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
7198 #define EXTI_SWIER_SWIER17_Pos    (17U)
7199 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
7200 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
7201 #define EXTI_SWIER_SWIER18_Pos    (18U)
7202 #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
7203 #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
7204 #define EXTI_SWIER_SWIER19_Pos    (19U)
7205 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
7206 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
7207 #define EXTI_SWIER_SWIER20_Pos    (20U)
7208 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
7209 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
7210 #define EXTI_SWIER_SWIER21_Pos    (21U)
7211 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
7212 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
7213 #define EXTI_SWIER_SWIER22_Pos    (22U)
7214 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
7215 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
7216 
7217 /*******************  Bit definition for EXTI_PR register  ********************/
7218 #define EXTI_PR_PR0_Pos           (0U)
7219 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
7220 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
7221 #define EXTI_PR_PR1_Pos           (1U)
7222 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
7223 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
7224 #define EXTI_PR_PR2_Pos           (2U)
7225 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
7226 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
7227 #define EXTI_PR_PR3_Pos           (3U)
7228 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
7229 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
7230 #define EXTI_PR_PR4_Pos           (4U)
7231 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
7232 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
7233 #define EXTI_PR_PR5_Pos           (5U)
7234 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
7235 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
7236 #define EXTI_PR_PR6_Pos           (6U)
7237 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
7238 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
7239 #define EXTI_PR_PR7_Pos           (7U)
7240 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
7241 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
7242 #define EXTI_PR_PR8_Pos           (8U)
7243 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
7244 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
7245 #define EXTI_PR_PR9_Pos           (9U)
7246 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
7247 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
7248 #define EXTI_PR_PR10_Pos          (10U)
7249 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
7250 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
7251 #define EXTI_PR_PR11_Pos          (11U)
7252 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
7253 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
7254 #define EXTI_PR_PR12_Pos          (12U)
7255 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
7256 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
7257 #define EXTI_PR_PR13_Pos          (13U)
7258 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
7259 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
7260 #define EXTI_PR_PR14_Pos          (14U)
7261 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
7262 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
7263 #define EXTI_PR_PR15_Pos          (15U)
7264 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
7265 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
7266 #define EXTI_PR_PR16_Pos          (16U)
7267 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
7268 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
7269 #define EXTI_PR_PR17_Pos          (17U)
7270 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
7271 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
7272 #define EXTI_PR_PR18_Pos          (18U)
7273 #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
7274 #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
7275 #define EXTI_PR_PR19_Pos          (19U)
7276 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
7277 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
7278 #define EXTI_PR_PR20_Pos          (20U)
7279 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
7280 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
7281 #define EXTI_PR_PR21_Pos          (21U)
7282 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
7283 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
7284 #define EXTI_PR_PR22_Pos          (22U)
7285 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
7286 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
7287 
7288 /******************************************************************************/
7289 /*                                                                            */
7290 /*                                    FLASH                                   */
7291 /*                                                                            */
7292 /******************************************************************************/
7293 /*******************  Bits definition for FLASH_ACR register  *****************/
7294 #define FLASH_ACR_LATENCY_Pos          (0U)
7295 #define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
7296 #define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
7297 #define FLASH_ACR_LATENCY_0WS          0x00000000U
7298 #define FLASH_ACR_LATENCY_1WS          0x00000001U
7299 #define FLASH_ACR_LATENCY_2WS          0x00000002U
7300 #define FLASH_ACR_LATENCY_3WS          0x00000003U
7301 #define FLASH_ACR_LATENCY_4WS          0x00000004U
7302 #define FLASH_ACR_LATENCY_5WS          0x00000005U
7303 #define FLASH_ACR_LATENCY_6WS          0x00000006U
7304 #define FLASH_ACR_LATENCY_7WS          0x00000007U
7305 
7306 #define FLASH_ACR_LATENCY_8WS          0x00000008U
7307 #define FLASH_ACR_LATENCY_9WS          0x00000009U
7308 #define FLASH_ACR_LATENCY_10WS         0x0000000AU
7309 #define FLASH_ACR_LATENCY_11WS         0x0000000BU
7310 #define FLASH_ACR_LATENCY_12WS         0x0000000CU
7311 #define FLASH_ACR_LATENCY_13WS         0x0000000DU
7312 #define FLASH_ACR_LATENCY_14WS         0x0000000EU
7313 #define FLASH_ACR_LATENCY_15WS         0x0000000FU
7314 #define FLASH_ACR_PRFTEN_Pos           (8U)
7315 #define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
7316 #define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk
7317 #define FLASH_ACR_ICEN_Pos             (9U)
7318 #define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
7319 #define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk
7320 #define FLASH_ACR_DCEN_Pos             (10U)
7321 #define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
7322 #define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk
7323 #define FLASH_ACR_ICRST_Pos            (11U)
7324 #define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
7325 #define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk
7326 #define FLASH_ACR_DCRST_Pos            (12U)
7327 #define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
7328 #define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk
7329 #define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)
7330 #define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
7331 #define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk
7332 #define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)
7333 #define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
7334 #define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk
7335 
7336 /*******************  Bits definition for FLASH_SR register  ******************/
7337 #define FLASH_SR_EOP_Pos               (0U)
7338 #define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
7339 #define FLASH_SR_EOP                   FLASH_SR_EOP_Msk
7340 #define FLASH_SR_SOP_Pos               (1U)
7341 #define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
7342 #define FLASH_SR_SOP                   FLASH_SR_SOP_Msk
7343 #define FLASH_SR_WRPERR_Pos            (4U)
7344 #define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
7345 #define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk
7346 #define FLASH_SR_PGAERR_Pos            (5U)
7347 #define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
7348 #define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk
7349 #define FLASH_SR_PGPERR_Pos            (6U)
7350 #define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
7351 #define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk
7352 #define FLASH_SR_PGSERR_Pos            (7U)
7353 #define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
7354 #define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk
7355 #define FLASH_SR_RDERR_Pos            (8U)
7356 #define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */
7357 #define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk
7358 #define FLASH_SR_BSY_Pos               (16U)
7359 #define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
7360 #define FLASH_SR_BSY                   FLASH_SR_BSY_Msk
7361 
7362 /*******************  Bits definition for FLASH_CR register  ******************/
7363 #define FLASH_CR_PG_Pos                (0U)
7364 #define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
7365 #define FLASH_CR_PG                    FLASH_CR_PG_Msk
7366 #define FLASH_CR_SER_Pos               (1U)
7367 #define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
7368 #define FLASH_CR_SER                   FLASH_CR_SER_Msk
7369 #define FLASH_CR_MER_Pos               (2U)
7370 #define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
7371 #define FLASH_CR_MER                   FLASH_CR_MER_Msk
7372 #define FLASH_CR_MER1                        FLASH_CR_MER
7373 #define FLASH_CR_SNB_Pos               (3U)
7374 #define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
7375 #define FLASH_CR_SNB                   FLASH_CR_SNB_Msk
7376 #define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
7377 #define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
7378 #define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
7379 #define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
7380 #define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
7381 #define FLASH_CR_PSIZE_Pos             (8U)
7382 #define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
7383 #define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk
7384 #define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
7385 #define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
7386 #define FLASH_CR_MER2_Pos              (15U)
7387 #define FLASH_CR_MER2_Msk              (0x1UL << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */
7388 #define FLASH_CR_MER2                  FLASH_CR_MER2_Msk
7389 #define FLASH_CR_STRT_Pos              (16U)
7390 #define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
7391 #define FLASH_CR_STRT                  FLASH_CR_STRT_Msk
7392 #define FLASH_CR_EOPIE_Pos             (24U)
7393 #define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
7394 #define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk
7395 #define FLASH_CR_LOCK_Pos              (31U)
7396 #define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
7397 #define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk
7398 
7399 /*******************  Bits definition for FLASH_OPTCR register  ***************/
7400 #define FLASH_OPTCR_OPTLOCK_Pos        (0U)
7401 #define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
7402 #define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk
7403 #define FLASH_OPTCR_OPTSTRT_Pos        (1U)
7404 #define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
7405 #define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk
7406 
7407 #define FLASH_OPTCR_BOR_LEV_0          0x00000004U
7408 #define FLASH_OPTCR_BOR_LEV_1          0x00000008U
7409 #define FLASH_OPTCR_BOR_LEV_Pos        (2U)
7410 #define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
7411 #define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk
7412 #define FLASH_OPTCR_BFB2_Pos           (4U)
7413 #define FLASH_OPTCR_BFB2_Msk           (0x1UL << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */
7414 #define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk
7415 #define FLASH_OPTCR_WDG_SW_Pos         (5U)
7416 #define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
7417 #define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk
7418 #define FLASH_OPTCR_nRST_STOP_Pos      (6U)
7419 #define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
7420 #define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk
7421 #define FLASH_OPTCR_nRST_STDBY_Pos     (7U)
7422 #define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
7423 #define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk
7424 #define FLASH_OPTCR_RDP_Pos            (8U)
7425 #define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
7426 #define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk
7427 #define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
7428 #define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
7429 #define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
7430 #define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
7431 #define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
7432 #define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
7433 #define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
7434 #define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
7435 #define FLASH_OPTCR_nWRP_Pos           (16U)
7436 #define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
7437 #define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk
7438 #define FLASH_OPTCR_nWRP_0             0x00010000U
7439 #define FLASH_OPTCR_nWRP_1             0x00020000U
7440 #define FLASH_OPTCR_nWRP_2             0x00040000U
7441 #define FLASH_OPTCR_nWRP_3             0x00080000U
7442 #define FLASH_OPTCR_nWRP_4             0x00100000U
7443 #define FLASH_OPTCR_nWRP_5             0x00200000U
7444 #define FLASH_OPTCR_nWRP_6             0x00400000U
7445 #define FLASH_OPTCR_nWRP_7             0x00800000U
7446 #define FLASH_OPTCR_nWRP_8             0x01000000U
7447 #define FLASH_OPTCR_nWRP_9             0x02000000U
7448 #define FLASH_OPTCR_nWRP_10            0x04000000U
7449 #define FLASH_OPTCR_nWRP_11            0x08000000U
7450 #define FLASH_OPTCR_DB1M_Pos           (30U)
7451 #define FLASH_OPTCR_DB1M_Msk           (0x1UL << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */
7452 #define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk
7453 #define FLASH_OPTCR_SPRMOD_Pos         (31U)
7454 #define FLASH_OPTCR_SPRMOD_Msk         (0x1UL << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */
7455 #define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk
7456 
7457 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
7458 #define FLASH_OPTCR1_nWRP_Pos          (16U)
7459 #define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
7460 #define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk
7461 #define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
7462 #define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
7463 #define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
7464 #define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
7465 #define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
7466 #define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
7467 #define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
7468 #define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
7469 #define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
7470 #define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
7471 #define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
7472 #define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
7473 
7474 /******************************************************************************/
7475 /*                                                                            */
7476 /*                          Flexible Memory Controller                        */
7477 /*                                                                            */
7478 /******************************************************************************/
7479 /******************  Bit definition for FMC_BCR1 register  *******************/
7480 #define FMC_BCR1_MBKEN_Pos          (0U)
7481 #define FMC_BCR1_MBKEN_Msk          (0x1UL << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */
7482 #define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7483 #define FMC_BCR1_MUXEN_Pos          (1U)
7484 #define FMC_BCR1_MUXEN_Msk          (0x1UL << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */
7485 #define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7486 
7487 #define FMC_BCR1_MTYP_Pos           (2U)
7488 #define FMC_BCR1_MTYP_Msk           (0x3UL << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */
7489 #define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7490 #define FMC_BCR1_MTYP_0             (0x1UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */
7491 #define FMC_BCR1_MTYP_1             (0x2UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */
7492 
7493 #define FMC_BCR1_MWID_Pos           (4U)
7494 #define FMC_BCR1_MWID_Msk           (0x3UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */
7495 #define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7496 #define FMC_BCR1_MWID_0             (0x1UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */
7497 #define FMC_BCR1_MWID_1             (0x2UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */
7498 
7499 #define FMC_BCR1_FACCEN_Pos         (6U)
7500 #define FMC_BCR1_FACCEN_Msk         (0x1UL << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */
7501 #define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */
7502 #define FMC_BCR1_BURSTEN_Pos        (8U)
7503 #define FMC_BCR1_BURSTEN_Msk        (0x1UL << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */
7504 #define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */
7505 #define FMC_BCR1_WAITPOL_Pos        (9U)
7506 #define FMC_BCR1_WAITPOL_Msk        (0x1UL << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */
7507 #define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7508 #define FMC_BCR1_WRAPMOD_Pos        (10U)
7509 #define FMC_BCR1_WRAPMOD_Msk        (0x1UL << FMC_BCR1_WRAPMOD_Pos)             /*!< 0x00000400 */
7510 #define FMC_BCR1_WRAPMOD            FMC_BCR1_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7511 #define FMC_BCR1_WAITCFG_Pos        (11U)
7512 #define FMC_BCR1_WAITCFG_Msk        (0x1UL << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */
7513 #define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */
7514 #define FMC_BCR1_WREN_Pos           (12U)
7515 #define FMC_BCR1_WREN_Msk           (0x1UL << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */
7516 #define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */
7517 #define FMC_BCR1_WAITEN_Pos         (13U)
7518 #define FMC_BCR1_WAITEN_Msk         (0x1UL << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */
7519 #define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */
7520 #define FMC_BCR1_EXTMOD_Pos         (14U)
7521 #define FMC_BCR1_EXTMOD_Msk         (0x1UL << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */
7522 #define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */
7523 #define FMC_BCR1_ASYNCWAIT_Pos      (15U)
7524 #define FMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7525 #define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7526 #define FMC_BCR1_CPSIZE_Pos         (16U)
7527 #define FMC_BCR1_CPSIZE_Msk         (0x7UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */
7528 #define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */
7529 #define FMC_BCR1_CPSIZE_0           (0x1UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */
7530 #define FMC_BCR1_CPSIZE_1           (0x2UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */
7531 #define FMC_BCR1_CPSIZE_2           (0x4UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */
7532 #define FMC_BCR1_CBURSTRW_Pos       (19U)
7533 #define FMC_BCR1_CBURSTRW_Msk       (0x1UL << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */
7534 #define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */
7535 #define FMC_BCR1_CCLKEN_Pos         (20U)
7536 #define FMC_BCR1_CCLKEN_Msk         (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
7537 #define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */
7538 
7539 /******************  Bit definition for FMC_BCR2 register  *******************/
7540 #define FMC_BCR2_MBKEN_Pos          (0U)
7541 #define FMC_BCR2_MBKEN_Msk          (0x1UL << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */
7542 #define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7543 #define FMC_BCR2_MUXEN_Pos          (1U)
7544 #define FMC_BCR2_MUXEN_Msk          (0x1UL << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */
7545 #define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7546 
7547 #define FMC_BCR2_MTYP_Pos           (2U)
7548 #define FMC_BCR2_MTYP_Msk           (0x3UL << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */
7549 #define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7550 #define FMC_BCR2_MTYP_0             (0x1UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */
7551 #define FMC_BCR2_MTYP_1             (0x2UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */
7552 
7553 #define FMC_BCR2_MWID_Pos           (4U)
7554 #define FMC_BCR2_MWID_Msk           (0x3UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */
7555 #define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7556 #define FMC_BCR2_MWID_0             (0x1UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */
7557 #define FMC_BCR2_MWID_1             (0x2UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */
7558 
7559 #define FMC_BCR2_FACCEN_Pos         (6U)
7560 #define FMC_BCR2_FACCEN_Msk         (0x1UL << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */
7561 #define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */
7562 #define FMC_BCR2_BURSTEN_Pos        (8U)
7563 #define FMC_BCR2_BURSTEN_Msk        (0x1UL << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */
7564 #define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */
7565 #define FMC_BCR2_WAITPOL_Pos        (9U)
7566 #define FMC_BCR2_WAITPOL_Msk        (0x1UL << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */
7567 #define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7568 #define FMC_BCR2_WRAPMOD_Pos        (10U)
7569 #define FMC_BCR2_WRAPMOD_Msk        (0x1UL << FMC_BCR2_WRAPMOD_Pos)             /*!< 0x00000400 */
7570 #define FMC_BCR2_WRAPMOD            FMC_BCR2_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7571 #define FMC_BCR2_WAITCFG_Pos        (11U)
7572 #define FMC_BCR2_WAITCFG_Msk        (0x1UL << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */
7573 #define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */
7574 #define FMC_BCR2_WREN_Pos           (12U)
7575 #define FMC_BCR2_WREN_Msk           (0x1UL << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */
7576 #define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */
7577 #define FMC_BCR2_WAITEN_Pos         (13U)
7578 #define FMC_BCR2_WAITEN_Msk         (0x1UL << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */
7579 #define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */
7580 #define FMC_BCR2_EXTMOD_Pos         (14U)
7581 #define FMC_BCR2_EXTMOD_Msk         (0x1UL << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */
7582 #define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */
7583 #define FMC_BCR2_ASYNCWAIT_Pos      (15U)
7584 #define FMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7585 #define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7586 #define FMC_BCR2_CPSIZE_Pos         (16U)
7587 #define FMC_BCR2_CPSIZE_Msk         (0x7UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00070000 */
7588 #define FMC_BCR2_CPSIZE             FMC_BCR2_CPSIZE_Msk                        /*!<CRAM page size */
7589 #define FMC_BCR2_CPSIZE_0           (0x1UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00010000 */
7590 #define FMC_BCR2_CPSIZE_1           (0x2UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00020000 */
7591 #define FMC_BCR2_CPSIZE_2           (0x4UL << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00040000 */
7592 #define FMC_BCR2_CBURSTRW_Pos       (19U)
7593 #define FMC_BCR2_CBURSTRW_Msk       (0x1UL << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */
7594 #define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */
7595 
7596 /******************  Bit definition for FMC_BCR3 register  *******************/
7597 #define FMC_BCR3_MBKEN_Pos          (0U)
7598 #define FMC_BCR3_MBKEN_Msk          (0x1UL << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */
7599 #define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7600 #define FMC_BCR3_MUXEN_Pos          (1U)
7601 #define FMC_BCR3_MUXEN_Msk          (0x1UL << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */
7602 #define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7603 
7604 #define FMC_BCR3_MTYP_Pos           (2U)
7605 #define FMC_BCR3_MTYP_Msk           (0x3UL << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */
7606 #define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7607 #define FMC_BCR3_MTYP_0             (0x1UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */
7608 #define FMC_BCR3_MTYP_1             (0x2UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */
7609 
7610 #define FMC_BCR3_MWID_Pos           (4U)
7611 #define FMC_BCR3_MWID_Msk           (0x3UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */
7612 #define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7613 #define FMC_BCR3_MWID_0             (0x1UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */
7614 #define FMC_BCR3_MWID_1             (0x2UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */
7615 
7616 #define FMC_BCR3_FACCEN_Pos         (6U)
7617 #define FMC_BCR3_FACCEN_Msk         (0x1UL << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */
7618 #define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */
7619 #define FMC_BCR3_BURSTEN_Pos        (8U)
7620 #define FMC_BCR3_BURSTEN_Msk        (0x1UL << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */
7621 #define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */
7622 #define FMC_BCR3_WAITPOL_Pos        (9U)
7623 #define FMC_BCR3_WAITPOL_Msk        (0x1UL << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */
7624 #define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7625 #define FMC_BCR3_WRAPMOD_Pos        (10U)
7626 #define FMC_BCR3_WRAPMOD_Msk        (0x1UL << FMC_BCR3_WRAPMOD_Pos)             /*!< 0x00000400 */
7627 #define FMC_BCR3_WRAPMOD            FMC_BCR3_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7628 #define FMC_BCR3_WAITCFG_Pos        (11U)
7629 #define FMC_BCR3_WAITCFG_Msk        (0x1UL << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */
7630 #define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */
7631 #define FMC_BCR3_WREN_Pos           (12U)
7632 #define FMC_BCR3_WREN_Msk           (0x1UL << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */
7633 #define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */
7634 #define FMC_BCR3_WAITEN_Pos         (13U)
7635 #define FMC_BCR3_WAITEN_Msk         (0x1UL << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */
7636 #define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */
7637 #define FMC_BCR3_EXTMOD_Pos         (14U)
7638 #define FMC_BCR3_EXTMOD_Msk         (0x1UL << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */
7639 #define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */
7640 #define FMC_BCR3_ASYNCWAIT_Pos      (15U)
7641 #define FMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7642 #define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7643 #define FMC_BCR3_CPSIZE_Pos         (16U)
7644 #define FMC_BCR3_CPSIZE_Msk         (0x7UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00070000 */
7645 #define FMC_BCR3_CPSIZE             FMC_BCR3_CPSIZE_Msk                        /*!<CRAM page size */
7646 #define FMC_BCR3_CPSIZE_0           (0x1UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00010000 */
7647 #define FMC_BCR3_CPSIZE_1           (0x2UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00020000 */
7648 #define FMC_BCR3_CPSIZE_2           (0x4UL << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00040000 */
7649 #define FMC_BCR3_CBURSTRW_Pos       (19U)
7650 #define FMC_BCR3_CBURSTRW_Msk       (0x1UL << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */
7651 #define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */
7652 
7653 /******************  Bit definition for FMC_BCR4 register  *******************/
7654 #define FMC_BCR4_MBKEN_Pos          (0U)
7655 #define FMC_BCR4_MBKEN_Msk          (0x1UL << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */
7656 #define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */
7657 #define FMC_BCR4_MUXEN_Pos          (1U)
7658 #define FMC_BCR4_MUXEN_Msk          (0x1UL << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */
7659 #define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
7660 
7661 #define FMC_BCR4_MTYP_Pos           (2U)
7662 #define FMC_BCR4_MTYP_Msk           (0x3UL << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */
7663 #define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
7664 #define FMC_BCR4_MTYP_0             (0x1UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */
7665 #define FMC_BCR4_MTYP_1             (0x2UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */
7666 
7667 #define FMC_BCR4_MWID_Pos           (4U)
7668 #define FMC_BCR4_MWID_Msk           (0x3UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */
7669 #define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
7670 #define FMC_BCR4_MWID_0             (0x1UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */
7671 #define FMC_BCR4_MWID_1             (0x2UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */
7672 
7673 #define FMC_BCR4_FACCEN_Pos         (6U)
7674 #define FMC_BCR4_FACCEN_Msk         (0x1UL << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */
7675 #define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */
7676 #define FMC_BCR4_BURSTEN_Pos        (8U)
7677 #define FMC_BCR4_BURSTEN_Msk        (0x1UL << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */
7678 #define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */
7679 #define FMC_BCR4_WAITPOL_Pos        (9U)
7680 #define FMC_BCR4_WAITPOL_Msk        (0x1UL << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */
7681 #define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
7682 #define FMC_BCR4_WRAPMOD_Pos        (10U)
7683 #define FMC_BCR4_WRAPMOD_Msk        (0x1UL << FMC_BCR4_WRAPMOD_Pos)             /*!< 0x00000400 */
7684 #define FMC_BCR4_WRAPMOD            FMC_BCR4_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
7685 #define FMC_BCR4_WAITCFG_Pos        (11U)
7686 #define FMC_BCR4_WAITCFG_Msk        (0x1UL << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */
7687 #define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */
7688 #define FMC_BCR4_WREN_Pos           (12U)
7689 #define FMC_BCR4_WREN_Msk           (0x1UL << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */
7690 #define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */
7691 #define FMC_BCR4_WAITEN_Pos         (13U)
7692 #define FMC_BCR4_WAITEN_Msk         (0x1UL << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */
7693 #define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */
7694 #define FMC_BCR4_EXTMOD_Pos         (14U)
7695 #define FMC_BCR4_EXTMOD_Msk         (0x1UL << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */
7696 #define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */
7697 #define FMC_BCR4_ASYNCWAIT_Pos      (15U)
7698 #define FMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */
7699 #define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
7700 #define FMC_BCR4_CPSIZE_Pos         (16U)
7701 #define FMC_BCR4_CPSIZE_Msk         (0x7UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00070000 */
7702 #define FMC_BCR4_CPSIZE             FMC_BCR4_CPSIZE_Msk                        /*!<CRAM page size */
7703 #define FMC_BCR4_CPSIZE_0           (0x1UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00010000 */
7704 #define FMC_BCR4_CPSIZE_1           (0x2UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00020000 */
7705 #define FMC_BCR4_CPSIZE_2           (0x4UL << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00040000 */
7706 #define FMC_BCR4_CBURSTRW_Pos       (19U)
7707 #define FMC_BCR4_CBURSTRW_Msk       (0x1UL << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */
7708 #define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */
7709 
7710 /******************  Bit definition for FMC_BTR1 register  ******************/
7711 #define FMC_BTR1_ADDSET_Pos         (0U)
7712 #define FMC_BTR1_ADDSET_Msk         (0xFUL << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */
7713 #define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7714 #define FMC_BTR1_ADDSET_0           (0x1UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */
7715 #define FMC_BTR1_ADDSET_1           (0x2UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */
7716 #define FMC_BTR1_ADDSET_2           (0x4UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */
7717 #define FMC_BTR1_ADDSET_3           (0x8UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */
7718 
7719 #define FMC_BTR1_ADDHLD_Pos         (4U)
7720 #define FMC_BTR1_ADDHLD_Msk         (0xFUL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
7721 #define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
7722 #define FMC_BTR1_ADDHLD_0           (0x1UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */
7723 #define FMC_BTR1_ADDHLD_1           (0x2UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */
7724 #define FMC_BTR1_ADDHLD_2           (0x4UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */
7725 #define FMC_BTR1_ADDHLD_3           (0x8UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */
7726 
7727 #define FMC_BTR1_DATAST_Pos         (8U)
7728 #define FMC_BTR1_DATAST_Msk         (0xFFUL << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */
7729 #define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7730 #define FMC_BTR1_DATAST_0           (0x01UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */
7731 #define FMC_BTR1_DATAST_1           (0x02UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */
7732 #define FMC_BTR1_DATAST_2           (0x04UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */
7733 #define FMC_BTR1_DATAST_3           (0x08UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */
7734 #define FMC_BTR1_DATAST_4           (0x10UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */
7735 #define FMC_BTR1_DATAST_5           (0x20UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */
7736 #define FMC_BTR1_DATAST_6           (0x40UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */
7737 #define FMC_BTR1_DATAST_7           (0x80UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */
7738 
7739 #define FMC_BTR1_BUSTURN_Pos        (16U)
7740 #define FMC_BTR1_BUSTURN_Msk        (0xFUL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
7741 #define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7742 #define FMC_BTR1_BUSTURN_0          (0x1UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */
7743 #define FMC_BTR1_BUSTURN_1          (0x2UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */
7744 #define FMC_BTR1_BUSTURN_2          (0x4UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */
7745 #define FMC_BTR1_BUSTURN_3          (0x8UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */
7746 
7747 #define FMC_BTR1_CLKDIV_Pos         (20U)
7748 #define FMC_BTR1_CLKDIV_Msk         (0xFUL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
7749 #define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7750 #define FMC_BTR1_CLKDIV_0           (0x1UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */
7751 #define FMC_BTR1_CLKDIV_1           (0x2UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */
7752 #define FMC_BTR1_CLKDIV_2           (0x4UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */
7753 #define FMC_BTR1_CLKDIV_3           (0x8UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */
7754 
7755 #define FMC_BTR1_DATLAT_Pos         (24U)
7756 #define FMC_BTR1_DATLAT_Msk         (0xFUL << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */
7757 #define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7758 #define FMC_BTR1_DATLAT_0           (0x1UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */
7759 #define FMC_BTR1_DATLAT_1           (0x2UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */
7760 #define FMC_BTR1_DATLAT_2           (0x4UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */
7761 #define FMC_BTR1_DATLAT_3           (0x8UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */
7762 
7763 #define FMC_BTR1_ACCMOD_Pos         (28U)
7764 #define FMC_BTR1_ACCMOD_Msk         (0x3UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */
7765 #define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7766 #define FMC_BTR1_ACCMOD_0           (0x1UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */
7767 #define FMC_BTR1_ACCMOD_1           (0x2UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */
7768 
7769 /******************  Bit definition for FMC_BTR2 register  *******************/
7770 #define FMC_BTR2_ADDSET_Pos         (0U)
7771 #define FMC_BTR2_ADDSET_Msk         (0xFUL << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */
7772 #define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7773 #define FMC_BTR2_ADDSET_0           (0x1UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */
7774 #define FMC_BTR2_ADDSET_1           (0x2UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */
7775 #define FMC_BTR2_ADDSET_2           (0x4UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */
7776 #define FMC_BTR2_ADDSET_3           (0x8UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */
7777 
7778 #define FMC_BTR2_ADDHLD_Pos         (4U)
7779 #define FMC_BTR2_ADDHLD_Msk         (0xFUL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
7780 #define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7781 #define FMC_BTR2_ADDHLD_0           (0x1UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */
7782 #define FMC_BTR2_ADDHLD_1           (0x2UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */
7783 #define FMC_BTR2_ADDHLD_2           (0x4UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */
7784 #define FMC_BTR2_ADDHLD_3           (0x8UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */
7785 
7786 #define FMC_BTR2_DATAST_Pos         (8U)
7787 #define FMC_BTR2_DATAST_Msk         (0xFFUL << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */
7788 #define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7789 #define FMC_BTR2_DATAST_0           (0x01UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */
7790 #define FMC_BTR2_DATAST_1           (0x02UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */
7791 #define FMC_BTR2_DATAST_2           (0x04UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */
7792 #define FMC_BTR2_DATAST_3           (0x08UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */
7793 #define FMC_BTR2_DATAST_4           (0x10UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */
7794 #define FMC_BTR2_DATAST_5           (0x20UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */
7795 #define FMC_BTR2_DATAST_6           (0x40UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */
7796 #define FMC_BTR2_DATAST_7           (0x80UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */
7797 
7798 #define FMC_BTR2_BUSTURN_Pos        (16U)
7799 #define FMC_BTR2_BUSTURN_Msk        (0xFUL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
7800 #define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7801 #define FMC_BTR2_BUSTURN_0          (0x1UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */
7802 #define FMC_BTR2_BUSTURN_1          (0x2UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */
7803 #define FMC_BTR2_BUSTURN_2          (0x4UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */
7804 #define FMC_BTR2_BUSTURN_3          (0x8UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */
7805 
7806 #define FMC_BTR2_CLKDIV_Pos         (20U)
7807 #define FMC_BTR2_CLKDIV_Msk         (0xFUL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
7808 #define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7809 #define FMC_BTR2_CLKDIV_0           (0x1UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */
7810 #define FMC_BTR2_CLKDIV_1           (0x2UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */
7811 #define FMC_BTR2_CLKDIV_2           (0x4UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */
7812 #define FMC_BTR2_CLKDIV_3           (0x8UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */
7813 
7814 #define FMC_BTR2_DATLAT_Pos         (24U)
7815 #define FMC_BTR2_DATLAT_Msk         (0xFUL << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */
7816 #define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7817 #define FMC_BTR2_DATLAT_0           (0x1UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */
7818 #define FMC_BTR2_DATLAT_1           (0x2UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */
7819 #define FMC_BTR2_DATLAT_2           (0x4UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */
7820 #define FMC_BTR2_DATLAT_3           (0x8UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */
7821 
7822 #define FMC_BTR2_ACCMOD_Pos         (28U)
7823 #define FMC_BTR2_ACCMOD_Msk         (0x3UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */
7824 #define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7825 #define FMC_BTR2_ACCMOD_0           (0x1UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */
7826 #define FMC_BTR2_ACCMOD_1           (0x2UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */
7827 
7828 /*******************  Bit definition for FMC_BTR3 register  *******************/
7829 #define FMC_BTR3_ADDSET_Pos         (0U)
7830 #define FMC_BTR3_ADDSET_Msk         (0xFUL << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */
7831 #define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7832 #define FMC_BTR3_ADDSET_0           (0x1UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */
7833 #define FMC_BTR3_ADDSET_1           (0x2UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */
7834 #define FMC_BTR3_ADDSET_2           (0x4UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */
7835 #define FMC_BTR3_ADDSET_3           (0x8UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */
7836 
7837 #define FMC_BTR3_ADDHLD_Pos         (4U)
7838 #define FMC_BTR3_ADDHLD_Msk         (0xFUL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
7839 #define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7840 #define FMC_BTR3_ADDHLD_0           (0x1UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */
7841 #define FMC_BTR3_ADDHLD_1           (0x2UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */
7842 #define FMC_BTR3_ADDHLD_2           (0x4UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */
7843 #define FMC_BTR3_ADDHLD_3           (0x8UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */
7844 
7845 #define FMC_BTR3_DATAST_Pos         (8U)
7846 #define FMC_BTR3_DATAST_Msk         (0xFFUL << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */
7847 #define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7848 #define FMC_BTR3_DATAST_0           (0x01UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */
7849 #define FMC_BTR3_DATAST_1           (0x02UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */
7850 #define FMC_BTR3_DATAST_2           (0x04UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */
7851 #define FMC_BTR3_DATAST_3           (0x08UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */
7852 #define FMC_BTR3_DATAST_4           (0x10UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */
7853 #define FMC_BTR3_DATAST_5           (0x20UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */
7854 #define FMC_BTR3_DATAST_6           (0x40UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */
7855 #define FMC_BTR3_DATAST_7           (0x80UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */
7856 
7857 #define FMC_BTR3_BUSTURN_Pos        (16U)
7858 #define FMC_BTR3_BUSTURN_Msk        (0xFUL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
7859 #define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7860 #define FMC_BTR3_BUSTURN_0          (0x1UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */
7861 #define FMC_BTR3_BUSTURN_1          (0x2UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */
7862 #define FMC_BTR3_BUSTURN_2          (0x4UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */
7863 #define FMC_BTR3_BUSTURN_3          (0x8UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */
7864 
7865 #define FMC_BTR3_CLKDIV_Pos         (20U)
7866 #define FMC_BTR3_CLKDIV_Msk         (0xFUL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
7867 #define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7868 #define FMC_BTR3_CLKDIV_0           (0x1UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */
7869 #define FMC_BTR3_CLKDIV_1           (0x2UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */
7870 #define FMC_BTR3_CLKDIV_2           (0x4UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */
7871 #define FMC_BTR3_CLKDIV_3           (0x8UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */
7872 
7873 #define FMC_BTR3_DATLAT_Pos         (24U)
7874 #define FMC_BTR3_DATLAT_Msk         (0xFUL << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */
7875 #define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7876 #define FMC_BTR3_DATLAT_0           (0x1UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */
7877 #define FMC_BTR3_DATLAT_1           (0x2UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */
7878 #define FMC_BTR3_DATLAT_2           (0x4UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */
7879 #define FMC_BTR3_DATLAT_3           (0x8UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */
7880 
7881 #define FMC_BTR3_ACCMOD_Pos         (28U)
7882 #define FMC_BTR3_ACCMOD_Msk         (0x3UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */
7883 #define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7884 #define FMC_BTR3_ACCMOD_0           (0x1UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */
7885 #define FMC_BTR3_ACCMOD_1           (0x2UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */
7886 
7887 /******************  Bit definition for FMC_BTR4 register  *******************/
7888 #define FMC_BTR4_ADDSET_Pos         (0U)
7889 #define FMC_BTR4_ADDSET_Msk         (0xFUL << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */
7890 #define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
7891 #define FMC_BTR4_ADDSET_0           (0x1UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */
7892 #define FMC_BTR4_ADDSET_1           (0x2UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */
7893 #define FMC_BTR4_ADDSET_2           (0x4UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */
7894 #define FMC_BTR4_ADDSET_3           (0x8UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */
7895 
7896 #define FMC_BTR4_ADDHLD_Pos         (4U)
7897 #define FMC_BTR4_ADDHLD_Msk         (0xFUL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
7898 #define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7899 #define FMC_BTR4_ADDHLD_0           (0x1UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */
7900 #define FMC_BTR4_ADDHLD_1           (0x2UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */
7901 #define FMC_BTR4_ADDHLD_2           (0x4UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */
7902 #define FMC_BTR4_ADDHLD_3           (0x8UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */
7903 
7904 #define FMC_BTR4_DATAST_Pos         (8U)
7905 #define FMC_BTR4_DATAST_Msk         (0xFFUL << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */
7906 #define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
7907 #define FMC_BTR4_DATAST_0           (0x01UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */
7908 #define FMC_BTR4_DATAST_1           (0x02UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */
7909 #define FMC_BTR4_DATAST_2           (0x04UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */
7910 #define FMC_BTR4_DATAST_3           (0x08UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */
7911 #define FMC_BTR4_DATAST_4           (0x10UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */
7912 #define FMC_BTR4_DATAST_5           (0x20UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */
7913 #define FMC_BTR4_DATAST_6           (0x40UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */
7914 #define FMC_BTR4_DATAST_7           (0x80UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */
7915 
7916 #define FMC_BTR4_BUSTURN_Pos        (16U)
7917 #define FMC_BTR4_BUSTURN_Msk        (0xFUL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
7918 #define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7919 #define FMC_BTR4_BUSTURN_0          (0x1UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */
7920 #define FMC_BTR4_BUSTURN_1          (0x2UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */
7921 #define FMC_BTR4_BUSTURN_2          (0x4UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */
7922 #define FMC_BTR4_BUSTURN_3          (0x8UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */
7923 
7924 #define FMC_BTR4_CLKDIV_Pos         (20U)
7925 #define FMC_BTR4_CLKDIV_Msk         (0xFUL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
7926 #define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7927 #define FMC_BTR4_CLKDIV_0           (0x1UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */
7928 #define FMC_BTR4_CLKDIV_1           (0x2UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */
7929 #define FMC_BTR4_CLKDIV_2           (0x4UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */
7930 #define FMC_BTR4_CLKDIV_3           (0x8UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */
7931 
7932 #define FMC_BTR4_DATLAT_Pos         (24U)
7933 #define FMC_BTR4_DATLAT_Msk         (0xFUL << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */
7934 #define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
7935 #define FMC_BTR4_DATLAT_0           (0x1UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */
7936 #define FMC_BTR4_DATLAT_1           (0x2UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */
7937 #define FMC_BTR4_DATLAT_2           (0x4UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */
7938 #define FMC_BTR4_DATLAT_3           (0x8UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */
7939 
7940 #define FMC_BTR4_ACCMOD_Pos         (28U)
7941 #define FMC_BTR4_ACCMOD_Msk         (0x3UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */
7942 #define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
7943 #define FMC_BTR4_ACCMOD_0           (0x1UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */
7944 #define FMC_BTR4_ACCMOD_1           (0x2UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */
7945 
7946 /******************  Bit definition for FMC_BWTR1 register  ******************/
7947 #define FMC_BWTR1_ADDSET_Pos        (0U)
7948 #define FMC_BWTR1_ADDSET_Msk        (0xFUL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */
7949 #define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7950 #define FMC_BWTR1_ADDSET_0          (0x1UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */
7951 #define FMC_BWTR1_ADDSET_1          (0x2UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */
7952 #define FMC_BWTR1_ADDSET_2          (0x4UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */
7953 #define FMC_BWTR1_ADDSET_3          (0x8UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */
7954 
7955 #define FMC_BWTR1_ADDHLD_Pos        (4U)
7956 #define FMC_BWTR1_ADDHLD_Msk        (0xFUL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */
7957 #define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7958 #define FMC_BWTR1_ADDHLD_0          (0x1UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */
7959 #define FMC_BWTR1_ADDHLD_1          (0x2UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */
7960 #define FMC_BWTR1_ADDHLD_2          (0x4UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */
7961 #define FMC_BWTR1_ADDHLD_3          (0x8UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */
7962 
7963 #define FMC_BWTR1_DATAST_Pos        (8U)
7964 #define FMC_BWTR1_DATAST_Msk        (0xFFUL << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */
7965 #define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
7966 #define FMC_BWTR1_DATAST_0          (0x01UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */
7967 #define FMC_BWTR1_DATAST_1          (0x02UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */
7968 #define FMC_BWTR1_DATAST_2          (0x04UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */
7969 #define FMC_BWTR1_DATAST_3          (0x08UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */
7970 #define FMC_BWTR1_DATAST_4          (0x10UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */
7971 #define FMC_BWTR1_DATAST_5          (0x20UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */
7972 #define FMC_BWTR1_DATAST_6          (0x40UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */
7973 #define FMC_BWTR1_DATAST_7          (0x80UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */
7974 
7975 #define FMC_BWTR1_BUSTURN_Pos       (16U)
7976 #define FMC_BWTR1_BUSTURN_Msk       (0xFUL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */
7977 #define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7978 #define FMC_BWTR1_BUSTURN_0         (0x1UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */
7979 #define FMC_BWTR1_BUSTURN_1         (0x2UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */
7980 #define FMC_BWTR1_BUSTURN_2         (0x4UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */
7981 #define FMC_BWTR1_BUSTURN_3         (0x8UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */
7982 
7983 #define FMC_BWTR1_ACCMOD_Pos        (28U)
7984 #define FMC_BWTR1_ACCMOD_Msk        (0x3UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */
7985 #define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
7986 #define FMC_BWTR1_ACCMOD_0          (0x1UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */
7987 #define FMC_BWTR1_ACCMOD_1          (0x2UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */
7988 
7989 /******************  Bit definition for FMC_BWTR2 register  ******************/
7990 #define FMC_BWTR2_ADDSET_Pos        (0U)
7991 #define FMC_BWTR2_ADDSET_Msk        (0xFUL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */
7992 #define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
7993 #define FMC_BWTR2_ADDSET_0          (0x1UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */
7994 #define FMC_BWTR2_ADDSET_1          (0x2UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */
7995 #define FMC_BWTR2_ADDSET_2          (0x4UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */
7996 #define FMC_BWTR2_ADDSET_3          (0x8UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */
7997 
7998 #define FMC_BWTR2_ADDHLD_Pos        (4U)
7999 #define FMC_BWTR2_ADDHLD_Msk        (0xFUL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */
8000 #define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8001 #define FMC_BWTR2_ADDHLD_0          (0x1UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */
8002 #define FMC_BWTR2_ADDHLD_1          (0x2UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */
8003 #define FMC_BWTR2_ADDHLD_2          (0x4UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */
8004 #define FMC_BWTR2_ADDHLD_3          (0x8UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */
8005 
8006 #define FMC_BWTR2_DATAST_Pos        (8U)
8007 #define FMC_BWTR2_DATAST_Msk        (0xFFUL << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */
8008 #define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
8009 #define FMC_BWTR2_DATAST_0          (0x01UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */
8010 #define FMC_BWTR2_DATAST_1          (0x02UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */
8011 #define FMC_BWTR2_DATAST_2          (0x04UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */
8012 #define FMC_BWTR2_DATAST_3          (0x08UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */
8013 #define FMC_BWTR2_DATAST_4          (0x10UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */
8014 #define FMC_BWTR2_DATAST_5          (0x20UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */
8015 #define FMC_BWTR2_DATAST_6          (0x40UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */
8016 #define FMC_BWTR2_DATAST_7          (0x80UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */
8017 
8018 #define FMC_BWTR2_BUSTURN_Pos       (16U)
8019 #define FMC_BWTR2_BUSTURN_Msk       (0xFUL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */
8020 #define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
8021 #define FMC_BWTR2_BUSTURN_0         (0x1UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */
8022 #define FMC_BWTR2_BUSTURN_1         (0x2UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */
8023 #define FMC_BWTR2_BUSTURN_2         (0x4UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */
8024 #define FMC_BWTR2_BUSTURN_3         (0x8UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */
8025 
8026 #define FMC_BWTR2_ACCMOD_Pos        (28U)
8027 #define FMC_BWTR2_ACCMOD_Msk        (0x3UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */
8028 #define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
8029 #define FMC_BWTR2_ACCMOD_0          (0x1UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */
8030 #define FMC_BWTR2_ACCMOD_1          (0x2UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */
8031 
8032 /******************  Bit definition for FMC_BWTR3 register  ******************/
8033 #define FMC_BWTR3_ADDSET_Pos        (0U)
8034 #define FMC_BWTR3_ADDSET_Msk        (0xFUL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */
8035 #define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
8036 #define FMC_BWTR3_ADDSET_0          (0x1UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */
8037 #define FMC_BWTR3_ADDSET_1          (0x2UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */
8038 #define FMC_BWTR3_ADDSET_2          (0x4UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */
8039 #define FMC_BWTR3_ADDSET_3          (0x8UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */
8040 
8041 #define FMC_BWTR3_ADDHLD_Pos        (4U)
8042 #define FMC_BWTR3_ADDHLD_Msk        (0xFUL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */
8043 #define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8044 #define FMC_BWTR3_ADDHLD_0          (0x1UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */
8045 #define FMC_BWTR3_ADDHLD_1          (0x2UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */
8046 #define FMC_BWTR3_ADDHLD_2          (0x4UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */
8047 #define FMC_BWTR3_ADDHLD_3          (0x8UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */
8048 
8049 #define FMC_BWTR3_DATAST_Pos        (8U)
8050 #define FMC_BWTR3_DATAST_Msk        (0xFFUL << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */
8051 #define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
8052 #define FMC_BWTR3_DATAST_0          (0x01UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */
8053 #define FMC_BWTR3_DATAST_1          (0x02UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */
8054 #define FMC_BWTR3_DATAST_2          (0x04UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */
8055 #define FMC_BWTR3_DATAST_3          (0x08UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */
8056 #define FMC_BWTR3_DATAST_4          (0x10UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */
8057 #define FMC_BWTR3_DATAST_5          (0x20UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */
8058 #define FMC_BWTR3_DATAST_6          (0x40UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */
8059 #define FMC_BWTR3_DATAST_7          (0x80UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */
8060 
8061 #define FMC_BWTR3_BUSTURN_Pos       (16U)
8062 #define FMC_BWTR3_BUSTURN_Msk       (0xFUL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */
8063 #define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
8064 #define FMC_BWTR3_BUSTURN_0         (0x1UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */
8065 #define FMC_BWTR3_BUSTURN_1         (0x2UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */
8066 #define FMC_BWTR3_BUSTURN_2         (0x4UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */
8067 #define FMC_BWTR3_BUSTURN_3         (0x8UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */
8068 
8069 #define FMC_BWTR3_ACCMOD_Pos        (28U)
8070 #define FMC_BWTR3_ACCMOD_Msk        (0x3UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */
8071 #define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
8072 #define FMC_BWTR3_ACCMOD_0          (0x1UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */
8073 #define FMC_BWTR3_ACCMOD_1          (0x2UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */
8074 
8075 /******************  Bit definition for FMC_BWTR4 register  ******************/
8076 #define FMC_BWTR4_ADDSET_Pos        (0U)
8077 #define FMC_BWTR4_ADDSET_Msk        (0xFUL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */
8078 #define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
8079 #define FMC_BWTR4_ADDSET_0          (0x1UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */
8080 #define FMC_BWTR4_ADDSET_1          (0x2UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */
8081 #define FMC_BWTR4_ADDSET_2          (0x4UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */
8082 #define FMC_BWTR4_ADDSET_3          (0x8UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */
8083 
8084 #define FMC_BWTR4_ADDHLD_Pos        (4U)
8085 #define FMC_BWTR4_ADDHLD_Msk        (0xFUL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */
8086 #define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8087 #define FMC_BWTR4_ADDHLD_0          (0x1UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */
8088 #define FMC_BWTR4_ADDHLD_1          (0x2UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */
8089 #define FMC_BWTR4_ADDHLD_2          (0x4UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */
8090 #define FMC_BWTR4_ADDHLD_3          (0x8UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */
8091 
8092 #define FMC_BWTR4_DATAST_Pos        (8U)
8093 #define FMC_BWTR4_DATAST_Msk        (0xFFUL << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */
8094 #define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
8095 #define FMC_BWTR4_DATAST_0          (0x01UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */
8096 #define FMC_BWTR4_DATAST_1          (0x02UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */
8097 #define FMC_BWTR4_DATAST_2          (0x04UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */
8098 #define FMC_BWTR4_DATAST_3          (0x08UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */
8099 #define FMC_BWTR4_DATAST_4          (0x10UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */
8100 #define FMC_BWTR4_DATAST_5          (0x20UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */
8101 #define FMC_BWTR4_DATAST_6          (0x40UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */
8102 #define FMC_BWTR4_DATAST_7          (0x80UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */
8103 
8104 #define FMC_BWTR4_BUSTURN_Pos       (16U)
8105 #define FMC_BWTR4_BUSTURN_Msk       (0xFUL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */
8106 #define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
8107 #define FMC_BWTR4_BUSTURN_0         (0x1UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */
8108 #define FMC_BWTR4_BUSTURN_1         (0x2UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */
8109 #define FMC_BWTR4_BUSTURN_2         (0x4UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */
8110 #define FMC_BWTR4_BUSTURN_3         (0x8UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */
8111 
8112 #define FMC_BWTR4_ACCMOD_Pos        (28U)
8113 #define FMC_BWTR4_ACCMOD_Msk        (0x3UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */
8114 #define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
8115 #define FMC_BWTR4_ACCMOD_0          (0x1UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */
8116 #define FMC_BWTR4_ACCMOD_1          (0x2UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */
8117 
8118 /******************  Bit definition for FMC_PCR2 register  *******************/
8119 
8120 #define FMC_PCR2_PWAITEN_Pos        (1U)
8121 #define FMC_PCR2_PWAITEN_Msk        (0x1UL << FMC_PCR2_PWAITEN_Pos)             /*!< 0x00000002 */
8122 #define FMC_PCR2_PWAITEN            FMC_PCR2_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
8123 #define FMC_PCR2_PBKEN_Pos          (2U)
8124 #define FMC_PCR2_PBKEN_Msk          (0x1UL << FMC_PCR2_PBKEN_Pos)               /*!< 0x00000004 */
8125 #define FMC_PCR2_PBKEN              FMC_PCR2_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
8126 #define FMC_PCR2_PTYP_Pos           (3U)
8127 #define FMC_PCR2_PTYP_Msk           (0x1UL << FMC_PCR2_PTYP_Pos)                /*!< 0x00000008 */
8128 #define FMC_PCR2_PTYP               FMC_PCR2_PTYP_Msk                          /*!<Memory type                               */
8129 
8130 #define FMC_PCR2_PWID_Pos           (4U)
8131 #define FMC_PCR2_PWID_Msk           (0x3UL << FMC_PCR2_PWID_Pos)                /*!< 0x00000030 */
8132 #define FMC_PCR2_PWID               FMC_PCR2_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
8133 #define FMC_PCR2_PWID_0             (0x1UL << FMC_PCR2_PWID_Pos)                /*!< 0x00000010 */
8134 #define FMC_PCR2_PWID_1             (0x2UL << FMC_PCR2_PWID_Pos)                /*!< 0x00000020 */
8135 
8136 #define FMC_PCR2_ECCEN_Pos          (6U)
8137 #define FMC_PCR2_ECCEN_Msk          (0x1UL << FMC_PCR2_ECCEN_Pos)               /*!< 0x00000040 */
8138 #define FMC_PCR2_ECCEN              FMC_PCR2_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
8139 
8140 #define FMC_PCR2_TCLR_Pos           (9U)
8141 #define FMC_PCR2_TCLR_Msk           (0xFUL << FMC_PCR2_TCLR_Pos)                /*!< 0x00001E00 */
8142 #define FMC_PCR2_TCLR               FMC_PCR2_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
8143 #define FMC_PCR2_TCLR_0             (0x1UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00000200 */
8144 #define FMC_PCR2_TCLR_1             (0x2UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00000400 */
8145 #define FMC_PCR2_TCLR_2             (0x4UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00000800 */
8146 #define FMC_PCR2_TCLR_3             (0x8UL << FMC_PCR2_TCLR_Pos)                /*!< 0x00001000 */
8147 
8148 #define FMC_PCR2_TAR_Pos            (13U)
8149 #define FMC_PCR2_TAR_Msk            (0xFUL << FMC_PCR2_TAR_Pos)                 /*!< 0x0001E000 */
8150 #define FMC_PCR2_TAR                FMC_PCR2_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
8151 #define FMC_PCR2_TAR_0              (0x1UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00002000 */
8152 #define FMC_PCR2_TAR_1              (0x2UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00004000 */
8153 #define FMC_PCR2_TAR_2              (0x4UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00008000 */
8154 #define FMC_PCR2_TAR_3              (0x8UL << FMC_PCR2_TAR_Pos)                 /*!< 0x00010000 */
8155 
8156 #define FMC_PCR2_ECCPS_Pos          (17U)
8157 #define FMC_PCR2_ECCPS_Msk          (0x7UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x000E0000 */
8158 #define FMC_PCR2_ECCPS              FMC_PCR2_ECCPS_Msk                         /*!<ECCPS[1:0] bits (ECC page size)           */
8159 #define FMC_PCR2_ECCPS_0            (0x1UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x00020000 */
8160 #define FMC_PCR2_ECCPS_1            (0x2UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x00040000 */
8161 #define FMC_PCR2_ECCPS_2            (0x4UL << FMC_PCR2_ECCPS_Pos)               /*!< 0x00080000 */
8162 
8163 /******************  Bit definition for FMC_PCR3 register  *******************/
8164 #define FMC_PCR3_PWAITEN_Pos        (1U)
8165 #define FMC_PCR3_PWAITEN_Msk        (0x1UL << FMC_PCR3_PWAITEN_Pos)             /*!< 0x00000002 */
8166 #define FMC_PCR3_PWAITEN            FMC_PCR3_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
8167 #define FMC_PCR3_PBKEN_Pos          (2U)
8168 #define FMC_PCR3_PBKEN_Msk          (0x1UL << FMC_PCR3_PBKEN_Pos)               /*!< 0x00000004 */
8169 #define FMC_PCR3_PBKEN              FMC_PCR3_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
8170 #define FMC_PCR3_PTYP_Pos           (3U)
8171 #define FMC_PCR3_PTYP_Msk           (0x1UL << FMC_PCR3_PTYP_Pos)                /*!< 0x00000008 */
8172 #define FMC_PCR3_PTYP               FMC_PCR3_PTYP_Msk                          /*!<Memory type                               */
8173 
8174 #define FMC_PCR3_PWID_Pos           (4U)
8175 #define FMC_PCR3_PWID_Msk           (0x3UL << FMC_PCR3_PWID_Pos)                /*!< 0x00000030 */
8176 #define FMC_PCR3_PWID               FMC_PCR3_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
8177 #define FMC_PCR3_PWID_0             (0x1UL << FMC_PCR3_PWID_Pos)                /*!< 0x00000010 */
8178 #define FMC_PCR3_PWID_1             (0x2UL << FMC_PCR3_PWID_Pos)                /*!< 0x00000020 */
8179 
8180 #define FMC_PCR3_ECCEN_Pos          (6U)
8181 #define FMC_PCR3_ECCEN_Msk          (0x1UL << FMC_PCR3_ECCEN_Pos)               /*!< 0x00000040 */
8182 #define FMC_PCR3_ECCEN              FMC_PCR3_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
8183 
8184 #define FMC_PCR3_TCLR_Pos           (9U)
8185 #define FMC_PCR3_TCLR_Msk           (0xFUL << FMC_PCR3_TCLR_Pos)                /*!< 0x00001E00 */
8186 #define FMC_PCR3_TCLR               FMC_PCR3_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
8187 #define FMC_PCR3_TCLR_0             (0x1UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00000200 */
8188 #define FMC_PCR3_TCLR_1             (0x2UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00000400 */
8189 #define FMC_PCR3_TCLR_2             (0x4UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00000800 */
8190 #define FMC_PCR3_TCLR_3             (0x8UL << FMC_PCR3_TCLR_Pos)                /*!< 0x00001000 */
8191 
8192 #define FMC_PCR3_TAR_Pos            (13U)
8193 #define FMC_PCR3_TAR_Msk            (0xFUL << FMC_PCR3_TAR_Pos)                 /*!< 0x0001E000 */
8194 #define FMC_PCR3_TAR                FMC_PCR3_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
8195 #define FMC_PCR3_TAR_0              (0x1UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00002000 */
8196 #define FMC_PCR3_TAR_1              (0x2UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00004000 */
8197 #define FMC_PCR3_TAR_2              (0x4UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00008000 */
8198 #define FMC_PCR3_TAR_3              (0x8UL << FMC_PCR3_TAR_Pos)                 /*!< 0x00010000 */
8199 
8200 #define FMC_PCR3_ECCPS_Pos          (17U)
8201 #define FMC_PCR3_ECCPS_Msk          (0x7UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x000E0000 */
8202 #define FMC_PCR3_ECCPS              FMC_PCR3_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
8203 #define FMC_PCR3_ECCPS_0            (0x1UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x00020000 */
8204 #define FMC_PCR3_ECCPS_1            (0x2UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x00040000 */
8205 #define FMC_PCR3_ECCPS_2            (0x4UL << FMC_PCR3_ECCPS_Pos)               /*!< 0x00080000 */
8206 
8207 /******************  Bit definition for FMC_PCR4 register  *******************/
8208 #define FMC_PCR4_PWAITEN_Pos        (1U)
8209 #define FMC_PCR4_PWAITEN_Msk        (0x1UL << FMC_PCR4_PWAITEN_Pos)             /*!< 0x00000002 */
8210 #define FMC_PCR4_PWAITEN            FMC_PCR4_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
8211 #define FMC_PCR4_PBKEN_Pos          (2U)
8212 #define FMC_PCR4_PBKEN_Msk          (0x1UL << FMC_PCR4_PBKEN_Pos)               /*!< 0x00000004 */
8213 #define FMC_PCR4_PBKEN              FMC_PCR4_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
8214 #define FMC_PCR4_PTYP_Pos           (3U)
8215 #define FMC_PCR4_PTYP_Msk           (0x1UL << FMC_PCR4_PTYP_Pos)                /*!< 0x00000008 */
8216 #define FMC_PCR4_PTYP               FMC_PCR4_PTYP_Msk                          /*!<Memory type                               */
8217 
8218 #define FMC_PCR4_PWID_Pos           (4U)
8219 #define FMC_PCR4_PWID_Msk           (0x3UL << FMC_PCR4_PWID_Pos)                /*!< 0x00000030 */
8220 #define FMC_PCR4_PWID               FMC_PCR4_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
8221 #define FMC_PCR4_PWID_0             (0x1UL << FMC_PCR4_PWID_Pos)                /*!< 0x00000010 */
8222 #define FMC_PCR4_PWID_1             (0x2UL << FMC_PCR4_PWID_Pos)                /*!< 0x00000020 */
8223 
8224 #define FMC_PCR4_ECCEN_Pos          (6U)
8225 #define FMC_PCR4_ECCEN_Msk          (0x1UL << FMC_PCR4_ECCEN_Pos)               /*!< 0x00000040 */
8226 #define FMC_PCR4_ECCEN              FMC_PCR4_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
8227 
8228 #define FMC_PCR4_TCLR_Pos           (9U)
8229 #define FMC_PCR4_TCLR_Msk           (0xFUL << FMC_PCR4_TCLR_Pos)                /*!< 0x00001E00 */
8230 #define FMC_PCR4_TCLR               FMC_PCR4_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
8231 #define FMC_PCR4_TCLR_0             (0x1UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00000200 */
8232 #define FMC_PCR4_TCLR_1             (0x2UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00000400 */
8233 #define FMC_PCR4_TCLR_2             (0x4UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00000800 */
8234 #define FMC_PCR4_TCLR_3             (0x8UL << FMC_PCR4_TCLR_Pos)                /*!< 0x00001000 */
8235 
8236 #define FMC_PCR4_TAR_Pos            (13U)
8237 #define FMC_PCR4_TAR_Msk            (0xFUL << FMC_PCR4_TAR_Pos)                 /*!< 0x0001E000 */
8238 #define FMC_PCR4_TAR                FMC_PCR4_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
8239 #define FMC_PCR4_TAR_0              (0x1UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00002000 */
8240 #define FMC_PCR4_TAR_1              (0x2UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00004000 */
8241 #define FMC_PCR4_TAR_2              (0x4UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00008000 */
8242 #define FMC_PCR4_TAR_3              (0x8UL << FMC_PCR4_TAR_Pos)                 /*!< 0x00010000 */
8243 
8244 #define FMC_PCR4_ECCPS_Pos          (17U)
8245 #define FMC_PCR4_ECCPS_Msk          (0x7UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x000E0000 */
8246 #define FMC_PCR4_ECCPS              FMC_PCR4_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
8247 #define FMC_PCR4_ECCPS_0            (0x1UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x00020000 */
8248 #define FMC_PCR4_ECCPS_1            (0x2UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x00040000 */
8249 #define FMC_PCR4_ECCPS_2            (0x4UL << FMC_PCR4_ECCPS_Pos)               /*!< 0x00080000 */
8250 
8251 /*******************  Bit definition for FMC_SR2 register  *******************/
8252 #define FMC_SR2_IRS_Pos             (0U)
8253 #define FMC_SR2_IRS_Msk             (0x1UL << FMC_SR2_IRS_Pos)                  /*!< 0x00000001 */
8254 #define FMC_SR2_IRS                 FMC_SR2_IRS_Msk                            /*!<Interrupt Rising Edge status                */
8255 #define FMC_SR2_ILS_Pos             (1U)
8256 #define FMC_SR2_ILS_Msk             (0x1UL << FMC_SR2_ILS_Pos)                  /*!< 0x00000002 */
8257 #define FMC_SR2_ILS                 FMC_SR2_ILS_Msk                            /*!<Interrupt Level status                      */
8258 #define FMC_SR2_IFS_Pos             (2U)
8259 #define FMC_SR2_IFS_Msk             (0x1UL << FMC_SR2_IFS_Pos)                  /*!< 0x00000004 */
8260 #define FMC_SR2_IFS                 FMC_SR2_IFS_Msk                            /*!<Interrupt Falling Edge status               */
8261 #define FMC_SR2_IREN_Pos            (3U)
8262 #define FMC_SR2_IREN_Msk            (0x1UL << FMC_SR2_IREN_Pos)                 /*!< 0x00000008 */
8263 #define FMC_SR2_IREN                FMC_SR2_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
8264 #define FMC_SR2_ILEN_Pos            (4U)
8265 #define FMC_SR2_ILEN_Msk            (0x1UL << FMC_SR2_ILEN_Pos)                 /*!< 0x00000010 */
8266 #define FMC_SR2_ILEN                FMC_SR2_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
8267 #define FMC_SR2_IFEN_Pos            (5U)
8268 #define FMC_SR2_IFEN_Msk            (0x1UL << FMC_SR2_IFEN_Pos)                 /*!< 0x00000020 */
8269 #define FMC_SR2_IFEN                FMC_SR2_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
8270 #define FMC_SR2_FEMPT_Pos           (6U)
8271 #define FMC_SR2_FEMPT_Msk           (0x1UL << FMC_SR2_FEMPT_Pos)                /*!< 0x00000040 */
8272 #define FMC_SR2_FEMPT               FMC_SR2_FEMPT_Msk                          /*!<FIFO empty                                  */
8273 
8274 /*******************  Bit definition for FMC_SR3 register  *******************/
8275 #define FMC_SR3_IRS_Pos             (0U)
8276 #define FMC_SR3_IRS_Msk             (0x1UL << FMC_SR3_IRS_Pos)                  /*!< 0x00000001 */
8277 #define FMC_SR3_IRS                 FMC_SR3_IRS_Msk                            /*!<Interrupt Rising Edge status                */
8278 #define FMC_SR3_ILS_Pos             (1U)
8279 #define FMC_SR3_ILS_Msk             (0x1UL << FMC_SR3_ILS_Pos)                  /*!< 0x00000002 */
8280 #define FMC_SR3_ILS                 FMC_SR3_ILS_Msk                            /*!<Interrupt Level status                      */
8281 #define FMC_SR3_IFS_Pos             (2U)
8282 #define FMC_SR3_IFS_Msk             (0x1UL << FMC_SR3_IFS_Pos)                  /*!< 0x00000004 */
8283 #define FMC_SR3_IFS                 FMC_SR3_IFS_Msk                            /*!<Interrupt Falling Edge status               */
8284 #define FMC_SR3_IREN_Pos            (3U)
8285 #define FMC_SR3_IREN_Msk            (0x1UL << FMC_SR3_IREN_Pos)                 /*!< 0x00000008 */
8286 #define FMC_SR3_IREN                FMC_SR3_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
8287 #define FMC_SR3_ILEN_Pos            (4U)
8288 #define FMC_SR3_ILEN_Msk            (0x1UL << FMC_SR3_ILEN_Pos)                 /*!< 0x00000010 */
8289 #define FMC_SR3_ILEN                FMC_SR3_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
8290 #define FMC_SR3_IFEN_Pos            (5U)
8291 #define FMC_SR3_IFEN_Msk            (0x1UL << FMC_SR3_IFEN_Pos)                 /*!< 0x00000020 */
8292 #define FMC_SR3_IFEN                FMC_SR3_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
8293 #define FMC_SR3_FEMPT_Pos           (6U)
8294 #define FMC_SR3_FEMPT_Msk           (0x1UL << FMC_SR3_FEMPT_Pos)                /*!< 0x00000040 */
8295 #define FMC_SR3_FEMPT               FMC_SR3_FEMPT_Msk                          /*!<FIFO empty                                  */
8296 
8297 /*******************  Bit definition for FMC_SR4 register  *******************/
8298 #define FMC_SR4_IRS_Pos             (0U)
8299 #define FMC_SR4_IRS_Msk             (0x1UL << FMC_SR4_IRS_Pos)                  /*!< 0x00000001 */
8300 #define FMC_SR4_IRS                 FMC_SR4_IRS_Msk                            /*!<Interrupt Rising Edge status                */
8301 #define FMC_SR4_ILS_Pos             (1U)
8302 #define FMC_SR4_ILS_Msk             (0x1UL << FMC_SR4_ILS_Pos)                  /*!< 0x00000002 */
8303 #define FMC_SR4_ILS                 FMC_SR4_ILS_Msk                            /*!<Interrupt Level status                      */
8304 #define FMC_SR4_IFS_Pos             (2U)
8305 #define FMC_SR4_IFS_Msk             (0x1UL << FMC_SR4_IFS_Pos)                  /*!< 0x00000004 */
8306 #define FMC_SR4_IFS                 FMC_SR4_IFS_Msk                            /*!<Interrupt Falling Edge status               */
8307 #define FMC_SR4_IREN_Pos            (3U)
8308 #define FMC_SR4_IREN_Msk            (0x1UL << FMC_SR4_IREN_Pos)                 /*!< 0x00000008 */
8309 #define FMC_SR4_IREN                FMC_SR4_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
8310 #define FMC_SR4_ILEN_Pos            (4U)
8311 #define FMC_SR4_ILEN_Msk            (0x1UL << FMC_SR4_ILEN_Pos)                 /*!< 0x00000010 */
8312 #define FMC_SR4_ILEN                FMC_SR4_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
8313 #define FMC_SR4_IFEN_Pos            (5U)
8314 #define FMC_SR4_IFEN_Msk            (0x1UL << FMC_SR4_IFEN_Pos)                 /*!< 0x00000020 */
8315 #define FMC_SR4_IFEN                FMC_SR4_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
8316 #define FMC_SR4_FEMPT_Pos           (6U)
8317 #define FMC_SR4_FEMPT_Msk           (0x1UL << FMC_SR4_FEMPT_Pos)                /*!< 0x00000040 */
8318 #define FMC_SR4_FEMPT               FMC_SR4_FEMPT_Msk                          /*!<FIFO empty                                  */
8319 
8320 /******************  Bit definition for FMC_PMEM2 register  ******************/
8321 #define FMC_PMEM2_MEMSET2_Pos       (0U)
8322 #define FMC_PMEM2_MEMSET2_Msk       (0xFFUL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x000000FF */
8323 #define FMC_PMEM2_MEMSET2           FMC_PMEM2_MEMSET2_Msk                      /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
8324 #define FMC_PMEM2_MEMSET2_0         (0x01UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000001 */
8325 #define FMC_PMEM2_MEMSET2_1         (0x02UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000002 */
8326 #define FMC_PMEM2_MEMSET2_2         (0x04UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000004 */
8327 #define FMC_PMEM2_MEMSET2_3         (0x08UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000008 */
8328 #define FMC_PMEM2_MEMSET2_4         (0x10UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000010 */
8329 #define FMC_PMEM2_MEMSET2_5         (0x20UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000020 */
8330 #define FMC_PMEM2_MEMSET2_6         (0x40UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000040 */
8331 #define FMC_PMEM2_MEMSET2_7         (0x80UL << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000080 */
8332 
8333 #define FMC_PMEM2_MEMWAIT2_Pos      (8U)
8334 #define FMC_PMEM2_MEMWAIT2_Msk      (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x0000FF00 */
8335 #define FMC_PMEM2_MEMWAIT2          FMC_PMEM2_MEMWAIT2_Msk                     /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
8336 #define FMC_PMEM2_MEMWAIT2_0        (0x01UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000100 */
8337 #define FMC_PMEM2_MEMWAIT2_1        (0x02UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000200 */
8338 #define FMC_PMEM2_MEMWAIT2_2        (0x04UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000400 */
8339 #define FMC_PMEM2_MEMWAIT2_3        (0x08UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000800 */
8340 #define FMC_PMEM2_MEMWAIT2_4        (0x10UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00001000 */
8341 #define FMC_PMEM2_MEMWAIT2_5        (0x20UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00002000 */
8342 #define FMC_PMEM2_MEMWAIT2_6        (0x40UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00004000 */
8343 #define FMC_PMEM2_MEMWAIT2_7        (0x80UL << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00008000 */
8344 
8345 #define FMC_PMEM2_MEMHOLD2_Pos      (16U)
8346 #define FMC_PMEM2_MEMHOLD2_Msk      (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00FF0000 */
8347 #define FMC_PMEM2_MEMHOLD2          FMC_PMEM2_MEMHOLD2_Msk                     /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
8348 #define FMC_PMEM2_MEMHOLD2_0        (0x01UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00010000 */
8349 #define FMC_PMEM2_MEMHOLD2_1        (0x02UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00020000 */
8350 #define FMC_PMEM2_MEMHOLD2_2        (0x04UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00040000 */
8351 #define FMC_PMEM2_MEMHOLD2_3        (0x08UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00080000 */
8352 #define FMC_PMEM2_MEMHOLD2_4        (0x10UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00100000 */
8353 #define FMC_PMEM2_MEMHOLD2_5        (0x20UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00200000 */
8354 #define FMC_PMEM2_MEMHOLD2_6        (0x40UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00400000 */
8355 #define FMC_PMEM2_MEMHOLD2_7        (0x80UL << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00800000 */
8356 
8357 #define FMC_PMEM2_MEMHIZ2_Pos       (24U)
8358 #define FMC_PMEM2_MEMHIZ2_Msk       (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0xFF000000 */
8359 #define FMC_PMEM2_MEMHIZ2           FMC_PMEM2_MEMHIZ2_Msk                      /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
8360 #define FMC_PMEM2_MEMHIZ2_0         (0x01UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x01000000 */
8361 #define FMC_PMEM2_MEMHIZ2_1         (0x02UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x02000000 */
8362 #define FMC_PMEM2_MEMHIZ2_2         (0x04UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x04000000 */
8363 #define FMC_PMEM2_MEMHIZ2_3         (0x08UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x08000000 */
8364 #define FMC_PMEM2_MEMHIZ2_4         (0x10UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x10000000 */
8365 #define FMC_PMEM2_MEMHIZ2_5         (0x20UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x20000000 */
8366 #define FMC_PMEM2_MEMHIZ2_6         (0x40UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x40000000 */
8367 #define FMC_PMEM2_MEMHIZ2_7         (0x80UL << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x80000000 */
8368 
8369 /******************  Bit definition for FMC_PMEM3 register  ******************/
8370 #define FMC_PMEM3_MEMSET3_Pos       (0U)
8371 #define FMC_PMEM3_MEMSET3_Msk       (0xFFUL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x000000FF */
8372 #define FMC_PMEM3_MEMSET3           FMC_PMEM3_MEMSET3_Msk                      /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
8373 #define FMC_PMEM3_MEMSET3_0         (0x01UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000001 */
8374 #define FMC_PMEM3_MEMSET3_1         (0x02UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000002 */
8375 #define FMC_PMEM3_MEMSET3_2         (0x04UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000004 */
8376 #define FMC_PMEM3_MEMSET3_3         (0x08UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000008 */
8377 #define FMC_PMEM3_MEMSET3_4         (0x10UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000010 */
8378 #define FMC_PMEM3_MEMSET3_5         (0x20UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000020 */
8379 #define FMC_PMEM3_MEMSET3_6         (0x40UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000040 */
8380 #define FMC_PMEM3_MEMSET3_7         (0x80UL << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000080 */
8381 
8382 #define FMC_PMEM3_MEMWAIT3_Pos      (8U)
8383 #define FMC_PMEM3_MEMWAIT3_Msk      (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x0000FF00 */
8384 #define FMC_PMEM3_MEMWAIT3          FMC_PMEM3_MEMWAIT3_Msk                     /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
8385 #define FMC_PMEM3_MEMWAIT3_0        (0x01UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000100 */
8386 #define FMC_PMEM3_MEMWAIT3_1        (0x02UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000200 */
8387 #define FMC_PMEM3_MEMWAIT3_2        (0x04UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000400 */
8388 #define FMC_PMEM3_MEMWAIT3_3        (0x08UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000800 */
8389 #define FMC_PMEM3_MEMWAIT3_4        (0x10UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00001000 */
8390 #define FMC_PMEM3_MEMWAIT3_5        (0x20UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00002000 */
8391 #define FMC_PMEM3_MEMWAIT3_6        (0x40UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00004000 */
8392 #define FMC_PMEM3_MEMWAIT3_7        (0x80UL << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00008000 */
8393 
8394 #define FMC_PMEM3_MEMHOLD3_Pos      (16U)
8395 #define FMC_PMEM3_MEMHOLD3_Msk      (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00FF0000 */
8396 #define FMC_PMEM3_MEMHOLD3          FMC_PMEM3_MEMHOLD3_Msk                     /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
8397 #define FMC_PMEM3_MEMHOLD3_0        (0x01UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00010000 */
8398 #define FMC_PMEM3_MEMHOLD3_1        (0x02UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00020000 */
8399 #define FMC_PMEM3_MEMHOLD3_2        (0x04UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00040000 */
8400 #define FMC_PMEM3_MEMHOLD3_3        (0x08UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00080000 */
8401 #define FMC_PMEM3_MEMHOLD3_4        (0x10UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00100000 */
8402 #define FMC_PMEM3_MEMHOLD3_5        (0x20UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00200000 */
8403 #define FMC_PMEM3_MEMHOLD3_6        (0x40UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00400000 */
8404 #define FMC_PMEM3_MEMHOLD3_7        (0x80UL << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00800000 */
8405 
8406 #define FMC_PMEM3_MEMHIZ3_Pos       (24U)
8407 #define FMC_PMEM3_MEMHIZ3_Msk       (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0xFF000000 */
8408 #define FMC_PMEM3_MEMHIZ3           FMC_PMEM3_MEMHIZ3_Msk                      /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
8409 #define FMC_PMEM3_MEMHIZ3_0         (0x01UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x01000000 */
8410 #define FMC_PMEM3_MEMHIZ3_1         (0x02UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x02000000 */
8411 #define FMC_PMEM3_MEMHIZ3_2         (0x04UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x04000000 */
8412 #define FMC_PMEM3_MEMHIZ3_3         (0x08UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x08000000 */
8413 #define FMC_PMEM3_MEMHIZ3_4         (0x10UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x10000000 */
8414 #define FMC_PMEM3_MEMHIZ3_5         (0x20UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x20000000 */
8415 #define FMC_PMEM3_MEMHIZ3_6         (0x40UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x40000000 */
8416 #define FMC_PMEM3_MEMHIZ3_7         (0x80UL << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x80000000 */
8417 
8418 /******************  Bit definition for FMC_PMEM4 register  ******************/
8419 #define FMC_PMEM4_MEMSET4_Pos       (0U)
8420 #define FMC_PMEM4_MEMSET4_Msk       (0xFFUL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x000000FF */
8421 #define FMC_PMEM4_MEMSET4           FMC_PMEM4_MEMSET4_Msk                      /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
8422 #define FMC_PMEM4_MEMSET4_0         (0x01UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000001 */
8423 #define FMC_PMEM4_MEMSET4_1         (0x02UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000002 */
8424 #define FMC_PMEM4_MEMSET4_2         (0x04UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000004 */
8425 #define FMC_PMEM4_MEMSET4_3         (0x08UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000008 */
8426 #define FMC_PMEM4_MEMSET4_4         (0x10UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000010 */
8427 #define FMC_PMEM4_MEMSET4_5         (0x20UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000020 */
8428 #define FMC_PMEM4_MEMSET4_6         (0x40UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000040 */
8429 #define FMC_PMEM4_MEMSET4_7         (0x80UL << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000080 */
8430 
8431 #define FMC_PMEM4_MEMWAIT4_Pos      (8U)
8432 #define FMC_PMEM4_MEMWAIT4_Msk      (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x0000FF00 */
8433 #define FMC_PMEM4_MEMWAIT4          FMC_PMEM4_MEMWAIT4_Msk                     /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
8434 #define FMC_PMEM4_MEMWAIT4_0        (0x01UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000100 */
8435 #define FMC_PMEM4_MEMWAIT4_1        (0x02UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000200 */
8436 #define FMC_PMEM4_MEMWAIT4_2        (0x04UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000400 */
8437 #define FMC_PMEM4_MEMWAIT4_3        (0x08UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000800 */
8438 #define FMC_PMEM4_MEMWAIT4_4        (0x10UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00001000 */
8439 #define FMC_PMEM4_MEMWAIT4_5        (0x20UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00002000 */
8440 #define FMC_PMEM4_MEMWAIT4_6        (0x40UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00004000 */
8441 #define FMC_PMEM4_MEMWAIT4_7        (0x80UL << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00008000 */
8442 
8443 #define FMC_PMEM4_MEMHOLD4_Pos      (16U)
8444 #define FMC_PMEM4_MEMHOLD4_Msk      (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00FF0000 */
8445 #define FMC_PMEM4_MEMHOLD4          FMC_PMEM4_MEMHOLD4_Msk                     /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
8446 #define FMC_PMEM4_MEMHOLD4_0        (0x01UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00010000 */
8447 #define FMC_PMEM4_MEMHOLD4_1        (0x02UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00020000 */
8448 #define FMC_PMEM4_MEMHOLD4_2        (0x04UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00040000 */
8449 #define FMC_PMEM4_MEMHOLD4_3        (0x08UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00080000 */
8450 #define FMC_PMEM4_MEMHOLD4_4        (0x10UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00100000 */
8451 #define FMC_PMEM4_MEMHOLD4_5        (0x20UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00200000 */
8452 #define FMC_PMEM4_MEMHOLD4_6        (0x40UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00400000 */
8453 #define FMC_PMEM4_MEMHOLD4_7        (0x80UL << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00800000 */
8454 
8455 #define FMC_PMEM4_MEMHIZ4_Pos       (24U)
8456 #define FMC_PMEM4_MEMHIZ4_Msk       (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0xFF000000 */
8457 #define FMC_PMEM4_MEMHIZ4           FMC_PMEM4_MEMHIZ4_Msk                      /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
8458 #define FMC_PMEM4_MEMHIZ4_0         (0x01UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x01000000 */
8459 #define FMC_PMEM4_MEMHIZ4_1         (0x02UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x02000000 */
8460 #define FMC_PMEM4_MEMHIZ4_2         (0x04UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x04000000 */
8461 #define FMC_PMEM4_MEMHIZ4_3         (0x08UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x08000000 */
8462 #define FMC_PMEM4_MEMHIZ4_4         (0x10UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x10000000 */
8463 #define FMC_PMEM4_MEMHIZ4_5         (0x20UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x20000000 */
8464 #define FMC_PMEM4_MEMHIZ4_6         (0x40UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x40000000 */
8465 #define FMC_PMEM4_MEMHIZ4_7         (0x80UL << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x80000000 */
8466 
8467 /******************  Bit definition for FMC_PATT2 register  ******************/
8468 #define FMC_PATT2_ATTSET2_Pos       (0U)
8469 #define FMC_PATT2_ATTSET2_Msk       (0xFFUL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x000000FF */
8470 #define FMC_PATT2_ATTSET2           FMC_PATT2_ATTSET2_Msk                      /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
8471 #define FMC_PATT2_ATTSET2_0         (0x01UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000001 */
8472 #define FMC_PATT2_ATTSET2_1         (0x02UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000002 */
8473 #define FMC_PATT2_ATTSET2_2         (0x04UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000004 */
8474 #define FMC_PATT2_ATTSET2_3         (0x08UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000008 */
8475 #define FMC_PATT2_ATTSET2_4         (0x10UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000010 */
8476 #define FMC_PATT2_ATTSET2_5         (0x20UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000020 */
8477 #define FMC_PATT2_ATTSET2_6         (0x40UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000040 */
8478 #define FMC_PATT2_ATTSET2_7         (0x80UL << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000080 */
8479 
8480 #define FMC_PATT2_ATTWAIT2_Pos      (8U)
8481 #define FMC_PATT2_ATTWAIT2_Msk      (0xFFUL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x0000FF00 */
8482 #define FMC_PATT2_ATTWAIT2          FMC_PATT2_ATTWAIT2_Msk                     /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
8483 #define FMC_PATT2_ATTWAIT2_0        (0x01UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000100 */
8484 #define FMC_PATT2_ATTWAIT2_1        (0x02UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000200 */
8485 #define FMC_PATT2_ATTWAIT2_2        (0x04UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000400 */
8486 #define FMC_PATT2_ATTWAIT2_3        (0x08UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000800 */
8487 #define FMC_PATT2_ATTWAIT2_4        (0x10UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00001000 */
8488 #define FMC_PATT2_ATTWAIT2_5        (0x20UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00002000 */
8489 #define FMC_PATT2_ATTWAIT2_6        (0x40UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00004000 */
8490 #define FMC_PATT2_ATTWAIT2_7        (0x80UL << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00008000 */
8491 
8492 #define FMC_PATT2_ATTHOLD2_Pos      (16U)
8493 #define FMC_PATT2_ATTHOLD2_Msk      (0xFFUL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00FF0000 */
8494 #define FMC_PATT2_ATTHOLD2          FMC_PATT2_ATTHOLD2_Msk                     /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
8495 #define FMC_PATT2_ATTHOLD2_0        (0x01UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00010000 */
8496 #define FMC_PATT2_ATTHOLD2_1        (0x02UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00020000 */
8497 #define FMC_PATT2_ATTHOLD2_2        (0x04UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00040000 */
8498 #define FMC_PATT2_ATTHOLD2_3        (0x08UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00080000 */
8499 #define FMC_PATT2_ATTHOLD2_4        (0x10UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00100000 */
8500 #define FMC_PATT2_ATTHOLD2_5        (0x20UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00200000 */
8501 #define FMC_PATT2_ATTHOLD2_6        (0x40UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00400000 */
8502 #define FMC_PATT2_ATTHOLD2_7        (0x80UL << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00800000 */
8503 
8504 #define FMC_PATT2_ATTHIZ2_Pos       (24U)
8505 #define FMC_PATT2_ATTHIZ2_Msk       (0xFFUL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0xFF000000 */
8506 #define FMC_PATT2_ATTHIZ2           FMC_PATT2_ATTHIZ2_Msk                      /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
8507 #define FMC_PATT2_ATTHIZ2_0         (0x01UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x01000000 */
8508 #define FMC_PATT2_ATTHIZ2_1         (0x02UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x02000000 */
8509 #define FMC_PATT2_ATTHIZ2_2         (0x04UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x04000000 */
8510 #define FMC_PATT2_ATTHIZ2_3         (0x08UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x08000000 */
8511 #define FMC_PATT2_ATTHIZ2_4         (0x10UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x10000000 */
8512 #define FMC_PATT2_ATTHIZ2_5         (0x20UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x20000000 */
8513 #define FMC_PATT2_ATTHIZ2_6         (0x40UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x40000000 */
8514 #define FMC_PATT2_ATTHIZ2_7         (0x80UL << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x80000000 */
8515 
8516 /******************  Bit definition for FMC_PATT3 register  ******************/
8517 #define FMC_PATT3_ATTSET3_Pos       (0U)
8518 #define FMC_PATT3_ATTSET3_Msk       (0xFFUL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x000000FF */
8519 #define FMC_PATT3_ATTSET3           FMC_PATT3_ATTSET3_Msk                      /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
8520 #define FMC_PATT3_ATTSET3_0         (0x01UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000001 */
8521 #define FMC_PATT3_ATTSET3_1         (0x02UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000002 */
8522 #define FMC_PATT3_ATTSET3_2         (0x04UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000004 */
8523 #define FMC_PATT3_ATTSET3_3         (0x08UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000008 */
8524 #define FMC_PATT3_ATTSET3_4         (0x10UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000010 */
8525 #define FMC_PATT3_ATTSET3_5         (0x20UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000020 */
8526 #define FMC_PATT3_ATTSET3_6         (0x40UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000040 */
8527 #define FMC_PATT3_ATTSET3_7         (0x80UL << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000080 */
8528 
8529 #define FMC_PATT3_ATTWAIT3_Pos      (8U)
8530 #define FMC_PATT3_ATTWAIT3_Msk      (0xFFUL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x0000FF00 */
8531 #define FMC_PATT3_ATTWAIT3          FMC_PATT3_ATTWAIT3_Msk                     /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
8532 #define FMC_PATT3_ATTWAIT3_0        (0x01UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000100 */
8533 #define FMC_PATT3_ATTWAIT3_1        (0x02UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000200 */
8534 #define FMC_PATT3_ATTWAIT3_2        (0x04UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000400 */
8535 #define FMC_PATT3_ATTWAIT3_3        (0x08UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000800 */
8536 #define FMC_PATT3_ATTWAIT3_4        (0x10UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00001000 */
8537 #define FMC_PATT3_ATTWAIT3_5        (0x20UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00002000 */
8538 #define FMC_PATT3_ATTWAIT3_6        (0x40UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00004000 */
8539 #define FMC_PATT3_ATTWAIT3_7        (0x80UL << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00008000 */
8540 
8541 #define FMC_PATT3_ATTHOLD3_Pos      (16U)
8542 #define FMC_PATT3_ATTHOLD3_Msk      (0xFFUL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00FF0000 */
8543 #define FMC_PATT3_ATTHOLD3          FMC_PATT3_ATTHOLD3_Msk                     /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
8544 #define FMC_PATT3_ATTHOLD3_0        (0x01UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00010000 */
8545 #define FMC_PATT3_ATTHOLD3_1        (0x02UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00020000 */
8546 #define FMC_PATT3_ATTHOLD3_2        (0x04UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00040000 */
8547 #define FMC_PATT3_ATTHOLD3_3        (0x08UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00080000 */
8548 #define FMC_PATT3_ATTHOLD3_4        (0x10UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00100000 */
8549 #define FMC_PATT3_ATTHOLD3_5        (0x20UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00200000 */
8550 #define FMC_PATT3_ATTHOLD3_6        (0x40UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00400000 */
8551 #define FMC_PATT3_ATTHOLD3_7        (0x80UL << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00800000 */
8552 
8553 #define FMC_PATT3_ATTHIZ3_Pos       (24U)
8554 #define FMC_PATT3_ATTHIZ3_Msk       (0xFFUL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0xFF000000 */
8555 #define FMC_PATT3_ATTHIZ3           FMC_PATT3_ATTHIZ3_Msk                      /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
8556 #define FMC_PATT3_ATTHIZ3_0         (0x01UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x01000000 */
8557 #define FMC_PATT3_ATTHIZ3_1         (0x02UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x02000000 */
8558 #define FMC_PATT3_ATTHIZ3_2         (0x04UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x04000000 */
8559 #define FMC_PATT3_ATTHIZ3_3         (0x08UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x08000000 */
8560 #define FMC_PATT3_ATTHIZ3_4         (0x10UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x10000000 */
8561 #define FMC_PATT3_ATTHIZ3_5         (0x20UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x20000000 */
8562 #define FMC_PATT3_ATTHIZ3_6         (0x40UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x40000000 */
8563 #define FMC_PATT3_ATTHIZ3_7         (0x80UL << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x80000000 */
8564 
8565 /******************  Bit definition for FMC_PATT4 register  ******************/
8566 #define FMC_PATT4_ATTSET4_Pos       (0U)
8567 #define FMC_PATT4_ATTSET4_Msk       (0xFFUL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x000000FF */
8568 #define FMC_PATT4_ATTSET4           FMC_PATT4_ATTSET4_Msk                      /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
8569 #define FMC_PATT4_ATTSET4_0         (0x01UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000001 */
8570 #define FMC_PATT4_ATTSET4_1         (0x02UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000002 */
8571 #define FMC_PATT4_ATTSET4_2         (0x04UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000004 */
8572 #define FMC_PATT4_ATTSET4_3         (0x08UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000008 */
8573 #define FMC_PATT4_ATTSET4_4         (0x10UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000010 */
8574 #define FMC_PATT4_ATTSET4_5         (0x20UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000020 */
8575 #define FMC_PATT4_ATTSET4_6         (0x40UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000040 */
8576 #define FMC_PATT4_ATTSET4_7         (0x80UL << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000080 */
8577 
8578 #define FMC_PATT4_ATTWAIT4_Pos      (8U)
8579 #define FMC_PATT4_ATTWAIT4_Msk      (0xFFUL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x0000FF00 */
8580 #define FMC_PATT4_ATTWAIT4          FMC_PATT4_ATTWAIT4_Msk                     /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
8581 #define FMC_PATT4_ATTWAIT4_0        (0x01UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000100 */
8582 #define FMC_PATT4_ATTWAIT4_1        (0x02UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000200 */
8583 #define FMC_PATT4_ATTWAIT4_2        (0x04UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000400 */
8584 #define FMC_PATT4_ATTWAIT4_3        (0x08UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000800 */
8585 #define FMC_PATT4_ATTWAIT4_4        (0x10UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00001000 */
8586 #define FMC_PATT4_ATTWAIT4_5        (0x20UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00002000 */
8587 #define FMC_PATT4_ATTWAIT4_6        (0x40UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00004000 */
8588 #define FMC_PATT4_ATTWAIT4_7        (0x80UL << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00008000 */
8589 
8590 #define FMC_PATT4_ATTHOLD4_Pos      (16U)
8591 #define FMC_PATT4_ATTHOLD4_Msk      (0xFFUL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00FF0000 */
8592 #define FMC_PATT4_ATTHOLD4          FMC_PATT4_ATTHOLD4_Msk                     /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
8593 #define FMC_PATT4_ATTHOLD4_0        (0x01UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00010000 */
8594 #define FMC_PATT4_ATTHOLD4_1        (0x02UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00020000 */
8595 #define FMC_PATT4_ATTHOLD4_2        (0x04UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00040000 */
8596 #define FMC_PATT4_ATTHOLD4_3        (0x08UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00080000 */
8597 #define FMC_PATT4_ATTHOLD4_4        (0x10UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00100000 */
8598 #define FMC_PATT4_ATTHOLD4_5        (0x20UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00200000 */
8599 #define FMC_PATT4_ATTHOLD4_6        (0x40UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00400000 */
8600 #define FMC_PATT4_ATTHOLD4_7        (0x80UL << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00800000 */
8601 
8602 #define FMC_PATT4_ATTHIZ4_Pos       (24U)
8603 #define FMC_PATT4_ATTHIZ4_Msk       (0xFFUL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0xFF000000 */
8604 #define FMC_PATT4_ATTHIZ4           FMC_PATT4_ATTHIZ4_Msk                      /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
8605 #define FMC_PATT4_ATTHIZ4_0         (0x01UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x01000000 */
8606 #define FMC_PATT4_ATTHIZ4_1         (0x02UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x02000000 */
8607 #define FMC_PATT4_ATTHIZ4_2         (0x04UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x04000000 */
8608 #define FMC_PATT4_ATTHIZ4_3         (0x08UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x08000000 */
8609 #define FMC_PATT4_ATTHIZ4_4         (0x10UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x10000000 */
8610 #define FMC_PATT4_ATTHIZ4_5         (0x20UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x20000000 */
8611 #define FMC_PATT4_ATTHIZ4_6         (0x40UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x40000000 */
8612 #define FMC_PATT4_ATTHIZ4_7         (0x80UL << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x80000000 */
8613 
8614 /******************  Bit definition for FMC_PIO4 register  *******************/
8615 #define FMC_PIO4_IOSET4_Pos         (0U)
8616 #define FMC_PIO4_IOSET4_Msk         (0xFFUL << FMC_PIO4_IOSET4_Pos)             /*!< 0x000000FF */
8617 #define FMC_PIO4_IOSET4             FMC_PIO4_IOSET4_Msk                        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
8618 #define FMC_PIO4_IOSET4_0           (0x01UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000001 */
8619 #define FMC_PIO4_IOSET4_1           (0x02UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000002 */
8620 #define FMC_PIO4_IOSET4_2           (0x04UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000004 */
8621 #define FMC_PIO4_IOSET4_3           (0x08UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000008 */
8622 #define FMC_PIO4_IOSET4_4           (0x10UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000010 */
8623 #define FMC_PIO4_IOSET4_5           (0x20UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000020 */
8624 #define FMC_PIO4_IOSET4_6           (0x40UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000040 */
8625 #define FMC_PIO4_IOSET4_7           (0x80UL << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000080 */
8626 
8627 #define FMC_PIO4_IOWAIT4_Pos        (8U)
8628 #define FMC_PIO4_IOWAIT4_Msk        (0xFFUL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x0000FF00 */
8629 #define FMC_PIO4_IOWAIT4            FMC_PIO4_IOWAIT4_Msk                       /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
8630 #define FMC_PIO4_IOWAIT4_0          (0x01UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000100 */
8631 #define FMC_PIO4_IOWAIT4_1          (0x02UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000200 */
8632 #define FMC_PIO4_IOWAIT4_2          (0x04UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000400 */
8633 #define FMC_PIO4_IOWAIT4_3          (0x08UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000800 */
8634 #define FMC_PIO4_IOWAIT4_4          (0x10UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00001000 */
8635 #define FMC_PIO4_IOWAIT4_5          (0x20UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00002000 */
8636 #define FMC_PIO4_IOWAIT4_6          (0x40UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00004000 */
8637 #define FMC_PIO4_IOWAIT4_7          (0x80UL << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00008000 */
8638 
8639 #define FMC_PIO4_IOHOLD4_Pos        (16U)
8640 #define FMC_PIO4_IOHOLD4_Msk        (0xFFUL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00FF0000 */
8641 #define FMC_PIO4_IOHOLD4            FMC_PIO4_IOHOLD4_Msk                       /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
8642 #define FMC_PIO4_IOHOLD4_0          (0x01UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00010000 */
8643 #define FMC_PIO4_IOHOLD4_1          (0x02UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00020000 */
8644 #define FMC_PIO4_IOHOLD4_2          (0x04UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00040000 */
8645 #define FMC_PIO4_IOHOLD4_3          (0x08UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00080000 */
8646 #define FMC_PIO4_IOHOLD4_4          (0x10UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00100000 */
8647 #define FMC_PIO4_IOHOLD4_5          (0x20UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00200000 */
8648 #define FMC_PIO4_IOHOLD4_6          (0x40UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00400000 */
8649 #define FMC_PIO4_IOHOLD4_7          (0x80UL << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00800000 */
8650 
8651 #define FMC_PIO4_IOHIZ4_Pos         (24U)
8652 #define FMC_PIO4_IOHIZ4_Msk         (0xFFUL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0xFF000000 */
8653 #define FMC_PIO4_IOHIZ4             FMC_PIO4_IOHIZ4_Msk                        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
8654 #define FMC_PIO4_IOHIZ4_0           (0x01UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x01000000 */
8655 #define FMC_PIO4_IOHIZ4_1           (0x02UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x02000000 */
8656 #define FMC_PIO4_IOHIZ4_2           (0x04UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x04000000 */
8657 #define FMC_PIO4_IOHIZ4_3           (0x08UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x08000000 */
8658 #define FMC_PIO4_IOHIZ4_4           (0x10UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x10000000 */
8659 #define FMC_PIO4_IOHIZ4_5           (0x20UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x20000000 */
8660 #define FMC_PIO4_IOHIZ4_6           (0x40UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x40000000 */
8661 #define FMC_PIO4_IOHIZ4_7           (0x80UL << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x80000000 */
8662 
8663 
8664 /******************  Bit definition for FMC_ECCR2 register  ******************/
8665 #define FMC_ECCR2_ECC2_Pos          (0U)
8666 #define FMC_ECCR2_ECC2_Msk          (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos)        /*!< 0xFFFFFFFF */
8667 #define FMC_ECCR2_ECC2              FMC_ECCR2_ECC2_Msk                         /*!<ECC result */
8668 
8669 /******************  Bit definition for FMC_ECCR3 register  ******************/
8670 #define FMC_ECCR3_ECC3_Pos          (0U)
8671 #define FMC_ECCR3_ECC3_Msk          (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
8672 #define FMC_ECCR3_ECC3              FMC_ECCR3_ECC3_Msk                         /*!<ECC result */
8673 
8674 /******************  Bit definition for FMC_SDCR1 register  ******************/
8675 #define FMC_SDCR1_NC_Pos            (0U)
8676 #define FMC_SDCR1_NC_Msk            (0x3UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */
8677 #define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
8678 #define FMC_SDCR1_NC_0              (0x1UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */
8679 #define FMC_SDCR1_NC_1              (0x2UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */
8680 
8681 #define FMC_SDCR1_NR_Pos            (2U)
8682 #define FMC_SDCR1_NR_Msk            (0x3UL << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */
8683 #define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
8684 #define FMC_SDCR1_NR_0              (0x1UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */
8685 #define FMC_SDCR1_NR_1              (0x2UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */
8686 
8687 #define FMC_SDCR1_MWID_Pos          (4U)
8688 #define FMC_SDCR1_MWID_Msk          (0x3UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */
8689 #define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
8690 #define FMC_SDCR1_MWID_0            (0x1UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */
8691 #define FMC_SDCR1_MWID_1            (0x2UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */
8692 
8693 #define FMC_SDCR1_NB_Pos            (6U)
8694 #define FMC_SDCR1_NB_Msk            (0x1UL << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */
8695 #define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */
8696 
8697 #define FMC_SDCR1_CAS_Pos           (7U)
8698 #define FMC_SDCR1_CAS_Msk           (0x3UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */
8699 #define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
8700 #define FMC_SDCR1_CAS_0             (0x1UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */
8701 #define FMC_SDCR1_CAS_1             (0x2UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */
8702 
8703 #define FMC_SDCR1_WP_Pos            (9U)
8704 #define FMC_SDCR1_WP_Msk            (0x1UL << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */
8705 #define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */
8706 
8707 #define FMC_SDCR1_SDCLK_Pos         (10U)
8708 #define FMC_SDCR1_SDCLK_Msk         (0x3UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */
8709 #define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */
8710 #define FMC_SDCR1_SDCLK_0           (0x1UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */
8711 #define FMC_SDCR1_SDCLK_1           (0x2UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */
8712 
8713 #define FMC_SDCR1_RBURST_Pos        (12U)
8714 #define FMC_SDCR1_RBURST_Msk        (0x1UL << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */
8715 #define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */
8716 
8717 #define FMC_SDCR1_RPIPE_Pos         (13U)
8718 #define FMC_SDCR1_RPIPE_Msk         (0x3UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */
8719 #define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */
8720 #define FMC_SDCR1_RPIPE_0           (0x1UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */
8721 #define FMC_SDCR1_RPIPE_1           (0x2UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */
8722 
8723 /******************  Bit definition for FMC_SDCR2 register  ******************/
8724 #define FMC_SDCR2_NC_Pos            (0U)
8725 #define FMC_SDCR2_NC_Msk            (0x3UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */
8726 #define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
8727 #define FMC_SDCR2_NC_0              (0x1UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */
8728 #define FMC_SDCR2_NC_1              (0x2UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */
8729 
8730 #define FMC_SDCR2_NR_Pos            (2U)
8731 #define FMC_SDCR2_NR_Msk            (0x3UL << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */
8732 #define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
8733 #define FMC_SDCR2_NR_0              (0x1UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */
8734 #define FMC_SDCR2_NR_1              (0x2UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */
8735 
8736 #define FMC_SDCR2_MWID_Pos          (4U)
8737 #define FMC_SDCR2_MWID_Msk          (0x3UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */
8738 #define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
8739 #define FMC_SDCR2_MWID_0            (0x1UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */
8740 #define FMC_SDCR2_MWID_1            (0x2UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */
8741 
8742 #define FMC_SDCR2_NB_Pos            (6U)
8743 #define FMC_SDCR2_NB_Msk            (0x1UL << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */
8744 #define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */
8745 
8746 #define FMC_SDCR2_CAS_Pos           (7U)
8747 #define FMC_SDCR2_CAS_Msk           (0x3UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */
8748 #define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
8749 #define FMC_SDCR2_CAS_0             (0x1UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */
8750 #define FMC_SDCR2_CAS_1             (0x2UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */
8751 
8752 #define FMC_SDCR2_WP_Pos            (9U)
8753 #define FMC_SDCR2_WP_Msk            (0x1UL << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */
8754 #define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */
8755 
8756 #define FMC_SDCR2_SDCLK_Pos         (10U)
8757 #define FMC_SDCR2_SDCLK_Msk         (0x3UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */
8758 #define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */
8759 #define FMC_SDCR2_SDCLK_0           (0x1UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */
8760 #define FMC_SDCR2_SDCLK_1           (0x2UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */
8761 
8762 #define FMC_SDCR2_RBURST_Pos        (12U)
8763 #define FMC_SDCR2_RBURST_Msk        (0x1UL << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */
8764 #define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */
8765 
8766 #define FMC_SDCR2_RPIPE_Pos         (13U)
8767 #define FMC_SDCR2_RPIPE_Msk         (0x3UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */
8768 #define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */
8769 #define FMC_SDCR2_RPIPE_0           (0x1UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */
8770 #define FMC_SDCR2_RPIPE_1           (0x2UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */
8771 
8772 /******************  Bit definition for FMC_SDTR1 register  ******************/
8773 #define FMC_SDTR1_TMRD_Pos          (0U)
8774 #define FMC_SDTR1_TMRD_Msk          (0xFUL << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */
8775 #define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
8776 #define FMC_SDTR1_TMRD_0            (0x1UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */
8777 #define FMC_SDTR1_TMRD_1            (0x2UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */
8778 #define FMC_SDTR1_TMRD_2            (0x4UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */
8779 #define FMC_SDTR1_TMRD_3            (0x8UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */
8780 
8781 #define FMC_SDTR1_TXSR_Pos          (4U)
8782 #define FMC_SDTR1_TXSR_Msk          (0xFUL << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */
8783 #define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
8784 #define FMC_SDTR1_TXSR_0            (0x1UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */
8785 #define FMC_SDTR1_TXSR_1            (0x2UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */
8786 #define FMC_SDTR1_TXSR_2            (0x4UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */
8787 #define FMC_SDTR1_TXSR_3            (0x8UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */
8788 
8789 #define FMC_SDTR1_TRAS_Pos          (8U)
8790 #define FMC_SDTR1_TRAS_Msk          (0xFUL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */
8791 #define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
8792 #define FMC_SDTR1_TRAS_0            (0x1UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */
8793 #define FMC_SDTR1_TRAS_1            (0x2UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */
8794 #define FMC_SDTR1_TRAS_2            (0x4UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */
8795 #define FMC_SDTR1_TRAS_3            (0x8UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */
8796 
8797 #define FMC_SDTR1_TRC_Pos           (12U)
8798 #define FMC_SDTR1_TRC_Msk           (0xFUL << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */
8799 #define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
8800 #define FMC_SDTR1_TRC_0             (0x1UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */
8801 #define FMC_SDTR1_TRC_1             (0x2UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */
8802 #define FMC_SDTR1_TRC_2             (0x4UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */
8803 
8804 #define FMC_SDTR1_TWR_Pos           (16U)
8805 #define FMC_SDTR1_TWR_Msk           (0xFUL << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */
8806 #define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
8807 #define FMC_SDTR1_TWR_0             (0x1UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */
8808 #define FMC_SDTR1_TWR_1             (0x2UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */
8809 #define FMC_SDTR1_TWR_2             (0x4UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */
8810 
8811 #define FMC_SDTR1_TRP_Pos           (20U)
8812 #define FMC_SDTR1_TRP_Msk           (0xFUL << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */
8813 #define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
8814 #define FMC_SDTR1_TRP_0             (0x1UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */
8815 #define FMC_SDTR1_TRP_1             (0x2UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */
8816 #define FMC_SDTR1_TRP_2             (0x4UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */
8817 
8818 #define FMC_SDTR1_TRCD_Pos          (24U)
8819 #define FMC_SDTR1_TRCD_Msk          (0xFUL << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */
8820 #define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
8821 #define FMC_SDTR1_TRCD_0            (0x1UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */
8822 #define FMC_SDTR1_TRCD_1            (0x2UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */
8823 #define FMC_SDTR1_TRCD_2            (0x4UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */
8824 
8825 /******************  Bit definition for FMC_SDTR2 register  ******************/
8826 #define FMC_SDTR2_TMRD_Pos          (0U)
8827 #define FMC_SDTR2_TMRD_Msk          (0xFUL << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */
8828 #define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
8829 #define FMC_SDTR2_TMRD_0            (0x1UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */
8830 #define FMC_SDTR2_TMRD_1            (0x2UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */
8831 #define FMC_SDTR2_TMRD_2            (0x4UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */
8832 #define FMC_SDTR2_TMRD_3            (0x8UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */
8833 
8834 #define FMC_SDTR2_TXSR_Pos          (4U)
8835 #define FMC_SDTR2_TXSR_Msk          (0xFUL << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */
8836 #define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
8837 #define FMC_SDTR2_TXSR_0            (0x1UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */
8838 #define FMC_SDTR2_TXSR_1            (0x2UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */
8839 #define FMC_SDTR2_TXSR_2            (0x4UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */
8840 #define FMC_SDTR2_TXSR_3            (0x8UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */
8841 
8842 #define FMC_SDTR2_TRAS_Pos          (8U)
8843 #define FMC_SDTR2_TRAS_Msk          (0xFUL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */
8844 #define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
8845 #define FMC_SDTR2_TRAS_0            (0x1UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */
8846 #define FMC_SDTR2_TRAS_1            (0x2UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */
8847 #define FMC_SDTR2_TRAS_2            (0x4UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */
8848 #define FMC_SDTR2_TRAS_3            (0x8UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */
8849 
8850 #define FMC_SDTR2_TRC_Pos           (12U)
8851 #define FMC_SDTR2_TRC_Msk           (0xFUL << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */
8852 #define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
8853 #define FMC_SDTR2_TRC_0             (0x1UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */
8854 #define FMC_SDTR2_TRC_1             (0x2UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */
8855 #define FMC_SDTR2_TRC_2             (0x4UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */
8856 
8857 #define FMC_SDTR2_TWR_Pos           (16U)
8858 #define FMC_SDTR2_TWR_Msk           (0xFUL << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */
8859 #define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
8860 #define FMC_SDTR2_TWR_0             (0x1UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */
8861 #define FMC_SDTR2_TWR_1             (0x2UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */
8862 #define FMC_SDTR2_TWR_2             (0x4UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */
8863 
8864 #define FMC_SDTR2_TRP_Pos           (20U)
8865 #define FMC_SDTR2_TRP_Msk           (0xFUL << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */
8866 #define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
8867 #define FMC_SDTR2_TRP_0             (0x1UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */
8868 #define FMC_SDTR2_TRP_1             (0x2UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */
8869 #define FMC_SDTR2_TRP_2             (0x4UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */
8870 
8871 #define FMC_SDTR2_TRCD_Pos          (24U)
8872 #define FMC_SDTR2_TRCD_Msk          (0xFUL << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */
8873 #define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
8874 #define FMC_SDTR2_TRCD_0            (0x1UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */
8875 #define FMC_SDTR2_TRCD_1            (0x2UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */
8876 #define FMC_SDTR2_TRCD_2            (0x4UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */
8877 
8878 /******************  Bit definition for FMC_SDCMR register  ******************/
8879 #define FMC_SDCMR_MODE_Pos          (0U)
8880 #define FMC_SDCMR_MODE_Msk          (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
8881 #define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */
8882 #define FMC_SDCMR_MODE_0            (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
8883 #define FMC_SDCMR_MODE_1            (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
8884 #define FMC_SDCMR_MODE_2            (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
8885 
8886 #define FMC_SDCMR_CTB2_Pos          (3U)
8887 #define FMC_SDCMR_CTB2_Msk          (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
8888 #define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */
8889 
8890 #define FMC_SDCMR_CTB1_Pos          (4U)
8891 #define FMC_SDCMR_CTB1_Msk          (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
8892 #define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */
8893 
8894 #define FMC_SDCMR_NRFS_Pos          (5U)
8895 #define FMC_SDCMR_NRFS_Msk          (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
8896 #define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */
8897 #define FMC_SDCMR_NRFS_0            (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
8898 #define FMC_SDCMR_NRFS_1            (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
8899 #define FMC_SDCMR_NRFS_2            (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
8900 #define FMC_SDCMR_NRFS_3            (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
8901 
8902 #define FMC_SDCMR_MRD_Pos           (9U)
8903 #define FMC_SDCMR_MRD_Msk           (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
8904 #define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */
8905 
8906 /******************  Bit definition for FMC_SDRTR register  ******************/
8907 #define FMC_SDRTR_CRE_Pos           (0U)
8908 #define FMC_SDRTR_CRE_Msk           (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
8909 #define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */
8910 
8911 #define FMC_SDRTR_COUNT_Pos         (1U)
8912 #define FMC_SDRTR_COUNT_Msk         (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
8913 #define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */
8914 
8915 #define FMC_SDRTR_REIE_Pos          (14U)
8916 #define FMC_SDRTR_REIE_Msk          (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
8917 #define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */
8918 
8919 /******************  Bit definition for FMC_SDSR register  ******************/
8920 #define FMC_SDSR_RE_Pos             (0U)
8921 #define FMC_SDSR_RE_Msk             (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
8922 #define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */
8923 
8924 #define FMC_SDSR_MODES1_Pos         (1U)
8925 #define FMC_SDSR_MODES1_Msk         (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
8926 #define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */
8927 #define FMC_SDSR_MODES1_0           (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
8928 #define FMC_SDSR_MODES1_1           (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
8929 
8930 #define FMC_SDSR_MODES2_Pos         (3U)
8931 #define FMC_SDSR_MODES2_Msk         (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
8932 #define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */
8933 #define FMC_SDSR_MODES2_0           (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
8934 #define FMC_SDSR_MODES2_1           (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
8935 #define FMC_SDSR_BUSY_Pos           (5U)
8936 #define FMC_SDSR_BUSY_Msk           (0x1UL << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */
8937 #define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */
8938 
8939 /******************************************************************************/
8940 /*                                                                            */
8941 /*                            General Purpose I/O                             */
8942 /*                                                                            */
8943 /******************************************************************************/
8944 /******************  Bits definition for GPIO_MODER register  *****************/
8945 #define GPIO_MODER_MODER0_Pos            (0U)
8946 #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
8947 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
8948 #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
8949 #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
8950 #define GPIO_MODER_MODER1_Pos            (2U)
8951 #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
8952 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
8953 #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
8954 #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
8955 #define GPIO_MODER_MODER2_Pos            (4U)
8956 #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
8957 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
8958 #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
8959 #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
8960 #define GPIO_MODER_MODER3_Pos            (6U)
8961 #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
8962 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
8963 #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
8964 #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
8965 #define GPIO_MODER_MODER4_Pos            (8U)
8966 #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
8967 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
8968 #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
8969 #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
8970 #define GPIO_MODER_MODER5_Pos            (10U)
8971 #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
8972 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
8973 #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
8974 #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
8975 #define GPIO_MODER_MODER6_Pos            (12U)
8976 #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
8977 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
8978 #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
8979 #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
8980 #define GPIO_MODER_MODER7_Pos            (14U)
8981 #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
8982 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
8983 #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
8984 #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
8985 #define GPIO_MODER_MODER8_Pos            (16U)
8986 #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
8987 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
8988 #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
8989 #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
8990 #define GPIO_MODER_MODER9_Pos            (18U)
8991 #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
8992 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
8993 #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
8994 #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
8995 #define GPIO_MODER_MODER10_Pos           (20U)
8996 #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
8997 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
8998 #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
8999 #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
9000 #define GPIO_MODER_MODER11_Pos           (22U)
9001 #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
9002 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
9003 #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
9004 #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
9005 #define GPIO_MODER_MODER12_Pos           (24U)
9006 #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
9007 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
9008 #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
9009 #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
9010 #define GPIO_MODER_MODER13_Pos           (26U)
9011 #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
9012 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
9013 #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
9014 #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
9015 #define GPIO_MODER_MODER14_Pos           (28U)
9016 #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
9017 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
9018 #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
9019 #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
9020 #define GPIO_MODER_MODER15_Pos           (30U)
9021 #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
9022 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
9023 #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
9024 #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
9025 
9026 /* Legacy defines */
9027 #define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos
9028 #define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
9029 #define GPIO_MODER_MODE0                 GPIO_MODER_MODER0
9030 #define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
9031 #define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
9032 #define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos
9033 #define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
9034 #define GPIO_MODER_MODE1                 GPIO_MODER_MODER1
9035 #define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
9036 #define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
9037 #define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS
9038 #define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
9039 #define GPIO_MODER_MODE2                 GPIO_MODER_MODER2
9040 #define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
9041 #define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
9042 #define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos
9043 #define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
9044 #define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
9045 #define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
9046 #define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
9047 #define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
9048 #define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
9049 #define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
9050 #define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
9051 #define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
9052 #define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
9053 #define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
9054 #define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
9055 #define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
9056 #define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
9057 #define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
9058 #define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
9059 #define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
9060 #define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
9061 #define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
9062 #define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
9063 #define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
9064 #define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
9065 #define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
9066 #define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
9067 #define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
9068 #define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk
9069 #define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
9070 #define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
9071 #define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
9072 #define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
9073 #define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
9074 #define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
9075 #define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
9076 #define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
9077 #define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
9078 #define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
9079 #define GPIO_MODER_MODE10                GPIO_MODER_MODER10
9080 #define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
9081 #define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
9082 #define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
9083 #define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
9084 #define GPIO_MODER_MODE11                GPIO_MODER_MODER11
9085 #define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
9086 #define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
9087 #define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
9088 #define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
9089 #define GPIO_MODER_MODE12                GPIO_MODER_MODER12
9090 #define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
9091 #define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
9092 #define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
9093 #define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
9094 #define GPIO_MODER_MODE13                GPIO_MODER_MODER13
9095 #define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
9096 #define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
9097 #define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
9098 #define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
9099 #define GPIO_MODER_MODE14                GPIO_MODER_MODER14
9100 #define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
9101 #define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
9102 #define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
9103 #define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
9104 #define GPIO_MODER_MODE15                GPIO_MODER_MODER15
9105 #define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
9106 #define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
9107 
9108 /******************  Bits definition for GPIO_OTYPER register  ****************/
9109 #define GPIO_OTYPER_OT0_Pos              (0U)
9110 #define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
9111 #define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk
9112 #define GPIO_OTYPER_OT1_Pos              (1U)
9113 #define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
9114 #define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk
9115 #define GPIO_OTYPER_OT2_Pos              (2U)
9116 #define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
9117 #define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk
9118 #define GPIO_OTYPER_OT3_Pos              (3U)
9119 #define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
9120 #define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk
9121 #define GPIO_OTYPER_OT4_Pos              (4U)
9122 #define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
9123 #define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk
9124 #define GPIO_OTYPER_OT5_Pos              (5U)
9125 #define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
9126 #define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk
9127 #define GPIO_OTYPER_OT6_Pos              (6U)
9128 #define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
9129 #define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk
9130 #define GPIO_OTYPER_OT7_Pos              (7U)
9131 #define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
9132 #define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk
9133 #define GPIO_OTYPER_OT8_Pos              (8U)
9134 #define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
9135 #define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk
9136 #define GPIO_OTYPER_OT9_Pos              (9U)
9137 #define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
9138 #define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk
9139 #define GPIO_OTYPER_OT10_Pos             (10U)
9140 #define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
9141 #define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk
9142 #define GPIO_OTYPER_OT11_Pos             (11U)
9143 #define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
9144 #define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk
9145 #define GPIO_OTYPER_OT12_Pos             (12U)
9146 #define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
9147 #define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk
9148 #define GPIO_OTYPER_OT13_Pos             (13U)
9149 #define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
9150 #define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk
9151 #define GPIO_OTYPER_OT14_Pos             (14U)
9152 #define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
9153 #define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk
9154 #define GPIO_OTYPER_OT15_Pos             (15U)
9155 #define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
9156 #define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk
9157 
9158 /* Legacy defines */
9159 #define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
9160 #define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
9161 #define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
9162 #define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
9163 #define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
9164 #define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
9165 #define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
9166 #define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
9167 #define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
9168 #define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
9169 #define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
9170 #define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
9171 #define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
9172 #define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
9173 #define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
9174 #define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
9175 
9176 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
9177 #define GPIO_OSPEEDR_OSPEED0_Pos         (0U)
9178 #define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
9179 #define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk
9180 #define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
9181 #define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
9182 #define GPIO_OSPEEDR_OSPEED1_Pos         (2U)
9183 #define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
9184 #define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk
9185 #define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
9186 #define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
9187 #define GPIO_OSPEEDR_OSPEED2_Pos         (4U)
9188 #define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
9189 #define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk
9190 #define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
9191 #define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
9192 #define GPIO_OSPEEDR_OSPEED3_Pos         (6U)
9193 #define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
9194 #define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk
9195 #define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
9196 #define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
9197 #define GPIO_OSPEEDR_OSPEED4_Pos         (8U)
9198 #define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
9199 #define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk
9200 #define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
9201 #define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
9202 #define GPIO_OSPEEDR_OSPEED5_Pos         (10U)
9203 #define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
9204 #define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk
9205 #define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
9206 #define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
9207 #define GPIO_OSPEEDR_OSPEED6_Pos         (12U)
9208 #define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
9209 #define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk
9210 #define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
9211 #define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
9212 #define GPIO_OSPEEDR_OSPEED7_Pos         (14U)
9213 #define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
9214 #define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk
9215 #define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
9216 #define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
9217 #define GPIO_OSPEEDR_OSPEED8_Pos         (16U)
9218 #define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
9219 #define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk
9220 #define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
9221 #define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
9222 #define GPIO_OSPEEDR_OSPEED9_Pos         (18U)
9223 #define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
9224 #define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk
9225 #define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
9226 #define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
9227 #define GPIO_OSPEEDR_OSPEED10_Pos        (20U)
9228 #define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
9229 #define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk
9230 #define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
9231 #define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
9232 #define GPIO_OSPEEDR_OSPEED11_Pos        (22U)
9233 #define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
9234 #define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk
9235 #define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
9236 #define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
9237 #define GPIO_OSPEEDR_OSPEED12_Pos        (24U)
9238 #define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
9239 #define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk
9240 #define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
9241 #define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
9242 #define GPIO_OSPEEDR_OSPEED13_Pos        (26U)
9243 #define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
9244 #define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk
9245 #define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
9246 #define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
9247 #define GPIO_OSPEEDR_OSPEED14_Pos        (28U)
9248 #define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
9249 #define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk
9250 #define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
9251 #define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
9252 #define GPIO_OSPEEDR_OSPEED15_Pos        (30U)
9253 #define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
9254 #define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk
9255 #define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
9256 #define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
9257 
9258 /* Legacy defines */
9259 #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
9260 #define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
9261 #define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
9262 #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
9263 #define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
9264 #define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
9265 #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
9266 #define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
9267 #define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
9268 #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
9269 #define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
9270 #define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
9271 #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
9272 #define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
9273 #define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
9274 #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
9275 #define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
9276 #define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
9277 #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
9278 #define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
9279 #define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
9280 #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
9281 #define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
9282 #define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
9283 #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
9284 #define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
9285 #define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
9286 #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
9287 #define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
9288 #define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
9289 #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
9290 #define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
9291 #define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
9292 #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
9293 #define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
9294 #define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
9295 #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
9296 #define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
9297 #define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
9298 #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
9299 #define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
9300 #define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
9301 #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
9302 #define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
9303 #define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
9304 #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
9305 #define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
9306 #define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
9307 
9308 /******************  Bits definition for GPIO_PUPDR register  *****************/
9309 #define GPIO_PUPDR_PUPD0_Pos             (0U)
9310 #define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
9311 #define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk
9312 #define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
9313 #define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
9314 #define GPIO_PUPDR_PUPD1_Pos             (2U)
9315 #define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
9316 #define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk
9317 #define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
9318 #define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
9319 #define GPIO_PUPDR_PUPD2_Pos             (4U)
9320 #define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
9321 #define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk
9322 #define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
9323 #define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
9324 #define GPIO_PUPDR_PUPD3_Pos             (6U)
9325 #define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
9326 #define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk
9327 #define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
9328 #define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
9329 #define GPIO_PUPDR_PUPD4_Pos             (8U)
9330 #define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
9331 #define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk
9332 #define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
9333 #define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
9334 #define GPIO_PUPDR_PUPD5_Pos             (10U)
9335 #define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
9336 #define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk
9337 #define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
9338 #define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
9339 #define GPIO_PUPDR_PUPD6_Pos             (12U)
9340 #define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
9341 #define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk
9342 #define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
9343 #define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
9344 #define GPIO_PUPDR_PUPD7_Pos             (14U)
9345 #define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
9346 #define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk
9347 #define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
9348 #define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
9349 #define GPIO_PUPDR_PUPD8_Pos             (16U)
9350 #define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
9351 #define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk
9352 #define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
9353 #define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
9354 #define GPIO_PUPDR_PUPD9_Pos             (18U)
9355 #define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
9356 #define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk
9357 #define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
9358 #define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
9359 #define GPIO_PUPDR_PUPD10_Pos            (20U)
9360 #define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
9361 #define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk
9362 #define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
9363 #define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
9364 #define GPIO_PUPDR_PUPD11_Pos            (22U)
9365 #define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
9366 #define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk
9367 #define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
9368 #define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
9369 #define GPIO_PUPDR_PUPD12_Pos            (24U)
9370 #define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
9371 #define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk
9372 #define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
9373 #define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
9374 #define GPIO_PUPDR_PUPD13_Pos            (26U)
9375 #define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
9376 #define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk
9377 #define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
9378 #define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
9379 #define GPIO_PUPDR_PUPD14_Pos            (28U)
9380 #define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
9381 #define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk
9382 #define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
9383 #define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
9384 #define GPIO_PUPDR_PUPD15_Pos            (30U)
9385 #define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
9386 #define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk
9387 #define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
9388 #define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
9389 
9390 /* Legacy defines */
9391 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
9392 #define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
9393 #define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
9394 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
9395 #define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
9396 #define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
9397 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
9398 #define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
9399 #define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
9400 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
9401 #define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
9402 #define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
9403 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
9404 #define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
9405 #define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
9406 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
9407 #define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
9408 #define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
9409 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
9410 #define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
9411 #define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
9412 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
9413 #define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
9414 #define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
9415 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
9416 #define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
9417 #define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
9418 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
9419 #define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
9420 #define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
9421 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
9422 #define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
9423 #define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
9424 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
9425 #define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
9426 #define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
9427 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
9428 #define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
9429 #define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
9430 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
9431 #define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
9432 #define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
9433 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
9434 #define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
9435 #define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
9436 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
9437 #define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
9438 #define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
9439 
9440 /******************  Bits definition for GPIO_IDR register  *******************/
9441 #define GPIO_IDR_ID0_Pos                 (0U)
9442 #define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
9443 #define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk
9444 #define GPIO_IDR_ID1_Pos                 (1U)
9445 #define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
9446 #define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk
9447 #define GPIO_IDR_ID2_Pos                 (2U)
9448 #define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
9449 #define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk
9450 #define GPIO_IDR_ID3_Pos                 (3U)
9451 #define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
9452 #define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk
9453 #define GPIO_IDR_ID4_Pos                 (4U)
9454 #define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
9455 #define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk
9456 #define GPIO_IDR_ID5_Pos                 (5U)
9457 #define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
9458 #define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk
9459 #define GPIO_IDR_ID6_Pos                 (6U)
9460 #define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
9461 #define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk
9462 #define GPIO_IDR_ID7_Pos                 (7U)
9463 #define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
9464 #define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk
9465 #define GPIO_IDR_ID8_Pos                 (8U)
9466 #define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
9467 #define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk
9468 #define GPIO_IDR_ID9_Pos                 (9U)
9469 #define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
9470 #define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk
9471 #define GPIO_IDR_ID10_Pos                (10U)
9472 #define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
9473 #define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk
9474 #define GPIO_IDR_ID11_Pos                (11U)
9475 #define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
9476 #define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk
9477 #define GPIO_IDR_ID12_Pos                (12U)
9478 #define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
9479 #define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk
9480 #define GPIO_IDR_ID13_Pos                (13U)
9481 #define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
9482 #define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk
9483 #define GPIO_IDR_ID14_Pos                (14U)
9484 #define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
9485 #define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk
9486 #define GPIO_IDR_ID15_Pos                (15U)
9487 #define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
9488 #define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk
9489 
9490 /* Legacy defines */
9491 #define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
9492 #define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
9493 #define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
9494 #define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
9495 #define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
9496 #define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
9497 #define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
9498 #define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
9499 #define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
9500 #define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
9501 #define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
9502 #define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
9503 #define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
9504 #define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
9505 #define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
9506 #define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
9507 
9508 /******************  Bits definition for GPIO_ODR register  *******************/
9509 #define GPIO_ODR_OD0_Pos                 (0U)
9510 #define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
9511 #define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk
9512 #define GPIO_ODR_OD1_Pos                 (1U)
9513 #define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
9514 #define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk
9515 #define GPIO_ODR_OD2_Pos                 (2U)
9516 #define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
9517 #define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk
9518 #define GPIO_ODR_OD3_Pos                 (3U)
9519 #define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
9520 #define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk
9521 #define GPIO_ODR_OD4_Pos                 (4U)
9522 #define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
9523 #define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk
9524 #define GPIO_ODR_OD5_Pos                 (5U)
9525 #define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
9526 #define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk
9527 #define GPIO_ODR_OD6_Pos                 (6U)
9528 #define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
9529 #define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk
9530 #define GPIO_ODR_OD7_Pos                 (7U)
9531 #define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
9532 #define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk
9533 #define GPIO_ODR_OD8_Pos                 (8U)
9534 #define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
9535 #define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk
9536 #define GPIO_ODR_OD9_Pos                 (9U)
9537 #define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
9538 #define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk
9539 #define GPIO_ODR_OD10_Pos                (10U)
9540 #define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
9541 #define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk
9542 #define GPIO_ODR_OD11_Pos                (11U)
9543 #define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
9544 #define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk
9545 #define GPIO_ODR_OD12_Pos                (12U)
9546 #define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
9547 #define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk
9548 #define GPIO_ODR_OD13_Pos                (13U)
9549 #define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
9550 #define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk
9551 #define GPIO_ODR_OD14_Pos                (14U)
9552 #define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
9553 #define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk
9554 #define GPIO_ODR_OD15_Pos                (15U)
9555 #define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
9556 #define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk
9557 /* Legacy defines */
9558 #define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
9559 #define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
9560 #define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
9561 #define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
9562 #define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
9563 #define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
9564 #define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
9565 #define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
9566 #define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
9567 #define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
9568 #define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
9569 #define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
9570 #define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
9571 #define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
9572 #define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
9573 #define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
9574 
9575 /******************  Bits definition for GPIO_BSRR register  ******************/
9576 #define GPIO_BSRR_BS0_Pos                (0U)
9577 #define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
9578 #define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk
9579 #define GPIO_BSRR_BS1_Pos                (1U)
9580 #define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
9581 #define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk
9582 #define GPIO_BSRR_BS2_Pos                (2U)
9583 #define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
9584 #define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk
9585 #define GPIO_BSRR_BS3_Pos                (3U)
9586 #define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
9587 #define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk
9588 #define GPIO_BSRR_BS4_Pos                (4U)
9589 #define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
9590 #define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk
9591 #define GPIO_BSRR_BS5_Pos                (5U)
9592 #define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
9593 #define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk
9594 #define GPIO_BSRR_BS6_Pos                (6U)
9595 #define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
9596 #define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk
9597 #define GPIO_BSRR_BS7_Pos                (7U)
9598 #define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
9599 #define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk
9600 #define GPIO_BSRR_BS8_Pos                (8U)
9601 #define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
9602 #define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk
9603 #define GPIO_BSRR_BS9_Pos                (9U)
9604 #define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
9605 #define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk
9606 #define GPIO_BSRR_BS10_Pos               (10U)
9607 #define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
9608 #define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk
9609 #define GPIO_BSRR_BS11_Pos               (11U)
9610 #define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
9611 #define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk
9612 #define GPIO_BSRR_BS12_Pos               (12U)
9613 #define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
9614 #define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk
9615 #define GPIO_BSRR_BS13_Pos               (13U)
9616 #define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
9617 #define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk
9618 #define GPIO_BSRR_BS14_Pos               (14U)
9619 #define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
9620 #define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk
9621 #define GPIO_BSRR_BS15_Pos               (15U)
9622 #define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
9623 #define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk
9624 #define GPIO_BSRR_BR0_Pos                (16U)
9625 #define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
9626 #define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk
9627 #define GPIO_BSRR_BR1_Pos                (17U)
9628 #define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
9629 #define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk
9630 #define GPIO_BSRR_BR2_Pos                (18U)
9631 #define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
9632 #define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk
9633 #define GPIO_BSRR_BR3_Pos                (19U)
9634 #define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
9635 #define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk
9636 #define GPIO_BSRR_BR4_Pos                (20U)
9637 #define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
9638 #define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk
9639 #define GPIO_BSRR_BR5_Pos                (21U)
9640 #define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
9641 #define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk
9642 #define GPIO_BSRR_BR6_Pos                (22U)
9643 #define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
9644 #define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk
9645 #define GPIO_BSRR_BR7_Pos                (23U)
9646 #define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
9647 #define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk
9648 #define GPIO_BSRR_BR8_Pos                (24U)
9649 #define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
9650 #define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk
9651 #define GPIO_BSRR_BR9_Pos                (25U)
9652 #define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
9653 #define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk
9654 #define GPIO_BSRR_BR10_Pos               (26U)
9655 #define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
9656 #define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk
9657 #define GPIO_BSRR_BR11_Pos               (27U)
9658 #define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
9659 #define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk
9660 #define GPIO_BSRR_BR12_Pos               (28U)
9661 #define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
9662 #define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk
9663 #define GPIO_BSRR_BR13_Pos               (29U)
9664 #define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
9665 #define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk
9666 #define GPIO_BSRR_BR14_Pos               (30U)
9667 #define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
9668 #define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk
9669 #define GPIO_BSRR_BR15_Pos               (31U)
9670 #define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
9671 #define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk
9672 
9673 /* Legacy defines */
9674 #define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
9675 #define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
9676 #define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
9677 #define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
9678 #define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
9679 #define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
9680 #define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
9681 #define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
9682 #define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
9683 #define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
9684 #define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
9685 #define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
9686 #define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
9687 #define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
9688 #define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
9689 #define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
9690 #define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
9691 #define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
9692 #define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
9693 #define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
9694 #define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
9695 #define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
9696 #define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
9697 #define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
9698 #define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
9699 #define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
9700 #define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
9701 #define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
9702 #define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
9703 #define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
9704 #define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
9705 #define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
9706 #define GPIO_BRR_BR0                     GPIO_BSRR_BR0
9707 #define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
9708 #define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
9709 #define GPIO_BRR_BR1                     GPIO_BSRR_BR1
9710 #define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
9711 #define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
9712 #define GPIO_BRR_BR2                     GPIO_BSRR_BR2
9713 #define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
9714 #define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
9715 #define GPIO_BRR_BR3                     GPIO_BSRR_BR3
9716 #define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
9717 #define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
9718 #define GPIO_BRR_BR4                     GPIO_BSRR_BR4
9719 #define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
9720 #define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
9721 #define GPIO_BRR_BR5                     GPIO_BSRR_BR5
9722 #define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
9723 #define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
9724 #define GPIO_BRR_BR6                     GPIO_BSRR_BR6
9725 #define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
9726 #define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
9727 #define GPIO_BRR_BR7                     GPIO_BSRR_BR7
9728 #define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
9729 #define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
9730 #define GPIO_BRR_BR8                     GPIO_BSRR_BR8
9731 #define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
9732 #define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
9733 #define GPIO_BRR_BR9                     GPIO_BSRR_BR9
9734 #define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
9735 #define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
9736 #define GPIO_BRR_BR10                    GPIO_BSRR_BR10
9737 #define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
9738 #define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
9739 #define GPIO_BRR_BR11                    GPIO_BSRR_BR11
9740 #define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
9741 #define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
9742 #define GPIO_BRR_BR12                    GPIO_BSRR_BR12
9743 #define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
9744 #define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
9745 #define GPIO_BRR_BR13                    GPIO_BSRR_BR13
9746 #define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
9747 #define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
9748 #define GPIO_BRR_BR14                    GPIO_BSRR_BR14
9749 #define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
9750 #define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
9751 #define GPIO_BRR_BR15                    GPIO_BSRR_BR15
9752 #define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
9753 #define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk
9754 /****************** Bit definition for GPIO_LCKR register *********************/
9755 #define GPIO_LCKR_LCK0_Pos               (0U)
9756 #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
9757 #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
9758 #define GPIO_LCKR_LCK1_Pos               (1U)
9759 #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
9760 #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
9761 #define GPIO_LCKR_LCK2_Pos               (2U)
9762 #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
9763 #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
9764 #define GPIO_LCKR_LCK3_Pos               (3U)
9765 #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
9766 #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
9767 #define GPIO_LCKR_LCK4_Pos               (4U)
9768 #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
9769 #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
9770 #define GPIO_LCKR_LCK5_Pos               (5U)
9771 #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
9772 #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
9773 #define GPIO_LCKR_LCK6_Pos               (6U)
9774 #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
9775 #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
9776 #define GPIO_LCKR_LCK7_Pos               (7U)
9777 #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
9778 #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
9779 #define GPIO_LCKR_LCK8_Pos               (8U)
9780 #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
9781 #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
9782 #define GPIO_LCKR_LCK9_Pos               (9U)
9783 #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
9784 #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
9785 #define GPIO_LCKR_LCK10_Pos              (10U)
9786 #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
9787 #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
9788 #define GPIO_LCKR_LCK11_Pos              (11U)
9789 #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
9790 #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
9791 #define GPIO_LCKR_LCK12_Pos              (12U)
9792 #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
9793 #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
9794 #define GPIO_LCKR_LCK13_Pos              (13U)
9795 #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
9796 #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
9797 #define GPIO_LCKR_LCK14_Pos              (14U)
9798 #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
9799 #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
9800 #define GPIO_LCKR_LCK15_Pos              (15U)
9801 #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
9802 #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
9803 #define GPIO_LCKR_LCKK_Pos               (16U)
9804 #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
9805 #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
9806 /****************** Bit definition for GPIO_AFRL register *********************/
9807 #define GPIO_AFRL_AFSEL0_Pos             (0U)
9808 #define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
9809 #define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk
9810 #define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
9811 #define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
9812 #define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
9813 #define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
9814 #define GPIO_AFRL_AFSEL1_Pos             (4U)
9815 #define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
9816 #define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk
9817 #define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
9818 #define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
9819 #define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
9820 #define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
9821 #define GPIO_AFRL_AFSEL2_Pos             (8U)
9822 #define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
9823 #define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk
9824 #define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
9825 #define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
9826 #define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
9827 #define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
9828 #define GPIO_AFRL_AFSEL3_Pos             (12U)
9829 #define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
9830 #define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk
9831 #define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
9832 #define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
9833 #define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
9834 #define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
9835 #define GPIO_AFRL_AFSEL4_Pos             (16U)
9836 #define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
9837 #define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk
9838 #define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
9839 #define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
9840 #define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
9841 #define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
9842 #define GPIO_AFRL_AFSEL5_Pos             (20U)
9843 #define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
9844 #define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk
9845 #define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
9846 #define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
9847 #define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
9848 #define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
9849 #define GPIO_AFRL_AFSEL6_Pos             (24U)
9850 #define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
9851 #define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk
9852 #define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
9853 #define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
9854 #define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
9855 #define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
9856 #define GPIO_AFRL_AFSEL7_Pos             (28U)
9857 #define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
9858 #define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk
9859 #define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
9860 #define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
9861 #define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
9862 #define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
9863 
9864 /* Legacy defines */
9865 #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
9866 #define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
9867 #define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
9868 #define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
9869 #define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
9870 #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
9871 #define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
9872 #define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
9873 #define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
9874 #define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
9875 #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
9876 #define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
9877 #define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
9878 #define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
9879 #define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
9880 #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
9881 #define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
9882 #define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
9883 #define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
9884 #define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
9885 #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
9886 #define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
9887 #define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
9888 #define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
9889 #define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
9890 #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
9891 #define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
9892 #define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
9893 #define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
9894 #define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
9895 #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
9896 #define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
9897 #define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
9898 #define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
9899 #define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
9900 #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
9901 #define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
9902 #define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
9903 #define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
9904 #define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
9905 
9906 /****************** Bit definition for GPIO_AFRH register *********************/
9907 #define GPIO_AFRH_AFSEL8_Pos             (0U)
9908 #define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
9909 #define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk
9910 #define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
9911 #define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
9912 #define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
9913 #define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
9914 #define GPIO_AFRH_AFSEL9_Pos             (4U)
9915 #define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
9916 #define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk
9917 #define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
9918 #define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
9919 #define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
9920 #define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
9921 #define GPIO_AFRH_AFSEL10_Pos            (8U)
9922 #define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
9923 #define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk
9924 #define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
9925 #define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
9926 #define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
9927 #define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
9928 #define GPIO_AFRH_AFSEL11_Pos            (12U)
9929 #define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
9930 #define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk
9931 #define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
9932 #define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
9933 #define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
9934 #define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
9935 #define GPIO_AFRH_AFSEL12_Pos            (16U)
9936 #define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
9937 #define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk
9938 #define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
9939 #define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
9940 #define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
9941 #define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
9942 #define GPIO_AFRH_AFSEL13_Pos            (20U)
9943 #define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
9944 #define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk
9945 #define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
9946 #define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
9947 #define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
9948 #define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
9949 #define GPIO_AFRH_AFSEL14_Pos            (24U)
9950 #define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
9951 #define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk
9952 #define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
9953 #define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
9954 #define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
9955 #define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
9956 #define GPIO_AFRH_AFSEL15_Pos            (28U)
9957 #define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
9958 #define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk
9959 #define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
9960 #define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
9961 #define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
9962 #define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
9963 
9964 /* Legacy defines */
9965 #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
9966 #define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
9967 #define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
9968 #define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
9969 #define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
9970 #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
9971 #define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
9972 #define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
9973 #define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
9974 #define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
9975 #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
9976 #define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
9977 #define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
9978 #define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
9979 #define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
9980 #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
9981 #define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
9982 #define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
9983 #define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
9984 #define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
9985 #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
9986 #define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
9987 #define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
9988 #define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
9989 #define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
9990 #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
9991 #define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
9992 #define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
9993 #define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
9994 #define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
9995 #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
9996 #define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
9997 #define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
9998 #define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
9999 #define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
10000 #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
10001 #define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
10002 #define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
10003 #define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
10004 #define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
10005 
10006 
10007 /******************************************************************************/
10008 /*                                                                            */
10009 /*                                    HASH                                    */
10010 /*                                                                            */
10011 /******************************************************************************/
10012 /******************  Bits definition for HASH_CR register  ********************/
10013 #define HASH_CR_INIT_Pos          (2U)
10014 #define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                   /*!< 0x00000004 */
10015 #define HASH_CR_INIT              HASH_CR_INIT_Msk
10016 #define HASH_CR_DMAE_Pos          (3U)
10017 #define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                   /*!< 0x00000008 */
10018 #define HASH_CR_DMAE              HASH_CR_DMAE_Msk
10019 #define HASH_CR_DATATYPE_Pos      (4U)
10020 #define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000030 */
10021 #define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk
10022 #define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */
10023 #define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */
10024 #define HASH_CR_MODE_Pos          (6U)
10025 #define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                   /*!< 0x00000040 */
10026 #define HASH_CR_MODE              HASH_CR_MODE_Msk
10027 #define HASH_CR_ALGO_Pos          (7U)
10028 #define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040080 */
10029 #define HASH_CR_ALGO              HASH_CR_ALGO_Msk
10030 #define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */
10031 #define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */
10032 #define HASH_CR_NBW_Pos           (8U)
10033 #define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                    /*!< 0x00000F00 */
10034 #define HASH_CR_NBW               HASH_CR_NBW_Msk
10035 #define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */
10036 #define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */
10037 #define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */
10038 #define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */
10039 #define HASH_CR_DINNE_Pos         (12U)
10040 #define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                  /*!< 0x00001000 */
10041 #define HASH_CR_DINNE             HASH_CR_DINNE_Msk
10042 #define HASH_CR_MDMAT_Pos         (13U)
10043 #define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                  /*!< 0x00002000 */
10044 #define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk
10045 #define HASH_CR_LKEY_Pos          (16U)
10046 #define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                   /*!< 0x00010000 */
10047 #define HASH_CR_LKEY              HASH_CR_LKEY_Msk
10048 
10049 /******************  Bits definition for HASH_STR register  *******************/
10050 #define HASH_STR_NBLW_Pos         (0U)
10051 #define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                 /*!< 0x0000001F */
10052 #define HASH_STR_NBLW             HASH_STR_NBLW_Msk
10053 #define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */
10054 #define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */
10055 #define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */
10056 #define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */
10057 #define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */
10058 #define HASH_STR_DCAL_Pos         (8U)
10059 #define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                  /*!< 0x00000100 */
10060 #define HASH_STR_DCAL             HASH_STR_DCAL_Msk
10061 /* Aliases for HASH_STR register */
10062 #define HASH_STR_NBW                         HASH_STR_NBLW
10063 #define HASH_STR_NBW_0                       HASH_STR_NBLW_0
10064 #define HASH_STR_NBW_1                       HASH_STR_NBLW_1
10065 #define HASH_STR_NBW_2                       HASH_STR_NBLW_2
10066 #define HASH_STR_NBW_3                       HASH_STR_NBLW_3
10067 #define HASH_STR_NBW_4                       HASH_STR_NBLW_4
10068 
10069 /******************  Bits definition for HASH_IMR register  *******************/
10070 #define HASH_IMR_DINIE_Pos        (0U)
10071 #define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                 /*!< 0x00000001 */
10072 #define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk
10073 #define HASH_IMR_DCIE_Pos         (1U)
10074 #define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                  /*!< 0x00000002 */
10075 #define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk
10076 /* Aliases for HASH_IMR register */
10077 #define HASH_IMR_DINIM                       HASH_IMR_DINIE
10078 #define HASH_IMR_DCIM                        HASH_IMR_DCIE
10079 
10080 /******************  Bits definition for HASH_SR register  ********************/
10081 #define HASH_SR_DINIS_Pos         (0U)
10082 #define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                  /*!< 0x00000001 */
10083 #define HASH_SR_DINIS             HASH_SR_DINIS_Msk
10084 #define HASH_SR_DCIS_Pos          (1U)
10085 #define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                   /*!< 0x00000002 */
10086 #define HASH_SR_DCIS              HASH_SR_DCIS_Msk
10087 #define HASH_SR_DMAS_Pos          (2U)
10088 #define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                   /*!< 0x00000004 */
10089 #define HASH_SR_DMAS              HASH_SR_DMAS_Msk
10090 #define HASH_SR_BUSY_Pos          (3U)
10091 #define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                   /*!< 0x00000008 */
10092 #define HASH_SR_BUSY              HASH_SR_BUSY_Msk
10093 
10094 /******************************************************************************/
10095 /*                                                                            */
10096 /*                      Inter-integrated Circuit Interface                    */
10097 /*                                                                            */
10098 /******************************************************************************/
10099 /*******************  Bit definition for I2C_CR1 register  ********************/
10100 #define I2C_CR1_PE_Pos            (0U)
10101 #define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
10102 #define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
10103 #define I2C_CR1_SMBUS_Pos         (1U)
10104 #define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
10105 #define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
10106 #define I2C_CR1_SMBTYPE_Pos       (3U)
10107 #define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
10108 #define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
10109 #define I2C_CR1_ENARP_Pos         (4U)
10110 #define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
10111 #define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
10112 #define I2C_CR1_ENPEC_Pos         (5U)
10113 #define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
10114 #define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
10115 #define I2C_CR1_ENGC_Pos          (6U)
10116 #define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
10117 #define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
10118 #define I2C_CR1_NOSTRETCH_Pos     (7U)
10119 #define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
10120 #define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
10121 #define I2C_CR1_START_Pos         (8U)
10122 #define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
10123 #define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
10124 #define I2C_CR1_STOP_Pos          (9U)
10125 #define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
10126 #define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
10127 #define I2C_CR1_ACK_Pos           (10U)
10128 #define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
10129 #define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
10130 #define I2C_CR1_POS_Pos           (11U)
10131 #define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
10132 #define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
10133 #define I2C_CR1_PEC_Pos           (12U)
10134 #define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
10135 #define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
10136 #define I2C_CR1_ALERT_Pos         (13U)
10137 #define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
10138 #define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
10139 #define I2C_CR1_SWRST_Pos         (15U)
10140 #define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
10141 #define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
10142 
10143 /*******************  Bit definition for I2C_CR2 register  ********************/
10144 #define I2C_CR2_FREQ_Pos          (0U)
10145 #define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
10146 #define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
10147 #define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
10148 #define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
10149 #define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
10150 #define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
10151 #define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
10152 #define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
10153 
10154 #define I2C_CR2_ITERREN_Pos       (8U)
10155 #define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
10156 #define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
10157 #define I2C_CR2_ITEVTEN_Pos       (9U)
10158 #define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
10159 #define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
10160 #define I2C_CR2_ITBUFEN_Pos       (10U)
10161 #define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
10162 #define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
10163 #define I2C_CR2_DMAEN_Pos         (11U)
10164 #define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
10165 #define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
10166 #define I2C_CR2_LAST_Pos          (12U)
10167 #define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
10168 #define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
10169 
10170 /*******************  Bit definition for I2C_OAR1 register  *******************/
10171 #define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
10172 #define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
10173 
10174 #define I2C_OAR1_ADD0_Pos         (0U)
10175 #define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
10176 #define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
10177 #define I2C_OAR1_ADD1_Pos         (1U)
10178 #define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
10179 #define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
10180 #define I2C_OAR1_ADD2_Pos         (2U)
10181 #define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
10182 #define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
10183 #define I2C_OAR1_ADD3_Pos         (3U)
10184 #define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
10185 #define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
10186 #define I2C_OAR1_ADD4_Pos         (4U)
10187 #define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
10188 #define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
10189 #define I2C_OAR1_ADD5_Pos         (5U)
10190 #define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
10191 #define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
10192 #define I2C_OAR1_ADD6_Pos         (6U)
10193 #define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
10194 #define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
10195 #define I2C_OAR1_ADD7_Pos         (7U)
10196 #define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
10197 #define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
10198 #define I2C_OAR1_ADD8_Pos         (8U)
10199 #define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
10200 #define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
10201 #define I2C_OAR1_ADD9_Pos         (9U)
10202 #define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
10203 #define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
10204 
10205 #define I2C_OAR1_ADDMODE_Pos      (15U)
10206 #define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
10207 #define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
10208 
10209 /*******************  Bit definition for I2C_OAR2 register  *******************/
10210 #define I2C_OAR2_ENDUAL_Pos       (0U)
10211 #define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
10212 #define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
10213 #define I2C_OAR2_ADD2_Pos         (1U)
10214 #define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
10215 #define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
10216 
10217 /********************  Bit definition for I2C_DR register  ********************/
10218 #define I2C_DR_DR_Pos             (0U)
10219 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
10220 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
10221 
10222 /*******************  Bit definition for I2C_SR1 register  ********************/
10223 #define I2C_SR1_SB_Pos            (0U)
10224 #define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
10225 #define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
10226 #define I2C_SR1_ADDR_Pos          (1U)
10227 #define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
10228 #define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
10229 #define I2C_SR1_BTF_Pos           (2U)
10230 #define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
10231 #define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
10232 #define I2C_SR1_ADD10_Pos         (3U)
10233 #define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
10234 #define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
10235 #define I2C_SR1_STOPF_Pos         (4U)
10236 #define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
10237 #define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
10238 #define I2C_SR1_RXNE_Pos          (6U)
10239 #define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
10240 #define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
10241 #define I2C_SR1_TXE_Pos           (7U)
10242 #define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
10243 #define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
10244 #define I2C_SR1_BERR_Pos          (8U)
10245 #define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
10246 #define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
10247 #define I2C_SR1_ARLO_Pos          (9U)
10248 #define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
10249 #define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
10250 #define I2C_SR1_AF_Pos            (10U)
10251 #define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
10252 #define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
10253 #define I2C_SR1_OVR_Pos           (11U)
10254 #define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
10255 #define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
10256 #define I2C_SR1_PECERR_Pos        (12U)
10257 #define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
10258 #define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
10259 #define I2C_SR1_TIMEOUT_Pos       (14U)
10260 #define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
10261 #define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
10262 #define I2C_SR1_SMBALERT_Pos      (15U)
10263 #define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
10264 #define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
10265 
10266 /*******************  Bit definition for I2C_SR2 register  ********************/
10267 #define I2C_SR2_MSL_Pos           (0U)
10268 #define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
10269 #define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
10270 #define I2C_SR2_BUSY_Pos          (1U)
10271 #define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
10272 #define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
10273 #define I2C_SR2_TRA_Pos           (2U)
10274 #define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
10275 #define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
10276 #define I2C_SR2_GENCALL_Pos       (4U)
10277 #define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
10278 #define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
10279 #define I2C_SR2_SMBDEFAULT_Pos    (5U)
10280 #define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
10281 #define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
10282 #define I2C_SR2_SMBHOST_Pos       (6U)
10283 #define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
10284 #define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
10285 #define I2C_SR2_DUALF_Pos         (7U)
10286 #define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
10287 #define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
10288 #define I2C_SR2_PEC_Pos           (8U)
10289 #define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
10290 #define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
10291 
10292 /*******************  Bit definition for I2C_CCR register  ********************/
10293 #define I2C_CCR_CCR_Pos           (0U)
10294 #define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
10295 #define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
10296 #define I2C_CCR_DUTY_Pos          (14U)
10297 #define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
10298 #define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
10299 #define I2C_CCR_FS_Pos            (15U)
10300 #define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
10301 #define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
10302 
10303 /******************  Bit definition for I2C_TRISE register  *******************/
10304 #define I2C_TRISE_TRISE_Pos       (0U)
10305 #define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
10306 #define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
10307 
10308 /******************  Bit definition for I2C_FLTR register  *******************/
10309 #define I2C_FLTR_DNF_Pos          (0U)
10310 #define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
10311 #define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
10312 #define I2C_FLTR_ANOFF_Pos        (4U)
10313 #define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
10314 #define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
10315 
10316 /******************************************************************************/
10317 /*                                                                            */
10318 /*                           Independent WATCHDOG                             */
10319 /*                                                                            */
10320 /******************************************************************************/
10321 /*******************  Bit definition for IWDG_KR register  ********************/
10322 #define IWDG_KR_KEY_Pos     (0U)
10323 #define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
10324 #define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
10325 
10326 /*******************  Bit definition for IWDG_PR register  ********************/
10327 #define IWDG_PR_PR_Pos      (0U)
10328 #define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
10329 #define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
10330 #define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
10331 #define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
10332 #define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
10333 
10334 /*******************  Bit definition for IWDG_RLR register  *******************/
10335 #define IWDG_RLR_RL_Pos     (0U)
10336 #define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
10337 #define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
10338 
10339 /*******************  Bit definition for IWDG_SR register  ********************/
10340 #define IWDG_SR_PVU_Pos     (0U)
10341 #define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
10342 #define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
10343 #define IWDG_SR_RVU_Pos     (1U)
10344 #define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
10345 #define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
10346 
10347 
10348 /******************************************************************************/
10349 /*                                                                            */
10350 /*                      LCD-TFT Display Controller (LTDC)                     */
10351 /*                                                                            */
10352 /******************************************************************************/
10353 
10354 /********************  Bit definition for LTDC_SSCR register  *****************/
10355 
10356 #define LTDC_SSCR_VSH_Pos            (0U)
10357 #define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */
10358 #define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height */
10359 #define LTDC_SSCR_HSW_Pos            (16U)
10360 #define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */
10361 #define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
10362 
10363 /********************  Bit definition for LTDC_BPCR register  *****************/
10364 
10365 #define LTDC_BPCR_AVBP_Pos           (0U)
10366 #define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */
10367 #define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch */
10368 #define LTDC_BPCR_AHBP_Pos           (16U)
10369 #define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */
10370 #define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
10371 
10372 /********************  Bit definition for LTDC_AWCR register  *****************/
10373 
10374 #define LTDC_AWCR_AAH_Pos            (0U)
10375 #define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */
10376 #define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */
10377 #define LTDC_AWCR_AAW_Pos            (16U)
10378 #define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */
10379 #define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
10380 
10381 /********************  Bit definition for LTDC_TWCR register  *****************/
10382 
10383 #define LTDC_TWCR_TOTALH_Pos         (0U)
10384 #define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */
10385 #define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
10386 #define LTDC_TWCR_TOTALW_Pos         (16U)
10387 #define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */
10388 #define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
10389 
10390 /********************  Bit definition for LTDC_GCR register  ******************/
10391 
10392 #define LTDC_GCR_LTDCEN_Pos          (0U)
10393 #define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */
10394 #define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit */
10395 #define LTDC_GCR_DBW_Pos             (4U)
10396 #define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */
10397 #define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width */
10398 #define LTDC_GCR_DGW_Pos             (8U)
10399 #define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */
10400 #define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width */
10401 #define LTDC_GCR_DRW_Pos             (12U)
10402 #define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */
10403 #define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width */
10404 #define LTDC_GCR_DEN_Pos             (16U)
10405 #define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */
10406 #define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable */
10407 #define LTDC_GCR_PCPOL_Pos           (28U)
10408 #define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */
10409 #define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity */
10410 #define LTDC_GCR_DEPOL_Pos           (29U)
10411 #define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */
10412 #define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity */
10413 #define LTDC_GCR_VSPOL_Pos           (30U)
10414 #define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */
10415 #define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity */
10416 #define LTDC_GCR_HSPOL_Pos           (31U)
10417 #define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */
10418 #define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
10419 
10420 /* Legacy defines */
10421 #define LTDC_GCR_DTEN                       LTDC_GCR_DEN
10422 
10423 /********************  Bit definition for LTDC_SRCR register  *****************/
10424 
10425 #define LTDC_SRCR_IMR_Pos            (0U)
10426 #define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */
10427 #define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload */
10428 #define LTDC_SRCR_VBR_Pos            (1U)
10429 #define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */
10430 #define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
10431 
10432 /********************  Bit definition for LTDC_BCCR register  *****************/
10433 
10434 #define LTDC_BCCR_BCBLUE_Pos         (0U)
10435 #define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */
10436 #define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value */
10437 #define LTDC_BCCR_BCGREEN_Pos        (8U)
10438 #define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */
10439 #define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
10440 #define LTDC_BCCR_BCRED_Pos          (16U)
10441 #define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */
10442 #define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value */
10443 
10444 /********************  Bit definition for LTDC_IER register  ******************/
10445 
10446 #define LTDC_IER_LIE_Pos             (0U)
10447 #define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */
10448 #define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable */
10449 #define LTDC_IER_FUIE_Pos            (1U)
10450 #define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */
10451 #define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable */
10452 #define LTDC_IER_TERRIE_Pos          (2U)
10453 #define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */
10454 #define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable */
10455 #define LTDC_IER_RRIE_Pos            (3U)
10456 #define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */
10457 #define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
10458 
10459 /********************  Bit definition for LTDC_ISR register  ******************/
10460 
10461 #define LTDC_ISR_LIF_Pos             (0U)
10462 #define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */
10463 #define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
10464 #define LTDC_ISR_FUIF_Pos            (1U)
10465 #define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */
10466 #define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
10467 #define LTDC_ISR_TERRIF_Pos          (2U)
10468 #define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */
10469 #define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
10470 #define LTDC_ISR_RRIF_Pos            (3U)
10471 #define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */
10472 #define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
10473 
10474 /********************  Bit definition for LTDC_ICR register  ******************/
10475 
10476 #define LTDC_ICR_CLIF_Pos            (0U)
10477 #define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */
10478 #define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
10479 #define LTDC_ICR_CFUIF_Pos           (1U)
10480 #define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */
10481 #define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
10482 #define LTDC_ICR_CTERRIF_Pos         (2U)
10483 #define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */
10484 #define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
10485 #define LTDC_ICR_CRRIF_Pos           (3U)
10486 #define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */
10487 #define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
10488 
10489 /********************  Bit definition for LTDC_LIPCR register  ****************/
10490 
10491 #define LTDC_LIPCR_LIPOS_Pos         (0U)
10492 #define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */
10493 #define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
10494 
10495 /********************  Bit definition for LTDC_CPSR register  *****************/
10496 
10497 #define LTDC_CPSR_CYPOS_Pos          (0U)
10498 #define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */
10499 #define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
10500 #define LTDC_CPSR_CXPOS_Pos          (16U)
10501 #define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */
10502 #define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
10503 
10504 /********************  Bit definition for LTDC_CDSR register  *****************/
10505 
10506 #define LTDC_CDSR_VDES_Pos           (0U)
10507 #define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */
10508 #define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status */
10509 #define LTDC_CDSR_HDES_Pos           (1U)
10510 #define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */
10511 #define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status */
10512 #define LTDC_CDSR_VSYNCS_Pos         (2U)
10513 #define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */
10514 #define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status */
10515 #define LTDC_CDSR_HSYNCS_Pos         (3U)
10516 #define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */
10517 #define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
10518 
10519 /********************  Bit definition for LTDC_LxCR register  *****************/
10520 
10521 #define LTDC_LxCR_LEN_Pos            (0U)
10522 #define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */
10523 #define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable */
10524 #define LTDC_LxCR_COLKEN_Pos         (1U)
10525 #define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */
10526 #define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable */
10527 #define LTDC_LxCR_CLUTEN_Pos         (4U)
10528 #define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */
10529 #define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
10530 
10531 /********************  Bit definition for LTDC_LxWHPCR register  **************/
10532 
10533 #define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
10534 #define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */
10535 #define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
10536 #define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
10537 #define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */
10538 #define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position */
10539 
10540 /********************  Bit definition for LTDC_LxWVPCR register  **************/
10541 
10542 #define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
10543 #define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */
10544 #define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
10545 #define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
10546 #define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */
10547 #define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position */
10548 
10549 /********************  Bit definition for LTDC_LxCKCR register  ***************/
10550 
10551 #define LTDC_LxCKCR_CKBLUE_Pos       (0U)
10552 #define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */
10553 #define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value */
10554 #define LTDC_LxCKCR_CKGREEN_Pos      (8U)
10555 #define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */
10556 #define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
10557 #define LTDC_LxCKCR_CKRED_Pos        (16U)
10558 #define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */
10559 #define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value */
10560 
10561 /********************  Bit definition for LTDC_LxPFCR register  ***************/
10562 
10563 #define LTDC_LxPFCR_PF_Pos           (0U)
10564 #define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */
10565 #define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
10566 
10567 /********************  Bit definition for LTDC_LxCACR register  ***************/
10568 
10569 #define LTDC_LxCACR_CONSTA_Pos       (0U)
10570 #define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */
10571 #define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
10572 
10573 /********************  Bit definition for LTDC_LxDCCR register  ***************/
10574 
10575 #define LTDC_LxDCCR_DCBLUE_Pos       (0U)
10576 #define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */
10577 #define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue */
10578 #define LTDC_LxDCCR_DCGREEN_Pos      (8U)
10579 #define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */
10580 #define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
10581 #define LTDC_LxDCCR_DCRED_Pos        (16U)
10582 #define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */
10583 #define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red */
10584 #define LTDC_LxDCCR_DCALPHA_Pos      (24U)
10585 #define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */
10586 #define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
10587 
10588 /********************  Bit definition for LTDC_LxBFCR register  ***************/
10589 
10590 #define LTDC_LxBFCR_BF2_Pos          (0U)
10591 #define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */
10592 #define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
10593 #define LTDC_LxBFCR_BF1_Pos          (8U)
10594 #define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */
10595 #define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
10596 
10597 /********************  Bit definition for LTDC_LxCFBAR register  **************/
10598 
10599 #define LTDC_LxCFBAR_CFBADD_Pos      (0U)
10600 #define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */
10601 #define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
10602 
10603 /********************  Bit definition for LTDC_LxCFBLR register  **************/
10604 
10605 #define LTDC_LxCFBLR_CFBLL_Pos       (0U)
10606 #define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */
10607 #define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length */
10608 #define LTDC_LxCFBLR_CFBP_Pos        (16U)
10609 #define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */
10610 #define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
10611 
10612 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
10613 
10614 #define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
10615 #define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */
10616 #define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
10617 
10618 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
10619 
10620 #define LTDC_LxCLUTWR_BLUE_Pos       (0U)
10621 #define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */
10622 #define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value */
10623 #define LTDC_LxCLUTWR_GREEN_Pos      (8U)
10624 #define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */
10625 #define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value */
10626 #define LTDC_LxCLUTWR_RED_Pos        (16U)
10627 #define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */
10628 #define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value */
10629 #define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
10630 #define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */
10631 #define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
10632 
10633 
10634 /******************************************************************************/
10635 /*                                                                            */
10636 /*                             Power Control                                  */
10637 /*                                                                            */
10638 /******************************************************************************/
10639 /********************  Bit definition for PWR_CR register  ********************/
10640 #define PWR_CR_LPDS_Pos        (0U)
10641 #define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
10642 #define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
10643 #define PWR_CR_PDDS_Pos        (1U)
10644 #define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
10645 #define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
10646 #define PWR_CR_CWUF_Pos        (2U)
10647 #define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
10648 #define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
10649 #define PWR_CR_CSBF_Pos        (3U)
10650 #define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
10651 #define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
10652 #define PWR_CR_PVDE_Pos        (4U)
10653 #define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
10654 #define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
10655 
10656 #define PWR_CR_PLS_Pos         (5U)
10657 #define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
10658 #define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
10659 #define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
10660 #define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
10661 #define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
10662 
10663 /*!< PVD level configuration */
10664 #define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
10665 #define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
10666 #define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
10667 #define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
10668 #define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
10669 #define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
10670 #define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
10671 #define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
10672 #define PWR_CR_DBP_Pos         (8U)
10673 #define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
10674 #define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
10675 #define PWR_CR_FPDS_Pos        (9U)
10676 #define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
10677 #define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
10678 #define PWR_CR_LPLVDS_Pos      (10U)
10679 #define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
10680 #define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
10681 #define PWR_CR_MRLVDS_Pos      (11U)
10682 #define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
10683 #define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */
10684 #define PWR_CR_ADCDC1_Pos      (13U)
10685 #define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
10686 #define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */
10687 #define PWR_CR_VOS_Pos         (14U)
10688 #define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
10689 #define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10690 #define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
10691 #define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
10692 #define PWR_CR_ODEN_Pos        (16U)
10693 #define PWR_CR_ODEN_Msk        (0x1UL << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */
10694 #define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */
10695 #define PWR_CR_ODSWEN_Pos      (17U)
10696 #define PWR_CR_ODSWEN_Msk      (0x1UL << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */
10697 #define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */
10698 #define PWR_CR_UDEN_Pos        (18U)
10699 #define PWR_CR_UDEN_Msk        (0x3UL << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */
10700 #define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */
10701 #define PWR_CR_UDEN_0          (0x1UL << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */
10702 #define PWR_CR_UDEN_1          (0x2UL << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */
10703 
10704 /* Legacy define */
10705 #define  PWR_CR_PMODE                        PWR_CR_VOS
10706 #define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
10707 #define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
10708 
10709 /*******************  Bit definition for PWR_CSR register  ********************/
10710 #define PWR_CSR_WUF_Pos        (0U)
10711 #define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
10712 #define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
10713 #define PWR_CSR_SBF_Pos        (1U)
10714 #define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
10715 #define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
10716 #define PWR_CSR_PVDO_Pos       (2U)
10717 #define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
10718 #define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
10719 #define PWR_CSR_BRR_Pos        (3U)
10720 #define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
10721 #define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
10722 #define PWR_CSR_EWUP_Pos       (8U)
10723 #define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
10724 #define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
10725 #define PWR_CSR_BRE_Pos        (9U)
10726 #define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
10727 #define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
10728 #define PWR_CSR_VOSRDY_Pos     (14U)
10729 #define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
10730 #define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
10731 #define PWR_CSR_ODRDY_Pos      (16U)
10732 #define PWR_CSR_ODRDY_Msk      (0x1UL << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */
10733 #define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */
10734 #define PWR_CSR_ODSWRDY_Pos    (17U)
10735 #define PWR_CSR_ODSWRDY_Msk    (0x1UL << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */
10736 #define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */
10737 #define PWR_CSR_UDRDY_Pos      (18U)
10738 #define PWR_CSR_UDRDY_Msk      (0x3UL << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */
10739 #define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */
10740 /* Legacy define */
10741 #define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY
10742 
10743 /* Legacy define */
10744 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
10745 
10746 /******************************************************************************/
10747 /*                                                                            */
10748 /*                         Reset and Clock Control                            */
10749 /*                                                                            */
10750 /******************************************************************************/
10751 /********************  Bit definition for RCC_CR register  ********************/
10752 #define RCC_CR_HSION_Pos                   (0U)
10753 #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
10754 #define RCC_CR_HSION                       RCC_CR_HSION_Msk
10755 #define RCC_CR_HSIRDY_Pos                  (1U)
10756 #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
10757 #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
10758 
10759 #define RCC_CR_HSITRIM_Pos                 (3U)
10760 #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
10761 #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
10762 #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
10763 #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
10764 #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
10765 #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
10766 #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
10767 
10768 #define RCC_CR_HSICAL_Pos                  (8U)
10769 #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
10770 #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
10771 #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
10772 #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
10773 #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
10774 #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
10775 #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
10776 #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
10777 #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
10778 #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
10779 
10780 #define RCC_CR_HSEON_Pos                   (16U)
10781 #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
10782 #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
10783 #define RCC_CR_HSERDY_Pos                  (17U)
10784 #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
10785 #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
10786 #define RCC_CR_HSEBYP_Pos                  (18U)
10787 #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
10788 #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
10789 #define RCC_CR_CSSON_Pos                   (19U)
10790 #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
10791 #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
10792 #define RCC_CR_PLLON_Pos                   (24U)
10793 #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
10794 #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
10795 #define RCC_CR_PLLRDY_Pos                  (25U)
10796 #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
10797 #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
10798 /*
10799  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10800  */
10801 #define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
10802 
10803 #define RCC_CR_PLLI2SON_Pos                (26U)
10804 #define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
10805 #define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk
10806 #define RCC_CR_PLLI2SRDY_Pos               (27U)
10807 #define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
10808 #define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk
10809 /*
10810  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10811  */
10812 #define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */
10813 
10814 #define RCC_CR_PLLSAION_Pos                (28U)
10815 #define RCC_CR_PLLSAION_Msk                (0x1UL << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */
10816 #define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk
10817 #define RCC_CR_PLLSAIRDY_Pos               (29U)
10818 #define RCC_CR_PLLSAIRDY_Msk               (0x1UL << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */
10819 #define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk
10820 
10821 /********************  Bit definition for RCC_PLLCFGR register  ***************/
10822 #define RCC_PLLCFGR_PLLM_Pos               (0U)
10823 #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
10824 #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
10825 #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
10826 #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
10827 #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
10828 #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
10829 #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
10830 #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
10831 
10832 #define RCC_PLLCFGR_PLLN_Pos               (6U)
10833 #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
10834 #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
10835 #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
10836 #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
10837 #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
10838 #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
10839 #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
10840 #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
10841 #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
10842 #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
10843 #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
10844 
10845 #define RCC_PLLCFGR_PLLP_Pos               (16U)
10846 #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
10847 #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
10848 #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
10849 #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
10850 
10851 #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
10852 #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
10853 #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
10854 #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
10855 #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10856 #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
10857 #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
10858 
10859 #define RCC_PLLCFGR_PLLQ_Pos               (24U)
10860 #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
10861 #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
10862 #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
10863 #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
10864 #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
10865 #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
10866 
10867 
10868 /********************  Bit definition for RCC_CFGR register  ******************/
10869 /*!< SW configuration */
10870 #define RCC_CFGR_SW_Pos                    (0U)
10871 #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
10872 #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
10873 #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
10874 #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
10875 
10876 #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
10877 #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
10878 #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
10879 
10880 /*!< SWS configuration */
10881 #define RCC_CFGR_SWS_Pos                   (2U)
10882 #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
10883 #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
10884 #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
10885 #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
10886 
10887 #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
10888 #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
10889 #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
10890 
10891 /*!< HPRE configuration */
10892 #define RCC_CFGR_HPRE_Pos                  (4U)
10893 #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
10894 #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
10895 #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
10896 #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
10897 #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
10898 #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
10899 
10900 #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
10901 #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
10902 #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
10903 #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
10904 #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
10905 #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
10906 #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
10907 #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
10908 #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
10909 
10910 /*!< PPRE1 configuration */
10911 #define RCC_CFGR_PPRE1_Pos                 (10U)
10912 #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
10913 #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
10914 #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
10915 #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
10916 #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
10917 
10918 #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
10919 #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
10920 #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
10921 #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
10922 #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
10923 
10924 /*!< PPRE2 configuration */
10925 #define RCC_CFGR_PPRE2_Pos                 (13U)
10926 #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
10927 #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
10928 #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
10929 #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
10930 #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
10931 
10932 #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
10933 #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
10934 #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
10935 #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
10936 #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
10937 
10938 /*!< RTCPRE configuration */
10939 #define RCC_CFGR_RTCPRE_Pos                (16U)
10940 #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
10941 #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
10942 #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
10943 #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
10944 #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
10945 #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
10946 #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
10947 
10948 /*!< MCO1 configuration */
10949 #define RCC_CFGR_MCO1_Pos                  (21U)
10950 #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
10951 #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
10952 #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
10953 #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
10954 
10955 #define RCC_CFGR_I2SSRC_Pos                (23U)
10956 #define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
10957 #define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk
10958 
10959 #define RCC_CFGR_MCO1PRE_Pos               (24U)
10960 #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
10961 #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
10962 #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
10963 #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
10964 #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
10965 
10966 #define RCC_CFGR_MCO2PRE_Pos               (27U)
10967 #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
10968 #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
10969 #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
10970 #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
10971 #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
10972 
10973 #define RCC_CFGR_MCO2_Pos                  (30U)
10974 #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
10975 #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
10976 #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
10977 #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
10978 
10979 /********************  Bit definition for RCC_CIR register  *******************/
10980 #define RCC_CIR_LSIRDYF_Pos                (0U)
10981 #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
10982 #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
10983 #define RCC_CIR_LSERDYF_Pos                (1U)
10984 #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
10985 #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
10986 #define RCC_CIR_HSIRDYF_Pos                (2U)
10987 #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
10988 #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
10989 #define RCC_CIR_HSERDYF_Pos                (3U)
10990 #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
10991 #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
10992 #define RCC_CIR_PLLRDYF_Pos                (4U)
10993 #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
10994 #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
10995 #define RCC_CIR_PLLI2SRDYF_Pos             (5U)
10996 #define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
10997 #define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk
10998 
10999 #define RCC_CIR_PLLSAIRDYF_Pos             (6U)
11000 #define RCC_CIR_PLLSAIRDYF_Msk             (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */
11001 #define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk
11002 #define RCC_CIR_CSSF_Pos                   (7U)
11003 #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
11004 #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
11005 #define RCC_CIR_LSIRDYIE_Pos               (8U)
11006 #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
11007 #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
11008 #define RCC_CIR_LSERDYIE_Pos               (9U)
11009 #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
11010 #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
11011 #define RCC_CIR_HSIRDYIE_Pos               (10U)
11012 #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
11013 #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
11014 #define RCC_CIR_HSERDYIE_Pos               (11U)
11015 #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
11016 #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
11017 #define RCC_CIR_PLLRDYIE_Pos               (12U)
11018 #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
11019 #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
11020 #define RCC_CIR_PLLI2SRDYIE_Pos            (13U)
11021 #define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
11022 #define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk
11023 
11024 #define RCC_CIR_PLLSAIRDYIE_Pos            (14U)
11025 #define RCC_CIR_PLLSAIRDYIE_Msk            (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */
11026 #define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk
11027 #define RCC_CIR_LSIRDYC_Pos                (16U)
11028 #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
11029 #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
11030 #define RCC_CIR_LSERDYC_Pos                (17U)
11031 #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
11032 #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
11033 #define RCC_CIR_HSIRDYC_Pos                (18U)
11034 #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
11035 #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
11036 #define RCC_CIR_HSERDYC_Pos                (19U)
11037 #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
11038 #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
11039 #define RCC_CIR_PLLRDYC_Pos                (20U)
11040 #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
11041 #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
11042 #define RCC_CIR_PLLI2SRDYC_Pos             (21U)
11043 #define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
11044 #define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk
11045 #define RCC_CIR_PLLSAIRDYC_Pos             (22U)
11046 #define RCC_CIR_PLLSAIRDYC_Msk             (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */
11047 #define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk
11048 
11049 #define RCC_CIR_CSSC_Pos                   (23U)
11050 #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
11051 #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
11052 
11053 /********************  Bit definition for RCC_AHB1RSTR register  **************/
11054 #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
11055 #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
11056 #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
11057 #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
11058 #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
11059 #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
11060 #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
11061 #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
11062 #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
11063 #define RCC_AHB1RSTR_GPIODRST_Pos          (3U)
11064 #define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
11065 #define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk
11066 #define RCC_AHB1RSTR_GPIOERST_Pos          (4U)
11067 #define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
11068 #define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk
11069 #define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)
11070 #define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
11071 #define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk
11072 #define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)
11073 #define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
11074 #define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk
11075 #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
11076 #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
11077 #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
11078 #define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)
11079 #define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
11080 #define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk
11081 #define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)
11082 #define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
11083 #define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk
11084 #define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)
11085 #define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
11086 #define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk
11087 #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
11088 #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
11089 #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
11090 #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
11091 #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
11092 #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
11093 #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
11094 #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
11095 #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
11096 #define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)
11097 #define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
11098 #define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk
11099 #define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)
11100 #define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
11101 #define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk
11102 #define RCC_AHB1RSTR_OTGHRST_Pos           (29U)
11103 #define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
11104 #define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk
11105 
11106 /********************  Bit definition for RCC_AHB2RSTR register  **************/
11107 #define RCC_AHB2RSTR_DCMIRST_Pos           (0U)
11108 #define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
11109 #define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk
11110 #define RCC_AHB2RSTR_CRYPRST_Pos           (4U)
11111 #define RCC_AHB2RSTR_CRYPRST_Msk           (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)  /*!< 0x00000010 */
11112 #define RCC_AHB2RSTR_CRYPRST               RCC_AHB2RSTR_CRYPRST_Msk
11113 #define RCC_AHB2RSTR_HASHRST_Pos           (5U)
11114 #define RCC_AHB2RSTR_HASHRST_Msk           (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)  /*!< 0x00000020 */
11115 #define RCC_AHB2RSTR_HASHRST               RCC_AHB2RSTR_HASHRST_Msk
11116  /* maintained for legacy purpose */
11117 #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
11118 #define RCC_AHB2RSTR_RNGRST_Pos            (6U)
11119 #define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
11120 #define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk
11121 #define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)
11122 #define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
11123 #define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk
11124 /********************  Bit definition for RCC_AHB3RSTR register  **************/
11125 #define RCC_AHB3RSTR_FMCRST_Pos            (0U)
11126 #define RCC_AHB3RSTR_FMCRST_Msk            (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */
11127 #define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk
11128 
11129 
11130 /********************  Bit definition for RCC_APB1RSTR register  **************/
11131 #define RCC_APB1RSTR_TIM2RST_Pos           (0U)
11132 #define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
11133 #define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk
11134 #define RCC_APB1RSTR_TIM3RST_Pos           (1U)
11135 #define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
11136 #define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk
11137 #define RCC_APB1RSTR_TIM4RST_Pos           (2U)
11138 #define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
11139 #define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk
11140 #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
11141 #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
11142 #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
11143 #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
11144 #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
11145 #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
11146 #define RCC_APB1RSTR_TIM7RST_Pos           (5U)
11147 #define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
11148 #define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk
11149 #define RCC_APB1RSTR_TIM12RST_Pos          (6U)
11150 #define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
11151 #define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk
11152 #define RCC_APB1RSTR_TIM13RST_Pos          (7U)
11153 #define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
11154 #define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk
11155 #define RCC_APB1RSTR_TIM14RST_Pos          (8U)
11156 #define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
11157 #define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk
11158 #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
11159 #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
11160 #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
11161 #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
11162 #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
11163 #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
11164 #define RCC_APB1RSTR_SPI3RST_Pos           (15U)
11165 #define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
11166 #define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk
11167 #define RCC_APB1RSTR_USART2RST_Pos         (17U)
11168 #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
11169 #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
11170 #define RCC_APB1RSTR_USART3RST_Pos         (18U)
11171 #define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
11172 #define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk
11173 #define RCC_APB1RSTR_UART4RST_Pos          (19U)
11174 #define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
11175 #define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk
11176 #define RCC_APB1RSTR_UART5RST_Pos          (20U)
11177 #define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
11178 #define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk
11179 #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
11180 #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
11181 #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
11182 #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
11183 #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
11184 #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
11185 #define RCC_APB1RSTR_I2C3RST_Pos           (23U)
11186 #define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
11187 #define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk
11188 #define RCC_APB1RSTR_CAN1RST_Pos           (25U)
11189 #define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
11190 #define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk
11191 #define RCC_APB1RSTR_CAN2RST_Pos           (26U)
11192 #define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
11193 #define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk
11194 #define RCC_APB1RSTR_PWRRST_Pos            (28U)
11195 #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
11196 #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
11197 #define RCC_APB1RSTR_DACRST_Pos            (29U)
11198 #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
11199 #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
11200 #define RCC_APB1RSTR_UART7RST_Pos          (30U)
11201 #define RCC_APB1RSTR_UART7RST_Msk          (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
11202 #define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk
11203 #define RCC_APB1RSTR_UART8RST_Pos          (31U)
11204 #define RCC_APB1RSTR_UART8RST_Msk          (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
11205 #define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk
11206 
11207 /********************  Bit definition for RCC_APB2RSTR register  **************/
11208 #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
11209 #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
11210 #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
11211 #define RCC_APB2RSTR_TIM8RST_Pos           (1U)
11212 #define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
11213 #define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk
11214 #define RCC_APB2RSTR_USART1RST_Pos         (4U)
11215 #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
11216 #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
11217 #define RCC_APB2RSTR_USART6RST_Pos         (5U)
11218 #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
11219 #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
11220 #define RCC_APB2RSTR_ADCRST_Pos            (8U)
11221 #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
11222 #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
11223 #define RCC_APB2RSTR_SDIORST_Pos           (11U)
11224 #define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
11225 #define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk
11226 #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
11227 #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
11228 #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
11229 #define RCC_APB2RSTR_SPI4RST_Pos           (13U)
11230 #define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
11231 #define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk
11232 #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
11233 #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
11234 #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
11235 #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
11236 #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
11237 #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
11238 #define RCC_APB2RSTR_TIM10RST_Pos          (17U)
11239 #define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
11240 #define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk
11241 #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
11242 #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
11243 #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
11244 #define RCC_APB2RSTR_SPI5RST_Pos           (20U)
11245 #define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
11246 #define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk
11247 #define RCC_APB2RSTR_SPI6RST_Pos           (21U)
11248 #define RCC_APB2RSTR_SPI6RST_Msk           (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */
11249 #define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk
11250 #define RCC_APB2RSTR_SAI1RST_Pos           (22U)
11251 #define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
11252 #define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk
11253 #define RCC_APB2RSTR_LTDCRST_Pos           (26U)
11254 #define RCC_APB2RSTR_LTDCRST_Msk           (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)  /*!< 0x04000000 */
11255 #define RCC_APB2RSTR_LTDCRST               RCC_APB2RSTR_LTDCRST_Msk
11256 
11257 /* Old SPI1RST bit definition, maintained for legacy purpose */
11258 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
11259 
11260 /********************  Bit definition for RCC_AHB1ENR register  ***************/
11261 #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
11262 #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
11263 #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
11264 #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
11265 #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
11266 #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
11267 #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
11268 #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
11269 #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
11270 #define RCC_AHB1ENR_GPIODEN_Pos            (3U)
11271 #define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
11272 #define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk
11273 #define RCC_AHB1ENR_GPIOEEN_Pos            (4U)
11274 #define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
11275 #define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk
11276 #define RCC_AHB1ENR_GPIOFEN_Pos            (5U)
11277 #define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
11278 #define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk
11279 #define RCC_AHB1ENR_GPIOGEN_Pos            (6U)
11280 #define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
11281 #define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk
11282 #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
11283 #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
11284 #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
11285 #define RCC_AHB1ENR_GPIOIEN_Pos            (8U)
11286 #define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
11287 #define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk
11288 #define RCC_AHB1ENR_GPIOJEN_Pos            (9U)
11289 #define RCC_AHB1ENR_GPIOJEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */
11290 #define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk
11291 #define RCC_AHB1ENR_GPIOKEN_Pos            (10U)
11292 #define RCC_AHB1ENR_GPIOKEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */
11293 #define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk
11294 #define RCC_AHB1ENR_CRCEN_Pos              (12U)
11295 #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
11296 #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
11297 #define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)
11298 #define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
11299 #define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk
11300 #define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)
11301 #define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
11302 #define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk
11303 #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
11304 #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
11305 #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
11306 #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
11307 #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
11308 #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
11309 #define RCC_AHB1ENR_DMA2DEN_Pos            (23U)
11310 #define RCC_AHB1ENR_DMA2DEN_Msk            (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */
11311 #define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk
11312 #define RCC_AHB1ENR_ETHMACEN_Pos           (25U)
11313 #define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
11314 #define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk
11315 #define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)
11316 #define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
11317 #define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk
11318 #define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)
11319 #define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
11320 #define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk
11321 #define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)
11322 #define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
11323 #define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk
11324 #define RCC_AHB1ENR_OTGHSEN_Pos            (29U)
11325 #define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
11326 #define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk
11327 #define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)
11328 #define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
11329 #define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk
11330 /********************  Bit definition for RCC_AHB2ENR register  ***************/
11331 /*
11332  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11333  */
11334 #define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
11335 
11336 #define RCC_AHB2ENR_DCMIEN_Pos             (0U)
11337 #define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
11338 #define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk
11339 #define RCC_AHB2ENR_CRYPEN_Pos             (4U)
11340 #define RCC_AHB2ENR_CRYPEN_Msk             (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)    /*!< 0x00000010 */
11341 #define RCC_AHB2ENR_CRYPEN                 RCC_AHB2ENR_CRYPEN_Msk
11342 #define RCC_AHB2ENR_HASHEN_Pos             (5U)
11343 #define RCC_AHB2ENR_HASHEN_Msk             (0x1UL << RCC_AHB2ENR_HASHEN_Pos)    /*!< 0x00000020 */
11344 #define RCC_AHB2ENR_HASHEN                 RCC_AHB2ENR_HASHEN_Msk
11345 #define RCC_AHB2ENR_RNGEN_Pos              (6U)
11346 #define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
11347 #define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk
11348 #define RCC_AHB2ENR_OTGFSEN_Pos            (7U)
11349 #define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
11350 #define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk
11351 
11352 /********************  Bit definition for RCC_AHB3ENR register  ***************/
11353 /*
11354  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11355  */
11356 #define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
11357 
11358 #define RCC_AHB3ENR_FMCEN_Pos              (0U)
11359 #define RCC_AHB3ENR_FMCEN_Msk              (0x1UL << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */
11360 #define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk
11361 
11362 /********************  Bit definition for RCC_APB1ENR register  ***************/
11363 #define RCC_APB1ENR_TIM2EN_Pos             (0U)
11364 #define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
11365 #define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk
11366 #define RCC_APB1ENR_TIM3EN_Pos             (1U)
11367 #define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
11368 #define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk
11369 #define RCC_APB1ENR_TIM4EN_Pos             (2U)
11370 #define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
11371 #define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk
11372 #define RCC_APB1ENR_TIM5EN_Pos             (3U)
11373 #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
11374 #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
11375 #define RCC_APB1ENR_TIM6EN_Pos             (4U)
11376 #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
11377 #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
11378 #define RCC_APB1ENR_TIM7EN_Pos             (5U)
11379 #define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
11380 #define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk
11381 #define RCC_APB1ENR_TIM12EN_Pos            (6U)
11382 #define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
11383 #define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk
11384 #define RCC_APB1ENR_TIM13EN_Pos            (7U)
11385 #define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
11386 #define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk
11387 #define RCC_APB1ENR_TIM14EN_Pos            (8U)
11388 #define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
11389 #define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk
11390 #define RCC_APB1ENR_WWDGEN_Pos             (11U)
11391 #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
11392 #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
11393 #define RCC_APB1ENR_SPI2EN_Pos             (14U)
11394 #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
11395 #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
11396 #define RCC_APB1ENR_SPI3EN_Pos             (15U)
11397 #define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
11398 #define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk
11399 #define RCC_APB1ENR_USART2EN_Pos           (17U)
11400 #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
11401 #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
11402 #define RCC_APB1ENR_USART3EN_Pos           (18U)
11403 #define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
11404 #define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk
11405 #define RCC_APB1ENR_UART4EN_Pos            (19U)
11406 #define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
11407 #define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk
11408 #define RCC_APB1ENR_UART5EN_Pos            (20U)
11409 #define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
11410 #define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk
11411 #define RCC_APB1ENR_I2C1EN_Pos             (21U)
11412 #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
11413 #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
11414 #define RCC_APB1ENR_I2C2EN_Pos             (22U)
11415 #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
11416 #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
11417 #define RCC_APB1ENR_I2C3EN_Pos             (23U)
11418 #define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
11419 #define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk
11420 #define RCC_APB1ENR_CAN1EN_Pos             (25U)
11421 #define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
11422 #define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk
11423 #define RCC_APB1ENR_CAN2EN_Pos             (26U)
11424 #define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
11425 #define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk
11426 #define RCC_APB1ENR_PWREN_Pos              (28U)
11427 #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
11428 #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
11429 #define RCC_APB1ENR_DACEN_Pos              (29U)
11430 #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
11431 #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
11432 #define RCC_APB1ENR_UART7EN_Pos            (30U)
11433 #define RCC_APB1ENR_UART7EN_Msk            (0x1UL << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */
11434 #define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk
11435 #define RCC_APB1ENR_UART8EN_Pos            (31U)
11436 #define RCC_APB1ENR_UART8EN_Msk            (0x1UL << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */
11437 #define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk
11438 
11439 /********************  Bit definition for RCC_APB2ENR register  ***************/
11440 #define RCC_APB2ENR_TIM1EN_Pos             (0U)
11441 #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
11442 #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
11443 #define RCC_APB2ENR_TIM8EN_Pos             (1U)
11444 #define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
11445 #define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk
11446 #define RCC_APB2ENR_USART1EN_Pos           (4U)
11447 #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
11448 #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
11449 #define RCC_APB2ENR_USART6EN_Pos           (5U)
11450 #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
11451 #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
11452 #define RCC_APB2ENR_ADC1EN_Pos             (8U)
11453 #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
11454 #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
11455 #define RCC_APB2ENR_ADC2EN_Pos             (9U)
11456 #define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
11457 #define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk
11458 #define RCC_APB2ENR_ADC3EN_Pos             (10U)
11459 #define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
11460 #define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk
11461 #define RCC_APB2ENR_SDIOEN_Pos             (11U)
11462 #define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
11463 #define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk
11464 #define RCC_APB2ENR_SPI1EN_Pos             (12U)
11465 #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
11466 #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
11467 #define RCC_APB2ENR_SPI4EN_Pos             (13U)
11468 #define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
11469 #define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk
11470 #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
11471 #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
11472 #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
11473 #define RCC_APB2ENR_TIM9EN_Pos             (16U)
11474 #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
11475 #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
11476 #define RCC_APB2ENR_TIM10EN_Pos            (17U)
11477 #define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
11478 #define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk
11479 #define RCC_APB2ENR_TIM11EN_Pos            (18U)
11480 #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
11481 #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
11482 #define RCC_APB2ENR_SPI5EN_Pos             (20U)
11483 #define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
11484 #define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk
11485 #define RCC_APB2ENR_SPI6EN_Pos             (21U)
11486 #define RCC_APB2ENR_SPI6EN_Msk             (0x1UL << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */
11487 #define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk
11488 #define RCC_APB2ENR_SAI1EN_Pos             (22U)
11489 #define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
11490 #define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk
11491 #define RCC_APB2ENR_LTDCEN_Pos             (26U)
11492 #define RCC_APB2ENR_LTDCEN_Msk             (0x1UL << RCC_APB2ENR_LTDCEN_Pos)    /*!< 0x04000000 */
11493 #define RCC_APB2ENR_LTDCEN                 RCC_APB2ENR_LTDCEN_Msk
11494 
11495 /********************  Bit definition for RCC_AHB1LPENR register  *************/
11496 #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
11497 #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
11498 #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
11499 #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
11500 #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
11501 #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
11502 #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
11503 #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
11504 #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
11505 #define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)
11506 #define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
11507 #define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk
11508 #define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)
11509 #define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
11510 #define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk
11511 #define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)
11512 #define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
11513 #define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk
11514 #define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)
11515 #define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
11516 #define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk
11517 #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
11518 #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
11519 #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
11520 #define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)
11521 #define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
11522 #define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk
11523 #define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)
11524 #define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
11525 #define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk
11526 #define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)
11527 #define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
11528 #define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk
11529 #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
11530 #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
11531 #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
11532 #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
11533 #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
11534 #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
11535 #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
11536 #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
11537 #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
11538 #define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)
11539 #define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
11540 #define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk
11541 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)
11542 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
11543 #define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11544 #define RCC_AHB1LPENR_SRAM3LPEN_Pos        (19U)
11545 #define RCC_AHB1LPENR_SRAM3LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
11546 #define RCC_AHB1LPENR_SRAM3LPEN            RCC_AHB1LPENR_SRAM3LPEN_Msk
11547 #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
11548 #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
11549 #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
11550 #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
11551 #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
11552 #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
11553 #define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)
11554 #define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
11555 #define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk
11556 
11557 #define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)
11558 #define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
11559 #define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk
11560 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)
11561 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
11562 #define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11563 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)
11564 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
11565 #define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11566 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)
11567 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
11568 #define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11569 #define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)
11570 #define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
11571 #define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk
11572 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)
11573 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
11574 #define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11575 
11576 /********************  Bit definition for RCC_AHB2LPENR register  *************/
11577 #define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)
11578 #define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
11579 #define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk
11580 #define RCC_AHB2LPENR_CRYPLPEN_Pos         (4U)
11581 #define RCC_AHB2LPENR_CRYPLPEN_Msk         (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
11582 #define RCC_AHB2LPENR_CRYPLPEN             RCC_AHB2LPENR_CRYPLPEN_Msk
11583 #define RCC_AHB2LPENR_HASHLPEN_Pos         (5U)
11584 #define RCC_AHB2LPENR_HASHLPEN_Msk         (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
11585 #define RCC_AHB2LPENR_HASHLPEN             RCC_AHB2LPENR_HASHLPEN_Msk
11586 #define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)
11587 #define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
11588 #define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk
11589 #define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)
11590 #define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
11591 #define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk
11592 
11593 /********************  Bit definition for RCC_AHB3LPENR register  *************/
11594 #define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)
11595 #define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
11596 #define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk
11597 
11598 /********************  Bit definition for RCC_APB1LPENR register  *************/
11599 #define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)
11600 #define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
11601 #define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk
11602 #define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)
11603 #define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
11604 #define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk
11605 #define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)
11606 #define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
11607 #define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk
11608 #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
11609 #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
11610 #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
11611 #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
11612 #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
11613 #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
11614 #define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)
11615 #define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
11616 #define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk
11617 #define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)
11618 #define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
11619 #define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk
11620 #define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)
11621 #define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
11622 #define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk
11623 #define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)
11624 #define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
11625 #define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk
11626 #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
11627 #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
11628 #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
11629 #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
11630 #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
11631 #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
11632 #define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)
11633 #define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
11634 #define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk
11635 #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
11636 #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
11637 #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
11638 #define RCC_APB1LPENR_USART3LPEN_Pos       (18U)
11639 #define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
11640 #define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk
11641 #define RCC_APB1LPENR_UART4LPEN_Pos        (19U)
11642 #define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
11643 #define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk
11644 #define RCC_APB1LPENR_UART5LPEN_Pos        (20U)
11645 #define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
11646 #define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk
11647 #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
11648 #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
11649 #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
11650 #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
11651 #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
11652 #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
11653 #define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)
11654 #define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
11655 #define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk
11656 #define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)
11657 #define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
11658 #define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk
11659 #define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)
11660 #define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
11661 #define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk
11662 #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
11663 #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
11664 #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
11665 #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
11666 #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
11667 #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
11668 #define RCC_APB1LPENR_UART7LPEN_Pos        (30U)
11669 #define RCC_APB1LPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
11670 #define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk
11671 #define RCC_APB1LPENR_UART8LPEN_Pos        (31U)
11672 #define RCC_APB1LPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
11673 #define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk
11674 
11675 /********************  Bit definition for RCC_APB2LPENR register  *************/
11676 #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
11677 #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
11678 #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
11679 #define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)
11680 #define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
11681 #define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk
11682 #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
11683 #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
11684 #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
11685 #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
11686 #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
11687 #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
11688 #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
11689 #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
11690 #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
11691 #define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)
11692 #define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
11693 #define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk
11694 #define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)
11695 #define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
11696 #define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk
11697 #define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)
11698 #define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
11699 #define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk
11700 #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
11701 #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
11702 #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
11703 #define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)
11704 #define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
11705 #define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk
11706 #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
11707 #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
11708 #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
11709 #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
11710 #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
11711 #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
11712 #define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)
11713 #define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
11714 #define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk
11715 #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
11716 #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
11717 #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
11718 #define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)
11719 #define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
11720 #define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk
11721 #define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)
11722 #define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
11723 #define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk
11724 #define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)
11725 #define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
11726 #define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk
11727 #define RCC_APB2LPENR_LTDCLPEN_Pos         (26U)
11728 #define RCC_APB2LPENR_LTDCLPEN_Msk         (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
11729 #define RCC_APB2LPENR_LTDCLPEN             RCC_APB2LPENR_LTDCLPEN_Msk
11730 
11731 /********************  Bit definition for RCC_BDCR register  ******************/
11732 #define RCC_BDCR_LSEON_Pos                 (0U)
11733 #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
11734 #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
11735 #define RCC_BDCR_LSERDY_Pos                (1U)
11736 #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
11737 #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
11738 #define RCC_BDCR_LSEBYP_Pos                (2U)
11739 #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
11740 #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
11741 
11742 #define RCC_BDCR_RTCSEL_Pos                (8U)
11743 #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
11744 #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
11745 #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
11746 #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
11747 
11748 #define RCC_BDCR_RTCEN_Pos                 (15U)
11749 #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
11750 #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
11751 #define RCC_BDCR_BDRST_Pos                 (16U)
11752 #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
11753 #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
11754 
11755 /********************  Bit definition for RCC_CSR register  *******************/
11756 #define RCC_CSR_LSION_Pos                  (0U)
11757 #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
11758 #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
11759 #define RCC_CSR_LSIRDY_Pos                 (1U)
11760 #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
11761 #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
11762 #define RCC_CSR_RMVF_Pos                   (24U)
11763 #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
11764 #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
11765 #define RCC_CSR_BORRSTF_Pos                (25U)
11766 #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
11767 #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
11768 #define RCC_CSR_PINRSTF_Pos                (26U)
11769 #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
11770 #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
11771 #define RCC_CSR_PORRSTF_Pos                (27U)
11772 #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
11773 #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
11774 #define RCC_CSR_SFTRSTF_Pos                (28U)
11775 #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
11776 #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
11777 #define RCC_CSR_IWDGRSTF_Pos               (29U)
11778 #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
11779 #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
11780 #define RCC_CSR_WWDGRSTF_Pos               (30U)
11781 #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
11782 #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
11783 #define RCC_CSR_LPWRRSTF_Pos               (31U)
11784 #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
11785 #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
11786 /* Legacy defines */
11787 #define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
11788 #define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
11789 
11790 /********************  Bit definition for RCC_SSCGR register  *****************/
11791 #define RCC_SSCGR_MODPER_Pos               (0U)
11792 #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
11793 #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
11794 #define RCC_SSCGR_INCSTEP_Pos              (13U)
11795 #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
11796 #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
11797 #define RCC_SSCGR_SPREADSEL_Pos            (30U)
11798 #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
11799 #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
11800 #define RCC_SSCGR_SSCGEN_Pos               (31U)
11801 #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
11802 #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
11803 
11804 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
11805 #define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)
11806 #define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
11807 #define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk
11808 #define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11809 #define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11810 #define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11811 #define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11812 #define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11813 #define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11814 #define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11815 #define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11816 #define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11817 
11818 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)
11819 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11820 #define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk
11821 #define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11822 #define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11823 #define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11824 #define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11825 #define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)
11826 #define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11827 #define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk
11828 #define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11829 #define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11830 #define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11831 
11832 /********************  Bit definition for RCC_PLLSAICFGR register  ************/
11833 #define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)
11834 #define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11835 #define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk
11836 #define RCC_PLLSAICFGR_PLLSAIN_0           (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11837 #define RCC_PLLSAICFGR_PLLSAIN_1           (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11838 #define RCC_PLLSAICFGR_PLLSAIN_2           (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11839 #define RCC_PLLSAICFGR_PLLSAIN_3           (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11840 #define RCC_PLLSAICFGR_PLLSAIN_4           (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11841 #define RCC_PLLSAICFGR_PLLSAIN_5           (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11842 #define RCC_PLLSAICFGR_PLLSAIN_6           (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11843 #define RCC_PLLSAICFGR_PLLSAIN_7           (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11844 #define RCC_PLLSAICFGR_PLLSAIN_8           (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11845 
11846 
11847 #define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)
11848 #define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11849 #define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk
11850 #define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11851 #define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11852 #define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11853 #define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11854 
11855 #define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)
11856 #define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
11857 #define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk
11858 #define RCC_PLLSAICFGR_PLLSAIR_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
11859 #define RCC_PLLSAICFGR_PLLSAIR_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
11860 #define RCC_PLLSAICFGR_PLLSAIR_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
11861 
11862 /********************  Bit definition for RCC_DCKCFGR register  ***************/
11863 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)
11864 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
11865 #define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk
11866 #define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
11867 #define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
11868 #define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
11869 #define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
11870 #define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
11871 
11872 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)
11873 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
11874 #define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk
11875 #define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
11876 #define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
11877 #define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
11878 #define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
11879 #define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
11880 #define RCC_DCKCFGR_PLLSAIDIVR_Pos        (16U)
11881 #define RCC_DCKCFGR_PLLSAIDIVR_Msk        (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11882 #define RCC_DCKCFGR_PLLSAIDIVR            RCC_DCKCFGR_PLLSAIDIVR_Msk
11883 #define RCC_DCKCFGR_PLLSAIDIVR_0          (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11884 #define RCC_DCKCFGR_PLLSAIDIVR_1          (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
11885 
11886 #define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)
11887 #define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */
11888 #define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk
11889 #define RCC_DCKCFGR_SAI1ASRC_0             (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */
11890 #define RCC_DCKCFGR_SAI1ASRC_1             (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */
11891 #define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)
11892 #define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */
11893 #define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk
11894 #define RCC_DCKCFGR_SAI1BSRC_0             (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */
11895 #define RCC_DCKCFGR_SAI1BSRC_1             (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */
11896 #define RCC_DCKCFGR_TIMPRE_Pos             (24U)
11897 #define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
11898 #define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk
11899 
11900 
11901 /******************************************************************************/
11902 /*                                                                            */
11903 /*                                    RNG                                     */
11904 /*                                                                            */
11905 /******************************************************************************/
11906 /********************  Bits definition for RNG_CR register  *******************/
11907 #define RNG_CR_RNGEN_Pos    (2U)
11908 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
11909 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
11910 #define RNG_CR_IE_Pos       (3U)
11911 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
11912 #define RNG_CR_IE           RNG_CR_IE_Msk
11913 
11914 /********************  Bits definition for RNG_SR register  *******************/
11915 #define RNG_SR_DRDY_Pos     (0U)
11916 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
11917 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
11918 #define RNG_SR_CECS_Pos     (1U)
11919 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
11920 #define RNG_SR_CECS         RNG_SR_CECS_Msk
11921 #define RNG_SR_SECS_Pos     (2U)
11922 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
11923 #define RNG_SR_SECS         RNG_SR_SECS_Msk
11924 #define RNG_SR_CEIS_Pos     (5U)
11925 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
11926 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
11927 #define RNG_SR_SEIS_Pos     (6U)
11928 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
11929 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
11930 
11931 /******************************************************************************/
11932 /*                                                                            */
11933 /*                           Real-Time Clock (RTC)                            */
11934 /*                                                                            */
11935 /******************************************************************************/
11936 /*
11937  * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
11938  */
11939 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
11940 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
11941 /********************  Bits definition for RTC_TR register  *******************/
11942 #define RTC_TR_PM_Pos                 (22U)
11943 #define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
11944 #define RTC_TR_PM                     RTC_TR_PM_Msk
11945 #define RTC_TR_HT_Pos                 (20U)
11946 #define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
11947 #define RTC_TR_HT                     RTC_TR_HT_Msk
11948 #define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
11949 #define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
11950 #define RTC_TR_HU_Pos                 (16U)
11951 #define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
11952 #define RTC_TR_HU                     RTC_TR_HU_Msk
11953 #define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
11954 #define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
11955 #define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
11956 #define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
11957 #define RTC_TR_MNT_Pos                (12U)
11958 #define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
11959 #define RTC_TR_MNT                    RTC_TR_MNT_Msk
11960 #define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
11961 #define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
11962 #define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
11963 #define RTC_TR_MNU_Pos                (8U)
11964 #define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
11965 #define RTC_TR_MNU                    RTC_TR_MNU_Msk
11966 #define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
11967 #define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
11968 #define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
11969 #define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
11970 #define RTC_TR_ST_Pos                 (4U)
11971 #define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
11972 #define RTC_TR_ST                     RTC_TR_ST_Msk
11973 #define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
11974 #define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
11975 #define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
11976 #define RTC_TR_SU_Pos                 (0U)
11977 #define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
11978 #define RTC_TR_SU                     RTC_TR_SU_Msk
11979 #define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
11980 #define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
11981 #define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
11982 #define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
11983 
11984 /********************  Bits definition for RTC_DR register  *******************/
11985 #define RTC_DR_YT_Pos                 (20U)
11986 #define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
11987 #define RTC_DR_YT                     RTC_DR_YT_Msk
11988 #define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
11989 #define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
11990 #define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
11991 #define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
11992 #define RTC_DR_YU_Pos                 (16U)
11993 #define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
11994 #define RTC_DR_YU                     RTC_DR_YU_Msk
11995 #define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
11996 #define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
11997 #define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
11998 #define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
11999 #define RTC_DR_WDU_Pos                (13U)
12000 #define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
12001 #define RTC_DR_WDU                    RTC_DR_WDU_Msk
12002 #define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
12003 #define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
12004 #define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
12005 #define RTC_DR_MT_Pos                 (12U)
12006 #define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
12007 #define RTC_DR_MT                     RTC_DR_MT_Msk
12008 #define RTC_DR_MU_Pos                 (8U)
12009 #define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
12010 #define RTC_DR_MU                     RTC_DR_MU_Msk
12011 #define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
12012 #define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
12013 #define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
12014 #define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
12015 #define RTC_DR_DT_Pos                 (4U)
12016 #define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
12017 #define RTC_DR_DT                     RTC_DR_DT_Msk
12018 #define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
12019 #define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
12020 #define RTC_DR_DU_Pos                 (0U)
12021 #define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
12022 #define RTC_DR_DU                     RTC_DR_DU_Msk
12023 #define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
12024 #define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
12025 #define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
12026 #define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
12027 
12028 /********************  Bits definition for RTC_CR register  *******************/
12029 #define RTC_CR_COE_Pos                (23U)
12030 #define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
12031 #define RTC_CR_COE                    RTC_CR_COE_Msk
12032 #define RTC_CR_OSEL_Pos               (21U)
12033 #define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
12034 #define RTC_CR_OSEL                   RTC_CR_OSEL_Msk
12035 #define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
12036 #define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
12037 #define RTC_CR_POL_Pos                (20U)
12038 #define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
12039 #define RTC_CR_POL                    RTC_CR_POL_Msk
12040 #define RTC_CR_COSEL_Pos              (19U)
12041 #define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
12042 #define RTC_CR_COSEL                  RTC_CR_COSEL_Msk
12043 #define RTC_CR_BKP_Pos                 (18U)
12044 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
12045 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
12046 #define RTC_CR_SUB1H_Pos              (17U)
12047 #define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
12048 #define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk
12049 #define RTC_CR_ADD1H_Pos              (16U)
12050 #define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
12051 #define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk
12052 #define RTC_CR_TSIE_Pos               (15U)
12053 #define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
12054 #define RTC_CR_TSIE                   RTC_CR_TSIE_Msk
12055 #define RTC_CR_WUTIE_Pos              (14U)
12056 #define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
12057 #define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk
12058 #define RTC_CR_ALRBIE_Pos             (13U)
12059 #define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
12060 #define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk
12061 #define RTC_CR_ALRAIE_Pos             (12U)
12062 #define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
12063 #define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk
12064 #define RTC_CR_TSE_Pos                (11U)
12065 #define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
12066 #define RTC_CR_TSE                    RTC_CR_TSE_Msk
12067 #define RTC_CR_WUTE_Pos               (10U)
12068 #define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
12069 #define RTC_CR_WUTE                   RTC_CR_WUTE_Msk
12070 #define RTC_CR_ALRBE_Pos              (9U)
12071 #define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
12072 #define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk
12073 #define RTC_CR_ALRAE_Pos              (8U)
12074 #define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
12075 #define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk
12076 #define RTC_CR_DCE_Pos                (7U)
12077 #define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
12078 #define RTC_CR_DCE                    RTC_CR_DCE_Msk
12079 #define RTC_CR_FMT_Pos                (6U)
12080 #define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
12081 #define RTC_CR_FMT                    RTC_CR_FMT_Msk
12082 #define RTC_CR_BYPSHAD_Pos            (5U)
12083 #define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
12084 #define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk
12085 #define RTC_CR_REFCKON_Pos            (4U)
12086 #define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
12087 #define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk
12088 #define RTC_CR_TSEDGE_Pos             (3U)
12089 #define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
12090 #define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk
12091 #define RTC_CR_WUCKSEL_Pos            (0U)
12092 #define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
12093 #define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk
12094 #define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
12095 #define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
12096 #define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
12097 
12098 /* Legacy defines */
12099 #define RTC_CR_BCK                     RTC_CR_BKP
12100 
12101 /********************  Bits definition for RTC_ISR register  ******************/
12102 #define RTC_ISR_RECALPF_Pos           (16U)
12103 #define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
12104 #define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk
12105 #define RTC_ISR_TAMP1F_Pos            (13U)
12106 #define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
12107 #define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk
12108 #define RTC_ISR_TAMP2F_Pos            (14U)
12109 #define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
12110 #define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk
12111 #define RTC_ISR_TSOVF_Pos             (12U)
12112 #define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
12113 #define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk
12114 #define RTC_ISR_TSF_Pos               (11U)
12115 #define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
12116 #define RTC_ISR_TSF                   RTC_ISR_TSF_Msk
12117 #define RTC_ISR_WUTF_Pos              (10U)
12118 #define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
12119 #define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk
12120 #define RTC_ISR_ALRBF_Pos             (9U)
12121 #define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
12122 #define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk
12123 #define RTC_ISR_ALRAF_Pos             (8U)
12124 #define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
12125 #define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk
12126 #define RTC_ISR_INIT_Pos              (7U)
12127 #define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
12128 #define RTC_ISR_INIT                  RTC_ISR_INIT_Msk
12129 #define RTC_ISR_INITF_Pos             (6U)
12130 #define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
12131 #define RTC_ISR_INITF                 RTC_ISR_INITF_Msk
12132 #define RTC_ISR_RSF_Pos               (5U)
12133 #define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
12134 #define RTC_ISR_RSF                   RTC_ISR_RSF_Msk
12135 #define RTC_ISR_INITS_Pos             (4U)
12136 #define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
12137 #define RTC_ISR_INITS                 RTC_ISR_INITS_Msk
12138 #define RTC_ISR_SHPF_Pos              (3U)
12139 #define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
12140 #define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk
12141 #define RTC_ISR_WUTWF_Pos             (2U)
12142 #define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
12143 #define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk
12144 #define RTC_ISR_ALRBWF_Pos            (1U)
12145 #define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
12146 #define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk
12147 #define RTC_ISR_ALRAWF_Pos            (0U)
12148 #define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
12149 #define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk
12150 
12151 /********************  Bits definition for RTC_PRER register  *****************/
12152 #define RTC_PRER_PREDIV_A_Pos         (16U)
12153 #define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
12154 #define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk
12155 #define RTC_PRER_PREDIV_S_Pos         (0U)
12156 #define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
12157 #define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk
12158 
12159 /********************  Bits definition for RTC_WUTR register  *****************/
12160 #define RTC_WUTR_WUT_Pos              (0U)
12161 #define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
12162 #define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk
12163 
12164 /********************  Bits definition for RTC_CALIBR register  ***************/
12165 #define RTC_CALIBR_DCS_Pos            (7U)
12166 #define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
12167 #define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk
12168 #define RTC_CALIBR_DC_Pos             (0U)
12169 #define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
12170 #define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk
12171 
12172 /********************  Bits definition for RTC_ALRMAR register  ***************/
12173 #define RTC_ALRMAR_MSK4_Pos           (31U)
12174 #define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
12175 #define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk
12176 #define RTC_ALRMAR_WDSEL_Pos          (30U)
12177 #define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
12178 #define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk
12179 #define RTC_ALRMAR_DT_Pos             (28U)
12180 #define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
12181 #define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk
12182 #define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
12183 #define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
12184 #define RTC_ALRMAR_DU_Pos             (24U)
12185 #define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
12186 #define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk
12187 #define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
12188 #define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
12189 #define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
12190 #define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
12191 #define RTC_ALRMAR_MSK3_Pos           (23U)
12192 #define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
12193 #define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk
12194 #define RTC_ALRMAR_PM_Pos             (22U)
12195 #define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
12196 #define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk
12197 #define RTC_ALRMAR_HT_Pos             (20U)
12198 #define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
12199 #define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk
12200 #define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
12201 #define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
12202 #define RTC_ALRMAR_HU_Pos             (16U)
12203 #define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
12204 #define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk
12205 #define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
12206 #define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
12207 #define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
12208 #define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
12209 #define RTC_ALRMAR_MSK2_Pos           (15U)
12210 #define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
12211 #define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk
12212 #define RTC_ALRMAR_MNT_Pos            (12U)
12213 #define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
12214 #define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk
12215 #define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
12216 #define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
12217 #define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
12218 #define RTC_ALRMAR_MNU_Pos            (8U)
12219 #define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
12220 #define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk
12221 #define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
12222 #define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
12223 #define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
12224 #define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
12225 #define RTC_ALRMAR_MSK1_Pos           (7U)
12226 #define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
12227 #define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk
12228 #define RTC_ALRMAR_ST_Pos             (4U)
12229 #define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
12230 #define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk
12231 #define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
12232 #define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
12233 #define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
12234 #define RTC_ALRMAR_SU_Pos             (0U)
12235 #define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
12236 #define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk
12237 #define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
12238 #define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
12239 #define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
12240 #define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
12241 
12242 /********************  Bits definition for RTC_ALRMBR register  ***************/
12243 #define RTC_ALRMBR_MSK4_Pos           (31U)
12244 #define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
12245 #define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk
12246 #define RTC_ALRMBR_WDSEL_Pos          (30U)
12247 #define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
12248 #define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk
12249 #define RTC_ALRMBR_DT_Pos             (28U)
12250 #define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
12251 #define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk
12252 #define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
12253 #define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
12254 #define RTC_ALRMBR_DU_Pos             (24U)
12255 #define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
12256 #define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk
12257 #define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
12258 #define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
12259 #define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
12260 #define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
12261 #define RTC_ALRMBR_MSK3_Pos           (23U)
12262 #define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
12263 #define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk
12264 #define RTC_ALRMBR_PM_Pos             (22U)
12265 #define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
12266 #define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk
12267 #define RTC_ALRMBR_HT_Pos             (20U)
12268 #define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
12269 #define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk
12270 #define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
12271 #define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
12272 #define RTC_ALRMBR_HU_Pos             (16U)
12273 #define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
12274 #define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk
12275 #define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
12276 #define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
12277 #define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
12278 #define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
12279 #define RTC_ALRMBR_MSK2_Pos           (15U)
12280 #define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
12281 #define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk
12282 #define RTC_ALRMBR_MNT_Pos            (12U)
12283 #define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
12284 #define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk
12285 #define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
12286 #define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
12287 #define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
12288 #define RTC_ALRMBR_MNU_Pos            (8U)
12289 #define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
12290 #define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk
12291 #define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
12292 #define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
12293 #define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
12294 #define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
12295 #define RTC_ALRMBR_MSK1_Pos           (7U)
12296 #define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
12297 #define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk
12298 #define RTC_ALRMBR_ST_Pos             (4U)
12299 #define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
12300 #define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk
12301 #define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
12302 #define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
12303 #define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
12304 #define RTC_ALRMBR_SU_Pos             (0U)
12305 #define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
12306 #define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk
12307 #define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
12308 #define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
12309 #define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
12310 #define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
12311 
12312 /********************  Bits definition for RTC_WPR register  ******************/
12313 #define RTC_WPR_KEY_Pos               (0U)
12314 #define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
12315 #define RTC_WPR_KEY                   RTC_WPR_KEY_Msk
12316 
12317 /********************  Bits definition for RTC_SSR register  ******************/
12318 #define RTC_SSR_SS_Pos                (0U)
12319 #define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
12320 #define RTC_SSR_SS                    RTC_SSR_SS_Msk
12321 
12322 /********************  Bits definition for RTC_SHIFTR register  ***************/
12323 #define RTC_SHIFTR_SUBFS_Pos          (0U)
12324 #define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
12325 #define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk
12326 #define RTC_SHIFTR_ADD1S_Pos          (31U)
12327 #define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
12328 #define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk
12329 
12330 /********************  Bits definition for RTC_TSTR register  *****************/
12331 #define RTC_TSTR_PM_Pos               (22U)
12332 #define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
12333 #define RTC_TSTR_PM                   RTC_TSTR_PM_Msk
12334 #define RTC_TSTR_HT_Pos               (20U)
12335 #define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
12336 #define RTC_TSTR_HT                   RTC_TSTR_HT_Msk
12337 #define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
12338 #define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
12339 #define RTC_TSTR_HU_Pos               (16U)
12340 #define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
12341 #define RTC_TSTR_HU                   RTC_TSTR_HU_Msk
12342 #define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
12343 #define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
12344 #define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
12345 #define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
12346 #define RTC_TSTR_MNT_Pos              (12U)
12347 #define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
12348 #define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk
12349 #define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
12350 #define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
12351 #define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
12352 #define RTC_TSTR_MNU_Pos              (8U)
12353 #define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
12354 #define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk
12355 #define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
12356 #define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
12357 #define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
12358 #define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
12359 #define RTC_TSTR_ST_Pos               (4U)
12360 #define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
12361 #define RTC_TSTR_ST                   RTC_TSTR_ST_Msk
12362 #define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
12363 #define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
12364 #define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
12365 #define RTC_TSTR_SU_Pos               (0U)
12366 #define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
12367 #define RTC_TSTR_SU                   RTC_TSTR_SU_Msk
12368 #define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
12369 #define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
12370 #define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
12371 #define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
12372 
12373 /********************  Bits definition for RTC_TSDR register  *****************/
12374 #define RTC_TSDR_WDU_Pos              (13U)
12375 #define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
12376 #define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk
12377 #define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
12378 #define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
12379 #define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
12380 #define RTC_TSDR_MT_Pos               (12U)
12381 #define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
12382 #define RTC_TSDR_MT                   RTC_TSDR_MT_Msk
12383 #define RTC_TSDR_MU_Pos               (8U)
12384 #define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
12385 #define RTC_TSDR_MU                   RTC_TSDR_MU_Msk
12386 #define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
12387 #define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
12388 #define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
12389 #define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
12390 #define RTC_TSDR_DT_Pos               (4U)
12391 #define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
12392 #define RTC_TSDR_DT                   RTC_TSDR_DT_Msk
12393 #define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
12394 #define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
12395 #define RTC_TSDR_DU_Pos               (0U)
12396 #define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
12397 #define RTC_TSDR_DU                   RTC_TSDR_DU_Msk
12398 #define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
12399 #define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
12400 #define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
12401 #define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
12402 
12403 /********************  Bits definition for RTC_TSSSR register  ****************/
12404 #define RTC_TSSSR_SS_Pos              (0U)
12405 #define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
12406 #define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk
12407 
12408 /********************  Bits definition for RTC_CAL register  *****************/
12409 #define RTC_CALR_CALP_Pos             (15U)
12410 #define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
12411 #define RTC_CALR_CALP                 RTC_CALR_CALP_Msk
12412 #define RTC_CALR_CALW8_Pos            (14U)
12413 #define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
12414 #define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk
12415 #define RTC_CALR_CALW16_Pos           (13U)
12416 #define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
12417 #define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk
12418 #define RTC_CALR_CALM_Pos             (0U)
12419 #define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
12420 #define RTC_CALR_CALM                 RTC_CALR_CALM_Msk
12421 #define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
12422 #define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
12423 #define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
12424 #define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
12425 #define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
12426 #define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
12427 #define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
12428 #define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
12429 #define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
12430 
12431 /********************  Bits definition for RTC_TAFCR register  ****************/
12432 #define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)
12433 #define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
12434 #define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk
12435 #define RTC_TAFCR_TSINSEL_Pos         (17U)
12436 #define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
12437 #define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk
12438 #define RTC_TAFCR_TAMP1INSEL_Pos      (16U)
12439 #define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
12440 #define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk
12441 #define RTC_TAFCR_TAMPPUDIS_Pos       (15U)
12442 #define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
12443 #define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk
12444 #define RTC_TAFCR_TAMPPRCH_Pos        (13U)
12445 #define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
12446 #define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk
12447 #define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
12448 #define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
12449 #define RTC_TAFCR_TAMPFLT_Pos         (11U)
12450 #define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
12451 #define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk
12452 #define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
12453 #define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
12454 #define RTC_TAFCR_TAMPFREQ_Pos        (8U)
12455 #define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
12456 #define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk
12457 #define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
12458 #define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
12459 #define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
12460 #define RTC_TAFCR_TAMPTS_Pos          (7U)
12461 #define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
12462 #define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk
12463 #define RTC_TAFCR_TAMP2TRG_Pos        (4U)
12464 #define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
12465 #define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk
12466 #define RTC_TAFCR_TAMP2E_Pos          (3U)
12467 #define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
12468 #define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk
12469 #define RTC_TAFCR_TAMPIE_Pos          (2U)
12470 #define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
12471 #define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk
12472 #define RTC_TAFCR_TAMP1TRG_Pos        (1U)
12473 #define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
12474 #define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk
12475 #define RTC_TAFCR_TAMP1E_Pos          (0U)
12476 #define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
12477 #define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk
12478 
12479 /* Legacy defines */
12480 #define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
12481 
12482 /********************  Bits definition for RTC_ALRMASSR register  *************/
12483 #define RTC_ALRMASSR_MASKSS_Pos       (24U)
12484 #define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
12485 #define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk
12486 #define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
12487 #define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
12488 #define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
12489 #define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
12490 #define RTC_ALRMASSR_SS_Pos           (0U)
12491 #define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
12492 #define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk
12493 
12494 /********************  Bits definition for RTC_ALRMBSSR register  *************/
12495 #define RTC_ALRMBSSR_MASKSS_Pos       (24U)
12496 #define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
12497 #define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk
12498 #define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
12499 #define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
12500 #define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
12501 #define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
12502 #define RTC_ALRMBSSR_SS_Pos           (0U)
12503 #define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
12504 #define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk
12505 
12506 /********************  Bits definition for RTC_BKP0R register  ****************/
12507 #define RTC_BKP0R_Pos                 (0U)
12508 #define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
12509 #define RTC_BKP0R                     RTC_BKP0R_Msk
12510 
12511 /********************  Bits definition for RTC_BKP1R register  ****************/
12512 #define RTC_BKP1R_Pos                 (0U)
12513 #define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
12514 #define RTC_BKP1R                     RTC_BKP1R_Msk
12515 
12516 /********************  Bits definition for RTC_BKP2R register  ****************/
12517 #define RTC_BKP2R_Pos                 (0U)
12518 #define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
12519 #define RTC_BKP2R                     RTC_BKP2R_Msk
12520 
12521 /********************  Bits definition for RTC_BKP3R register  ****************/
12522 #define RTC_BKP3R_Pos                 (0U)
12523 #define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
12524 #define RTC_BKP3R                     RTC_BKP3R_Msk
12525 
12526 /********************  Bits definition for RTC_BKP4R register  ****************/
12527 #define RTC_BKP4R_Pos                 (0U)
12528 #define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
12529 #define RTC_BKP4R                     RTC_BKP4R_Msk
12530 
12531 /********************  Bits definition for RTC_BKP5R register  ****************/
12532 #define RTC_BKP5R_Pos                 (0U)
12533 #define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
12534 #define RTC_BKP5R                     RTC_BKP5R_Msk
12535 
12536 /********************  Bits definition for RTC_BKP6R register  ****************/
12537 #define RTC_BKP6R_Pos                 (0U)
12538 #define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
12539 #define RTC_BKP6R                     RTC_BKP6R_Msk
12540 
12541 /********************  Bits definition for RTC_BKP7R register  ****************/
12542 #define RTC_BKP7R_Pos                 (0U)
12543 #define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
12544 #define RTC_BKP7R                     RTC_BKP7R_Msk
12545 
12546 /********************  Bits definition for RTC_BKP8R register  ****************/
12547 #define RTC_BKP8R_Pos                 (0U)
12548 #define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
12549 #define RTC_BKP8R                     RTC_BKP8R_Msk
12550 
12551 /********************  Bits definition for RTC_BKP9R register  ****************/
12552 #define RTC_BKP9R_Pos                 (0U)
12553 #define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
12554 #define RTC_BKP9R                     RTC_BKP9R_Msk
12555 
12556 /********************  Bits definition for RTC_BKP10R register  ***************/
12557 #define RTC_BKP10R_Pos                (0U)
12558 #define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
12559 #define RTC_BKP10R                    RTC_BKP10R_Msk
12560 
12561 /********************  Bits definition for RTC_BKP11R register  ***************/
12562 #define RTC_BKP11R_Pos                (0U)
12563 #define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
12564 #define RTC_BKP11R                    RTC_BKP11R_Msk
12565 
12566 /********************  Bits definition for RTC_BKP12R register  ***************/
12567 #define RTC_BKP12R_Pos                (0U)
12568 #define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
12569 #define RTC_BKP12R                    RTC_BKP12R_Msk
12570 
12571 /********************  Bits definition for RTC_BKP13R register  ***************/
12572 #define RTC_BKP13R_Pos                (0U)
12573 #define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
12574 #define RTC_BKP13R                    RTC_BKP13R_Msk
12575 
12576 /********************  Bits definition for RTC_BKP14R register  ***************/
12577 #define RTC_BKP14R_Pos                (0U)
12578 #define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
12579 #define RTC_BKP14R                    RTC_BKP14R_Msk
12580 
12581 /********************  Bits definition for RTC_BKP15R register  ***************/
12582 #define RTC_BKP15R_Pos                (0U)
12583 #define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
12584 #define RTC_BKP15R                    RTC_BKP15R_Msk
12585 
12586 /********************  Bits definition for RTC_BKP16R register  ***************/
12587 #define RTC_BKP16R_Pos                (0U)
12588 #define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
12589 #define RTC_BKP16R                    RTC_BKP16R_Msk
12590 
12591 /********************  Bits definition for RTC_BKP17R register  ***************/
12592 #define RTC_BKP17R_Pos                (0U)
12593 #define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
12594 #define RTC_BKP17R                    RTC_BKP17R_Msk
12595 
12596 /********************  Bits definition for RTC_BKP18R register  ***************/
12597 #define RTC_BKP18R_Pos                (0U)
12598 #define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
12599 #define RTC_BKP18R                    RTC_BKP18R_Msk
12600 
12601 /********************  Bits definition for RTC_BKP19R register  ***************/
12602 #define RTC_BKP19R_Pos                (0U)
12603 #define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
12604 #define RTC_BKP19R                    RTC_BKP19R_Msk
12605 
12606 /******************** Number of backup registers ******************************/
12607 #define RTC_BKP_NUMBER                       0x000000014U
12608 
12609 /******************************************************************************/
12610 /*                                                                            */
12611 /*                          Serial Audio Interface                            */
12612 /*                                                                            */
12613 /******************************************************************************/
12614 /********************  Bit definition for SAI_GCR register  *******************/
12615 #define SAI_GCR_SYNCIN_Pos         (0U)
12616 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
12617 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
12618 #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
12619 #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
12620 
12621 #define SAI_GCR_SYNCOUT_Pos        (4U)
12622 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
12623 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
12624 #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
12625 #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
12626 
12627 /*******************  Bit definition for SAI_xCR1 register  *******************/
12628 #define SAI_xCR1_MODE_Pos          (0U)
12629 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
12630 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
12631 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
12632 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
12633 
12634 #define SAI_xCR1_PRTCFG_Pos        (2U)
12635 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
12636 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
12637 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
12638 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
12639 
12640 #define SAI_xCR1_DS_Pos            (5U)
12641 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
12642 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
12643 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
12644 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
12645 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
12646 
12647 #define SAI_xCR1_LSBFIRST_Pos      (8U)
12648 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
12649 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
12650 #define SAI_xCR1_CKSTR_Pos         (9U)
12651 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
12652 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
12653 
12654 #define SAI_xCR1_SYNCEN_Pos        (10U)
12655 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
12656 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
12657 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
12658 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
12659 
12660 #define SAI_xCR1_MONO_Pos          (12U)
12661 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
12662 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
12663 #define SAI_xCR1_OUTDRIV_Pos       (13U)
12664 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
12665 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
12666 #define SAI_xCR1_SAIEN_Pos         (16U)
12667 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
12668 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
12669 #define SAI_xCR1_DMAEN_Pos         (17U)
12670 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
12671 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
12672 #define SAI_xCR1_NODIV_Pos         (19U)
12673 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
12674 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
12675 
12676 #define SAI_xCR1_MCKDIV_Pos        (20U)
12677 #define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
12678 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
12679 #define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
12680 #define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
12681 #define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
12682 #define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
12683 
12684 /*******************  Bit definition for SAI_xCR2 register  *******************/
12685 #define SAI_xCR2_FTH_Pos           (0U)
12686 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
12687 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
12688 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
12689 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
12690 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
12691 
12692 #define SAI_xCR2_FFLUSH_Pos        (3U)
12693 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
12694 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
12695 #define SAI_xCR2_TRIS_Pos          (4U)
12696 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
12697 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
12698 #define SAI_xCR2_MUTE_Pos          (5U)
12699 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
12700 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
12701 #define SAI_xCR2_MUTEVAL_Pos       (6U)
12702 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
12703 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
12704 
12705 #define SAI_xCR2_MUTECNT_Pos       (7U)
12706 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
12707 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
12708 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
12709 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
12710 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
12711 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
12712 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
12713 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
12714 
12715 #define SAI_xCR2_CPL_Pos           (13U)
12716 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
12717 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
12718 
12719 #define SAI_xCR2_COMP_Pos          (14U)
12720 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
12721 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
12722 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
12723 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
12724 
12725 /******************  Bit definition for SAI_xFRCR register  *******************/
12726 #define SAI_xFRCR_FRL_Pos          (0U)
12727 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
12728 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
12729 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
12730 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
12731 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
12732 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
12733 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
12734 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
12735 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
12736 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
12737 
12738 #define SAI_xFRCR_FSALL_Pos        (8U)
12739 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
12740 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
12741 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
12742 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
12743 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
12744 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
12745 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
12746 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
12747 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
12748 
12749 #define SAI_xFRCR_FSDEF_Pos        (16U)
12750 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
12751 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
12752 #define SAI_xFRCR_FSPOL_Pos        (17U)
12753 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
12754 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
12755 #define SAI_xFRCR_FSOFF_Pos        (18U)
12756 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
12757 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
12758 /* Legacy defines */
12759 #define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
12760 
12761 /******************  Bit definition for SAI_xSLOTR register  *******************/
12762 #define SAI_xSLOTR_FBOFF_Pos       (0U)
12763 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
12764 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
12765 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
12766 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
12767 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
12768 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
12769 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
12770 
12771 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
12772 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
12773 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
12774 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
12775 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
12776 
12777 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
12778 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
12779 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
12780 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
12781 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
12782 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
12783 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
12784 
12785 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
12786 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
12787 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
12788 
12789 /*******************  Bit definition for SAI_xIMR register  *******************/
12790 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
12791 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
12792 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
12793 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
12794 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
12795 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
12796 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
12797 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
12798 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
12799 #define SAI_xIMR_FREQIE_Pos        (3U)
12800 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
12801 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
12802 #define SAI_xIMR_CNRDYIE_Pos       (4U)
12803 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
12804 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
12805 #define SAI_xIMR_AFSDETIE_Pos      (5U)
12806 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
12807 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
12808 #define SAI_xIMR_LFSDETIE_Pos      (6U)
12809 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
12810 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
12811 
12812 /********************  Bit definition for SAI_xSR register  *******************/
12813 #define SAI_xSR_OVRUDR_Pos         (0U)
12814 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
12815 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
12816 #define SAI_xSR_MUTEDET_Pos        (1U)
12817 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
12818 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
12819 #define SAI_xSR_WCKCFG_Pos         (2U)
12820 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
12821 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
12822 #define SAI_xSR_FREQ_Pos           (3U)
12823 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
12824 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
12825 #define SAI_xSR_CNRDY_Pos          (4U)
12826 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
12827 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
12828 #define SAI_xSR_AFSDET_Pos         (5U)
12829 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
12830 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
12831 #define SAI_xSR_LFSDET_Pos         (6U)
12832 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
12833 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
12834 
12835 #define SAI_xSR_FLVL_Pos           (16U)
12836 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
12837 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
12838 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
12839 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
12840 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
12841 
12842 /******************  Bit definition for SAI_xCLRFR register  ******************/
12843 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
12844 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
12845 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
12846 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
12847 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
12848 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
12849 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
12850 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
12851 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
12852 #define SAI_xCLRFR_CFREQ_Pos       (3U)
12853 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
12854 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
12855 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
12856 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
12857 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
12858 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
12859 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
12860 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
12861 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
12862 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
12863 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
12864 
12865 /******************  Bit definition for SAI_xDR register  ******************/
12866 #define SAI_xDR_DATA_Pos           (0U)
12867 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
12868 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
12869 
12870 
12871 /******************************************************************************/
12872 /*                                                                            */
12873 /*                          SD host Interface                                 */
12874 /*                                                                            */
12875 /******************************************************************************/
12876 /******************  Bit definition for SDIO_POWER register  ******************/
12877 #define SDIO_POWER_PWRCTRL_Pos         (0U)
12878 #define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
12879 #define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12880 #define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
12881 #define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
12882 
12883 /******************  Bit definition for SDIO_CLKCR register  ******************/
12884 #define SDIO_CLKCR_CLKDIV_Pos          (0U)
12885 #define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
12886 #define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
12887 #define SDIO_CLKCR_CLKEN_Pos           (8U)
12888 #define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
12889 #define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
12890 #define SDIO_CLKCR_PWRSAV_Pos          (9U)
12891 #define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
12892 #define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
12893 #define SDIO_CLKCR_BYPASS_Pos          (10U)
12894 #define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
12895 #define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
12896 
12897 #define SDIO_CLKCR_WIDBUS_Pos          (11U)
12898 #define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
12899 #define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12900 #define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
12901 #define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
12902 
12903 #define SDIO_CLKCR_NEGEDGE_Pos         (13U)
12904 #define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
12905 #define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
12906 #define SDIO_CLKCR_HWFC_EN_Pos         (14U)
12907 #define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
12908 #define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
12909 
12910 /*******************  Bit definition for SDIO_ARG register  *******************/
12911 #define SDIO_ARG_CMDARG_Pos            (0U)
12912 #define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
12913 #define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
12914 
12915 /*******************  Bit definition for SDIO_CMD register  *******************/
12916 #define SDIO_CMD_CMDINDEX_Pos          (0U)
12917 #define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
12918 #define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
12919 
12920 #define SDIO_CMD_WAITRESP_Pos          (6U)
12921 #define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
12922 #define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
12923 #define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
12924 #define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
12925 
12926 #define SDIO_CMD_WAITINT_Pos           (8U)
12927 #define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
12928 #define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
12929 #define SDIO_CMD_WAITPEND_Pos          (9U)
12930 #define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
12931 #define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
12932 #define SDIO_CMD_CPSMEN_Pos            (10U)
12933 #define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
12934 #define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
12935 #define SDIO_CMD_SDIOSUSPEND_Pos       (11U)
12936 #define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
12937 #define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
12938 #define SDIO_CMD_ENCMDCOMPL_Pos        (12U)
12939 #define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */
12940 #define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */
12941 #define SDIO_CMD_NIEN_Pos              (13U)
12942 #define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */
12943 #define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */
12944 #define SDIO_CMD_CEATACMD_Pos          (14U)
12945 #define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */
12946 #define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */
12947 
12948 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
12949 #define SDIO_RESPCMD_RESPCMD_Pos       (0U)
12950 #define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
12951 #define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
12952 
12953 /******************  Bit definition for SDIO_RESP0 register  ******************/
12954 #define SDIO_RESP0_CARDSTATUS0_Pos     (0U)
12955 #define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
12956 #define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
12957 
12958 /******************  Bit definition for SDIO_RESP1 register  ******************/
12959 #define SDIO_RESP1_CARDSTATUS1_Pos     (0U)
12960 #define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
12961 #define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
12962 
12963 /******************  Bit definition for SDIO_RESP2 register  ******************/
12964 #define SDIO_RESP2_CARDSTATUS2_Pos     (0U)
12965 #define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
12966 #define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
12967 
12968 /******************  Bit definition for SDIO_RESP3 register  ******************/
12969 #define SDIO_RESP3_CARDSTATUS3_Pos     (0U)
12970 #define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
12971 #define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
12972 
12973 /******************  Bit definition for SDIO_RESP4 register  ******************/
12974 #define SDIO_RESP4_CARDSTATUS4_Pos     (0U)
12975 #define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
12976 #define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
12977 
12978 /******************  Bit definition for SDIO_DTIMER register  *****************/
12979 #define SDIO_DTIMER_DATATIME_Pos       (0U)
12980 #define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
12981 #define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
12982 
12983 /******************  Bit definition for SDIO_DLEN register  *******************/
12984 #define SDIO_DLEN_DATALENGTH_Pos       (0U)
12985 #define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
12986 #define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
12987 
12988 /******************  Bit definition for SDIO_DCTRL register  ******************/
12989 #define SDIO_DCTRL_DTEN_Pos            (0U)
12990 #define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
12991 #define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
12992 #define SDIO_DCTRL_DTDIR_Pos           (1U)
12993 #define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
12994 #define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
12995 #define SDIO_DCTRL_DTMODE_Pos          (2U)
12996 #define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
12997 #define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
12998 #define SDIO_DCTRL_DMAEN_Pos           (3U)
12999 #define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
13000 #define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
13001 
13002 #define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)
13003 #define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
13004 #define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
13005 #define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
13006 #define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
13007 #define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
13008 #define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
13009 
13010 #define SDIO_DCTRL_RWSTART_Pos         (8U)
13011 #define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
13012 #define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
13013 #define SDIO_DCTRL_RWSTOP_Pos          (9U)
13014 #define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
13015 #define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
13016 #define SDIO_DCTRL_RWMOD_Pos           (10U)
13017 #define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
13018 #define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
13019 #define SDIO_DCTRL_SDIOEN_Pos          (11U)
13020 #define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
13021 #define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
13022 
13023 /******************  Bit definition for SDIO_DCOUNT register  *****************/
13024 #define SDIO_DCOUNT_DATACOUNT_Pos      (0U)
13025 #define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
13026 #define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
13027 
13028 /******************  Bit definition for SDIO_STA register  ********************/
13029 #define SDIO_STA_CCRCFAIL_Pos          (0U)
13030 #define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
13031 #define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
13032 #define SDIO_STA_DCRCFAIL_Pos          (1U)
13033 #define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
13034 #define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
13035 #define SDIO_STA_CTIMEOUT_Pos          (2U)
13036 #define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
13037 #define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
13038 #define SDIO_STA_DTIMEOUT_Pos          (3U)
13039 #define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
13040 #define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
13041 #define SDIO_STA_TXUNDERR_Pos          (4U)
13042 #define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
13043 #define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
13044 #define SDIO_STA_RXOVERR_Pos           (5U)
13045 #define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
13046 #define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
13047 #define SDIO_STA_CMDREND_Pos           (6U)
13048 #define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
13049 #define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
13050 #define SDIO_STA_CMDSENT_Pos           (7U)
13051 #define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
13052 #define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
13053 #define SDIO_STA_DATAEND_Pos           (8U)
13054 #define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
13055 #define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
13056 #define SDIO_STA_STBITERR_Pos          (9U)
13057 #define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */
13058 #define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */
13059 #define SDIO_STA_DBCKEND_Pos           (10U)
13060 #define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
13061 #define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
13062 #define SDIO_STA_CMDACT_Pos            (11U)
13063 #define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
13064 #define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
13065 #define SDIO_STA_TXACT_Pos             (12U)
13066 #define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
13067 #define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
13068 #define SDIO_STA_RXACT_Pos             (13U)
13069 #define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
13070 #define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
13071 #define SDIO_STA_TXFIFOHE_Pos          (14U)
13072 #define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
13073 #define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
13074 #define SDIO_STA_RXFIFOHF_Pos          (15U)
13075 #define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
13076 #define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
13077 #define SDIO_STA_TXFIFOF_Pos           (16U)
13078 #define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
13079 #define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
13080 #define SDIO_STA_RXFIFOF_Pos           (17U)
13081 #define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
13082 #define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
13083 #define SDIO_STA_TXFIFOE_Pos           (18U)
13084 #define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
13085 #define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
13086 #define SDIO_STA_RXFIFOE_Pos           (19U)
13087 #define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
13088 #define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
13089 #define SDIO_STA_TXDAVL_Pos            (20U)
13090 #define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
13091 #define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
13092 #define SDIO_STA_RXDAVL_Pos            (21U)
13093 #define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
13094 #define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
13095 #define SDIO_STA_SDIOIT_Pos            (22U)
13096 #define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
13097 #define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
13098 #define SDIO_STA_CEATAEND_Pos          (23U)
13099 #define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */
13100 #define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */
13101 
13102 /*******************  Bit definition for SDIO_ICR register  *******************/
13103 #define SDIO_ICR_CCRCFAILC_Pos         (0U)
13104 #define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
13105 #define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
13106 #define SDIO_ICR_DCRCFAILC_Pos         (1U)
13107 #define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
13108 #define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
13109 #define SDIO_ICR_CTIMEOUTC_Pos         (2U)
13110 #define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
13111 #define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
13112 #define SDIO_ICR_DTIMEOUTC_Pos         (3U)
13113 #define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
13114 #define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
13115 #define SDIO_ICR_TXUNDERRC_Pos         (4U)
13116 #define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
13117 #define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
13118 #define SDIO_ICR_RXOVERRC_Pos          (5U)
13119 #define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
13120 #define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
13121 #define SDIO_ICR_CMDRENDC_Pos          (6U)
13122 #define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
13123 #define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
13124 #define SDIO_ICR_CMDSENTC_Pos          (7U)
13125 #define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
13126 #define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
13127 #define SDIO_ICR_DATAENDC_Pos          (8U)
13128 #define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
13129 #define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
13130 #define SDIO_ICR_STBITERRC_Pos         (9U)
13131 #define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */
13132 #define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */
13133 #define SDIO_ICR_DBCKENDC_Pos          (10U)
13134 #define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
13135 #define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
13136 #define SDIO_ICR_SDIOITC_Pos           (22U)
13137 #define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
13138 #define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
13139 #define SDIO_ICR_CEATAENDC_Pos         (23U)
13140 #define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */
13141 #define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */
13142 
13143 /******************  Bit definition for SDIO_MASK register  *******************/
13144 #define SDIO_MASK_CCRCFAILIE_Pos       (0U)
13145 #define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
13146 #define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
13147 #define SDIO_MASK_DCRCFAILIE_Pos       (1U)
13148 #define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
13149 #define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
13150 #define SDIO_MASK_CTIMEOUTIE_Pos       (2U)
13151 #define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
13152 #define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
13153 #define SDIO_MASK_DTIMEOUTIE_Pos       (3U)
13154 #define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
13155 #define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
13156 #define SDIO_MASK_TXUNDERRIE_Pos       (4U)
13157 #define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
13158 #define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
13159 #define SDIO_MASK_RXOVERRIE_Pos        (5U)
13160 #define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
13161 #define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
13162 #define SDIO_MASK_CMDRENDIE_Pos        (6U)
13163 #define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
13164 #define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
13165 #define SDIO_MASK_CMDSENTIE_Pos        (7U)
13166 #define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
13167 #define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
13168 #define SDIO_MASK_DATAENDIE_Pos        (8U)
13169 #define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
13170 #define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
13171 #define SDIO_MASK_STBITERRIE_Pos       (9U)
13172 #define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */
13173 #define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */
13174 #define SDIO_MASK_DBCKENDIE_Pos        (10U)
13175 #define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
13176 #define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
13177 #define SDIO_MASK_CMDACTIE_Pos         (11U)
13178 #define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
13179 #define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
13180 #define SDIO_MASK_TXACTIE_Pos          (12U)
13181 #define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
13182 #define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
13183 #define SDIO_MASK_RXACTIE_Pos          (13U)
13184 #define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
13185 #define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
13186 #define SDIO_MASK_TXFIFOHEIE_Pos       (14U)
13187 #define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
13188 #define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
13189 #define SDIO_MASK_RXFIFOHFIE_Pos       (15U)
13190 #define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
13191 #define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
13192 #define SDIO_MASK_TXFIFOFIE_Pos        (16U)
13193 #define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
13194 #define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
13195 #define SDIO_MASK_RXFIFOFIE_Pos        (17U)
13196 #define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
13197 #define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
13198 #define SDIO_MASK_TXFIFOEIE_Pos        (18U)
13199 #define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
13200 #define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
13201 #define SDIO_MASK_RXFIFOEIE_Pos        (19U)
13202 #define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
13203 #define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
13204 #define SDIO_MASK_TXDAVLIE_Pos         (20U)
13205 #define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
13206 #define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
13207 #define SDIO_MASK_RXDAVLIE_Pos         (21U)
13208 #define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
13209 #define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
13210 #define SDIO_MASK_SDIOITIE_Pos         (22U)
13211 #define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
13212 #define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
13213 #define SDIO_MASK_CEATAENDIE_Pos       (23U)
13214 #define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */
13215 #define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */
13216 
13217 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
13218 #define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)
13219 #define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
13220 #define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
13221 
13222 /******************  Bit definition for SDIO_FIFO register  *******************/
13223 #define SDIO_FIFO_FIFODATA_Pos         (0U)
13224 #define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
13225 #define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
13226 
13227 /******************************************************************************/
13228 /*                                                                            */
13229 /*                        Serial Peripheral Interface                         */
13230 /*                                                                            */
13231 /******************************************************************************/
13232 #define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */
13233 
13234 /*******************  Bit definition for SPI_CR1 register  ********************/
13235 #define SPI_CR1_CPHA_Pos            (0U)
13236 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
13237 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
13238 #define SPI_CR1_CPOL_Pos            (1U)
13239 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
13240 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
13241 #define SPI_CR1_MSTR_Pos            (2U)
13242 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
13243 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
13244 
13245 #define SPI_CR1_BR_Pos              (3U)
13246 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
13247 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
13248 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
13249 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
13250 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
13251 
13252 #define SPI_CR1_SPE_Pos             (6U)
13253 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
13254 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
13255 #define SPI_CR1_LSBFIRST_Pos        (7U)
13256 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
13257 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
13258 #define SPI_CR1_SSI_Pos             (8U)
13259 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
13260 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
13261 #define SPI_CR1_SSM_Pos             (9U)
13262 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
13263 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
13264 #define SPI_CR1_RXONLY_Pos          (10U)
13265 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
13266 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
13267 #define SPI_CR1_DFF_Pos             (11U)
13268 #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
13269 #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
13270 #define SPI_CR1_CRCNEXT_Pos         (12U)
13271 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
13272 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
13273 #define SPI_CR1_CRCEN_Pos           (13U)
13274 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
13275 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
13276 #define SPI_CR1_BIDIOE_Pos          (14U)
13277 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
13278 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
13279 #define SPI_CR1_BIDIMODE_Pos        (15U)
13280 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
13281 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
13282 
13283 /*******************  Bit definition for SPI_CR2 register  ********************/
13284 #define SPI_CR2_RXDMAEN_Pos         (0U)
13285 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
13286 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
13287 #define SPI_CR2_TXDMAEN_Pos         (1U)
13288 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
13289 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
13290 #define SPI_CR2_SSOE_Pos            (2U)
13291 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
13292 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
13293 #define SPI_CR2_FRF_Pos             (4U)
13294 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
13295 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
13296 #define SPI_CR2_ERRIE_Pos           (5U)
13297 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
13298 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
13299 #define SPI_CR2_RXNEIE_Pos          (6U)
13300 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
13301 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
13302 #define SPI_CR2_TXEIE_Pos           (7U)
13303 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
13304 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
13305 
13306 /********************  Bit definition for SPI_SR register  ********************/
13307 #define SPI_SR_RXNE_Pos             (0U)
13308 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
13309 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
13310 #define SPI_SR_TXE_Pos              (1U)
13311 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
13312 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
13313 #define SPI_SR_CHSIDE_Pos           (2U)
13314 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
13315 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
13316 #define SPI_SR_UDR_Pos              (3U)
13317 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
13318 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
13319 #define SPI_SR_CRCERR_Pos           (4U)
13320 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
13321 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
13322 #define SPI_SR_MODF_Pos             (5U)
13323 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
13324 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
13325 #define SPI_SR_OVR_Pos              (6U)
13326 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
13327 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
13328 #define SPI_SR_BSY_Pos              (7U)
13329 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
13330 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
13331 #define SPI_SR_FRE_Pos              (8U)
13332 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
13333 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
13334 
13335 /********************  Bit definition for SPI_DR register  ********************/
13336 #define SPI_DR_DR_Pos               (0U)
13337 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
13338 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
13339 
13340 /*******************  Bit definition for SPI_CRCPR register  ******************/
13341 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
13342 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
13343 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
13344 
13345 /******************  Bit definition for SPI_RXCRCR register  ******************/
13346 #define SPI_RXCRCR_RXCRC_Pos        (0U)
13347 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
13348 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
13349 
13350 /******************  Bit definition for SPI_TXCRCR register  ******************/
13351 #define SPI_TXCRCR_TXCRC_Pos        (0U)
13352 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
13353 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
13354 
13355 /******************  Bit definition for SPI_I2SCFGR register  *****************/
13356 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
13357 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
13358 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
13359 
13360 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
13361 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
13362 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
13363 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
13364 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
13365 
13366 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
13367 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
13368 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
13369 
13370 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
13371 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
13372 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
13373 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
13374 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
13375 
13376 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
13377 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
13378 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
13379 
13380 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
13381 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
13382 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
13383 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
13384 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
13385 
13386 #define SPI_I2SCFGR_I2SE_Pos        (10U)
13387 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
13388 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
13389 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
13390 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
13391 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
13392 
13393 /******************  Bit definition for SPI_I2SPR register  *******************/
13394 #define SPI_I2SPR_I2SDIV_Pos        (0U)
13395 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
13396 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
13397 #define SPI_I2SPR_ODD_Pos           (8U)
13398 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
13399 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
13400 #define SPI_I2SPR_MCKOE_Pos         (9U)
13401 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
13402 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
13403 
13404 /******************************************************************************/
13405 /*                                                                            */
13406 /*                                 SYSCFG                                     */
13407 /*                                                                            */
13408 /******************************************************************************/
13409 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
13410 #define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)
13411 #define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
13412 #define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
13413 #define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
13414 #define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
13415 #define SYSCFG_MEMRMP_MEM_MODE_2             (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
13416 #define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)
13417 #define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
13418 #define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */
13419 #define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)
13420 #define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
13421 #define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */
13422 #define SYSCFG_MEMRMP_SWP_FMC_0              (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
13423 /* Legacy Defines */
13424 #define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC
13425 /******************  Bit definition for SYSCFG_PMC register  ******************/
13426 #define SYSCFG_PMC_ADCxDC2_Pos               (16U)
13427 #define SYSCFG_PMC_ADCxDC2_Msk               (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */
13428 #define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
13429 #define SYSCFG_PMC_ADC1DC2_Pos               (16U)
13430 #define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
13431 #define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
13432 #define SYSCFG_PMC_ADC2DC2_Pos               (17U)
13433 #define SYSCFG_PMC_ADC2DC2_Msk               (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */
13434 #define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
13435 #define SYSCFG_PMC_ADC3DC2_Pos               (18U)
13436 #define SYSCFG_PMC_ADC3DC2_Msk               (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */
13437 #define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
13438 #define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)
13439 #define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
13440 #define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */
13441 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
13442 #define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL
13443 
13444 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
13445 #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
13446 #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
13447 #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
13448 #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
13449 #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
13450 #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
13451 #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
13452 #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
13453 #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
13454 #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
13455 #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
13456 #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
13457 /**
13458   * @brief   EXTI0 configuration
13459   */
13460 #define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
13461 #define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
13462 #define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
13463 #define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
13464 #define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
13465 #define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
13466 #define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
13467 #define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
13468 #define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
13469 #define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */
13470 #define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */
13471 
13472 /**
13473   * @brief   EXTI1 configuration
13474   */
13475 #define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
13476 #define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
13477 #define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
13478 #define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
13479 #define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
13480 #define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
13481 #define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
13482 #define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
13483 #define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
13484 #define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */
13485 #define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */
13486 
13487 /**
13488   * @brief   EXTI2 configuration
13489   */
13490 #define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
13491 #define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
13492 #define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
13493 #define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
13494 #define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
13495 #define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
13496 #define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
13497 #define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
13498 #define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
13499 #define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */
13500 #define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */
13501 
13502 /**
13503   * @brief   EXTI3 configuration
13504   */
13505 #define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
13506 #define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
13507 #define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
13508 #define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
13509 #define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
13510 #define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
13511 #define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
13512 #define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
13513 #define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
13514 #define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */
13515 #define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */
13516 
13517 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
13518 #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
13519 #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
13520 #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
13521 #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
13522 #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
13523 #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
13524 #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
13525 #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
13526 #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
13527 #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
13528 #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
13529 #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
13530 
13531 /**
13532   * @brief   EXTI4 configuration
13533   */
13534 #define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
13535 #define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
13536 #define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
13537 #define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
13538 #define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
13539 #define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
13540 #define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
13541 #define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
13542 #define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
13543 #define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */
13544 #define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */
13545 
13546 /**
13547   * @brief   EXTI5 configuration
13548   */
13549 #define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
13550 #define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
13551 #define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
13552 #define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
13553 #define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
13554 #define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
13555 #define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
13556 #define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
13557 #define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
13558 #define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */
13559 #define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */
13560 
13561 /**
13562   * @brief   EXTI6 configuration
13563   */
13564 #define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
13565 #define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
13566 #define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
13567 #define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
13568 #define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
13569 #define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
13570 #define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
13571 #define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
13572 #define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
13573 #define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */
13574 #define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */
13575 
13576 /**
13577   * @brief   EXTI7 configuration
13578   */
13579 #define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
13580 #define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
13581 #define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
13582 #define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
13583 #define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
13584 #define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
13585 #define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
13586 #define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
13587 #define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
13588 #define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */
13589 #define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */
13590 
13591 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
13592 #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
13593 #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
13594 #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
13595 #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
13596 #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
13597 #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
13598 #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
13599 #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
13600 #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
13601 #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
13602 #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
13603 #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
13604 
13605 /**
13606   * @brief   EXTI8 configuration
13607   */
13608 #define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
13609 #define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
13610 #define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
13611 #define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
13612 #define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
13613 #define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
13614 #define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
13615 #define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
13616 #define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
13617 #define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */
13618 
13619 /**
13620   * @brief   EXTI9 configuration
13621   */
13622 #define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
13623 #define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
13624 #define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
13625 #define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
13626 #define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
13627 #define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
13628 #define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
13629 #define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
13630 #define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
13631 #define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */
13632 
13633 /**
13634   * @brief   EXTI10 configuration
13635   */
13636 #define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
13637 #define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
13638 #define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
13639 #define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
13640 #define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
13641 #define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
13642 #define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
13643 #define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
13644 #define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
13645 #define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */
13646 
13647 /**
13648   * @brief   EXTI11 configuration
13649   */
13650 #define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
13651 #define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
13652 #define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
13653 #define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
13654 #define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
13655 #define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
13656 #define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
13657 #define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
13658 #define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
13659 #define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */
13660 
13661 
13662 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
13663 #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
13664 #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
13665 #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
13666 #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
13667 #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
13668 #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
13669 #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
13670 #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
13671 #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
13672 #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
13673 #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
13674 #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
13675 
13676 /**
13677   * @brief   EXTI12 configuration
13678   */
13679 #define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
13680 #define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
13681 #define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
13682 #define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
13683 #define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
13684 #define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
13685 #define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
13686 #define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
13687 #define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */
13688 #define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */
13689 
13690 /**
13691   * @brief   EXTI13 configuration
13692   */
13693 #define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
13694 #define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
13695 #define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
13696 #define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
13697 #define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
13698 #define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
13699 #define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
13700 #define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
13701 #define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */
13702 #define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */
13703 
13704 /**
13705   * @brief   EXTI14 configuration
13706   */
13707 #define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
13708 #define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
13709 #define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
13710 #define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
13711 #define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
13712 #define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
13713 #define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
13714 #define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
13715 #define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */
13716 #define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */
13717 
13718 /**
13719   * @brief   EXTI15 configuration
13720   */
13721 #define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
13722 #define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
13723 #define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
13724 #define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
13725 #define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
13726 #define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
13727 #define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
13728 #define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
13729 #define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */
13730 #define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */
13731 
13732 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
13733 #define SYSCFG_CMPCR_CMP_PD_Pos              (0U)
13734 #define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
13735 #define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
13736 #define SYSCFG_CMPCR_READY_Pos               (8U)
13737 #define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
13738 #define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
13739 
13740 /******************************************************************************/
13741 /*                                                                            */
13742 /*                                    TIM                                     */
13743 /*                                                                            */
13744 /******************************************************************************/
13745 /*******************  Bit definition for TIM_CR1 register  ********************/
13746 #define TIM_CR1_CEN_Pos           (0U)
13747 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
13748 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
13749 #define TIM_CR1_UDIS_Pos          (1U)
13750 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
13751 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
13752 #define TIM_CR1_URS_Pos           (2U)
13753 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
13754 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
13755 #define TIM_CR1_OPM_Pos           (3U)
13756 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
13757 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
13758 #define TIM_CR1_DIR_Pos           (4U)
13759 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
13760 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
13761 
13762 #define TIM_CR1_CMS_Pos           (5U)
13763 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
13764 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
13765 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
13766 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
13767 
13768 #define TIM_CR1_ARPE_Pos          (7U)
13769 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
13770 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
13771 
13772 #define TIM_CR1_CKD_Pos           (8U)
13773 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
13774 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
13775 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
13776 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
13777 
13778 /*******************  Bit definition for TIM_CR2 register  ********************/
13779 #define TIM_CR2_CCPC_Pos          (0U)
13780 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
13781 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
13782 #define TIM_CR2_CCUS_Pos          (2U)
13783 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
13784 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
13785 #define TIM_CR2_CCDS_Pos          (3U)
13786 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
13787 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
13788 
13789 #define TIM_CR2_MMS_Pos           (4U)
13790 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
13791 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
13792 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
13793 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
13794 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
13795 
13796 #define TIM_CR2_TI1S_Pos          (7U)
13797 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
13798 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
13799 #define TIM_CR2_OIS1_Pos          (8U)
13800 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
13801 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
13802 #define TIM_CR2_OIS1N_Pos         (9U)
13803 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
13804 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
13805 #define TIM_CR2_OIS2_Pos          (10U)
13806 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
13807 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
13808 #define TIM_CR2_OIS2N_Pos         (11U)
13809 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
13810 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
13811 #define TIM_CR2_OIS3_Pos          (12U)
13812 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
13813 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
13814 #define TIM_CR2_OIS3N_Pos         (13U)
13815 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
13816 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
13817 #define TIM_CR2_OIS4_Pos          (14U)
13818 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
13819 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
13820 
13821 /*******************  Bit definition for TIM_SMCR register  *******************/
13822 #define TIM_SMCR_SMS_Pos          (0U)
13823 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
13824 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
13825 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
13826 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
13827 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
13828 
13829 #define TIM_SMCR_TS_Pos           (4U)
13830 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
13831 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
13832 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
13833 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
13834 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
13835 
13836 #define TIM_SMCR_MSM_Pos          (7U)
13837 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
13838 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
13839 
13840 #define TIM_SMCR_ETF_Pos          (8U)
13841 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
13842 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
13843 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
13844 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
13845 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
13846 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
13847 
13848 #define TIM_SMCR_ETPS_Pos         (12U)
13849 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
13850 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
13851 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
13852 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
13853 
13854 #define TIM_SMCR_ECE_Pos          (14U)
13855 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
13856 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
13857 #define TIM_SMCR_ETP_Pos          (15U)
13858 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
13859 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
13860 
13861 /*******************  Bit definition for TIM_DIER register  *******************/
13862 #define TIM_DIER_UIE_Pos          (0U)
13863 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
13864 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
13865 #define TIM_DIER_CC1IE_Pos        (1U)
13866 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
13867 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
13868 #define TIM_DIER_CC2IE_Pos        (2U)
13869 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
13870 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
13871 #define TIM_DIER_CC3IE_Pos        (3U)
13872 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
13873 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
13874 #define TIM_DIER_CC4IE_Pos        (4U)
13875 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
13876 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
13877 #define TIM_DIER_COMIE_Pos        (5U)
13878 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
13879 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
13880 #define TIM_DIER_TIE_Pos          (6U)
13881 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
13882 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
13883 #define TIM_DIER_BIE_Pos          (7U)
13884 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
13885 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
13886 #define TIM_DIER_UDE_Pos          (8U)
13887 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
13888 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
13889 #define TIM_DIER_CC1DE_Pos        (9U)
13890 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
13891 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
13892 #define TIM_DIER_CC2DE_Pos        (10U)
13893 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
13894 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
13895 #define TIM_DIER_CC3DE_Pos        (11U)
13896 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
13897 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
13898 #define TIM_DIER_CC4DE_Pos        (12U)
13899 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
13900 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
13901 #define TIM_DIER_COMDE_Pos        (13U)
13902 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
13903 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
13904 #define TIM_DIER_TDE_Pos          (14U)
13905 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
13906 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
13907 
13908 /********************  Bit definition for TIM_SR register  ********************/
13909 #define TIM_SR_UIF_Pos            (0U)
13910 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
13911 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
13912 #define TIM_SR_CC1IF_Pos          (1U)
13913 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
13914 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
13915 #define TIM_SR_CC2IF_Pos          (2U)
13916 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
13917 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
13918 #define TIM_SR_CC3IF_Pos          (3U)
13919 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
13920 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
13921 #define TIM_SR_CC4IF_Pos          (4U)
13922 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
13923 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
13924 #define TIM_SR_COMIF_Pos          (5U)
13925 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
13926 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
13927 #define TIM_SR_TIF_Pos            (6U)
13928 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
13929 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
13930 #define TIM_SR_BIF_Pos            (7U)
13931 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
13932 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
13933 #define TIM_SR_CC1OF_Pos          (9U)
13934 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
13935 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
13936 #define TIM_SR_CC2OF_Pos          (10U)
13937 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
13938 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
13939 #define TIM_SR_CC3OF_Pos          (11U)
13940 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
13941 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
13942 #define TIM_SR_CC4OF_Pos          (12U)
13943 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
13944 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
13945 
13946 /*******************  Bit definition for TIM_EGR register  ********************/
13947 #define TIM_EGR_UG_Pos            (0U)
13948 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
13949 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
13950 #define TIM_EGR_CC1G_Pos          (1U)
13951 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
13952 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
13953 #define TIM_EGR_CC2G_Pos          (2U)
13954 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
13955 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
13956 #define TIM_EGR_CC3G_Pos          (3U)
13957 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
13958 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
13959 #define TIM_EGR_CC4G_Pos          (4U)
13960 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
13961 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
13962 #define TIM_EGR_COMG_Pos          (5U)
13963 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
13964 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
13965 #define TIM_EGR_TG_Pos            (6U)
13966 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
13967 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
13968 #define TIM_EGR_BG_Pos            (7U)
13969 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
13970 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
13971 
13972 /******************  Bit definition for TIM_CCMR1 register  *******************/
13973 #define TIM_CCMR1_CC1S_Pos        (0U)
13974 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
13975 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13976 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
13977 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
13978 
13979 #define TIM_CCMR1_OC1FE_Pos       (2U)
13980 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
13981 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
13982 #define TIM_CCMR1_OC1PE_Pos       (3U)
13983 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
13984 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
13985 
13986 #define TIM_CCMR1_OC1M_Pos        (4U)
13987 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
13988 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
13989 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
13990 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
13991 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
13992 
13993 #define TIM_CCMR1_OC1CE_Pos       (7U)
13994 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
13995 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
13996 
13997 #define TIM_CCMR1_CC2S_Pos        (8U)
13998 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
13999 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
14000 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
14001 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
14002 
14003 #define TIM_CCMR1_OC2FE_Pos       (10U)
14004 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
14005 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
14006 #define TIM_CCMR1_OC2PE_Pos       (11U)
14007 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
14008 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
14009 
14010 #define TIM_CCMR1_OC2M_Pos        (12U)
14011 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
14012 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
14013 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
14014 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
14015 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
14016 
14017 #define TIM_CCMR1_OC2CE_Pos       (15U)
14018 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
14019 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
14020 
14021 /*----------------------------------------------------------------------------*/
14022 
14023 #define TIM_CCMR1_IC1PSC_Pos      (2U)
14024 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
14025 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
14026 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
14027 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
14028 
14029 #define TIM_CCMR1_IC1F_Pos        (4U)
14030 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
14031 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
14032 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
14033 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
14034 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
14035 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
14036 
14037 #define TIM_CCMR1_IC2PSC_Pos      (10U)
14038 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
14039 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
14040 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
14041 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
14042 
14043 #define TIM_CCMR1_IC2F_Pos        (12U)
14044 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
14045 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
14046 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
14047 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
14048 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
14049 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
14050 
14051 /******************  Bit definition for TIM_CCMR2 register  *******************/
14052 #define TIM_CCMR2_CC3S_Pos        (0U)
14053 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
14054 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
14055 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
14056 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
14057 
14058 #define TIM_CCMR2_OC3FE_Pos       (2U)
14059 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
14060 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
14061 #define TIM_CCMR2_OC3PE_Pos       (3U)
14062 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
14063 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
14064 
14065 #define TIM_CCMR2_OC3M_Pos        (4U)
14066 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
14067 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
14068 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
14069 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
14070 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
14071 
14072 #define TIM_CCMR2_OC3CE_Pos       (7U)
14073 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
14074 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
14075 
14076 #define TIM_CCMR2_CC4S_Pos        (8U)
14077 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
14078 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
14079 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
14080 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
14081 
14082 #define TIM_CCMR2_OC4FE_Pos       (10U)
14083 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
14084 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
14085 #define TIM_CCMR2_OC4PE_Pos       (11U)
14086 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
14087 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
14088 
14089 #define TIM_CCMR2_OC4M_Pos        (12U)
14090 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
14091 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14092 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
14093 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
14094 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
14095 
14096 #define TIM_CCMR2_OC4CE_Pos       (15U)
14097 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
14098 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
14099 
14100 /*----------------------------------------------------------------------------*/
14101 
14102 #define TIM_CCMR2_IC3PSC_Pos      (2U)
14103 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
14104 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
14105 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
14106 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
14107 
14108 #define TIM_CCMR2_IC3F_Pos        (4U)
14109 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
14110 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
14111 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
14112 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
14113 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
14114 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
14115 
14116 #define TIM_CCMR2_IC4PSC_Pos      (10U)
14117 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
14118 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
14119 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
14120 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
14121 
14122 #define TIM_CCMR2_IC4F_Pos        (12U)
14123 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
14124 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
14125 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
14126 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
14127 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
14128 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
14129 
14130 /*******************  Bit definition for TIM_CCER register  *******************/
14131 #define TIM_CCER_CC1E_Pos         (0U)
14132 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
14133 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
14134 #define TIM_CCER_CC1P_Pos         (1U)
14135 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
14136 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
14137 #define TIM_CCER_CC1NE_Pos        (2U)
14138 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
14139 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
14140 #define TIM_CCER_CC1NP_Pos        (3U)
14141 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
14142 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
14143 #define TIM_CCER_CC2E_Pos         (4U)
14144 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
14145 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
14146 #define TIM_CCER_CC2P_Pos         (5U)
14147 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
14148 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
14149 #define TIM_CCER_CC2NE_Pos        (6U)
14150 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
14151 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
14152 #define TIM_CCER_CC2NP_Pos        (7U)
14153 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
14154 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
14155 #define TIM_CCER_CC3E_Pos         (8U)
14156 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
14157 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
14158 #define TIM_CCER_CC3P_Pos         (9U)
14159 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
14160 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
14161 #define TIM_CCER_CC3NE_Pos        (10U)
14162 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
14163 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
14164 #define TIM_CCER_CC3NP_Pos        (11U)
14165 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
14166 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
14167 #define TIM_CCER_CC4E_Pos         (12U)
14168 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
14169 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
14170 #define TIM_CCER_CC4P_Pos         (13U)
14171 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
14172 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
14173 #define TIM_CCER_CC4NP_Pos        (15U)
14174 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
14175 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
14176 
14177 /*******************  Bit definition for TIM_CNT register  ********************/
14178 #define TIM_CNT_CNT_Pos           (0U)
14179 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
14180 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
14181 
14182 /*******************  Bit definition for TIM_PSC register  ********************/
14183 #define TIM_PSC_PSC_Pos           (0U)
14184 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
14185 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
14186 
14187 /*******************  Bit definition for TIM_ARR register  ********************/
14188 #define TIM_ARR_ARR_Pos           (0U)
14189 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
14190 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
14191 
14192 /*******************  Bit definition for TIM_RCR register  ********************/
14193 #define TIM_RCR_REP_Pos           (0U)
14194 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
14195 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
14196 
14197 /*******************  Bit definition for TIM_CCR1 register  *******************/
14198 #define TIM_CCR1_CCR1_Pos         (0U)
14199 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
14200 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
14201 
14202 /*******************  Bit definition for TIM_CCR2 register  *******************/
14203 #define TIM_CCR2_CCR2_Pos         (0U)
14204 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
14205 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
14206 
14207 /*******************  Bit definition for TIM_CCR3 register  *******************/
14208 #define TIM_CCR3_CCR3_Pos         (0U)
14209 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
14210 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
14211 
14212 /*******************  Bit definition for TIM_CCR4 register  *******************/
14213 #define TIM_CCR4_CCR4_Pos         (0U)
14214 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
14215 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
14216 
14217 /*******************  Bit definition for TIM_BDTR register  *******************/
14218 #define TIM_BDTR_DTG_Pos          (0U)
14219 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
14220 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
14221 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
14222 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
14223 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
14224 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
14225 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
14226 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
14227 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
14228 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
14229 
14230 #define TIM_BDTR_LOCK_Pos         (8U)
14231 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
14232 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
14233 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
14234 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
14235 
14236 #define TIM_BDTR_OSSI_Pos         (10U)
14237 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
14238 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
14239 #define TIM_BDTR_OSSR_Pos         (11U)
14240 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
14241 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
14242 #define TIM_BDTR_BKE_Pos          (12U)
14243 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
14244 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
14245 #define TIM_BDTR_BKP_Pos          (13U)
14246 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
14247 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
14248 #define TIM_BDTR_AOE_Pos          (14U)
14249 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
14250 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
14251 #define TIM_BDTR_MOE_Pos          (15U)
14252 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
14253 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
14254 
14255 /*******************  Bit definition for TIM_DCR register  ********************/
14256 #define TIM_DCR_DBA_Pos           (0U)
14257 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
14258 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
14259 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
14260 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
14261 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
14262 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
14263 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
14264 
14265 #define TIM_DCR_DBL_Pos           (8U)
14266 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
14267 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
14268 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
14269 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
14270 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
14271 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
14272 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
14273 
14274 /*******************  Bit definition for TIM_DMAR register  *******************/
14275 #define TIM_DMAR_DMAB_Pos         (0U)
14276 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
14277 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
14278 
14279 /*******************  Bit definition for TIM_OR register  *********************/
14280 #define TIM_OR_TI1_RMP_Pos        (0U)
14281 #define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
14282 #define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
14283 #define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
14284 #define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
14285 
14286 #define TIM_OR_TI4_RMP_Pos        (6U)
14287 #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
14288 #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
14289 #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
14290 #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
14291 #define TIM_OR_ITR1_RMP_Pos       (10U)
14292 #define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
14293 #define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
14294 #define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
14295 #define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
14296 
14297 
14298 /******************************************************************************/
14299 /*                                                                            */
14300 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
14301 /*                                                                            */
14302 /******************************************************************************/
14303 /*******************  Bit definition for USART_SR register  *******************/
14304 #define USART_SR_PE_Pos               (0U)
14305 #define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
14306 #define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
14307 #define USART_SR_FE_Pos               (1U)
14308 #define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
14309 #define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
14310 #define USART_SR_NE_Pos               (2U)
14311 #define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
14312 #define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
14313 #define USART_SR_ORE_Pos              (3U)
14314 #define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
14315 #define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
14316 #define USART_SR_IDLE_Pos             (4U)
14317 #define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
14318 #define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
14319 #define USART_SR_RXNE_Pos             (5U)
14320 #define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
14321 #define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
14322 #define USART_SR_TC_Pos               (6U)
14323 #define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
14324 #define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
14325 #define USART_SR_TXE_Pos              (7U)
14326 #define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
14327 #define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
14328 #define USART_SR_LBD_Pos              (8U)
14329 #define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
14330 #define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
14331 #define USART_SR_CTS_Pos              (9U)
14332 #define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
14333 #define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
14334 
14335 /*******************  Bit definition for USART_DR register  *******************/
14336 #define USART_DR_DR_Pos               (0U)
14337 #define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
14338 #define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
14339 
14340 /******************  Bit definition for USART_BRR register  *******************/
14341 #define USART_BRR_DIV_Fraction_Pos    (0U)
14342 #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
14343 #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
14344 #define USART_BRR_DIV_Mantissa_Pos    (4U)
14345 #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
14346 #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
14347 
14348 /******************  Bit definition for USART_CR1 register  *******************/
14349 #define USART_CR1_SBK_Pos             (0U)
14350 #define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
14351 #define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
14352 #define USART_CR1_RWU_Pos             (1U)
14353 #define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
14354 #define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
14355 #define USART_CR1_RE_Pos              (2U)
14356 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
14357 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
14358 #define USART_CR1_TE_Pos              (3U)
14359 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
14360 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
14361 #define USART_CR1_IDLEIE_Pos          (4U)
14362 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
14363 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
14364 #define USART_CR1_RXNEIE_Pos          (5U)
14365 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
14366 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
14367 #define USART_CR1_TCIE_Pos            (6U)
14368 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
14369 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
14370 #define USART_CR1_TXEIE_Pos           (7U)
14371 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
14372 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
14373 #define USART_CR1_PEIE_Pos            (8U)
14374 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
14375 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
14376 #define USART_CR1_PS_Pos              (9U)
14377 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
14378 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
14379 #define USART_CR1_PCE_Pos             (10U)
14380 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
14381 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
14382 #define USART_CR1_WAKE_Pos            (11U)
14383 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
14384 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
14385 #define USART_CR1_M_Pos               (12U)
14386 #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
14387 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
14388 #define USART_CR1_UE_Pos              (13U)
14389 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
14390 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
14391 #define USART_CR1_OVER8_Pos           (15U)
14392 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
14393 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
14394 
14395 /******************  Bit definition for USART_CR2 register  *******************/
14396 #define USART_CR2_ADD_Pos             (0U)
14397 #define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
14398 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
14399 #define USART_CR2_LBDL_Pos            (5U)
14400 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
14401 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
14402 #define USART_CR2_LBDIE_Pos           (6U)
14403 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
14404 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
14405 #define USART_CR2_LBCL_Pos            (8U)
14406 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
14407 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
14408 #define USART_CR2_CPHA_Pos            (9U)
14409 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
14410 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
14411 #define USART_CR2_CPOL_Pos            (10U)
14412 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
14413 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
14414 #define USART_CR2_CLKEN_Pos           (11U)
14415 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
14416 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
14417 
14418 #define USART_CR2_STOP_Pos            (12U)
14419 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
14420 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
14421 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
14422 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
14423 
14424 #define USART_CR2_LINEN_Pos           (14U)
14425 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
14426 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
14427 
14428 /******************  Bit definition for USART_CR3 register  *******************/
14429 #define USART_CR3_EIE_Pos             (0U)
14430 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
14431 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
14432 #define USART_CR3_IREN_Pos            (1U)
14433 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
14434 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
14435 #define USART_CR3_IRLP_Pos            (2U)
14436 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
14437 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
14438 #define USART_CR3_HDSEL_Pos           (3U)
14439 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
14440 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
14441 #define USART_CR3_NACK_Pos            (4U)
14442 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
14443 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
14444 #define USART_CR3_SCEN_Pos            (5U)
14445 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
14446 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
14447 #define USART_CR3_DMAR_Pos            (6U)
14448 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
14449 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
14450 #define USART_CR3_DMAT_Pos            (7U)
14451 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
14452 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
14453 #define USART_CR3_RTSE_Pos            (8U)
14454 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
14455 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
14456 #define USART_CR3_CTSE_Pos            (9U)
14457 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
14458 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
14459 #define USART_CR3_CTSIE_Pos           (10U)
14460 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
14461 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
14462 #define USART_CR3_ONEBIT_Pos          (11U)
14463 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
14464 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
14465 
14466 /******************  Bit definition for USART_GTPR register  ******************/
14467 #define USART_GTPR_PSC_Pos            (0U)
14468 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
14469 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
14470 #define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
14471 #define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
14472 #define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
14473 #define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
14474 #define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
14475 #define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
14476 #define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
14477 #define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
14478 
14479 #define USART_GTPR_GT_Pos             (8U)
14480 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
14481 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
14482 
14483 /******************************************************************************/
14484 /*                                                                            */
14485 /*                            Window WATCHDOG                                 */
14486 /*                                                                            */
14487 /******************************************************************************/
14488 /*******************  Bit definition for WWDG_CR register  ********************/
14489 #define WWDG_CR_T_Pos           (0U)
14490 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
14491 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
14492 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
14493 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
14494 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
14495 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
14496 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
14497 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
14498 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
14499 /* Legacy defines */
14500 #define  WWDG_CR_T0                          WWDG_CR_T_0
14501 #define  WWDG_CR_T1                          WWDG_CR_T_1
14502 #define  WWDG_CR_T2                          WWDG_CR_T_2
14503 #define  WWDG_CR_T3                          WWDG_CR_T_3
14504 #define  WWDG_CR_T4                          WWDG_CR_T_4
14505 #define  WWDG_CR_T5                          WWDG_CR_T_5
14506 #define  WWDG_CR_T6                          WWDG_CR_T_6
14507 
14508 #define WWDG_CR_WDGA_Pos        (7U)
14509 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
14510 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
14511 
14512 /*******************  Bit definition for WWDG_CFR register  *******************/
14513 #define WWDG_CFR_W_Pos          (0U)
14514 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
14515 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
14516 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
14517 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
14518 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
14519 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
14520 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
14521 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
14522 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
14523 /* Legacy defines */
14524 #define  WWDG_CFR_W0                         WWDG_CFR_W_0
14525 #define  WWDG_CFR_W1                         WWDG_CFR_W_1
14526 #define  WWDG_CFR_W2                         WWDG_CFR_W_2
14527 #define  WWDG_CFR_W3                         WWDG_CFR_W_3
14528 #define  WWDG_CFR_W4                         WWDG_CFR_W_4
14529 #define  WWDG_CFR_W5                         WWDG_CFR_W_5
14530 #define  WWDG_CFR_W6                         WWDG_CFR_W_6
14531 
14532 #define WWDG_CFR_WDGTB_Pos      (7U)
14533 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
14534 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
14535 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
14536 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
14537 /* Legacy defines */
14538 #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
14539 #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
14540 
14541 #define WWDG_CFR_EWI_Pos        (9U)
14542 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
14543 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
14544 
14545 /*******************  Bit definition for WWDG_SR register  ********************/
14546 #define WWDG_SR_EWIF_Pos        (0U)
14547 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
14548 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
14549 
14550 
14551 /******************************************************************************/
14552 /*                                                                            */
14553 /*                                DBG                                         */
14554 /*                                                                            */
14555 /******************************************************************************/
14556 /********************  Bit definition for DBGMCU_IDCODE register  *************/
14557 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
14558 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
14559 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
14560 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
14561 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
14562 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
14563 
14564 /********************  Bit definition for DBGMCU_CR register  *****************/
14565 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
14566 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
14567 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
14568 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
14569 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
14570 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
14571 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
14572 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
14573 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
14574 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
14575 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
14576 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
14577 
14578 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
14579 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
14580 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
14581 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
14582 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
14583 
14584 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
14585 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
14586 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
14587 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
14588 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
14589 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
14590 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
14591 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
14592 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
14593 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
14594 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
14595 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
14596 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
14597 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
14598 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
14599 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
14600 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
14601 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
14602 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
14603 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)
14604 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
14605 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14606 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)
14607 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
14608 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14609 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
14610 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
14611 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14612 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
14613 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
14614 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14615 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
14616 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
14617 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14618 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
14619 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
14620 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14621 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
14622 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
14623 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14624 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
14625 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
14626 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14627 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)
14628 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
14629 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14630 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
14631 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
14632 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14633 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
14634 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
14635 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14636 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
14637 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
14638 
14639 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
14640 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
14641 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
14642 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14643 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
14644 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
14645 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14646 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
14647 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
14648 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14649 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)
14650 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
14651 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14652 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
14653 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
14654 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14655 
14656 /******************************************************************************/
14657 /*                                                                            */
14658 /*                Ethernet MAC Registers bits definitions                     */
14659 /*                                                                            */
14660 /******************************************************************************/
14661 /* Bit definition for Ethernet MAC Control Register register */
14662 #define ETH_MACCR_WD_Pos                              (23U)
14663 #define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
14664 #define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
14665 #define ETH_MACCR_JD_Pos                              (22U)
14666 #define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
14667 #define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
14668 #define ETH_MACCR_IFG_Pos                             (17U)
14669 #define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
14670 #define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
14671 #define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
14672 #define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
14673 #define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
14674 #define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
14675 #define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
14676 #define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
14677 #define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
14678 #define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
14679 #define ETH_MACCR_CSD_Pos                             (16U)
14680 #define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
14681 #define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
14682 #define ETH_MACCR_FES_Pos                             (14U)
14683 #define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
14684 #define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
14685 #define ETH_MACCR_ROD_Pos                             (13U)
14686 #define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
14687 #define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
14688 #define ETH_MACCR_LM_Pos                              (12U)
14689 #define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
14690 #define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
14691 #define ETH_MACCR_DM_Pos                              (11U)
14692 #define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
14693 #define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
14694 #define ETH_MACCR_IPCO_Pos                            (10U)
14695 #define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
14696 #define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
14697 #define ETH_MACCR_RD_Pos                              (9U)
14698 #define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
14699 #define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
14700 #define ETH_MACCR_APCS_Pos                            (7U)
14701 #define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
14702 #define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
14703 #define ETH_MACCR_BL_Pos                              (5U)
14704 #define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
14705 #define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
14706                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
14707 #define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
14708 #define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
14709 #define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
14710 #define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */
14711 #define ETH_MACCR_DC_Pos                              (4U)
14712 #define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
14713 #define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
14714 #define ETH_MACCR_TE_Pos                              (3U)
14715 #define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
14716 #define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
14717 #define ETH_MACCR_RE_Pos                              (2U)
14718 #define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
14719 #define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
14720 
14721 /* Bit definition for Ethernet MAC Frame Filter Register */
14722 #define ETH_MACFFR_RA_Pos                             (31U)
14723 #define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
14724 #define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
14725 #define ETH_MACFFR_HPF_Pos                            (10U)
14726 #define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
14727 #define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
14728 #define ETH_MACFFR_SAF_Pos                            (9U)
14729 #define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
14730 #define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
14731 #define ETH_MACFFR_SAIF_Pos                           (8U)
14732 #define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
14733 #define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */
14734 #define ETH_MACFFR_PCF_Pos                            (6U)
14735 #define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
14736 #define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
14737 #define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)
14738 #define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
14739 #define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
14740 #define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)
14741 #define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
14742 #define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
14743 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)
14744 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
14745 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
14746 #define ETH_MACFFR_BFD_Pos                            (5U)
14747 #define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
14748 #define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */
14749 #define ETH_MACFFR_PAM_Pos                            (4U)
14750 #define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
14751 #define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
14752 #define ETH_MACFFR_DAIF_Pos                           (3U)
14753 #define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
14754 #define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
14755 #define ETH_MACFFR_HM_Pos                             (2U)
14756 #define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
14757 #define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */
14758 #define ETH_MACFFR_HU_Pos                             (1U)
14759 #define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
14760 #define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
14761 #define ETH_MACFFR_PM_Pos                             (0U)
14762 #define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
14763 #define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
14764 
14765 /* Bit definition for Ethernet MAC Hash Table High Register */
14766 #define ETH_MACHTHR_HTH_Pos                           (0U)
14767 #define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
14768 #define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
14769 
14770 /* Bit definition for Ethernet MAC Hash Table Low Register */
14771 #define ETH_MACHTLR_HTL_Pos                           (0U)
14772 #define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
14773 #define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
14774 
14775 /* Bit definition for Ethernet MAC MII Address Register */
14776 #define ETH_MACMIIAR_PA_Pos                           (11U)
14777 #define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
14778 #define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
14779 #define ETH_MACMIIAR_MR_Pos                           (6U)
14780 #define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
14781 #define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
14782 #define ETH_MACMIIAR_CR_Pos                           (2U)
14783 #define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
14784 #define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
14785 #define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
14786 #define ETH_MACMIIAR_CR_Div62_Pos                     (2U)
14787 #define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
14788 #define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
14789 #define ETH_MACMIIAR_CR_Div16_Pos                     (3U)
14790 #define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
14791 #define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
14792 #define ETH_MACMIIAR_CR_Div26_Pos                     (2U)
14793 #define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
14794 #define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
14795 #define ETH_MACMIIAR_CR_Div102_Pos                    (4U)
14796 #define ETH_MACMIIAR_CR_Div102_Msk                    (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
14797 #define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
14798 #define ETH_MACMIIAR_MW_Pos                           (1U)
14799 #define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
14800 #define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
14801 #define ETH_MACMIIAR_MB_Pos                           (0U)
14802 #define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
14803 #define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */
14804 
14805 /* Bit definition for Ethernet MAC MII Data Register */
14806 #define ETH_MACMIIDR_MD_Pos                           (0U)
14807 #define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
14808 #define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
14809 
14810 /* Bit definition for Ethernet MAC Flow Control Register */
14811 #define ETH_MACFCR_PT_Pos                             (16U)
14812 #define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
14813 #define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
14814 #define ETH_MACFCR_ZQPD_Pos                           (7U)
14815 #define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
14816 #define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
14817 #define ETH_MACFCR_PLT_Pos                            (4U)
14818 #define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
14819 #define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
14820 #define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */
14821 #define ETH_MACFCR_PLT_Minus28_Pos                    (4U)
14822 #define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
14823 #define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */
14824 #define ETH_MACFCR_PLT_Minus144_Pos                   (5U)
14825 #define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
14826 #define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
14827 #define ETH_MACFCR_PLT_Minus256_Pos                   (4U)
14828 #define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
14829 #define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
14830 #define ETH_MACFCR_UPFD_Pos                           (3U)
14831 #define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
14832 #define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
14833 #define ETH_MACFCR_RFCE_Pos                           (2U)
14834 #define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
14835 #define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
14836 #define ETH_MACFCR_TFCE_Pos                           (1U)
14837 #define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
14838 #define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
14839 #define ETH_MACFCR_FCBBPA_Pos                         (0U)
14840 #define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
14841 #define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
14842 
14843 /* Bit definition for Ethernet MAC VLAN Tag Register */
14844 #define ETH_MACVLANTR_VLANTC_Pos                      (16U)
14845 #define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
14846 #define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
14847 #define ETH_MACVLANTR_VLANTI_Pos                      (0U)
14848 #define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
14849 #define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
14850 
14851 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
14852 #define ETH_MACRWUFFR_D_Pos                           (0U)
14853 #define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
14854 #define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
14855 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
14856    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
14857 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
14858    Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
14859    Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
14860    Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
14861    Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
14862                               RSVD - Filter1 Command - RSVD - Filter0 Command
14863    Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
14864    Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
14865    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
14866 
14867 /* Bit definition for Ethernet MAC PMT Control and Status Register */
14868 #define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)
14869 #define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
14870 #define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
14871 #define ETH_MACPMTCSR_GU_Pos                          (9U)
14872 #define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
14873 #define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */
14874 #define ETH_MACPMTCSR_WFR_Pos                         (6U)
14875 #define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
14876 #define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */
14877 #define ETH_MACPMTCSR_MPR_Pos                         (5U)
14878 #define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
14879 #define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */
14880 #define ETH_MACPMTCSR_WFE_Pos                         (2U)
14881 #define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
14882 #define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */
14883 #define ETH_MACPMTCSR_MPE_Pos                         (1U)
14884 #define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
14885 #define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */
14886 #define ETH_MACPMTCSR_PD_Pos                          (0U)
14887 #define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
14888 #define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */
14889 
14890 /* Bit definition for Ethernet MAC debug Register */
14891 #define ETH_MACDBGR_TFF_Pos                           (25U)
14892 #define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
14893 #define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
14894 #define ETH_MACDBGR_TFNE_Pos                          (24U)
14895 #define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
14896 #define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
14897 #define ETH_MACDBGR_TFWA_Pos                          (22U)
14898 #define ETH_MACDBGR_TFWA_Msk                          (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
14899 #define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */
14900 #define ETH_MACDBGR_TFRS_Pos                          (20U)
14901 #define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
14902 #define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
14903 #define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)
14904 #define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
14905 #define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
14906 #define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)
14907 #define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
14908 #define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
14909 #define ETH_MACDBGR_TFRS_READ_Pos                     (20U)
14910 #define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
14911 #define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
14912 #define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
14913 #define ETH_MACDBGR_MTP_Pos                           (19U)
14914 #define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
14915 #define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
14916 #define ETH_MACDBGR_MTFCS_Pos                         (17U)
14917 #define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
14918 #define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
14919 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)
14920 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
14921 #define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
14922 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)
14923 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
14924 #define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
14925 #define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)
14926 #define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
14927 #define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
14928 #define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
14929 #define ETH_MACDBGR_MMTEA_Pos                         (16U)
14930 #define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
14931 #define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
14932 #define ETH_MACDBGR_RFFL_Pos                          (8U)
14933 #define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
14934 #define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
14935 #define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)
14936 #define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
14937 #define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
14938 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)
14939 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
14940 #define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
14941 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)
14942 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
14943 #define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
14944 #define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
14945 #define ETH_MACDBGR_RFRCS_Pos                         (5U)
14946 #define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
14947 #define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
14948 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)
14949 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
14950 #define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
14951 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)
14952 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
14953 #define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
14954 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)
14955 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
14956 #define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
14957 #define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
14958 #define ETH_MACDBGR_RFWRA_Pos                         (4U)
14959 #define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
14960 #define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
14961 #define ETH_MACDBGR_MSFRWCS_Pos                       (1U)
14962 #define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
14963 #define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
14964 #define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
14965 #define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
14966 #define ETH_MACDBGR_MMRPEA_Pos                        (0U)
14967 #define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
14968 #define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
14969 
14970 /* Bit definition for Ethernet MAC Status Register */
14971 #define ETH_MACSR_TSTS_Pos                            (9U)
14972 #define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
14973 #define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
14974 #define ETH_MACSR_MMCTS_Pos                           (6U)
14975 #define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
14976 #define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */
14977 #define ETH_MACSR_MMMCRS_Pos                          (5U)
14978 #define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
14979 #define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */
14980 #define ETH_MACSR_MMCS_Pos                            (4U)
14981 #define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
14982 #define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */
14983 #define ETH_MACSR_PMTS_Pos                            (3U)
14984 #define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
14985 #define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */
14986 
14987 /* Bit definition for Ethernet MAC Interrupt Mask Register */
14988 #define ETH_MACIMR_TSTIM_Pos                          (9U)
14989 #define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
14990 #define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
14991 #define ETH_MACIMR_PMTIM_Pos                          (3U)
14992 #define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
14993 #define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */
14994 
14995 /* Bit definition for Ethernet MAC Address0 High Register */
14996 #define ETH_MACA0HR_MACA0H_Pos                        (0U)
14997 #define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
14998 #define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
14999 
15000 /* Bit definition for Ethernet MAC Address0 Low Register */
15001 #define ETH_MACA0LR_MACA0L_Pos                        (0U)
15002 #define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
15003 #define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
15004 
15005 /* Bit definition for Ethernet MAC Address1 High Register */
15006 #define ETH_MACA1HR_AE_Pos                            (31U)
15007 #define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
15008 #define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
15009 #define ETH_MACA1HR_SA_Pos                            (30U)
15010 #define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
15011 #define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
15012 #define ETH_MACA1HR_MBC_Pos                           (24U)
15013 #define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
15014 #define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
15015 #define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
15016 #define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
15017 #define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
15018 #define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
15019 #define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
15020 #define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */
15021 #define ETH_MACA1HR_MACA1H_Pos                        (0U)
15022 #define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
15023 #define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
15024 
15025 /* Bit definition for Ethernet MAC Address1 Low Register */
15026 #define ETH_MACA1LR_MACA1L_Pos                        (0U)
15027 #define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
15028 #define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
15029 
15030 /* Bit definition for Ethernet MAC Address2 High Register */
15031 #define ETH_MACA2HR_AE_Pos                            (31U)
15032 #define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
15033 #define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
15034 #define ETH_MACA2HR_SA_Pos                            (30U)
15035 #define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
15036 #define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
15037 #define ETH_MACA2HR_MBC_Pos                           (24U)
15038 #define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
15039 #define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
15040 #define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
15041 #define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
15042 #define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
15043 #define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
15044 #define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
15045 #define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
15046 #define ETH_MACA2HR_MACA2H_Pos                        (0U)
15047 #define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
15048 #define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
15049 
15050 /* Bit definition for Ethernet MAC Address2 Low Register */
15051 #define ETH_MACA2LR_MACA2L_Pos                        (0U)
15052 #define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
15053 #define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
15054 
15055 /* Bit definition for Ethernet MAC Address3 High Register */
15056 #define ETH_MACA3HR_AE_Pos                            (31U)
15057 #define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
15058 #define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
15059 #define ETH_MACA3HR_SA_Pos                            (30U)
15060 #define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
15061 #define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
15062 #define ETH_MACA3HR_MBC_Pos                           (24U)
15063 #define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
15064 #define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
15065 #define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
15066 #define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
15067 #define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
15068 #define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
15069 #define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
15070 #define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
15071 #define ETH_MACA3HR_MACA3H_Pos                        (0U)
15072 #define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
15073 #define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
15074 
15075 /* Bit definition for Ethernet MAC Address3 Low Register */
15076 #define ETH_MACA3LR_MACA3L_Pos                        (0U)
15077 #define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
15078 #define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
15079 
15080 /******************************************************************************/
15081 /*                Ethernet MMC Registers bits definition                      */
15082 /******************************************************************************/
15083 
15084 /* Bit definition for Ethernet MMC Contol Register */
15085 #define ETH_MMCCR_MCFHP_Pos                           (5U)
15086 #define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
15087 #define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
15088 #define ETH_MMCCR_MCP_Pos                             (4U)
15089 #define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
15090 #define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */
15091 #define ETH_MMCCR_MCF_Pos                             (3U)
15092 #define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
15093 #define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */
15094 #define ETH_MMCCR_ROR_Pos                             (2U)
15095 #define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
15096 #define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */
15097 #define ETH_MMCCR_CSR_Pos                             (1U)
15098 #define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
15099 #define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */
15100 #define ETH_MMCCR_CR_Pos                              (0U)
15101 #define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
15102 #define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */
15103 
15104 /* Bit definition for Ethernet MMC Receive Interrupt Register */
15105 #define ETH_MMCRIR_RGUFS_Pos                          (17U)
15106 #define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
15107 #define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
15108 #define ETH_MMCRIR_RFAES_Pos                          (6U)
15109 #define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
15110 #define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
15111 #define ETH_MMCRIR_RFCES_Pos                          (5U)
15112 #define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
15113 #define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
15114 
15115 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
15116 #define ETH_MMCTIR_TGFS_Pos                           (21U)
15117 #define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
15118 #define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
15119 #define ETH_MMCTIR_TGFMSCS_Pos                        (15U)
15120 #define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
15121 #define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
15122 #define ETH_MMCTIR_TGFSCS_Pos                         (14U)
15123 #define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
15124 #define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
15125 
15126 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
15127 #define ETH_MMCRIMR_RGUFM_Pos                         (17U)
15128 #define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
15129 #define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
15130 #define ETH_MMCRIMR_RFAEM_Pos                         (6U)
15131 #define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
15132 #define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
15133 #define ETH_MMCRIMR_RFCEM_Pos                         (5U)
15134 #define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
15135 #define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
15136 
15137 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
15138 #define ETH_MMCTIMR_TGFM_Pos                          (21U)
15139 #define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
15140 #define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
15141 #define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)
15142 #define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
15143 #define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
15144 #define ETH_MMCTIMR_TGFSCM_Pos                        (14U)
15145 #define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
15146 #define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
15147 
15148 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
15149 #define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)
15150 #define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
15151 #define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
15152 
15153 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
15154 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)
15155 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
15156 #define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
15157 
15158 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
15159 #define ETH_MMCTGFCR_TGFC_Pos                         (0U)
15160 #define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
15161 #define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
15162 
15163 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
15164 #define ETH_MMCRFCECR_RFCEC_Pos                       (0U)
15165 #define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
15166 #define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
15167 
15168 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
15169 #define ETH_MMCRFAECR_RFAEC_Pos                       (0U)
15170 #define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
15171 #define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
15172 
15173 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
15174 #define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)
15175 #define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
15176 #define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
15177 
15178 /******************************************************************************/
15179 /*               Ethernet PTP Registers bits definition                       */
15180 /******************************************************************************/
15181 
15182 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
15183 #define ETH_PTPTSCR_TSCNT_Pos                         (16U)
15184 #define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
15185 #define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
15186 #define ETH_PTPTSSR_TSSMRME_Pos                       (15U)
15187 #define ETH_PTPTSSR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
15188 #define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
15189 #define ETH_PTPTSSR_TSSEME_Pos                        (14U)
15190 #define ETH_PTPTSSR_TSSEME_Msk                        (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
15191 #define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
15192 #define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)
15193 #define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15194 #define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15195 #define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)
15196 #define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15197 #define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15198 #define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)
15199 #define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15200 #define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15201 #define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)
15202 #define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15203 #define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15204 #define ETH_PTPTSSR_TSSSR_Pos                         (9U)
15205 #define ETH_PTPTSSR_TSSSR_Msk                         (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
15206 #define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
15207 #define ETH_PTPTSSR_TSSARFE_Pos                       (8U)
15208 #define ETH_PTPTSSR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
15209 #define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
15210 
15211 #define ETH_PTPTSCR_TSARU_Pos                         (5U)
15212 #define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
15213 #define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
15214 #define ETH_PTPTSCR_TSITE_Pos                         (4U)
15215 #define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
15216 #define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
15217 #define ETH_PTPTSCR_TSSTU_Pos                         (3U)
15218 #define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
15219 #define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
15220 #define ETH_PTPTSCR_TSSTI_Pos                         (2U)
15221 #define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
15222 #define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
15223 #define ETH_PTPTSCR_TSFCU_Pos                         (1U)
15224 #define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
15225 #define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
15226 #define ETH_PTPTSCR_TSE_Pos                           (0U)
15227 #define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
15228 #define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
15229 
15230 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
15231 #define ETH_PTPSSIR_STSSI_Pos                         (0U)
15232 #define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
15233 #define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
15234 
15235 /* Bit definition for Ethernet PTP Time Stamp High Register */
15236 #define ETH_PTPTSHR_STS_Pos                           (0U)
15237 #define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
15238 #define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
15239 
15240 /* Bit definition for Ethernet PTP Time Stamp Low Register */
15241 #define ETH_PTPTSLR_STPNS_Pos                         (31U)
15242 #define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
15243 #define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
15244 #define ETH_PTPTSLR_STSS_Pos                          (0U)
15245 #define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
15246 #define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
15247 
15248 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
15249 #define ETH_PTPTSHUR_TSUS_Pos                         (0U)
15250 #define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
15251 #define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
15252 
15253 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
15254 #define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)
15255 #define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
15256 #define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
15257 #define ETH_PTPTSLUR_TSUSS_Pos                        (0U)
15258 #define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
15259 #define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
15260 
15261 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
15262 #define ETH_PTPTSAR_TSA_Pos                           (0U)
15263 #define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
15264 #define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
15265 
15266 /* Bit definition for Ethernet PTP Target Time High Register */
15267 #define ETH_PTPTTHR_TTSH_Pos                          (0U)
15268 #define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
15269 #define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
15270 
15271 /* Bit definition for Ethernet PTP Target Time Low Register */
15272 #define ETH_PTPTTLR_TTSL_Pos                          (0U)
15273 #define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
15274 #define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
15275 
15276 /* Bit definition for Ethernet PTP Time Stamp Status Register */
15277 #define ETH_PTPTSSR_TSTTR_Pos                         (5U)
15278 #define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
15279 #define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
15280 #define ETH_PTPTSSR_TSSO_Pos                          (4U)
15281 #define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
15282 #define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
15283 
15284 /******************************************************************************/
15285 /*                 Ethernet DMA Registers bits definition                     */
15286 /******************************************************************************/
15287 
15288 /* Bit definition for Ethernet DMA Bus Mode Register */
15289 #define ETH_DMABMR_AAB_Pos                            (25U)
15290 #define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
15291 #define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
15292 #define ETH_DMABMR_FPM_Pos                            (24U)
15293 #define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
15294 #define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
15295 #define ETH_DMABMR_USP_Pos                            (23U)
15296 #define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
15297 #define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
15298 #define ETH_DMABMR_RDP_Pos                            (17U)
15299 #define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
15300 #define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
15301 #define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
15302 #define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
15303 #define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15304 #define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15305 #define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15306 #define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15307 #define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15308 #define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15309 #define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15310 #define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15311 #define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
15312 #define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
15313 #define ETH_DMABMR_FB_Pos                             (16U)
15314 #define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
15315 #define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
15316 #define ETH_DMABMR_RTPR_Pos                           (14U)
15317 #define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
15318 #define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
15319 #define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
15320 #define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
15321 #define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
15322 #define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */
15323 #define ETH_DMABMR_PBL_Pos                            (8U)
15324 #define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
15325 #define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
15326 #define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
15327 #define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
15328 #define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15329 #define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15330 #define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15331 #define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15332 #define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15333 #define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15334 #define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15335 #define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15336 #define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15337 #define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15338 #define ETH_DMABMR_EDE_Pos                            (7U)
15339 #define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
15340 #define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
15341 #define ETH_DMABMR_DSL_Pos                            (2U)
15342 #define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
15343 #define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
15344 #define ETH_DMABMR_DA_Pos                             (1U)
15345 #define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
15346 #define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
15347 #define ETH_DMABMR_SR_Pos                             (0U)
15348 #define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
15349 #define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
15350 
15351 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15352 #define ETH_DMATPDR_TPD_Pos                           (0U)
15353 #define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
15354 #define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
15355 
15356 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
15357 #define ETH_DMARPDR_RPD_Pos                           (0U)
15358 #define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
15359 #define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
15360 
15361 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15362 #define ETH_DMARDLAR_SRL_Pos                          (0U)
15363 #define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
15364 #define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
15365 
15366 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15367 #define ETH_DMATDLAR_STL_Pos                          (0U)
15368 #define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
15369 #define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
15370 
15371 /* Bit definition for Ethernet DMA Status Register */
15372 #define ETH_DMASR_TSTS_Pos                            (29U)
15373 #define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
15374 #define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
15375 #define ETH_DMASR_PMTS_Pos                            (28U)
15376 #define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
15377 #define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
15378 #define ETH_DMASR_MMCS_Pos                            (27U)
15379 #define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
15380 #define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
15381 #define ETH_DMASR_EBS_Pos                             (23U)
15382 #define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
15383 #define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
15384   /* combination with EBS[2:0] for GetFlagStatus function */
15385 #define ETH_DMASR_EBS_DescAccess_Pos                  (25U)
15386 #define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
15387 #define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
15388 #define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)
15389 #define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
15390 #define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
15391 #define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)
15392 #define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
15393 #define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
15394 #define ETH_DMASR_TPS_Pos                             (20U)
15395 #define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
15396 #define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
15397 #define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
15398 #define ETH_DMASR_TPS_Fetching_Pos                    (20U)
15399 #define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
15400 #define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
15401 #define ETH_DMASR_TPS_Waiting_Pos                     (21U)
15402 #define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
15403 #define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
15404 #define ETH_DMASR_TPS_Reading_Pos                     (20U)
15405 #define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
15406 #define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
15407 #define ETH_DMASR_TPS_Suspended_Pos                   (21U)
15408 #define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
15409 #define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
15410 #define ETH_DMASR_TPS_Closing_Pos                     (20U)
15411 #define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
15412 #define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
15413 #define ETH_DMASR_RPS_Pos                             (17U)
15414 #define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
15415 #define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
15416 #define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
15417 #define ETH_DMASR_RPS_Fetching_Pos                    (17U)
15418 #define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
15419 #define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
15420 #define ETH_DMASR_RPS_Waiting_Pos                     (17U)
15421 #define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
15422 #define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
15423 #define ETH_DMASR_RPS_Suspended_Pos                   (19U)
15424 #define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
15425 #define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
15426 #define ETH_DMASR_RPS_Closing_Pos                     (17U)
15427 #define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
15428 #define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
15429 #define ETH_DMASR_RPS_Queuing_Pos                     (17U)
15430 #define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
15431 #define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
15432 #define ETH_DMASR_NIS_Pos                             (16U)
15433 #define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
15434 #define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
15435 #define ETH_DMASR_AIS_Pos                             (15U)
15436 #define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
15437 #define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
15438 #define ETH_DMASR_ERS_Pos                             (14U)
15439 #define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
15440 #define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
15441 #define ETH_DMASR_FBES_Pos                            (13U)
15442 #define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
15443 #define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
15444 #define ETH_DMASR_ETS_Pos                             (10U)
15445 #define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
15446 #define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
15447 #define ETH_DMASR_RWTS_Pos                            (9U)
15448 #define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
15449 #define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
15450 #define ETH_DMASR_RPSS_Pos                            (8U)
15451 #define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
15452 #define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
15453 #define ETH_DMASR_RBUS_Pos                            (7U)
15454 #define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
15455 #define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
15456 #define ETH_DMASR_RS_Pos                              (6U)
15457 #define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
15458 #define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
15459 #define ETH_DMASR_TUS_Pos                             (5U)
15460 #define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
15461 #define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
15462 #define ETH_DMASR_ROS_Pos                             (4U)
15463 #define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
15464 #define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
15465 #define ETH_DMASR_TJTS_Pos                            (3U)
15466 #define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
15467 #define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
15468 #define ETH_DMASR_TBUS_Pos                            (2U)
15469 #define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
15470 #define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
15471 #define ETH_DMASR_TPSS_Pos                            (1U)
15472 #define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
15473 #define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
15474 #define ETH_DMASR_TS_Pos                              (0U)
15475 #define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
15476 #define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
15477 
15478 /* Bit definition for Ethernet DMA Operation Mode Register */
15479 #define ETH_DMAOMR_DTCEFD_Pos                         (26U)
15480 #define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
15481 #define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
15482 #define ETH_DMAOMR_RSF_Pos                            (25U)
15483 #define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
15484 #define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
15485 #define ETH_DMAOMR_DFRF_Pos                           (24U)
15486 #define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
15487 #define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
15488 #define ETH_DMAOMR_TSF_Pos                            (21U)
15489 #define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
15490 #define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
15491 #define ETH_DMAOMR_FTF_Pos                            (20U)
15492 #define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
15493 #define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
15494 #define ETH_DMAOMR_TTC_Pos                            (14U)
15495 #define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
15496 #define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
15497 #define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
15498 #define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
15499 #define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
15500 #define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
15501 #define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
15502 #define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
15503 #define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
15504 #define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
15505 #define ETH_DMAOMR_ST_Pos                             (13U)
15506 #define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
15507 #define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
15508 #define ETH_DMAOMR_FEF_Pos                            (7U)
15509 #define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
15510 #define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
15511 #define ETH_DMAOMR_FUGF_Pos                           (6U)
15512 #define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
15513 #define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
15514 #define ETH_DMAOMR_RTC_Pos                            (3U)
15515 #define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
15516 #define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
15517 #define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
15518 #define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
15519 #define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
15520 #define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
15521 #define ETH_DMAOMR_OSF_Pos                            (2U)
15522 #define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
15523 #define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
15524 #define ETH_DMAOMR_SR_Pos                             (1U)
15525 #define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
15526 #define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
15527 
15528 /* Bit definition for Ethernet DMA Interrupt Enable Register */
15529 #define ETH_DMAIER_NISE_Pos                           (16U)
15530 #define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
15531 #define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
15532 #define ETH_DMAIER_AISE_Pos                           (15U)
15533 #define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
15534 #define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
15535 #define ETH_DMAIER_ERIE_Pos                           (14U)
15536 #define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
15537 #define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
15538 #define ETH_DMAIER_FBEIE_Pos                          (13U)
15539 #define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
15540 #define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
15541 #define ETH_DMAIER_ETIE_Pos                           (10U)
15542 #define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
15543 #define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
15544 #define ETH_DMAIER_RWTIE_Pos                          (9U)
15545 #define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
15546 #define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
15547 #define ETH_DMAIER_RPSIE_Pos                          (8U)
15548 #define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
15549 #define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
15550 #define ETH_DMAIER_RBUIE_Pos                          (7U)
15551 #define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
15552 #define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
15553 #define ETH_DMAIER_RIE_Pos                            (6U)
15554 #define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
15555 #define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
15556 #define ETH_DMAIER_TUIE_Pos                           (5U)
15557 #define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
15558 #define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
15559 #define ETH_DMAIER_ROIE_Pos                           (4U)
15560 #define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
15561 #define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
15562 #define ETH_DMAIER_TJTIE_Pos                          (3U)
15563 #define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
15564 #define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
15565 #define ETH_DMAIER_TBUIE_Pos                          (2U)
15566 #define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
15567 #define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
15568 #define ETH_DMAIER_TPSIE_Pos                          (1U)
15569 #define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
15570 #define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
15571 #define ETH_DMAIER_TIE_Pos                            (0U)
15572 #define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
15573 #define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
15574 
15575 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
15576 #define ETH_DMAMFBOCR_OFOC_Pos                        (28U)
15577 #define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
15578 #define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
15579 #define ETH_DMAMFBOCR_MFA_Pos                         (17U)
15580 #define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
15581 #define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
15582 #define ETH_DMAMFBOCR_OMFC_Pos                        (16U)
15583 #define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
15584 #define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
15585 #define ETH_DMAMFBOCR_MFC_Pos                         (0U)
15586 #define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
15587 #define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
15588 
15589 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
15590 #define ETH_DMACHTDR_HTDAP_Pos                        (0U)
15591 #define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
15592 #define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
15593 
15594 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
15595 #define ETH_DMACHRDR_HRDAP_Pos                        (0U)
15596 #define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
15597 #define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
15598 
15599 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
15600 #define ETH_DMACHTBAR_HTBAP_Pos                       (0U)
15601 #define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
15602 #define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
15603 
15604 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
15605 #define ETH_DMACHRBAR_HRBAP_Pos                       (0U)
15606 #define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
15607 #define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
15608 
15609 /******************************************************************************/
15610 /*                                                                            */
15611 /*                                       USB_OTG                              */
15612 /*                                                                            */
15613 /******************************************************************************/
15614 /********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
15615 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
15616 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
15617 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
15618 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
15619 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
15620 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
15621 #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
15622 #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
15623 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
15624 #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
15625 #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
15626 #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
15627 #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
15628 #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
15629 #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
15630 #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
15631 #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
15632 #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
15633 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
15634 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
15635 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
15636 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
15637 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
15638 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
15639 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
15640 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
15641 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
15642 #define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)
15643 #define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
15644 #define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */
15645 
15646 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
15647 
15648 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
15649 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
15650 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
15651 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
15652 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
15653 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
15654 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
15655 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
15656 
15657 /********************  Bit definition for USB_OTG_DCFG register  ********************/
15658 
15659 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
15660 #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
15661 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
15662 #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
15663 #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
15664 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
15665 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
15666 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
15667 
15668 #define USB_OTG_DCFG_DAD_Pos                     (4U)
15669 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
15670 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
15671 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
15672 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
15673 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
15674 #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
15675 #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
15676 #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
15677 #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
15678 
15679 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
15680 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
15681 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
15682 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
15683 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
15684 
15685 #define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
15686 #define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
15687 #define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
15688 
15689 #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
15690 #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
15691 #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
15692 
15693 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
15694 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
15695 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
15696 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
15697 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
15698 
15699 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
15700 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
15701 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
15702 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
15703 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
15704 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
15705 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
15706 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
15707 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
15708 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
15709 
15710 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
15711 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
15712 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
15713 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
15714 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
15715 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
15716 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
15717 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
15718 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
15719 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
15720 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
15721 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
15722 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
15723 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
15724 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
15725 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
15726 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
15727 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
15728 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
15729 
15730 /********************  Bit definition for USB_OTG_DCTL register  ********************/
15731 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
15732 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
15733 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
15734 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
15735 #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
15736 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
15737 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
15738 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
15739 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
15740 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
15741 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
15742 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
15743 
15744 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
15745 #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
15746 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
15747 #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
15748 #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
15749 #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
15750 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
15751 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
15752 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
15753 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
15754 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
15755 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
15756 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
15757 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
15758 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
15759 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
15760 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
15761 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
15762 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
15763 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
15764 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
15765 
15766 /********************  Bit definition for USB_OTG_HFIR register  ********************/
15767 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
15768 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
15769 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
15770 
15771 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
15772 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
15773 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
15774 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
15775 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
15776 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
15777 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
15778 
15779 /********************  Bit definition for USB_OTG_DSTS register  ********************/
15780 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
15781 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
15782 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
15783 
15784 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
15785 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
15786 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
15787 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
15788 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
15789 #define USB_OTG_DSTS_EERR_Pos                    (3U)
15790 #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
15791 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
15792 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
15793 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
15794 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
15795 
15796 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
15797 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
15798 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
15799 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
15800 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
15801 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
15802 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
15803 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
15804 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
15805 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
15806 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
15807 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
15808 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
15809 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
15810 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
15811 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
15812 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
15813 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
15814 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
15815 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
15816 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
15817 
15818 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
15819 
15820 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
15821 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
15822 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
15823 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
15824 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
15825 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
15826 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
15827 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
15828 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
15829 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
15830 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
15831 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
15832 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
15833 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
15834 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
15835 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
15836 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
15837 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
15838 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
15839 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
15840 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
15841 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
15842 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
15843 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
15844 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
15845 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
15846 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
15847 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
15848 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
15849 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
15850 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
15851 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
15852 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
15853 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
15854 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
15855 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
15856 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
15857 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
15858 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
15859 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
15860 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
15861 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
15862 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
15863 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
15864 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
15865 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
15866 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
15867 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
15868 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
15869 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
15870 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
15871 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
15872 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
15873 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
15874 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
15875 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
15876 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
15877 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
15878 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
15879 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
15880 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
15881 
15882 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
15883 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
15884 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
15885 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
15886 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
15887 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
15888 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
15889 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
15890 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
15891 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
15892 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
15893 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
15894 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
15895 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
15896 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
15897 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
15898 
15899 
15900 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
15901 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
15902 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
15903 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
15904 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
15905 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
15906 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
15907 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
15908 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
15909 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
15910 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
15911 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
15912 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
15913 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
15914 
15915 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
15916 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
15917 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15918 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
15919 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
15920 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
15921 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
15922 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
15923 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
15924 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
15925 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
15926 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
15927 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
15928 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
15929 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
15930 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
15931 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
15932 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
15933 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
15934 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
15935 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
15936 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
15937 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
15938 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
15939 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
15940 
15941 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
15942 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
15943 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
15944 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
15945 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
15946 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
15947 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
15948 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
15949 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
15950 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
15951 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
15952 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
15953 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
15954 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
15955 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
15956 
15957 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
15958 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
15959 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
15960 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
15961 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
15962 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
15963 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
15964 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
15965 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
15966 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
15967 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
15968 
15969 /********************  Bit definition for USB_OTG_HAINT register  ********************/
15970 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
15971 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
15972 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
15973 
15974 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
15975 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
15976 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
15977 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
15978 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
15979 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
15980 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
15981 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
15982 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
15983 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
15984 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
15985 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
15986 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
15987 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
15988 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
15989 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
15990 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
15991 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
15992 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
15993 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
15994 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
15995 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
15996 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
15997 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
15998 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
15999 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
16000 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
16001 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
16002 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
16003 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
16004 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
16005 #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
16006 #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
16007 #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
16008 #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
16009 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
16010 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
16011 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
16012 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
16013 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
16014 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
16015 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
16016 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
16017 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
16018 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
16019 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
16020 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
16021 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
16022 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
16023 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
16024 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
16025 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
16026 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
16027 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
16028 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
16029 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
16030 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
16031 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
16032 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
16033 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
16034 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
16035 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
16036 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
16037 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
16038 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
16039 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
16040 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
16041 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
16042 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
16043 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
16044 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
16045 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
16046 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
16047 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
16048 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
16049 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
16050 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
16051 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
16052 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
16053 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
16054 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
16055 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
16056 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
16057 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
16058 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
16059 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
16060 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
16061 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
16062 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
16063 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
16064 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
16065 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
16066 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
16067 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
16068 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
16069 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
16070 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
16071 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
16072 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
16073 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
16074 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
16075 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
16076 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
16077 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
16078 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
16079 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
16080 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
16081 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
16082 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
16083 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
16084 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
16085 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
16086 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
16087 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
16088 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
16089 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
16090 
16091 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
16092 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
16093 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
16094 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
16095 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
16096 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
16097 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
16098 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
16099 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
16100 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
16101 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
16102 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
16103 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
16104 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
16105 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
16106 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
16107 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
16108 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
16109 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
16110 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
16111 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
16112 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
16113 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
16114 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
16115 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
16116 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
16117 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
16118 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
16119 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
16120 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
16121 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
16122 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
16123 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
16124 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
16125 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
16126 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
16127 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
16128 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
16129 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
16130 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
16131 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
16132 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
16133 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
16134 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
16135 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
16136 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
16137 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
16138 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
16139 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
16140 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
16141 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
16142 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
16143 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
16144 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
16145 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
16146 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
16147 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
16148 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
16149 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
16150 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
16151 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
16152 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
16153 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
16154 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
16155 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
16156 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
16157 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
16158 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
16159 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
16160 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
16161 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
16162 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
16163 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
16164 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
16165 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
16166 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
16167 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
16168 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
16169 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
16170 
16171 /********************  Bit definition for USB_OTG_DAINT register  ********************/
16172 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
16173 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
16174 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
16175 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
16176 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
16177 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
16178 
16179 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
16180 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
16181 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
16182 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
16183 
16184 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
16185 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
16186 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
16187 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
16188 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
16189 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
16190 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
16191 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
16192 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
16193 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
16194 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
16195 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
16196 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
16197 
16198 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
16199 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
16200 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
16201 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
16202 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
16203 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
16204 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
16205 
16206 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
16207 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
16208 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
16209 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
16210 
16211 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
16212 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
16213 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
16214 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
16215 
16216 /********************  Bit definition for OTG register  ********************/
16217 #define USB_OTG_NPTXFSA_Pos                      (0U)
16218 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
16219 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
16220 #define USB_OTG_NPTXFD_Pos                       (16U)
16221 #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
16222 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
16223 #define USB_OTG_TX0FSA_Pos                       (0U)
16224 #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
16225 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
16226 #define USB_OTG_TX0FD_Pos                        (16U)
16227 #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
16228 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
16229 
16230 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
16231 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
16232 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
16233 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
16234 
16235 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
16236 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
16237 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
16238 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
16239 
16240 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
16241 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
16242 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
16243 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
16244 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
16245 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
16246 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
16247 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
16248 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
16249 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
16250 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
16251 
16252 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
16253 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
16254 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
16255 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
16256 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
16257 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
16258 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
16259 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
16260 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
16261 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
16262 
16263 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
16264 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
16265 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
16266 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
16267 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
16268 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
16269 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
16270 
16271 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
16272 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
16273 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
16274 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
16275 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
16276 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
16277 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
16278 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
16279 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
16280 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
16281 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
16282 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
16283 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
16284 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
16285 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
16286 
16287 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
16288 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
16289 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
16290 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
16291 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
16292 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
16293 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
16294 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
16295 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
16296 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
16297 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
16298 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
16299 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
16300 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
16301 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
16302 
16303 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
16304 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
16305 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
16306 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
16307 
16308 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
16309 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
16310 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
16311 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
16312 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
16313 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
16314 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
16315 
16316 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
16317 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
16318 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
16319 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
16320 #define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)
16321 #define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
16322 #define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/
16323 #define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)
16324 #define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
16325 #define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */
16326 #define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)
16327 #define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
16328 #define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */
16329 #define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)
16330 #define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
16331 #define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */
16332 #define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)
16333 #define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
16334 #define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/
16335 
16336 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
16337 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
16338 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
16339 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
16340 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
16341 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
16342 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
16343 
16344 /********************  Bit definition for USB_OTG_CID register  ********************/
16345 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
16346 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
16347 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
16348 
16349 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
16350 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
16351 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
16352 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
16353 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
16354 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
16355 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
16356 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
16357 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
16358 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
16359 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
16360 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
16361 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
16362 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
16363 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
16364 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
16365 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
16366 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
16367 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
16368 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
16369 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
16370 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
16371 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
16372 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
16373 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
16374 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
16375 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
16376 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
16377 
16378 /********************  Bit definition for USB_OTG_HPRT register  ********************/
16379 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
16380 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
16381 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
16382 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
16383 #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
16384 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
16385 #define USB_OTG_HPRT_PENA_Pos                    (2U)
16386 #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
16387 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
16388 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
16389 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
16390 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
16391 #define USB_OTG_HPRT_POCA_Pos                    (4U)
16392 #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
16393 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
16394 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
16395 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
16396 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
16397 #define USB_OTG_HPRT_PRES_Pos                    (6U)
16398 #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
16399 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
16400 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
16401 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
16402 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
16403 #define USB_OTG_HPRT_PRST_Pos                    (8U)
16404 #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
16405 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
16406 
16407 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
16408 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
16409 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
16410 #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
16411 #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
16412 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
16413 #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
16414 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
16415 
16416 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
16417 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
16418 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
16419 #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
16420 #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
16421 #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
16422 #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
16423 
16424 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
16425 #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
16426 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
16427 #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
16428 #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
16429 
16430 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
16431 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
16432 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
16433 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
16434 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
16435 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
16436 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
16437 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
16438 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
16439 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
16440 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
16441 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
16442 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
16443 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
16444 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
16445 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
16446 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
16447 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
16448 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
16449 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
16450 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
16451 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
16452 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
16453 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
16454 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
16455 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
16456 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
16457 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
16458 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
16459 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
16460 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
16461 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
16462 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
16463 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
16464 
16465 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
16466 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
16467 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
16468 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
16469 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
16470 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
16471 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
16472 
16473 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
16474 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
16475 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
16476 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
16477 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
16478 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
16479 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
16480 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
16481 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
16482 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
16483 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
16484 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
16485 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
16486 
16487 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
16488 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
16489 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
16490 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
16491 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
16492 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
16493 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
16494 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
16495 
16496 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
16497 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
16498 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
16499 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
16500 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
16501 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
16502 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
16503 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
16504 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
16505 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
16506 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
16507 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
16508 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
16509 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
16510 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
16511 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
16512 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
16513 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
16514 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
16515 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
16516 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
16517 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
16518 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
16519 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
16520 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
16521 
16522 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
16523 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
16524 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
16525 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
16526 
16527 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
16528 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
16529 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
16530 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
16531 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
16532 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
16533 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
16534 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
16535 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
16536 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
16537 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
16538 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
16539 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
16540 
16541 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
16542 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
16543 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
16544 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
16545 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
16546 
16547 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
16548 #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
16549 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
16550 #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
16551 #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
16552 
16553 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
16554 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
16555 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
16556 #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
16557 #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
16558 #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
16559 #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
16560 #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
16561 #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
16562 #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
16563 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
16564 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
16565 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
16566 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
16567 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
16568 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
16569 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
16570 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
16571 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
16572 
16573 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
16574 
16575 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
16576 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
16577 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
16578 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
16579 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
16580 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
16581 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
16582 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
16583 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
16584 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
16585 
16586 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
16587 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
16588 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
16589 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
16590 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
16591 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
16592 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
16593 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
16594 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
16595 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
16596 
16597 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
16598 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
16599 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
16600 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
16601 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
16602 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
16603 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
16604 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
16605 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
16606 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
16607 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
16608 
16609 /********************  Bit definition for USB_OTG_HCINT register  ********************/
16610 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
16611 #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
16612 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
16613 #define USB_OTG_HCINT_CHH_Pos                    (1U)
16614 #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
16615 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
16616 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
16617 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
16618 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
16619 #define USB_OTG_HCINT_STALL_Pos                  (3U)
16620 #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
16621 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
16622 #define USB_OTG_HCINT_NAK_Pos                    (4U)
16623 #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
16624 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
16625 #define USB_OTG_HCINT_ACK_Pos                    (5U)
16626 #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
16627 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
16628 #define USB_OTG_HCINT_NYET_Pos                   (6U)
16629 #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
16630 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
16631 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
16632 #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
16633 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
16634 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
16635 #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
16636 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
16637 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
16638 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
16639 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
16640 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
16641 #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
16642 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
16643 
16644 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
16645 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
16646 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
16647 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
16648 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
16649 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
16650 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
16651 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
16652 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
16653 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
16654 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
16655 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
16656 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
16657 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
16658 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
16659 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
16660 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
16661 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
16662 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
16663 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
16664 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
16665 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
16666 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
16667 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
16668 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
16669 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
16670 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
16671 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
16672 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
16673 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
16674 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
16675 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
16676 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
16677 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
16678 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
16679 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
16680 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
16681 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
16682 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
16683 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
16684 
16685 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
16686 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
16687 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
16688 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
16689 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
16690 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
16691 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
16692 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
16693 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
16694 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
16695 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
16696 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
16697 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
16698 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
16699 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
16700 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
16701 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
16702 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
16703 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
16704 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
16705 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
16706 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
16707 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
16708 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
16709 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
16710 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
16711 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
16712 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
16713 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
16714 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
16715 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
16716 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
16717 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
16718 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
16719 
16720 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
16721 
16722 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
16723 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16724 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
16725 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
16726 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16727 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
16728 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
16729 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
16730 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
16731 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
16732 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
16733 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16734 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
16735 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
16736 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16737 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
16738 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
16739 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
16740 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
16741 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
16742 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
16743 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
16744 #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
16745 #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
16746 
16747 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
16748 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
16749 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16750 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
16751 
16752 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
16753 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
16754 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
16755 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
16756 
16757 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
16758 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
16759 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
16760 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
16761 
16762 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
16763 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
16764 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
16765 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
16766 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
16767 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
16768 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
16769 
16770 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
16771 
16772 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
16773 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
16774 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
16775 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
16776 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
16777 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
16778 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
16779 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
16780 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
16781 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
16782 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
16783 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
16784 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
16785 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
16786 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
16787 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
16788 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
16789 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
16790 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
16791 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
16792 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
16793 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
16794 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
16795 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
16796 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
16797 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
16798 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
16799 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
16800 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
16801 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
16802 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
16803 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
16804 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
16805 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
16806 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
16807 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
16808 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
16809 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
16810 
16811 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
16812 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
16813 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
16814 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
16815 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
16816 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
16817 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
16818 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
16819 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
16820 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
16821 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
16822 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
16823 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
16824 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
16825 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
16826 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
16827 #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
16828 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
16829 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
16830 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
16831 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
16832 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
16833 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
16834 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
16835 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
16836 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
16837 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
16838 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
16839 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
16840 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
16841 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
16842 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
16843 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
16844 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
16845 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
16846 
16847 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
16848 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
16849 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
16850 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
16851 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
16852 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
16853 
16854 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
16855 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
16856 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
16857 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
16858 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
16859 
16860 /********************  Bit definition for PCGCCTL register  ********************/
16861 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
16862 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
16863 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
16864 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
16865 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
16866 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
16867 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
16868 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
16869 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
16870 
16871 /* Legacy define */
16872 /********************  Bit definition for OTG register  ********************/
16873 #define USB_OTG_CHNUM_Pos                        (0U)
16874 #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
16875 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
16876 #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
16877 #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
16878 #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
16879 #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
16880 #define USB_OTG_BCNT_Pos                         (4U)
16881 #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
16882 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
16883 
16884 #define USB_OTG_DPID_Pos                         (15U)
16885 #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
16886 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
16887 #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
16888 #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
16889 
16890 #define USB_OTG_PKTSTS_Pos                       (17U)
16891 #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
16892 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
16893 #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
16894 #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
16895 #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
16896 #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
16897 
16898 #define USB_OTG_EPNUM_Pos                        (0U)
16899 #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
16900 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
16901 #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
16902 #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
16903 #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
16904 #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
16905 
16906 #define USB_OTG_FRMNUM_Pos                       (21U)
16907 #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
16908 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
16909 #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
16910 #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
16911 #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
16912 #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
16913 /**
16914   * @}
16915   */
16916 
16917 /**
16918   * @}
16919   */
16920 
16921 /** @addtogroup Exported_macros
16922   * @{
16923   */
16924 
16925 /******************************* ADC Instances ********************************/
16926 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
16927                                        ((INSTANCE) == ADC2) || \
16928                                        ((INSTANCE) == ADC3))
16929 
16930 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16931 
16932 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16933 
16934 /******************************* CAN Instances ********************************/
16935 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
16936                                        ((INSTANCE) == CAN2))
16937 /******************************* CRC Instances ********************************/
16938 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
16939 
16940 /******************************* DAC Instances ********************************/
16941 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
16942 
16943 /******************************* DCMI Instances *******************************/
16944 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
16945 
16946 /******************************* DMA2D Instances *******************************/
16947 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
16948 
16949 /******************************** DMA Instances *******************************/
16950 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
16951                                               ((INSTANCE) == DMA1_Stream1) || \
16952                                               ((INSTANCE) == DMA1_Stream2) || \
16953                                               ((INSTANCE) == DMA1_Stream3) || \
16954                                               ((INSTANCE) == DMA1_Stream4) || \
16955                                               ((INSTANCE) == DMA1_Stream5) || \
16956                                               ((INSTANCE) == DMA1_Stream6) || \
16957                                               ((INSTANCE) == DMA1_Stream7) || \
16958                                               ((INSTANCE) == DMA2_Stream0) || \
16959                                               ((INSTANCE) == DMA2_Stream1) || \
16960                                               ((INSTANCE) == DMA2_Stream2) || \
16961                                               ((INSTANCE) == DMA2_Stream3) || \
16962                                               ((INSTANCE) == DMA2_Stream4) || \
16963                                               ((INSTANCE) == DMA2_Stream5) || \
16964                                               ((INSTANCE) == DMA2_Stream6) || \
16965                                               ((INSTANCE) == DMA2_Stream7))
16966 
16967 /******************************* GPIO Instances *******************************/
16968 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
16969                                         ((INSTANCE) == GPIOB) || \
16970                                         ((INSTANCE) == GPIOC) || \
16971                                         ((INSTANCE) == GPIOD) || \
16972                                         ((INSTANCE) == GPIOE) || \
16973                                         ((INSTANCE) == GPIOF) || \
16974                                         ((INSTANCE) == GPIOG) || \
16975                                         ((INSTANCE) == GPIOH) || \
16976                                         ((INSTANCE) == GPIOI) || \
16977                                         ((INSTANCE) == GPIOJ) || \
16978                                         ((INSTANCE) == GPIOK))
16979 
16980 /******************************** I2C Instances *******************************/
16981 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
16982                                        ((INSTANCE) == I2C2) || \
16983                                        ((INSTANCE) == I2C3))
16984 
16985 /******************************* SMBUS Instances ******************************/
16986 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
16987 
16988 /******************************** I2S Instances *******************************/
16989 
16990 #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
16991                                        ((INSTANCE) == SPI3))
16992 
16993 /*************************** I2S Extended Instances ***************************/
16994 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
16995                                            ((INSTANCE) == I2S3ext))
16996 /* Legacy Defines */
16997 #define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE
16998 
16999 /****************************** LTDC Instances ********************************/
17000 #define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
17001 /******************************* RNG Instances ********************************/
17002 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
17003 
17004 /****************************** RTC Instances *********************************/
17005 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
17006 
17007 /******************************* SAI Instances ********************************/
17008 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
17009                                      ((PERIPH) == SAI1_Block_B))
17010 /* Legacy define */
17011 
17012 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
17013 
17014 /******************************** SPI Instances *******************************/
17015 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \
17016                                        ((INSTANCE) == SPI2)  || \
17017                                        ((INSTANCE) == SPI3)  || \
17018                                        ((INSTANCE) == SPI4)  || \
17019                                        ((INSTANCE) == SPI5)  || \
17020                                        ((INSTANCE) == SPI6))
17021 
17022 
17023 /****************** TIM Instances : All supported instances *******************/
17024 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
17025                                     ((INSTANCE) == TIM2) || \
17026                                     ((INSTANCE) == TIM3) || \
17027                                     ((INSTANCE) == TIM4) || \
17028                                     ((INSTANCE) == TIM5) || \
17029                                     ((INSTANCE) == TIM6) || \
17030                                     ((INSTANCE) == TIM7) || \
17031                                     ((INSTANCE) == TIM8) || \
17032                                     ((INSTANCE) == TIM9) || \
17033                                     ((INSTANCE) == TIM10)|| \
17034                                     ((INSTANCE) == TIM11)|| \
17035                                     ((INSTANCE) == TIM12)|| \
17036                                     ((INSTANCE) == TIM13)|| \
17037                                     ((INSTANCE) == TIM14))
17038 
17039 /************* TIM Instances : at least 1 capture/compare channel *************/
17040 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
17041                                          ((INSTANCE) == TIM2)  || \
17042                                          ((INSTANCE) == TIM3)  || \
17043                                          ((INSTANCE) == TIM4)  || \
17044                                          ((INSTANCE) == TIM5)  || \
17045                                          ((INSTANCE) == TIM8)  || \
17046                                          ((INSTANCE) == TIM9)  || \
17047                                          ((INSTANCE) == TIM10) || \
17048                                          ((INSTANCE) == TIM11) || \
17049                                          ((INSTANCE) == TIM12) || \
17050                                          ((INSTANCE) == TIM13) || \
17051                                          ((INSTANCE) == TIM14))
17052 
17053 /************ TIM Instances : at least 2 capture/compare channels *************/
17054 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17055                                        ((INSTANCE) == TIM2) || \
17056                                        ((INSTANCE) == TIM3) || \
17057                                        ((INSTANCE) == TIM4) || \
17058                                        ((INSTANCE) == TIM5) || \
17059                                        ((INSTANCE) == TIM8) || \
17060                                        ((INSTANCE) == TIM9) || \
17061                                        ((INSTANCE) == TIM12))
17062 
17063 /************ TIM Instances : at least 3 capture/compare channels *************/
17064 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
17065                                          ((INSTANCE) == TIM2) || \
17066                                          ((INSTANCE) == TIM3) || \
17067                                          ((INSTANCE) == TIM4) || \
17068                                          ((INSTANCE) == TIM5) || \
17069                                          ((INSTANCE) == TIM8))
17070 
17071 /************ TIM Instances : at least 4 capture/compare channels *************/
17072 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17073                                        ((INSTANCE) == TIM2) || \
17074                                        ((INSTANCE) == TIM3) || \
17075                                        ((INSTANCE) == TIM4) || \
17076                                        ((INSTANCE) == TIM5) || \
17077                                        ((INSTANCE) == TIM8))
17078 
17079 /******************** TIM Instances : Advanced-control timers *****************/
17080 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17081                                            ((INSTANCE) == TIM8))
17082 
17083 /******************* TIM Instances : Timer input XOR function *****************/
17084 #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
17085                                          ((INSTANCE) == TIM2) || \
17086                                          ((INSTANCE) == TIM3) || \
17087                                          ((INSTANCE) == TIM4) || \
17088                                          ((INSTANCE) == TIM5) || \
17089                                          ((INSTANCE) == TIM8))
17090 
17091 /****************** TIM Instances : DMA requests generation (UDE) *************/
17092 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17093                                        ((INSTANCE) == TIM2) || \
17094                                        ((INSTANCE) == TIM3) || \
17095                                        ((INSTANCE) == TIM4) || \
17096                                        ((INSTANCE) == TIM5) || \
17097                                        ((INSTANCE) == TIM6) || \
17098                                        ((INSTANCE) == TIM7) || \
17099                                        ((INSTANCE) == TIM8))
17100 
17101 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
17102 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17103                                           ((INSTANCE) == TIM2) || \
17104                                           ((INSTANCE) == TIM3) || \
17105                                           ((INSTANCE) == TIM4) || \
17106                                           ((INSTANCE) == TIM5) || \
17107                                           ((INSTANCE) == TIM8))
17108 
17109 /************ TIM Instances : DMA requests generation (COMDE) *****************/
17110 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17111                                           ((INSTANCE) == TIM2) || \
17112                                           ((INSTANCE) == TIM3) || \
17113                                           ((INSTANCE) == TIM4) || \
17114                                           ((INSTANCE) == TIM5) || \
17115                                           ((INSTANCE) == TIM8))
17116 
17117 /******************** TIM Instances : DMA burst feature ***********************/
17118 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17119                                              ((INSTANCE) == TIM2) || \
17120                                              ((INSTANCE) == TIM3) || \
17121                                              ((INSTANCE) == TIM4) || \
17122                                              ((INSTANCE) == TIM5) || \
17123                                              ((INSTANCE) == TIM8))
17124 
17125 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
17126 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
17127                                           ((INSTANCE) == TIM2)  || \
17128                                           ((INSTANCE) == TIM3)  || \
17129                                           ((INSTANCE) == TIM4)  || \
17130                                           ((INSTANCE) == TIM5)  || \
17131                                           ((INSTANCE) == TIM6)  || \
17132                                           ((INSTANCE) == TIM7)  || \
17133                                           ((INSTANCE) == TIM8))
17134 
17135 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17136 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17137                                          ((INSTANCE) == TIM2) || \
17138                                          ((INSTANCE) == TIM3) || \
17139                                          ((INSTANCE) == TIM4) || \
17140                                          ((INSTANCE) == TIM5) || \
17141                                          ((INSTANCE) == TIM8) || \
17142                                          ((INSTANCE) == TIM9) || \
17143                                          ((INSTANCE) == TIM12))
17144 /********************** TIM Instances : 32 bit Counter ************************/
17145 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
17146                                               ((INSTANCE) == TIM5))
17147 
17148 /***************** TIM Instances : external trigger input availabe ************/
17149 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17150                                         ((INSTANCE) == TIM2) || \
17151                                         ((INSTANCE) == TIM3) || \
17152                                         ((INSTANCE) == TIM4) || \
17153                                         ((INSTANCE) == TIM5) || \
17154                                         ((INSTANCE) == TIM8))
17155 
17156 /****************** TIM Instances : remapping capability **********************/
17157 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
17158                                          ((INSTANCE) == TIM5)  || \
17159                                          ((INSTANCE) == TIM11))
17160 
17161 /******************* TIM Instances : output(s) available **********************/
17162 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
17163     ((((INSTANCE) == TIM1) &&                  \
17164      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17165       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17166       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17167       ((CHANNEL) == TIM_CHANNEL_4)))           \
17168     ||                                         \
17169     (((INSTANCE) == TIM2) &&                   \
17170      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17171       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17172       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17173       ((CHANNEL) == TIM_CHANNEL_4)))           \
17174     ||                                         \
17175     (((INSTANCE) == TIM3) &&                   \
17176      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17177       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17178       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17179       ((CHANNEL) == TIM_CHANNEL_4)))           \
17180     ||                                         \
17181     (((INSTANCE) == TIM4) &&                   \
17182      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17183       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17184       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17185       ((CHANNEL) == TIM_CHANNEL_4)))           \
17186     ||                                         \
17187     (((INSTANCE) == TIM5) &&                   \
17188      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17189       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17190       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17191       ((CHANNEL) == TIM_CHANNEL_4)))           \
17192     ||                                         \
17193     (((INSTANCE) == TIM8) &&                   \
17194      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17195       ((CHANNEL) == TIM_CHANNEL_2) ||          \
17196       ((CHANNEL) == TIM_CHANNEL_3) ||          \
17197       ((CHANNEL) == TIM_CHANNEL_4)))           \
17198     ||                                         \
17199     (((INSTANCE) == TIM9) &&                   \
17200      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17201       ((CHANNEL) == TIM_CHANNEL_2)))           \
17202     ||                                         \
17203     (((INSTANCE) == TIM10) &&                  \
17204      (((CHANNEL) == TIM_CHANNEL_1)))           \
17205     ||                                         \
17206     (((INSTANCE) == TIM11) &&                  \
17207      (((CHANNEL) == TIM_CHANNEL_1)))           \
17208     ||                                         \
17209     (((INSTANCE) == TIM12) &&                  \
17210      (((CHANNEL) == TIM_CHANNEL_1) ||          \
17211       ((CHANNEL) == TIM_CHANNEL_2)))           \
17212     ||                                         \
17213     (((INSTANCE) == TIM13) &&                  \
17214      (((CHANNEL) == TIM_CHANNEL_1)))           \
17215     ||                                         \
17216     (((INSTANCE) == TIM14) &&                  \
17217      (((CHANNEL) == TIM_CHANNEL_1))))
17218 
17219 /************ TIM Instances : complementary output(s) available ***************/
17220 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
17221    ((((INSTANCE) == TIM1) &&                    \
17222      (((CHANNEL) == TIM_CHANNEL_1) ||           \
17223       ((CHANNEL) == TIM_CHANNEL_2) ||           \
17224       ((CHANNEL) == TIM_CHANNEL_3)))            \
17225     ||                                          \
17226     (((INSTANCE) == TIM8) &&                    \
17227      (((CHANNEL) == TIM_CHANNEL_1) ||           \
17228       ((CHANNEL) == TIM_CHANNEL_2) ||           \
17229       ((CHANNEL) == TIM_CHANNEL_3))))
17230 
17231 /****************** TIM Instances : supporting counting mode selection ********/
17232 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17233                                                         ((INSTANCE) == TIM2) || \
17234                                                         ((INSTANCE) == TIM3) || \
17235                                                         ((INSTANCE) == TIM4) || \
17236                                                         ((INSTANCE) == TIM5) || \
17237                                                         ((INSTANCE) == TIM8))
17238 
17239 /****************** TIM Instances : supporting clock division *****************/
17240 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
17241                                                   ((INSTANCE) == TIM2) || \
17242                                                   ((INSTANCE) == TIM3) || \
17243                                                   ((INSTANCE) == TIM4) || \
17244                                                   ((INSTANCE) == TIM5) || \
17245                                                   ((INSTANCE) == TIM8) || \
17246                                                   ((INSTANCE) == TIM9) || \
17247                                                   ((INSTANCE) == TIM10)|| \
17248                                                   ((INSTANCE) == TIM11)|| \
17249                                                   ((INSTANCE) == TIM12)|| \
17250                                                   ((INSTANCE) == TIM13)|| \
17251                                                   ((INSTANCE) == TIM14))
17252 
17253 /****************** TIM Instances : supporting commutation event generation ***/
17254 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
17255                                                      ((INSTANCE) == TIM8))
17256 
17257 
17258 /****************** TIM Instances : supporting OCxREF clear *******************/
17259 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
17260                                                        ((INSTANCE) == TIM2) || \
17261                                                        ((INSTANCE) == TIM3) || \
17262                                                        ((INSTANCE) == TIM4) || \
17263                                                        ((INSTANCE) == TIM5) || \
17264                                                        ((INSTANCE) == TIM8))
17265 
17266 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
17267 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17268                                                         ((INSTANCE) == TIM2) || \
17269                                                         ((INSTANCE) == TIM3) || \
17270                                                         ((INSTANCE) == TIM4) || \
17271                                                         ((INSTANCE) == TIM5) || \
17272                                                         ((INSTANCE) == TIM8) || \
17273                                                         ((INSTANCE) == TIM9) || \
17274                                                         ((INSTANCE) == TIM12))
17275 
17276 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
17277 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17278                                                         ((INSTANCE) == TIM2) || \
17279                                                         ((INSTANCE) == TIM3) || \
17280                                                         ((INSTANCE) == TIM4) || \
17281                                                         ((INSTANCE) == TIM5) || \
17282                                                         ((INSTANCE) == TIM8))
17283 
17284 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
17285 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
17286                                                         ((INSTANCE) == TIM2) || \
17287                                                         ((INSTANCE) == TIM3) || \
17288                                                         ((INSTANCE) == TIM4) || \
17289                                                         ((INSTANCE) == TIM5) || \
17290                                                         ((INSTANCE) == TIM8) || \
17291                                                         ((INSTANCE) == TIM9) || \
17292                                                         ((INSTANCE) == TIM12))
17293 
17294 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
17295 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
17296                                                         ((INSTANCE) == TIM2) || \
17297                                                         ((INSTANCE) == TIM3) || \
17298                                                         ((INSTANCE) == TIM4) || \
17299                                                         ((INSTANCE) == TIM5) || \
17300                                                         ((INSTANCE) == TIM8) || \
17301                                                         ((INSTANCE) == TIM9) || \
17302                                                         ((INSTANCE) == TIM12))
17303 
17304 /****************** TIM Instances : supporting repetition counter *************/
17305 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17306                                                        ((INSTANCE) == TIM8))
17307 
17308 /****************** TIM Instances : supporting encoder interface **************/
17309 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17310                                                       ((INSTANCE) == TIM2) || \
17311                                                       ((INSTANCE) == TIM3) || \
17312                                                       ((INSTANCE) == TIM4) || \
17313                                                       ((INSTANCE) == TIM5) || \
17314                                                       ((INSTANCE) == TIM8) || \
17315                                                       ((INSTANCE) == TIM9) || \
17316                                                       ((INSTANCE) == TIM12))
17317 /****************** TIM Instances : supporting Hall sensor interface **********/
17318 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17319                                                           ((INSTANCE) == TIM2) || \
17320                                                           ((INSTANCE) == TIM3) || \
17321                                                           ((INSTANCE) == TIM4) || \
17322                                                           ((INSTANCE) == TIM5) || \
17323                                                           ((INSTANCE) == TIM8))
17324 /****************** TIM Instances : supporting the break function *************/
17325 #define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
17326                                           ((INSTANCE) == TIM8))
17327 
17328 /******************** USART Instances : Synchronous mode **********************/
17329 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17330                                      ((INSTANCE) == USART2) || \
17331                                      ((INSTANCE) == USART3) || \
17332                                      ((INSTANCE) == USART6))
17333 
17334 /******************** UART Instances : Half-Duplex mode **********************/
17335 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17336                                                ((INSTANCE) == USART2) || \
17337                                                ((INSTANCE) == USART3) || \
17338                                                ((INSTANCE) == UART4)  || \
17339                                                ((INSTANCE) == UART5)  || \
17340                                                ((INSTANCE) == USART6) || \
17341                                                ((INSTANCE) == UART7)  || \
17342                                                ((INSTANCE) == UART8))
17343 
17344 /* Legacy defines */
17345 #define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
17346 
17347 /****************** UART Instances : Hardware Flow control ********************/
17348 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17349                                            ((INSTANCE) == USART2) || \
17350                                            ((INSTANCE) == USART3) || \
17351                                            ((INSTANCE) == USART6))
17352 /******************** UART Instances : LIN mode **********************/
17353 #define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
17354 
17355 /********************* UART Instances : Smart card mode ***********************/
17356 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17357                                          ((INSTANCE) == USART2) || \
17358                                          ((INSTANCE) == USART3) || \
17359                                          ((INSTANCE) == USART6))
17360 
17361 /*********************** UART Instances : IRDA mode ***************************/
17362 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
17363                                     ((INSTANCE) == USART2) || \
17364                                     ((INSTANCE) == USART3) || \
17365                                     ((INSTANCE) == UART4)  || \
17366                                     ((INSTANCE) == UART5)  || \
17367                                     ((INSTANCE) == USART6) || \
17368                                     ((INSTANCE) == UART7)  || \
17369                                     ((INSTANCE) == UART8))
17370 
17371 /*********************** PCD Instances ****************************************/
17372 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17373                                        ((INSTANCE) == USB_OTG_HS))
17374 
17375 /*********************** HCD Instances ****************************************/
17376 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17377                                        ((INSTANCE) == USB_OTG_HS))
17378 
17379 /****************************** SDIO Instances ********************************/
17380 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
17381 
17382 /****************************** IWDG Instances ********************************/
17383 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
17384 
17385 /****************************** WWDG Instances ********************************/
17386 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
17387 
17388 /****************************** USB Exported Constants ************************/
17389 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
17390 #define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
17391 #define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
17392 #define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
17393 
17394 /*
17395  * @brief Specific devices reset values definitions
17396  */
17397 #define RCC_PLLCFGR_RST_VALUE              0x24003010U
17398 #define RCC_PLLI2SCFGR_RST_VALUE           0x24003000U
17399 #define RCC_PLLSAICFGR_RST_VALUE           0x24003000U
17400 
17401 #define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/
17402 #define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
17403 #define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
17404 #define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
17405 #define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
17406 #define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
17407 #define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
17408 #define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
17409 
17410 #define RCC_PLLN_MIN_VALUE                 50U
17411 #define RCC_PLLN_MAX_VALUE                432U
17412 
17413 #define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
17414 #define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
17415 #define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
17416 #define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
17417 #define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
17418 
17419 #define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
17420 #define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
17421 #define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
17422 #define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
17423 #define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */
17424 
17425 #define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
17426 #define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
17427 #define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
17428 
17429 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
17430 #define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
17431 #define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
17432 #define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
17433 /******************************************************************************/
17434 /*  For a painless codes migration between the STM32F4xx device product       */
17435 /*  lines, the aliases defined below are put in place to overcome the         */
17436 /*  differences in the interrupt handlers and IRQn definitions.               */
17437 /*  No need to update developed interrupt code when moving across             */
17438 /*  product lines within the same STM32F4 Family                              */
17439 /******************************************************************************/
17440 /* Aliases for __IRQn */
17441 #define FSMC_IRQn              FMC_IRQn
17442 
17443 /* Aliases for __IRQHandler */
17444 #define FSMC_IRQHandler        FMC_IRQHandler
17445 
17446 /**
17447   * @}
17448   */
17449 
17450 /**
17451   * @}
17452   */
17453 
17454 /**
17455   * @}
17456   */
17457 
17458 #ifdef __cplusplus
17459 }
17460 #endif /* __cplusplus */
17461 
17462 #endif /* __STM32F439xx_H */
17463 
17464 
17465 
17466 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
17467