1 #![cfg_attr(not(feature = "sync"), allow(dead_code, unreachable_pub))] 2 use std::ops::{Deref, DerefMut}; 3 4 /// Pads and aligns a value to the length of a cache line. 5 #[derive(Clone, Copy, Default, Hash, PartialEq, Eq)] 6 // Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache 7 // lines at a time, so we have to align to 128 bytes rather than 64. 8 // 9 // Sources: 10 // - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf 11 // - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107 12 // 13 // ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size. 14 // 15 // Sources: 16 // - https://www.mono-project.com/news/2016/09/12/arm64-icache/ 17 // 18 // powerpc64 has 128-byte cache line size. 19 // 20 // Sources: 21 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9 22 #[cfg_attr( 23 any( 24 target_arch = "x86_64", 25 target_arch = "aarch64", 26 target_arch = "powerpc64", 27 ), 28 repr(align(128)) 29 )] 30 // arm, mips and mips64 have 32-byte cache line size. 31 // 32 // Sources: 33 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7 34 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7 35 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7 36 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9 37 #[cfg_attr( 38 any(target_arch = "arm", target_arch = "mips", target_arch = "mips64",), 39 repr(align(32)) 40 )] 41 // s390x has 256-byte cache line size. 42 // 43 // Sources: 44 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7 45 #[cfg_attr(target_arch = "s390x", repr(align(256)))] 46 // x86, riscv and wasm have 64-byte cache line size. 47 // 48 // Sources: 49 // - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9 50 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7 51 // - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/riscv/include/asm/cache.h#L10 52 // 53 // All others are assumed to have 64-byte cache line size. 54 #[cfg_attr( 55 not(any( 56 target_arch = "x86_64", 57 target_arch = "aarch64", 58 target_arch = "powerpc64", 59 target_arch = "arm", 60 target_arch = "mips", 61 target_arch = "mips64", 62 target_arch = "s390x", 63 )), 64 repr(align(64)) 65 )] 66 pub(crate) struct CachePadded<T> { 67 value: T, 68 } 69 70 impl<T> CachePadded<T> { 71 /// Pads and aligns a value to the length of a cache line. new(value: T) -> CachePadded<T>72 pub(crate) fn new(value: T) -> CachePadded<T> { 73 CachePadded::<T> { value } 74 } 75 } 76 77 impl<T> Deref for CachePadded<T> { 78 type Target = T; 79 deref(&self) -> &T80 fn deref(&self) -> &T { 81 &self.value 82 } 83 } 84 85 impl<T> DerefMut for CachePadded<T> { deref_mut(&mut self) -> &mut T86 fn deref_mut(&mut self) -> &mut T { 87 &mut self.value 88 } 89 } 90