1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <memlayout.h> 4 5#include <arch/header.ld> 6 7/* 8 * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock 9 * must be placed after that. After the handoff, the space can be reclaimed. 10 */ 11 12SECTIONS 13{ 14 SRAM_START(0x2020000) 15 /* 17K hole, includes BL1 */ 16 /* Bootblock is preceded by 16 byte variable length BL2 checksum. */ 17 BOOTBLOCK(0x2024410, 32K - 16) 18 /* 15K hole */ 19 ROMSTAGE(0x2030000, 128K) 20 /* 32K hole */ 21 TTB(0x2058000, 16K) 22 PRERAM_CBFS_CACHE(0x205C000, 66K) 23 CBFS_MCACHE(0x206C800, 8K) 24 FMAP_CACHE(0x206E800, 2K) 25 STACK(0x206F000, 16K) 26 /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't 27 * seem to be implemented right now? */ 28 SRAM_END(0x2074000) 29 30 DRAM_START(0x20000000) 31 RAMSTAGE(0x20000000, 2M) 32 POSTRAM_CBFS_CACHE(0x21000000, 8M) 33 DMA_COHERENT(0x77300000, 1M) 34} 35