1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#include <memlayout.h> 4 5#include <arch/header.ld> 6 7/* 8 * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock 9 * must be placed after that. After the handoff, the space can be reclaimed. 10 */ 11 12SECTIONS 13{ 14 SRAM_START(0x2020000) 15 /* 13K hole, includes BL1 */ 16 BOOTBLOCK(0x2023400, 32K) 17 /* 19K hole */ 18 ROMSTAGE(0x2030000, 128K) 19 /* 32K hole */ 20 TTB(0x2058000, 16K) 21 PRERAM_CBFS_CACHE(0x205C000, 68K) 22 CBFS_MCACHE(0x206D000, 8K) 23 FMAP_CACHE(0x206F000, 2K) 24 TPM_LOG(0x206F800, 2K) 25 VBOOT2_WORK(0x2070000, 12K) 26 STACK(0x2074000, 16K) 27 SRAM_END(0x2078000) 28 29 DRAM_START(0x40000000) 30 RAMSTAGE(0x40000000, 2M) 31 POSTRAM_CBFS_CACHE(0x41000000, 8M) 32 DMA_COHERENT(0x77300000, 1M) 33} 34