xref: /aosp_15_r20/external/coreboot/src/soc/nvidia/tegra210/memlayout.ld (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <memlayout.h>
4
5#include <arch/header.ld>
6
7/*
8 * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
9 * so the bootblock loading address must be placed after that. After the
10 * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
11 * TODO: Did this change on Tegra210? What's the new valid range?
12 */
13
14SECTIONS
15{
16	SRAM_START(0x40000000)
17	PRERAM_CBMEM_CONSOLE(0x40000000, 2K)
18	FMAP_CACHE(0x40000800, 2K)
19	PRERAM_CBFS_CACHE(0x40001000, 20K)
20	CBFS_MCACHE(0x40006000, 8K)
21	VBOOT2_WORK(0x40008000, 12K)
22	TPM_LOG(0x4000B000, 2K)
23#if ENV_ARM64
24	STACK(0x4000B800, 3K)
25#else	/* AVP gets a separate stack to avoid any chance of handoff races. */
26	STACK(0x4000C400, 3K)
27#endif
28	TIMESTAMP(0x4000D000, 2K)
29	BOOTBLOCK(0x4000D800, 42K)
30	OVERLAP_VERSTAGE_ROMSTAGE(0x40018000, 160K)
31	SRAM_END(0x40040000)
32
33	DRAM_START(0x80000000)
34	POSTRAM_CBFS_CACHE(0x80100000, 1M)
35	RAMSTAGE(0x80200000, 2M)
36	TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M)
37}
38