1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_BLOCK_GPIO_DEFS_H_ 4 #define _SOC_BLOCK_GPIO_DEFS_H_ 5 6 #include <intelblocks/gpio.h> 7 8 #define _BIT_WIDTH(x) ((1 << (x)) - 1) 9 10 #define PAD_CFG0_TX_STATE_BIT 0 11 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) 12 #define PAD_CFG0_RX_STATE_BIT 1 13 #define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) 14 #define PAD_CFG0_TX_DISABLE (1 << 8) 15 #define PAD_CFG0_RX_DISABLE (1 << 9) 16 #define PAD_CFG0_MODE_SHIFT 10 17 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS) 18 #define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(4) 19 #else 20 #define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(3) 21 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */ 22 #define PAD_CFG0_MODE_MASK (PAD_CFG0_MODE_BIT_WIDTH << PAD_CFG0_MODE_SHIFT) 23 #define PAD_CFG0_MODE_FUNC(x) ((x) << PAD_CFG0_MODE_SHIFT) 24 #define PAD_CFG0_MODE_GPIO PAD_CFG0_MODE_FUNC(0) 25 #define PAD_CFG0_MODE_NF1 PAD_CFG0_MODE_FUNC(1) 26 #define PAD_CFG0_MODE_NF2 PAD_CFG0_MODE_FUNC(2) 27 #define PAD_CFG0_MODE_NF3 PAD_CFG0_MODE_FUNC(3) 28 #define PAD_CFG0_MODE_NF4 PAD_CFG0_MODE_FUNC(4) 29 #define PAD_CFG0_MODE_NF5 PAD_CFG0_MODE_FUNC(5) 30 #define PAD_CFG0_MODE_NF6 PAD_CFG0_MODE_FUNC(6) 31 #define PAD_CFG0_MODE_NF7 PAD_CFG0_MODE_FUNC(7) 32 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS) 33 #define PAD_CFG0_MODE_NF8 PAD_CFG0_MODE_FUNC(8) 34 #define PAD_CFG0_MODE_NF9 PAD_CFG0_MODE_FUNC(9) 35 #define PAD_CFG0_MODE_NF10 PAD_CFG0_MODE_FUNC(10) 36 #define PAD_CFG0_MODE_NF11 PAD_CFG0_MODE_FUNC(11) 37 #define PAD_CFG0_MODE_NF12 PAD_CFG0_MODE_FUNC(12) 38 #define PAD_CFG0_MODE_NF13 PAD_CFG0_MODE_FUNC(13) 39 #define PAD_CFG0_MODE_NF14 PAD_CFG0_MODE_FUNC(14) 40 #define PAD_CFG0_MODE_NF15 PAD_CFG0_MODE_FUNC(15) 41 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */ 42 #define PAD_CFG0_ROUTE_MASK (0xF << 17) 43 #define PAD_CFG0_ROUTE_NMI (1 << 17) 44 #define PAD_CFG0_ROUTE_SMI (1 << 18) 45 #define PAD_CFG0_ROUTE_SCI (1 << 19) 46 #define PAD_CFG0_ROUTE_IOAPIC (1 << 20) 47 #define PAD_CFG0_ROUTE_SWAPPED (1 << 27) 48 #define PAD_CFG0_RXTENCFG_MASK (3 << 21) 49 #define PAD_CFG0_RXINV_MASK (1 << 23) 50 #define PAD_CFG0_RX_POL_INVERT (1 << 23) 51 #define PAD_CFG0_RX_POL_NONE (0 << 23) 52 #define PAD_CFG0_PREGFRXSEL (1 << 24) 53 #define PAD_CFG0_TRIG_MASK (3 << 25) 54 #define PAD_CFG0_TRIG_LEVEL (0 << 25) 55 #define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ 56 #define PAD_CFG0_TRIG_OFF (2 << 25) 57 #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) 58 #define PAD_CFG0_NAFVWE_ENABLE (1 << 27) 59 #define PAD_CFG0_RXRAW1_MASK (1 << 28) 60 #define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) 61 #define PAD_CFG0_RESET_MASK (3 << 30) 62 #define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30) 63 #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) 64 #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) 65 #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) 66 /* 67 * Alder Lake PCH onwards a newer bit field has added 68 * for GPP as `Global Reset` 69 */ 70 #define PAD_CFG0_LOGICAL_RESET_GLBRST (3U << 30) 71 72 /* 73 * Use the fourth bit in IntSel field to indicate gpio 74 * ownership. This field is RO and hence not used during 75 * gpio configuration. 76 */ 77 #define PAD_CFG_OWN_GPIO_DRIVER (1 << 4) 78 #define PAD_CFG_OWN_GPIO_ACPI (0 << 4) 79 #define PAD_CFG_OWN_GPIO(own) PAD_CFG_OWN_GPIO_##own 80 81 #define PAD_CFG1_IRQ_MASK (0xff << 0) 82 #define PAD_CFG1_IOSTERM_MASK (0x3 << 8) 83 #define PAD_CFG1_IOSTERM_SAME (0x0 << 8) 84 #define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) 85 #define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) 86 #define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) 87 #define PAD_CFG1_PULL_MASK (0xf << 10) 88 #define PAD_CFG1_PULL_NONE (0x0 << 10) 89 #define PAD_CFG1_PULL_DN_5K (0x2 << 10) 90 #define PAD_CFG1_PULL_DN_20K (0x4 << 10) 91 #define PAD_CFG1_PULL_UP_1K (0x9 << 10) 92 #define PAD_CFG1_PULL_UP_5K (0xa << 10) 93 #define PAD_CFG1_PULL_UP_2K (0xb << 10) 94 #define PAD_CFG1_PULL_UP_20K (0xc << 10) 95 #define PAD_CFG1_PULL_UP_667 (0xd << 10) 96 #define PAD_CFG1_PULL_NATIVE (0xf << 10) 97 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) 98 /* Tx enabled driving last value driven, Rx enabled */ 99 #define PAD_CFG1_IOSSTATE_TxLASTRxE (0x0 << 14) 100 /* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller 101 * internally */ 102 #define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 14) 103 /* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller 104 * internally */ 105 #define PAD_CFG1_IOSSTATE_Tx0RxDCRx1 (0x2 << 14) 106 /* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller 107 * internally */ 108 #define PAD_CFG1_IOSSTATE_Tx1RxDCRx0 (0x3 << 14) 109 /* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller 110 * internally */ 111 #define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 14) 112 /* Tx enabled driving 0, Rx enabled */ 113 #define PAD_CFG1_IOSSTATE_Tx0RxE (0x5 << 14) 114 /* Tx enabled driving 1, Rx enabled */ 115 #define PAD_CFG1_IOSSTATE_Tx1RxE (0x6 << 14) 116 /* Hi-Z, Rx driving 0 back to its controller internally */ 117 #define PAD_CFG1_IOSSTATE_HIZCRx0 (0x7 << 14) 118 /* Hi-Z, Rx driving 1 back to its controller internally */ 119 #define PAD_CFG1_IOSSTATE_HIZCRx1 (0x8 << 14) 120 #define PAD_CFG1_IOSSTATE_TxDRxE (0x9 << 14) /* Tx disabled, Rx enabled */ 121 #define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */ 122 #define PAD_CFG1_IOSSTATE_MASK (0xf << 14) /* mask to extract Iostandby bits */ 123 #define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ 124 #else /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ 125 #define PAD_CFG1_IOSSTATE_MASK 0 126 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY */ 127 128 #define PAD_CFG2_DEBEN 1 129 /* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */ 130 #define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1) 131 #define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1) 132 #define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1) 133 #define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1) 134 #define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1) 135 #define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1) 136 #define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1) 137 #define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1) 138 #define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1) 139 #define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1) 140 #define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1) 141 #define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1) 142 #define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1) 143 #define PAD_CFG2_DEBOUNCE_MASK 0x1f 144 145 /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ 146 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) 147 #define PAD_CFG1_TOL_MASK (0x1 << 25) 148 #define PAD_CFG1_TOL_1V8 (0x1 << 25) 149 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */ 150 151 #define PAD_FUNC(value) PAD_CFG0_MODE_##value 152 #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value 153 #define PAD_RX_POL(value) PAD_CFG0_RX_POL_##value 154 #define PAD_IRQ_ROUTE(value) PAD_CFG0_ROUTE_##value 155 #define PAD_TRIG(value) PAD_CFG0_TRIG_##value 156 #define PAD_PULL(value) PAD_CFG1_PULL_##value 157 #define PAD_LOCK(value) GPIO_##value 158 159 /* Disable the input/output buffer of the pad */ 160 #define PAD_CFG0_BUF_NO_DISABLE (0) 161 #define PAD_CFG0_BUF_TX_DISABLE PAD_CFG0_TX_DISABLE 162 #define PAD_CFG0_BUF_RX_DISABLE PAD_CFG0_RX_DISABLE 163 #define PAD_CFG0_BUF_TX_RX_DISABLE \ 164 (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE) 165 166 #define PAD_BUF(value) PAD_CFG0_BUF_##value 167 168 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY) 169 #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value 170 #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value 171 #else 172 #define PAD_IOSSTATE(value) 0 173 #define PAD_IOSTERM(value) 0 174 #endif 175 176 #define PAD_IRQ_CFG(route, trig, inv) \ 177 (PAD_IRQ_ROUTE(route) | \ 178 PAD_TRIG(trig) | \ 179 PAD_RX_POL(inv)) 180 181 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) 182 #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ 183 (PAD_IRQ_ROUTE(route1) | \ 184 PAD_IRQ_ROUTE(route2) | \ 185 PAD_TRIG(trig) | \ 186 PAD_RX_POL(inv)) 187 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ 188 189 #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ 190 { \ 191 .pad = __pad, \ 192 .pad_config[0] = __config0, \ 193 .pad_config[1] = __config1, \ 194 .lock_action = PAD_LOCK(UNLOCK), \ 195 } 196 197 #define _PAD_CFG_STRUCT_LOCK(__pad, __config0, __config1, __action) \ 198 { \ 199 .pad = __pad, \ 200 .pad_config[0] = __config0, \ 201 .pad_config[1] = __config1, \ 202 .lock_action = __action, \ 203 } 204 205 #if GPIO_NUM_PAD_CFG_REGS > 2 206 #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ 207 { \ 208 .pad = __pad, \ 209 .pad_config[0] = __config0, \ 210 .pad_config[1] = __config1, \ 211 .pad_config[2] = __config2, \ 212 .lock_action = PAD_LOCK(UNLOCK), \ 213 } 214 #else 215 #define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ 216 _PAD_CFG_STRUCT(__pad, __config0, __config1) 217 #endif 218 219 /* Native function configuration */ 220 #define PAD_CFG_NF(pad, pull, rst, func) \ 221 _PAD_CFG_STRUCT(pad, \ 222 PAD_RESET(rst) | PAD_FUNC(func), \ 223 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) 224 225 /* Native function configuration with lock */ 226 #define PAD_CFG_NF_LOCK(pad, pull, func, lock_action) \ 227 _PAD_CFG_STRUCT_LOCK(pad, \ 228 PAD_RESET(PWROK) | PAD_FUNC(func), \ 229 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE), \ 230 PAD_LOCK(lock_action)) 231 232 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) 233 /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S 234 Not applicable to all SOCs. Refer EDS 235 */ 236 #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ 237 _PAD_CFG_STRUCT(pad, \ 238 PAD_RESET(rst) | PAD_FUNC(func), \ 239 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) 240 #endif 241 242 /* Native function configuration for standby state */ 243 #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ 244 _PAD_CFG_STRUCT(pad, \ 245 PAD_RESET(rst) | PAD_FUNC(func), \ 246 PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) 247 248 /* Native function configuration for standby state, also configuring 249 iostandby as masked */ 250 #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ 251 _PAD_CFG_STRUCT(pad, \ 252 PAD_RESET(rst) | PAD_FUNC(func), \ 253 PAD_PULL(pull) | PAD_IOSSTATE(IGNORE)) 254 255 /* Native function configuration for standby state, also configuring 256 iosstate and iosterm */ 257 #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ 258 _PAD_CFG_STRUCT(pad, \ 259 PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 260 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 261 262 /* Native function configuration with "native function virtual wire 263 messaging enable (NAFVWE_ENABLE)" */ 264 #define PAD_CFG_NF_VWEN(pad, pull, rst, func) \ 265 _PAD_CFG_STRUCT(pad, \ 266 PAD_RESET(rst) | PAD_FUNC(func) | PAD_CFG0_NAFVWE_ENABLE,\ 267 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) 268 269 /* General purpose output, no pullup/down. */ 270 #define PAD_CFG_GPO(pad, val, rst) \ 271 _PAD_CFG_STRUCT(pad, \ 272 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 273 PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ 274 PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) 275 276 /* General purpose output with lock, no pullup/down. */ 277 #define PAD_CFG_GPO_LOCK(pad, val, lock_action) \ 278 _PAD_CFG_STRUCT_LOCK(pad, \ 279 PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ 280 PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ 281 PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), \ 282 PAD_LOCK(lock_action)) 283 284 /* General purpose output, with termination specified */ 285 #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ 286 _PAD_CFG_STRUCT(pad, \ 287 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 288 PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ 289 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) 290 291 /* General purpose output, no pullup/down. */ 292 #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ 293 _PAD_CFG_STRUCT(pad, \ 294 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 295 PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ 296 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ 297 PAD_CFG_OWN_GPIO(DRIVER)) 298 299 /* General purpose output. */ 300 #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ 301 _PAD_CFG_STRUCT(pad, \ 302 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 303 PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ 304 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) 305 306 /* General purpose input */ 307 #define PAD_CFG_GPI(pad, pull, rst) \ 308 _PAD_CFG_STRUCT(pad, \ 309 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ 310 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) 311 312 /* General purpose input with lock */ 313 #define PAD_CFG_GPI_LOCK(pad, pull, lock_action) \ 314 _PAD_CFG_STRUCT_LOCK(pad, \ 315 PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE), \ 316 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \ 317 PAD_LOCK(lock_action)) 318 319 #define PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) \ 320 _PAD_CFG_STRUCT(pad, \ 321 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \ 322 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | PAD_IOSSTATE(iosstate)) 323 324 #define PAD_CFG_GPI_TRIG_IOS_OWN(pad, pull, rst, trig, iosstate, iosterm, own) \ 325 _PAD_CFG_STRUCT(pad, \ 326 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \ 327 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ 328 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 329 330 /* 331 * General purpose input. The following macro sets the 332 * Host Software Pad Ownership to GPIO Driver mode. 333 */ 334 #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ 335 _PAD_CFG_STRUCT(pad, \ 336 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 337 PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ 338 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) 339 340 #define PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, own) \ 341 _PAD_CFG_STRUCT(pad, \ 342 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 343 PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | \ 344 PAD_IRQ_ROUTE(SWAPPED), \ 345 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) 346 347 #define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, lock_action) \ 348 _PAD_CFG_STRUCT_LOCK(pad, \ 349 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 350 PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ 351 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) 352 353 #define PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, rst, trig, own, lock_action) \ 354 _PAD_CFG_STRUCT_LOCK(pad, \ 355 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 356 PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE) | \ 357 PAD_IRQ_ROUTE(SWAPPED), \ 358 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action)) 359 360 #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ 361 _PAD_CFG_STRUCT(pad, \ 362 PAD_FUNC(GPIO) | PAD_RESET(rst) | \ 363 PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ 364 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE)) 365 366 #define PAD_CFG_GPI_GPIO_DRIVER_LOCK(pad, pull, lock_action) \ 367 _PAD_CFG_STRUCT_LOCK(pad, \ 368 PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ 369 PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ 370 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE), \ 371 PAD_LOCK(lock_action)) 372 373 #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ 374 _PAD_CFG_STRUCT(pad, \ 375 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ 376 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ 377 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 378 379 #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ 380 _PAD_CFG_STRUCT(pad, \ 381 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ 382 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 383 384 /* GPIO Interrupt */ 385 #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ 386 PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER) 387 388 #define PAD_CFG_GPI_INT_SWAPPED(pad, pull, rst, trig) \ 389 PAD_CFG_GPI_TRIG_OWN_SWAPPED(pad, pull, rst, trig, DRIVER) 390 391 /* GPIO Interrupt with lock */ 392 #define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action) \ 393 PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, lock_action) 394 395 #define PAD_CFG_GPI_INT_LOCK_SWAPPED(pad, pull, trig, lock_action) \ 396 PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, PWROK, trig, DRIVER, lock_action) 397 398 /* 399 * No Connect configuration for unconnected or unused pad. 400 * Both TX and RX are disabled. RX disabling is done to avoid unnecessary 401 * setting of GPI_STS and to prevent triggering the internal logic by floating 402 * pads. 403 */ 404 #define PAD_NC(pad, pull) \ 405 _PAD_CFG_STRUCT(pad, \ 406 PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ 407 PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ 408 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) 409 410 /* No Connect configuration with lock */ 411 #define PAD_NC_LOCK(pad, pull, lock_action) \ 412 _PAD_CFG_STRUCT_LOCK(pad, \ 413 PAD_RESET(PWROK) | PAD_FUNC(GPIO) | \ 414 PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ 415 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \ 416 PAD_LOCK(lock_action)) 417 418 /* General purpose input, routed to APIC */ 419 #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ 420 _PAD_CFG_STRUCT(pad, \ 421 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 422 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ 423 PAD_IOSSTATE(TxDRxE)) 424 425 /* General purpose input with lock, routed to APIC */ 426 #define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, lock_action) \ 427 _PAD_CFG_STRUCT_LOCK(pad, \ 428 PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \ 429 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ 430 PAD_IOSSTATE(TxDRxE), \ 431 PAD_LOCK(lock_action)) 432 433 /* General purpose input, routed to APIC - with IOStandby Config*/ 434 #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 435 _PAD_CFG_STRUCT(pad, \ 436 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 437 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ 438 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 439 440 /* 441 * The following APIC macros assume the APIC will handle the filtering 442 * on its own end. One just needs to pass an active high message into the 443 * ITSS. 444 */ 445 #define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ 446 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) 447 448 #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ 449 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) 450 451 #define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ 452 PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT) 453 454 /* General purpose input, routed to SMI */ 455 #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ 456 _PAD_CFG_STRUCT(pad, \ 457 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 458 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ 459 PAD_IOSSTATE(TxDRxE)) 460 461 /* General purpose input, routed to SMI */ 462 #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 463 _PAD_CFG_STRUCT(pad, \ 464 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 465 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ 466 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 467 468 #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ 469 PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) 470 471 #define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ 472 PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) 473 474 /* General purpose input, routed to SCI */ 475 #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ 476 _PAD_CFG_STRUCT(pad, \ 477 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 478 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 479 PAD_IOSSTATE(TxDRxE)) 480 481 /* General purpose input with lock, routed to SCI */ 482 #define PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, inv, lock_action) \ 483 _PAD_CFG_STRUCT_LOCK(pad, \ 484 PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \ 485 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 486 PAD_IOSSTATE(TxDRxE), PAD_LOCK(lock_action)) 487 488 /* General purpose input, routed to SCI */ 489 #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 490 _PAD_CFG_STRUCT(pad, \ 491 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 492 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 493 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 494 495 #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ 496 PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) 497 498 #define PAD_CFG_GPI_SCI_LOW_LOCK(pad, pull, trig, lock_action) \ 499 PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, INVERT, lock_action) 500 501 #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ 502 PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) 503 504 #define PAD_CFG_GPI_SCI_HIGH_LOCK(pad, pull, trig, lock_action) \ 505 PAD_CFG_GPI_SCI_LOCK(pad, pull, trig, NONE, lock_action) 506 507 #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ 508 _PAD_CFG_STRUCT_3(pad, \ 509 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 510 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 511 PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) 512 513 #define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ 514 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) 515 516 #define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ 517 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) 518 519 /* General purpose input, routed to NMI */ 520 #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ 521 _PAD_CFG_STRUCT(pad, \ 522 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 523 PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ 524 PAD_IOSSTATE(TxDRxE)) 525 526 #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) 527 #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ 528 _PAD_CFG_STRUCT(pad, \ 529 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 530 PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ 531 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) 532 533 #define PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, rst, trig, inv, route1, route2, lock_action) \ 534 _PAD_CFG_STRUCT_LOCK(pad, \ 535 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ 536 PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ 537 PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \ 538 PAD_LOCK(lock_action)) 539 540 #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ 541 PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) 542 543 #define PAD_CFG_GPI_IRQ_WAKE_LOCK(pad, pull, trig, inv, lock_action) \ 544 PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, PWROK, trig, inv, IOAPIC, SCI, lock_action) 545 546 #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ 547 548 /* Native function configuration */ 549 #define PAD_CFG_NF_OWNERSHIP(pad, pull, rst, func, own) \ 550 _PAD_CFG_STRUCT(pad, \ 551 PAD_RESET(rst) | PAD_FUNC(func) | PAD_TRIG(OFF), \ 552 PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ 553 PAD_CFG_OWN_GPIO(own)) 554 555 #define PAD_CFG_GPIO_OWNERSHIP(pad, pull, rst, own) \ 556 _PAD_CFG_STRUCT(pad, \ 557 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(OFF), \ 558 PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) 559 560 #endif /* _SOC_BLOCK_GPIO_DEFS_H_ */ 561