10x00000000, 0x100000000, WB, # RAM 2# Above entry is needed because below 4G allocated memory range is 3# only known after FSP memory init completes. However, FSP migrates to memory 4# from cache as RAM before it exits FSP Memory Init. Hence we need to add 5# page table entries for this entire range before FSP Memory Init. The 6# overlapped MMIO ranges will be overridden by below entries. 70xd0000000, 0x100000000, UC, NX # All of MMIO 8# Maximum 16MiB of mmio SPI flash decode. 90xff000000, 0x100000000, WP, # memory-mapped SPI 10# MMIO XIP bootblock C_ENV_BOOTBLOCK_SIZE 110xffff8000, 0x100000000, WP, # XIP bootblock 12# DCACHE_RAM_BASE + DCACHE_RAM_SIZE 130xfef00000, 0xff000000, WB, NX # CAR 14# VERSTAGE_ADDR ~63KiB 150xfef40000, 0xfefc0000, WB, # verstage 16# ROMSTAGE_ADDR ~68KiB 170xfef20000, 0xfefc0000, WB, # romstage 18# FSP_M_ADDR ~408 KiB (non-debug) 190xfef40000, 0xfefc0000, WB, # fsp-m 20