1 /*
2 * Copyright (c) 2017-2021 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24 #include "arm_compute/runtime/NEON/functions/NEGEMMLowpOutputStage.h"
25
26 #include "arm_compute/core/ITensor.h"
27 #include "arm_compute/core/Validate.h"
28 #include "src/cpu/operators/CpuGemmLowpOutputStage.h"
29
30 namespace arm_compute
31 {
32 struct NEGEMMLowpOutputStage::Impl
33 {
34 const ITensor *src{ nullptr };
35 const ITensor *bias{ nullptr };
36 ITensor *dst{ nullptr };
37 ITensorPack run_pack{};
38 std::unique_ptr<cpu::CpuGemmLowpOutputStage> op{ nullptr };
39 };
40
NEGEMMLowpOutputStage()41 NEGEMMLowpOutputStage::NEGEMMLowpOutputStage()
42 : _impl(std::make_unique<Impl>())
43 {
44 }
45 NEGEMMLowpOutputStage::~NEGEMMLowpOutputStage() = default;
46
configure(const ITensor * input,const ITensor * bias,ITensor * output,const GEMMLowpOutputStageInfo & info)47 void NEGEMMLowpOutputStage::configure(const ITensor *input, const ITensor *bias, ITensor *output, const GEMMLowpOutputStageInfo &info)
48 {
49 // Perform validate step
50 ARM_COMPUTE_ERROR_ON_NULLPTR(input, output);
51 ARM_COMPUTE_ERROR_THROW_ON(NEGEMMLowpOutputStage::validate(input->info(), bias != nullptr ? bias->info() : nullptr, output->info(), info));
52 _impl->src = input;
53 _impl->bias = bias;
54 _impl->dst = output;
55 _impl->op = std::make_unique<cpu::CpuGemmLowpOutputStage>();
56 _impl->op->configure(input->info(), (bias == nullptr) ? nullptr : bias->info(), output->info(), info);
57
58 _impl->run_pack =
59 {
60 { TensorType::ACL_SRC, _impl->src },
61 { TensorType::ACL_BIAS, _impl->bias },
62 { TensorType::ACL_DST, _impl->dst }
63 };
64 }
65
validate(const ITensorInfo * input,const ITensorInfo * bias,const ITensorInfo * output,const GEMMLowpOutputStageInfo & info)66 Status NEGEMMLowpOutputStage::validate(const ITensorInfo *input, const ITensorInfo *bias, const ITensorInfo *output, const GEMMLowpOutputStageInfo &info)
67 {
68 return cpu::CpuGemmLowpOutputStage::validate(input, bias, output, info);
69 }
70
run()71 void NEGEMMLowpOutputStage::run()
72 {
73 _impl->op->run(_impl->run_pack);
74 }
75 } // namespace arm_compute
76