1 /* 2 * Copyright © 2018, VideoLAN and dav1d authors 3 * Copyright © 2018, Two Orioles, LLC 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, this 10 * list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef DAV1D_SRC_LEVELS_H 29 #define DAV1D_SRC_LEVELS_H 30 31 #include <stdint.h> 32 33 #include "dav1d/headers.h" 34 #include "common/attributes.h" 35 36 enum ObuMetaType { 37 OBU_META_HDR_CLL = 1, 38 OBU_META_HDR_MDCV = 2, 39 OBU_META_SCALABILITY = 3, 40 OBU_META_ITUT_T35 = 4, 41 OBU_META_TIMECODE = 5, 42 }; 43 44 enum TxfmSize { 45 TX_4X4, 46 TX_8X8, 47 TX_16X16, 48 TX_32X32, 49 TX_64X64, 50 N_TX_SIZES, 51 }; 52 53 enum BlockLevel { 54 BL_128X128, 55 BL_64X64, 56 BL_32X32, 57 BL_16X16, 58 BL_8X8, 59 N_BL_LEVELS, 60 }; 61 62 enum RectTxfmSize { 63 RTX_4X8 = N_TX_SIZES, 64 RTX_8X4, 65 RTX_8X16, 66 RTX_16X8, 67 RTX_16X32, 68 RTX_32X16, 69 RTX_32X64, 70 RTX_64X32, 71 RTX_4X16, 72 RTX_16X4, 73 RTX_8X32, 74 RTX_32X8, 75 RTX_16X64, 76 RTX_64X16, 77 N_RECT_TX_SIZES 78 }; 79 80 enum TxfmType { 81 DCT_DCT, // DCT in both horizontal and vertical 82 ADST_DCT, // ADST in vertical, DCT in horizontal 83 DCT_ADST, // DCT in vertical, ADST in horizontal 84 ADST_ADST, // ADST in both directions 85 FLIPADST_DCT, 86 DCT_FLIPADST, 87 FLIPADST_FLIPADST, 88 ADST_FLIPADST, 89 FLIPADST_ADST, 90 IDTX, 91 V_DCT, 92 H_DCT, 93 V_ADST, 94 H_ADST, 95 V_FLIPADST, 96 H_FLIPADST, 97 N_TX_TYPES, 98 WHT_WHT = N_TX_TYPES, 99 N_TX_TYPES_PLUS_LL, 100 }; 101 102 enum TxClass { 103 TX_CLASS_2D, 104 TX_CLASS_H, 105 TX_CLASS_V, 106 }; 107 108 enum IntraPredMode { 109 DC_PRED, 110 VERT_PRED, 111 HOR_PRED, 112 DIAG_DOWN_LEFT_PRED, 113 DIAG_DOWN_RIGHT_PRED, 114 VERT_RIGHT_PRED, 115 HOR_DOWN_PRED, 116 HOR_UP_PRED, 117 VERT_LEFT_PRED, 118 SMOOTH_PRED, 119 SMOOTH_V_PRED, 120 SMOOTH_H_PRED, 121 PAETH_PRED, 122 N_INTRA_PRED_MODES, 123 CFL_PRED = N_INTRA_PRED_MODES, 124 N_UV_INTRA_PRED_MODES, 125 N_IMPL_INTRA_PRED_MODES = N_UV_INTRA_PRED_MODES, 126 LEFT_DC_PRED = DIAG_DOWN_LEFT_PRED, 127 TOP_DC_PRED, 128 DC_128_PRED, 129 Z1_PRED, 130 Z2_PRED, 131 Z3_PRED, 132 FILTER_PRED = N_INTRA_PRED_MODES, 133 }; 134 135 enum InterIntraPredMode { 136 II_DC_PRED, 137 II_VERT_PRED, 138 II_HOR_PRED, 139 II_SMOOTH_PRED, 140 N_INTER_INTRA_PRED_MODES, 141 }; 142 143 enum BlockPartition { 144 PARTITION_NONE, // [ ] <-. 145 PARTITION_H, // [-] | 146 PARTITION_V, // [|] | 147 PARTITION_SPLIT, // [+] --' 148 PARTITION_T_TOP_SPLIT, // [⊥] i.e. split top, H bottom 149 PARTITION_T_BOTTOM_SPLIT, // [т] i.e. H top, split bottom 150 PARTITION_T_LEFT_SPLIT, // [-|] i.e. split left, V right 151 PARTITION_T_RIGHT_SPLIT, // [|-] i.e. V left, split right 152 PARTITION_H4, // [Ⲷ] 153 PARTITION_V4, // [Ⲽ] 154 N_PARTITIONS, 155 N_SUB8X8_PARTITIONS = PARTITION_T_TOP_SPLIT, 156 }; 157 158 enum BlockSize { 159 BS_128x128, 160 BS_128x64, 161 BS_64x128, 162 BS_64x64, 163 BS_64x32, 164 BS_64x16, 165 BS_32x64, 166 BS_32x32, 167 BS_32x16, 168 BS_32x8, 169 BS_16x64, 170 BS_16x32, 171 BS_16x16, 172 BS_16x8, 173 BS_16x4, 174 BS_8x32, 175 BS_8x16, 176 BS_8x8, 177 BS_8x4, 178 BS_4x16, 179 BS_4x8, 180 BS_4x4, 181 N_BS_SIZES, 182 }; 183 184 enum Filter2d { // order is horizontal, vertical 185 FILTER_2D_8TAP_REGULAR, 186 FILTER_2D_8TAP_REGULAR_SMOOTH, 187 FILTER_2D_8TAP_REGULAR_SHARP, 188 FILTER_2D_8TAP_SHARP_REGULAR, 189 FILTER_2D_8TAP_SHARP_SMOOTH, 190 FILTER_2D_8TAP_SHARP, 191 FILTER_2D_8TAP_SMOOTH_REGULAR, 192 FILTER_2D_8TAP_SMOOTH, 193 FILTER_2D_8TAP_SMOOTH_SHARP, 194 FILTER_2D_BILINEAR, 195 N_2D_FILTERS, 196 }; 197 198 enum MVJoint { 199 MV_JOINT_ZERO, 200 MV_JOINT_H, 201 MV_JOINT_V, 202 MV_JOINT_HV, 203 N_MV_JOINTS, 204 }; 205 206 enum InterPredMode { 207 NEARESTMV, 208 NEARMV, 209 GLOBALMV, 210 NEWMV, 211 N_INTER_PRED_MODES, 212 }; 213 214 enum DRL_PROXIMITY { 215 NEAREST_DRL, 216 NEARER_DRL, 217 NEAR_DRL, 218 NEARISH_DRL 219 }; 220 221 enum CompInterPredMode { 222 NEARESTMV_NEARESTMV, 223 NEARMV_NEARMV, 224 NEARESTMV_NEWMV, 225 NEWMV_NEARESTMV, 226 NEARMV_NEWMV, 227 NEWMV_NEARMV, 228 GLOBALMV_GLOBALMV, 229 NEWMV_NEWMV, 230 N_COMP_INTER_PRED_MODES, 231 }; 232 233 enum CompInterType { 234 COMP_INTER_NONE, 235 COMP_INTER_WEIGHTED_AVG, 236 COMP_INTER_AVG, 237 COMP_INTER_SEG, 238 COMP_INTER_WEDGE, 239 }; 240 241 enum InterIntraType { 242 INTER_INTRA_NONE, 243 INTER_INTRA_BLEND, 244 INTER_INTRA_WEDGE, 245 }; 246 247 typedef union mv { 248 struct { 249 int16_t y, x; 250 }; 251 uint32_t n; 252 } mv; 253 254 enum MotionMode { 255 MM_TRANSLATION, 256 MM_OBMC, 257 MM_WARP, 258 }; 259 260 #define QINDEX_RANGE 256 261 262 typedef struct Av1Block { 263 uint8_t bl, bs, bp; 264 uint8_t intra, seg_id, skip_mode, skip, uvtx; 265 union { 266 struct { 267 uint8_t y_mode, uv_mode, tx, pal_sz[2]; 268 int8_t y_angle, uv_angle, cfl_alpha[2]; 269 }; // intra 270 struct { 271 union { 272 struct { 273 union mv mv[2]; 274 uint8_t wedge_idx, mask_sign, interintra_mode; 275 }; 276 struct { 277 union mv mv2d; 278 int16_t matrix[4]; 279 }; 280 }; 281 uint8_t comp_type, inter_mode, motion_mode, drl_idx; 282 int8_t ref[2]; 283 uint8_t max_ytx, filter2d, interintra_type, tx_split0; 284 uint16_t tx_split1; 285 }; // inter 286 }; 287 } Av1Block; 288 289 #endif /* DAV1D_SRC_LEVELS_H */ 290