1// Copyright 2020 Google LLC 2// 3// This source code is licensed under the BSD-style license found in the 4// LICENSE file in the root directory of this source tree. 5 6$assert ELEMENTS_TILE % 4 == 0 7$assert ELEMENTS_TILE >= 4 8$SIMD_TILE = ELEMENTS_TILE // 4 9$ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ" 10$VMULADDQ_F32 = "vfmaq_f32" if FMA else "vmlaq_f32" 11#include <assert.h> 12 13#include <arm_neon.h> 14 15#include <xnnpack/common.h> 16#include <xnnpack/raddstoreexpminusmax.h> 17 18 19$PARAMS_STRUCT = "neonfma_rr1_p5" if FMA else "neon_rr2_p5" 20void xnn_f32_raddstoreexpminusmax_ukernel__${"neonfma" if FMA else "neon"}_rr${1 if FMA else 2}_p5_x${ELEMENTS_TILE}${"" if ACCUMULATORS == 1 else "_acc%d" % ACCUMULATORS}( 21 size_t elements, 22 const float* input, 23 const float* max, 24 float* output, 25 float* sum, 26 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS 27{ 28 assert(elements % sizeof(float) == 0); 29 30 const float32x4_t vi_max = vld1q_dup_f32(max); 31 const float32x4_t vlog2e = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.log2e); 32 const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.magic_bias); 33 $if FMA: 34 const float32x4_t vminus_ln2 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.minus_ln2); 35 $else: 36 const float32x4_t vminus_ln2_hi = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.minus_ln2_hi); 37 const float32x4_t vminus_ln2_lo = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.minus_ln2_lo); 38 const float32x4_t vc5 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c5); 39 const float32x4_t vc4 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c4); 40 const float32x4_t vc3 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c3); 41 const float32x4_t vc2 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c2); 42 const float32x4_t vc1 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c1); 43 const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.denorm_cutoff); 44 45 $if ELEMENTS_TILE > 4: 46 $for K in range(ACCUMULATORS): 47 float32x4_t vacc${K} = vmovq_n_f32(0.0f); 48 for (; elements >= ${ELEMENTS_TILE} * sizeof(float); elements -= ${ELEMENTS_TILE} * sizeof(float)) { 49 $for N in range(0, ELEMENTS_TILE, 4): 50 const float32x4_t vi${ABC[N:N+4]} = vld1q_f32(input); input += 4; 51 52 $for N in range(0, ELEMENTS_TILE, 4): 53 const float32x4_t vx${ABC[N:N+4]} = vsubq_f32(vi${ABC[N:N+4]}, vi_max); 54 55 $for N in range(0, ELEMENTS_TILE, 4): 56 float32x4_t vn${ABC[N:N+4]} = ${VMULADDQ_F32}(vmagic_bias, vx${ABC[N:N+4]}, vlog2e); 57 58 $for N in range(0, ELEMENTS_TILE, 4): 59 const float32x4_t vs${ABC[N:N+4]} = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), 23)); 60 61 $for N in range(0, ELEMENTS_TILE, 4): 62 vn${ABC[N:N+4]} = vsubq_f32(vn${ABC[N:N+4]}, vmagic_bias); 63 64 $if FMA: 65 $for N in range(0, ELEMENTS_TILE, 4): 66 float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vx${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2); 67 $else: 68 $for N in range(0, ELEMENTS_TILE, 4): 69 float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vx${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_hi); 70 71 $for N in range(0, ELEMENTS_TILE, 4): 72 vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_lo); 73 74 $for N in range(0, ELEMENTS_TILE, 4): 75 float32x4_t vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc4, vc5, vt${ABC[N:N+4]}); 76 77 $for N in range(0, ELEMENTS_TILE, 4): 78 vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc3, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); 79 80 $for N in range(0, ELEMENTS_TILE, 4): 81 vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc2, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); 82 83 $for N in range(0, ELEMENTS_TILE, 4): 84 vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc1, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); 85 86 $for N in range(0, ELEMENTS_TILE, 4): 87 vt${ABC[N:N+4]} = vmulq_f32(vt${ABC[N:N+4]}, vs${ABC[N:N+4]}); 88 89 $for N in range(0, ELEMENTS_TILE, 4): 90 float32x4_t vf${ABC[N:N+4]} = ${VMULADDQ_F32}(vs${ABC[N:N+4]}, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); 91 92 $for N in range(0, ELEMENTS_TILE, 4): 93 vf${ABC[N:N+4]} = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf${ABC[N:N+4]}), vcltq_f32(vx${ABC[N:N+4]}, vdenorm_cutoff))); 94 95 $for N in range(0, ELEMENTS_TILE, 4): 96 vst1q_f32(output, vf${ABC[N:N+4]}); output += 4; 97 98 $for N in range(0, ELEMENTS_TILE, 4): 99 vacc${N % ACCUMULATORS} = vaddq_f32(vacc${N % ACCUMULATORS}, vf${ABC[N:N+4]}); 100 } 101 $if ACCUMULATORS > 1: 102 $ACC_SLICE = 1 103 $while ACC_SLICE < ACCUMULATORS: 104 $for A in range(0, ACCUMULATORS, ACC_SLICE * 2): 105 $if A + ACC_SLICE < ACCUMULATORS: 106 vacc${A} = vaddq_f32(vacc${A}, vacc${A + ACC_SLICE}); 107 $ACC_SLICE *= 2 108 109 float32x4_t vacc = vacc0; 110 $else: 111 float32x4_t vacc = vmovq_n_f32(0.0f); 112 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) { 113 const float32x4_t vi = vld1q_f32(input); input += 4; 114 115 const float32x4_t vx = vsubq_f32(vi, vi_max); 116 117 float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vx, vlog2e); 118 119 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23)); 120 121 vn = vsubq_f32(vn, vmagic_bias); 122 123 $if FMA: 124 float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2); 125 $else: 126 float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2_hi); 127 vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo); 128 129 float32x4_t vp = ${VMULADDQ_F32}(vc4, vc5, vt); 130 vp = ${VMULADDQ_F32}(vc3, vp, vt); 131 vp = ${VMULADDQ_F32}(vc2, vp, vt); 132 vp = ${VMULADDQ_F32}(vc1, vp, vt); 133 134 vt = vmulq_f32(vt, vs); 135 float32x4_t vf = ${VMULADDQ_F32}(vs, vp, vt); 136 137 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff))); 138 139 vst1q_f32(output, vf); output += 4; 140 141 vacc = vaddq_f32(vacc, vf); 142 } 143#if XNN_ARCH_ARM64 144 float vacc_lo = vaddvq_f32(vacc); 145#else 146 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc)); 147#endif 148 if (elements != 0) { 149 assert(elements >= 1 * sizeof(float)); 150 assert(elements <= 3 * sizeof(float)); 151 const float32x4_t vi = vld1q_f32(input); input += 4; 152 153 const float32x4_t vx = vsubq_f32(vi, vi_max); 154 155 float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vx, vlog2e); 156 157 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23)); 158 159 vn = vsubq_f32(vn, vmagic_bias); 160 161 $if FMA: 162 float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2); 163 $else: 164 float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2_hi); 165 vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo); 166 167 float32x4_t vp = ${VMULADDQ_F32}(vc4, vc5, vt); 168 vp = ${VMULADDQ_F32}(vc3, vp, vt); 169 vp = ${VMULADDQ_F32}(vc2, vp, vt); 170 vp = ${VMULADDQ_F32}(vc1, vp, vt); 171 172 vt = vmulq_f32(vt, vs); 173 float32x4_t vf = ${VMULADDQ_F32}(vs, vp, vt); 174 175 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff))); 176 177 float32x2_t vf_lo = vget_low_f32(vf); 178 if (elements & (2 * sizeof(float))) { 179 vst1_f32(output, vf_lo); output += 2; 180 181 #if XNN_ARCH_ARM64 182 vacc_lo += vaddv_f32(vf_lo); 183 #else 184 vacc_lo = vadd_f32(vacc_lo, vf_lo); 185 #endif 186 187 vf_lo = vget_high_f32(vf); 188 } 189 if (elements & (1 * sizeof(float))) { 190 vst1_lane_f32(output, vf_lo, 0); 191 192 #if XNN_ARCH_ARM64 193 vacc_lo += vget_lane_f32(vf_lo, 0); 194 #else 195 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32))); 196 #endif 197 } 198 } 199#if XNN_ARCH_ARM64 200 *sum = vacc_lo; 201#else 202 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0); 203#endif 204} 205