1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neonfma_rr1_p5_x8(size_t elements,const float * input,const float * max,float * output,float * sum,const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f32_raddstoreexpminusmax_ukernel__neonfma_rr1_p5_x8(
19 size_t elements,
20 const float* input,
21 const float* max,
22 float* output,
23 float* sum,
24 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26 assert(elements % sizeof(float) == 0);
27
28 const float32x4_t vi_max = vld1q_dup_f32(max);
29 const float32x4_t vlog2e = vld1q_dup_f32(¶ms->neonfma_rr1_p5.log2e);
30 const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->neonfma_rr1_p5.magic_bias);
31 const float32x4_t vminus_ln2 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.minus_ln2);
32 const float32x4_t vc5 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c5);
33 const float32x4_t vc4 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c4);
34 const float32x4_t vc3 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c3);
35 const float32x4_t vc2 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c2);
36 const float32x4_t vc1 = vld1q_dup_f32(¶ms->neonfma_rr1_p5.c1);
37 const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->neonfma_rr1_p5.denorm_cutoff);
38
39 float32x4_t vacc0 = vmovq_n_f32(0.0f);
40 for (; elements >= 8 * sizeof(float); elements -= 8 * sizeof(float)) {
41 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
42 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
43
44 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
45 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
46
47 float32x4_t vn0123 = vfmaq_f32(vmagic_bias, vx0123, vlog2e);
48 float32x4_t vn4567 = vfmaq_f32(vmagic_bias, vx4567, vlog2e);
49
50 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
51 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
52
53 vn0123 = vsubq_f32(vn0123, vmagic_bias);
54 vn4567 = vsubq_f32(vn4567, vmagic_bias);
55
56 float32x4_t vt0123 = vfmaq_f32(vx0123, vn0123, vminus_ln2);
57 float32x4_t vt4567 = vfmaq_f32(vx4567, vn4567, vminus_ln2);
58
59 float32x4_t vp0123 = vfmaq_f32(vc4, vc5, vt0123);
60 float32x4_t vp4567 = vfmaq_f32(vc4, vc5, vt4567);
61
62 vp0123 = vfmaq_f32(vc3, vp0123, vt0123);
63 vp4567 = vfmaq_f32(vc3, vp4567, vt4567);
64
65 vp0123 = vfmaq_f32(vc2, vp0123, vt0123);
66 vp4567 = vfmaq_f32(vc2, vp4567, vt4567);
67
68 vp0123 = vfmaq_f32(vc1, vp0123, vt0123);
69 vp4567 = vfmaq_f32(vc1, vp4567, vt4567);
70
71 vt0123 = vmulq_f32(vt0123, vs0123);
72 vt4567 = vmulq_f32(vt4567, vs4567);
73
74 float32x4_t vf0123 = vfmaq_f32(vs0123, vp0123, vt0123);
75 float32x4_t vf4567 = vfmaq_f32(vs4567, vp4567, vt4567);
76
77 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
78 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
79
80 vst1q_f32(output, vf0123); output += 4;
81 vst1q_f32(output, vf4567); output += 4;
82
83 vacc0 = vaddq_f32(vacc0, vf0123);
84 vacc0 = vaddq_f32(vacc0, vf4567);
85 }
86
87 float32x4_t vacc = vacc0;
88 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
89 const float32x4_t vi = vld1q_f32(input); input += 4;
90
91 const float32x4_t vx = vsubq_f32(vi, vi_max);
92
93 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
94
95 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
96
97 vn = vsubq_f32(vn, vmagic_bias);
98
99 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2);
100
101 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
102 vp = vfmaq_f32(vc3, vp, vt);
103 vp = vfmaq_f32(vc2, vp, vt);
104 vp = vfmaq_f32(vc1, vp, vt);
105
106 vt = vmulq_f32(vt, vs);
107 float32x4_t vf = vfmaq_f32(vs, vp, vt);
108
109 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
110
111 vst1q_f32(output, vf); output += 4;
112
113 vacc = vaddq_f32(vacc, vf);
114 }
115 #if XNN_ARCH_ARM64
116 float vacc_lo = vaddvq_f32(vacc);
117 #else
118 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
119 #endif
120 if (elements != 0) {
121 assert(elements >= 1 * sizeof(float));
122 assert(elements <= 3 * sizeof(float));
123 const float32x4_t vi = vld1q_f32(input); input += 4;
124
125 const float32x4_t vx = vsubq_f32(vi, vi_max);
126
127 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
128
129 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
130
131 vn = vsubq_f32(vn, vmagic_bias);
132
133 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2);
134
135 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
136 vp = vfmaq_f32(vc3, vp, vt);
137 vp = vfmaq_f32(vc2, vp, vt);
138 vp = vfmaq_f32(vc1, vp, vt);
139
140 vt = vmulq_f32(vt, vs);
141 float32x4_t vf = vfmaq_f32(vs, vp, vt);
142
143 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
144
145 float32x2_t vf_lo = vget_low_f32(vf);
146 if (elements & (2 * sizeof(float))) {
147 vst1_f32(output, vf_lo); output += 2;
148
149 #if XNN_ARCH_ARM64
150 vacc_lo += vaddv_f32(vf_lo);
151 #else
152 vacc_lo = vadd_f32(vacc_lo, vf_lo);
153 #endif
154
155 vf_lo = vget_high_f32(vf);
156 }
157 if (elements & (1 * sizeof(float))) {
158 vst1_lane_f32(output, vf_lo, 0);
159
160 #if XNN_ARCH_ARM64
161 vacc_lo += vget_lane_f32(vf_lo, 0);
162 #else
163 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
164 #endif
165 }
166 }
167 #if XNN_ARCH_ARM64
168 *sum = vacc_lo;
169 #else
170 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
171 #endif
172 }
173