1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neon_rr2_p5_x16_acc4(size_t elements,const float * input,const float * max,float * output,float * sum,const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f32_raddstoreexpminusmax_ukernel__neon_rr2_p5_x16_acc4(
19 size_t elements,
20 const float* input,
21 const float* max,
22 float* output,
23 float* sum,
24 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26 assert(elements % sizeof(float) == 0);
27
28 const float32x4_t vi_max = vld1q_dup_f32(max);
29 const float32x4_t vlog2e = vld1q_dup_f32(¶ms->neon_rr2_p5.log2e);
30 const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->neon_rr2_p5.magic_bias);
31 const float32x4_t vminus_ln2_hi = vld1q_dup_f32(¶ms->neon_rr2_p5.minus_ln2_hi);
32 const float32x4_t vminus_ln2_lo = vld1q_dup_f32(¶ms->neon_rr2_p5.minus_ln2_lo);
33 const float32x4_t vc5 = vld1q_dup_f32(¶ms->neon_rr2_p5.c5);
34 const float32x4_t vc4 = vld1q_dup_f32(¶ms->neon_rr2_p5.c4);
35 const float32x4_t vc3 = vld1q_dup_f32(¶ms->neon_rr2_p5.c3);
36 const float32x4_t vc2 = vld1q_dup_f32(¶ms->neon_rr2_p5.c2);
37 const float32x4_t vc1 = vld1q_dup_f32(¶ms->neon_rr2_p5.c1);
38 const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->neon_rr2_p5.denorm_cutoff);
39
40 float32x4_t vacc0 = vmovq_n_f32(0.0f);
41 float32x4_t vacc1 = vmovq_n_f32(0.0f);
42 float32x4_t vacc2 = vmovq_n_f32(0.0f);
43 float32x4_t vacc3 = vmovq_n_f32(0.0f);
44 for (; elements >= 16 * sizeof(float); elements -= 16 * sizeof(float)) {
45 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
46 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
47 const float32x4_t vi89AB = vld1q_f32(input); input += 4;
48 const float32x4_t viCDEF = vld1q_f32(input); input += 4;
49
50 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
51 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
52 const float32x4_t vx89AB = vsubq_f32(vi89AB, vi_max);
53 const float32x4_t vxCDEF = vsubq_f32(viCDEF, vi_max);
54
55 float32x4_t vn0123 = vmlaq_f32(vmagic_bias, vx0123, vlog2e);
56 float32x4_t vn4567 = vmlaq_f32(vmagic_bias, vx4567, vlog2e);
57 float32x4_t vn89AB = vmlaq_f32(vmagic_bias, vx89AB, vlog2e);
58 float32x4_t vnCDEF = vmlaq_f32(vmagic_bias, vxCDEF, vlog2e);
59
60 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
61 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
62 const float32x4_t vs89AB = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn89AB), 23));
63 const float32x4_t vsCDEF = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnCDEF), 23));
64
65 vn0123 = vsubq_f32(vn0123, vmagic_bias);
66 vn4567 = vsubq_f32(vn4567, vmagic_bias);
67 vn89AB = vsubq_f32(vn89AB, vmagic_bias);
68 vnCDEF = vsubq_f32(vnCDEF, vmagic_bias);
69
70 float32x4_t vt0123 = vmlaq_f32(vx0123, vn0123, vminus_ln2_hi);
71 float32x4_t vt4567 = vmlaq_f32(vx4567, vn4567, vminus_ln2_hi);
72 float32x4_t vt89AB = vmlaq_f32(vx89AB, vn89AB, vminus_ln2_hi);
73 float32x4_t vtCDEF = vmlaq_f32(vxCDEF, vnCDEF, vminus_ln2_hi);
74
75 vt0123 = vmlaq_f32(vt0123, vn0123, vminus_ln2_lo);
76 vt4567 = vmlaq_f32(vt4567, vn4567, vminus_ln2_lo);
77 vt89AB = vmlaq_f32(vt89AB, vn89AB, vminus_ln2_lo);
78 vtCDEF = vmlaq_f32(vtCDEF, vnCDEF, vminus_ln2_lo);
79
80 float32x4_t vp0123 = vmlaq_f32(vc4, vc5, vt0123);
81 float32x4_t vp4567 = vmlaq_f32(vc4, vc5, vt4567);
82 float32x4_t vp89AB = vmlaq_f32(vc4, vc5, vt89AB);
83 float32x4_t vpCDEF = vmlaq_f32(vc4, vc5, vtCDEF);
84
85 vp0123 = vmlaq_f32(vc3, vp0123, vt0123);
86 vp4567 = vmlaq_f32(vc3, vp4567, vt4567);
87 vp89AB = vmlaq_f32(vc3, vp89AB, vt89AB);
88 vpCDEF = vmlaq_f32(vc3, vpCDEF, vtCDEF);
89
90 vp0123 = vmlaq_f32(vc2, vp0123, vt0123);
91 vp4567 = vmlaq_f32(vc2, vp4567, vt4567);
92 vp89AB = vmlaq_f32(vc2, vp89AB, vt89AB);
93 vpCDEF = vmlaq_f32(vc2, vpCDEF, vtCDEF);
94
95 vp0123 = vmlaq_f32(vc1, vp0123, vt0123);
96 vp4567 = vmlaq_f32(vc1, vp4567, vt4567);
97 vp89AB = vmlaq_f32(vc1, vp89AB, vt89AB);
98 vpCDEF = vmlaq_f32(vc1, vpCDEF, vtCDEF);
99
100 vt0123 = vmulq_f32(vt0123, vs0123);
101 vt4567 = vmulq_f32(vt4567, vs4567);
102 vt89AB = vmulq_f32(vt89AB, vs89AB);
103 vtCDEF = vmulq_f32(vtCDEF, vsCDEF);
104
105 float32x4_t vf0123 = vmlaq_f32(vs0123, vp0123, vt0123);
106 float32x4_t vf4567 = vmlaq_f32(vs4567, vp4567, vt4567);
107 float32x4_t vf89AB = vmlaq_f32(vs89AB, vp89AB, vt89AB);
108 float32x4_t vfCDEF = vmlaq_f32(vsCDEF, vpCDEF, vtCDEF);
109
110 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
111 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
112 vf89AB = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf89AB), vcltq_f32(vx89AB, vdenorm_cutoff)));
113 vfCDEF = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfCDEF), vcltq_f32(vxCDEF, vdenorm_cutoff)));
114
115 vst1q_f32(output, vf0123); output += 4;
116 vst1q_f32(output, vf4567); output += 4;
117 vst1q_f32(output, vf89AB); output += 4;
118 vst1q_f32(output, vfCDEF); output += 4;
119
120 vacc0 = vaddq_f32(vacc0, vf0123);
121 vacc0 = vaddq_f32(vacc0, vf4567);
122 vacc0 = vaddq_f32(vacc0, vf89AB);
123 vacc0 = vaddq_f32(vacc0, vfCDEF);
124 }
125 vacc0 = vaddq_f32(vacc0, vacc1);
126 vacc2 = vaddq_f32(vacc2, vacc3);
127 vacc0 = vaddq_f32(vacc0, vacc2);
128
129 float32x4_t vacc = vacc0;
130 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
131 const float32x4_t vi = vld1q_f32(input); input += 4;
132
133 const float32x4_t vx = vsubq_f32(vi, vi_max);
134
135 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
136
137 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
138
139 vn = vsubq_f32(vn, vmagic_bias);
140
141 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
142 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
143
144 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
145 vp = vmlaq_f32(vc3, vp, vt);
146 vp = vmlaq_f32(vc2, vp, vt);
147 vp = vmlaq_f32(vc1, vp, vt);
148
149 vt = vmulq_f32(vt, vs);
150 float32x4_t vf = vmlaq_f32(vs, vp, vt);
151
152 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
153
154 vst1q_f32(output, vf); output += 4;
155
156 vacc = vaddq_f32(vacc, vf);
157 }
158 #if XNN_ARCH_ARM64
159 float vacc_lo = vaddvq_f32(vacc);
160 #else
161 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
162 #endif
163 if (elements != 0) {
164 assert(elements >= 1 * sizeof(float));
165 assert(elements <= 3 * sizeof(float));
166 const float32x4_t vi = vld1q_f32(input); input += 4;
167
168 const float32x4_t vx = vsubq_f32(vi, vi_max);
169
170 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
171
172 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
173
174 vn = vsubq_f32(vn, vmagic_bias);
175
176 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
177 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
178
179 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
180 vp = vmlaq_f32(vc3, vp, vt);
181 vp = vmlaq_f32(vc2, vp, vt);
182 vp = vmlaq_f32(vc1, vp, vt);
183
184 vt = vmulq_f32(vt, vs);
185 float32x4_t vf = vmlaq_f32(vs, vp, vt);
186
187 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
188
189 float32x2_t vf_lo = vget_low_f32(vf);
190 if (elements & (2 * sizeof(float))) {
191 vst1_f32(output, vf_lo); output += 2;
192
193 #if XNN_ARCH_ARM64
194 vacc_lo += vaddv_f32(vf_lo);
195 #else
196 vacc_lo = vadd_f32(vacc_lo, vf_lo);
197 #endif
198
199 vf_lo = vget_high_f32(vf);
200 }
201 if (elements & (1 * sizeof(float))) {
202 vst1_lane_f32(output, vf_lo, 0);
203
204 #if XNN_ARCH_ARM64
205 vacc_lo += vget_lane_f32(vf_lo, 0);
206 #else
207 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
208 #endif
209 }
210 }
211 #if XNN_ARCH_ARM64
212 *sum = vacc_lo;
213 #else
214 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
215 #endif
216 }
217