1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neon_rr2_p5_x12_acc2(size_t elements,const float * input,const float * max,float * output,float * sum,const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f32_raddstoreexpminusmax_ukernel__neon_rr2_p5_x12_acc2(
19 size_t elements,
20 const float* input,
21 const float* max,
22 float* output,
23 float* sum,
24 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26 assert(elements % sizeof(float) == 0);
27
28 const float32x4_t vi_max = vld1q_dup_f32(max);
29 const float32x4_t vlog2e = vld1q_dup_f32(¶ms->neon_rr2_p5.log2e);
30 const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->neon_rr2_p5.magic_bias);
31 const float32x4_t vminus_ln2_hi = vld1q_dup_f32(¶ms->neon_rr2_p5.minus_ln2_hi);
32 const float32x4_t vminus_ln2_lo = vld1q_dup_f32(¶ms->neon_rr2_p5.minus_ln2_lo);
33 const float32x4_t vc5 = vld1q_dup_f32(¶ms->neon_rr2_p5.c5);
34 const float32x4_t vc4 = vld1q_dup_f32(¶ms->neon_rr2_p5.c4);
35 const float32x4_t vc3 = vld1q_dup_f32(¶ms->neon_rr2_p5.c3);
36 const float32x4_t vc2 = vld1q_dup_f32(¶ms->neon_rr2_p5.c2);
37 const float32x4_t vc1 = vld1q_dup_f32(¶ms->neon_rr2_p5.c1);
38 const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->neon_rr2_p5.denorm_cutoff);
39
40 float32x4_t vacc0 = vmovq_n_f32(0.0f);
41 float32x4_t vacc1 = vmovq_n_f32(0.0f);
42 for (; elements >= 12 * sizeof(float); elements -= 12 * sizeof(float)) {
43 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
44 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
45 const float32x4_t vi89AB = vld1q_f32(input); input += 4;
46
47 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
48 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
49 const float32x4_t vx89AB = vsubq_f32(vi89AB, vi_max);
50
51 float32x4_t vn0123 = vmlaq_f32(vmagic_bias, vx0123, vlog2e);
52 float32x4_t vn4567 = vmlaq_f32(vmagic_bias, vx4567, vlog2e);
53 float32x4_t vn89AB = vmlaq_f32(vmagic_bias, vx89AB, vlog2e);
54
55 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
56 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
57 const float32x4_t vs89AB = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn89AB), 23));
58
59 vn0123 = vsubq_f32(vn0123, vmagic_bias);
60 vn4567 = vsubq_f32(vn4567, vmagic_bias);
61 vn89AB = vsubq_f32(vn89AB, vmagic_bias);
62
63 float32x4_t vt0123 = vmlaq_f32(vx0123, vn0123, vminus_ln2_hi);
64 float32x4_t vt4567 = vmlaq_f32(vx4567, vn4567, vminus_ln2_hi);
65 float32x4_t vt89AB = vmlaq_f32(vx89AB, vn89AB, vminus_ln2_hi);
66
67 vt0123 = vmlaq_f32(vt0123, vn0123, vminus_ln2_lo);
68 vt4567 = vmlaq_f32(vt4567, vn4567, vminus_ln2_lo);
69 vt89AB = vmlaq_f32(vt89AB, vn89AB, vminus_ln2_lo);
70
71 float32x4_t vp0123 = vmlaq_f32(vc4, vc5, vt0123);
72 float32x4_t vp4567 = vmlaq_f32(vc4, vc5, vt4567);
73 float32x4_t vp89AB = vmlaq_f32(vc4, vc5, vt89AB);
74
75 vp0123 = vmlaq_f32(vc3, vp0123, vt0123);
76 vp4567 = vmlaq_f32(vc3, vp4567, vt4567);
77 vp89AB = vmlaq_f32(vc3, vp89AB, vt89AB);
78
79 vp0123 = vmlaq_f32(vc2, vp0123, vt0123);
80 vp4567 = vmlaq_f32(vc2, vp4567, vt4567);
81 vp89AB = vmlaq_f32(vc2, vp89AB, vt89AB);
82
83 vp0123 = vmlaq_f32(vc1, vp0123, vt0123);
84 vp4567 = vmlaq_f32(vc1, vp4567, vt4567);
85 vp89AB = vmlaq_f32(vc1, vp89AB, vt89AB);
86
87 vt0123 = vmulq_f32(vt0123, vs0123);
88 vt4567 = vmulq_f32(vt4567, vs4567);
89 vt89AB = vmulq_f32(vt89AB, vs89AB);
90
91 float32x4_t vf0123 = vmlaq_f32(vs0123, vp0123, vt0123);
92 float32x4_t vf4567 = vmlaq_f32(vs4567, vp4567, vt4567);
93 float32x4_t vf89AB = vmlaq_f32(vs89AB, vp89AB, vt89AB);
94
95 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
96 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
97 vf89AB = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf89AB), vcltq_f32(vx89AB, vdenorm_cutoff)));
98
99 vst1q_f32(output, vf0123); output += 4;
100 vst1q_f32(output, vf4567); output += 4;
101 vst1q_f32(output, vf89AB); output += 4;
102
103 vacc0 = vaddq_f32(vacc0, vf0123);
104 vacc0 = vaddq_f32(vacc0, vf4567);
105 vacc0 = vaddq_f32(vacc0, vf89AB);
106 }
107 vacc0 = vaddq_f32(vacc0, vacc1);
108
109 float32x4_t vacc = vacc0;
110 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
111 const float32x4_t vi = vld1q_f32(input); input += 4;
112
113 const float32x4_t vx = vsubq_f32(vi, vi_max);
114
115 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
116
117 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
118
119 vn = vsubq_f32(vn, vmagic_bias);
120
121 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
122 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
123
124 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
125 vp = vmlaq_f32(vc3, vp, vt);
126 vp = vmlaq_f32(vc2, vp, vt);
127 vp = vmlaq_f32(vc1, vp, vt);
128
129 vt = vmulq_f32(vt, vs);
130 float32x4_t vf = vmlaq_f32(vs, vp, vt);
131
132 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
133
134 vst1q_f32(output, vf); output += 4;
135
136 vacc = vaddq_f32(vacc, vf);
137 }
138 #if XNN_ARCH_ARM64
139 float vacc_lo = vaddvq_f32(vacc);
140 #else
141 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
142 #endif
143 if (elements != 0) {
144 assert(elements >= 1 * sizeof(float));
145 assert(elements <= 3 * sizeof(float));
146 const float32x4_t vi = vld1q_f32(input); input += 4;
147
148 const float32x4_t vx = vsubq_f32(vi, vi_max);
149
150 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
151
152 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
153
154 vn = vsubq_f32(vn, vmagic_bias);
155
156 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
157 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
158
159 float32x4_t vp = vmlaq_f32(vc4, vc5, vt);
160 vp = vmlaq_f32(vc3, vp, vt);
161 vp = vmlaq_f32(vc2, vp, vt);
162 vp = vmlaq_f32(vc1, vp, vt);
163
164 vt = vmulq_f32(vt, vs);
165 float32x4_t vf = vmlaq_f32(vs, vp, vt);
166
167 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
168
169 float32x2_t vf_lo = vget_low_f32(vf);
170 if (elements & (2 * sizeof(float))) {
171 vst1_f32(output, vf_lo); output += 2;
172
173 #if XNN_ARCH_ARM64
174 vacc_lo += vaddv_f32(vf_lo);
175 #else
176 vacc_lo = vadd_f32(vacc_lo, vf_lo);
177 #endif
178
179 vf_lo = vget_high_f32(vf);
180 }
181 if (elements & (1 * sizeof(float))) {
182 vst1_lane_f32(output, vf_lo, 0);
183
184 #if XNN_ARCH_ARM64
185 vacc_lo += vget_lane_f32(vf_lo, 0);
186 #else
187 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
188 #endif
189 }
190 }
191 #if XNN_ARCH_ARM64
192 *sum = vacc_lo;
193 #else
194 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
195 #endif
196 }
197