1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-lut64-p2.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
18 extern XNN_INTERNAL const float xnn_table_exp2_k_over_64[64];
19
xnn_f32_raddstoreexpminusmax_ukernel__neon_rr2_lut64_p2_x20(size_t elements,const float * input,const float * max,float * output,float * sum,const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])20 void xnn_f32_raddstoreexpminusmax_ukernel__neon_rr2_lut64_p2_x20(
21 size_t elements,
22 const float* input,
23 const float* max,
24 float* output,
25 float* sum,
26 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
27 {
28 assert(elements % sizeof(float) == 0);
29
30 const float32x4_t vi_max = vld1q_dup_f32(max);
31 const float32x4_t vlog2e = vld1q_dup_f32(¶ms->neon_rr2_lut64_p2.log2e);
32 const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->neon_rr2_lut64_p2.magic_bias);
33 const int32x4_t vindex_mask = vmovq_n_s32(INT32_C(0x3F));
34 const float32x4_t vminus_ln2_hi = vld1q_dup_f32(¶ms->neon_rr2_lut64_p2.minus_ln2_hi);
35 const float32x4_t vminus_ln2_lo = vld1q_dup_f32(¶ms->neon_rr2_lut64_p2.minus_ln2_lo);
36 const float32x4_t vc2 = vld1q_dup_f32(¶ms->neon_rr2_lut64_p2.c2);
37 const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->neon_rr2_lut64_p2.denorm_cutoff);
38
39 float32x4_t vacc0 = vmovq_n_f32(0.0f);
40 for (; elements >= 20 * sizeof(float); elements -= 20 * sizeof(float)) {
41 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
42 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
43 const float32x4_t vi89AB = vld1q_f32(input); input += 4;
44 const float32x4_t viCDEF = vld1q_f32(input); input += 4;
45 const float32x4_t viGHIJ = vld1q_f32(input); input += 4;
46
47 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
48 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
49 const float32x4_t vx89AB = vsubq_f32(vi89AB, vi_max);
50 const float32x4_t vxCDEF = vsubq_f32(viCDEF, vi_max);
51 const float32x4_t vxGHIJ = vsubq_f32(viGHIJ, vi_max);
52
53 float32x4_t vn0123 = vmlaq_f32(vmagic_bias, vx0123, vlog2e);
54 float32x4_t vn4567 = vmlaq_f32(vmagic_bias, vx4567, vlog2e);
55 float32x4_t vn89AB = vmlaq_f32(vmagic_bias, vx89AB, vlog2e);
56 float32x4_t vnCDEF = vmlaq_f32(vmagic_bias, vxCDEF, vlog2e);
57 float32x4_t vnGHIJ = vmlaq_f32(vmagic_bias, vxGHIJ, vlog2e);
58
59 const int32x4_t ve0123 = vshlq_n_s32(vbicq_s32(vreinterpretq_s32_f32(vn0123), vmovq_n_s32(INT32_C(0x3F))), 17);
60 const int32x4_t ve4567 = vshlq_n_s32(vbicq_s32(vreinterpretq_s32_f32(vn4567), vmovq_n_s32(INT32_C(0x3F))), 17);
61 const int32x4_t ve89AB = vshlq_n_s32(vbicq_s32(vreinterpretq_s32_f32(vn89AB), vmovq_n_s32(INT32_C(0x3F))), 17);
62 const int32x4_t veCDEF = vshlq_n_s32(vbicq_s32(vreinterpretq_s32_f32(vnCDEF), vmovq_n_s32(INT32_C(0x3F))), 17);
63 const int32x4_t veGHIJ = vshlq_n_s32(vbicq_s32(vreinterpretq_s32_f32(vnGHIJ), vmovq_n_s32(INT32_C(0x3F))), 17);
64
65 const uint64x2_t vidx0123 = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn0123), vindex_mask));
66 const uint64_t vidx01 = vgetq_lane_u64(vidx0123, 0);
67 const uint64_t vidx23 = vgetq_lane_u64(vidx0123, 1);
68 const uint64x2_t vidx4567 = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn4567), vindex_mask));
69 const uint64_t vidx45 = vgetq_lane_u64(vidx4567, 0);
70 const uint64_t vidx67 = vgetq_lane_u64(vidx4567, 1);
71 const uint64x2_t vidx89AB = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn89AB), vindex_mask));
72 const uint64_t vidx89 = vgetq_lane_u64(vidx89AB, 0);
73 const uint64_t vidxAB = vgetq_lane_u64(vidx89AB, 1);
74 const uint64x2_t vidxCDEF = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vnCDEF), vindex_mask));
75 const uint64_t vidxCD = vgetq_lane_u64(vidxCDEF, 0);
76 const uint64_t vidxEF = vgetq_lane_u64(vidxCDEF, 1);
77 const uint64x2_t vidxGHIJ = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vnGHIJ), vindex_mask));
78 const uint64_t vidxGH = vgetq_lane_u64(vidxGHIJ, 0);
79 const uint64_t vidxIJ = vgetq_lane_u64(vidxGHIJ, 1);
80
81 float32x2_t vl01 = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx01]);
82 float32x2_t vl23 = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx23]);
83 float32x2_t vl45 = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx45]);
84 float32x2_t vl67 = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx67]);
85 float32x2_t vl89 = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx89]);
86 float32x2_t vlAB = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidxAB]);
87 float32x2_t vlCD = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidxCD]);
88 float32x2_t vlEF = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidxEF]);
89 float32x2_t vlGH = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidxGH]);
90 float32x2_t vlIJ = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidxIJ]);
91
92 vl01 = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx01 >> 32)], vl01, 1);
93 vl23 = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx23 >> 32)], vl23, 1);
94 const float32x4_t vl0123 = vcombine_f32(vl01, vl23);
95 vl45 = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx45 >> 32)], vl45, 1);
96 vl67 = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx67 >> 32)], vl67, 1);
97 const float32x4_t vl4567 = vcombine_f32(vl45, vl67);
98 vl89 = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx89 >> 32)], vl89, 1);
99 vlAB = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidxAB >> 32)], vlAB, 1);
100 const float32x4_t vl89AB = vcombine_f32(vl89, vlAB);
101 vlCD = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidxCD >> 32)], vlCD, 1);
102 vlEF = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidxEF >> 32)], vlEF, 1);
103 const float32x4_t vlCDEF = vcombine_f32(vlCD, vlEF);
104 vlGH = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidxGH >> 32)], vlGH, 1);
105 vlIJ = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidxIJ >> 32)], vlIJ, 1);
106 const float32x4_t vlGHIJ = vcombine_f32(vlGH, vlIJ);
107
108 const float32x4_t vs0123 = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl0123), ve0123));
109 const float32x4_t vs4567 = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl4567), ve4567));
110 const float32x4_t vs89AB = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl89AB), ve89AB));
111 const float32x4_t vsCDEF = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vlCDEF), veCDEF));
112 const float32x4_t vsGHIJ = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vlGHIJ), veGHIJ));
113
114 vn0123 = vsubq_f32(vn0123, vmagic_bias);
115 vn4567 = vsubq_f32(vn4567, vmagic_bias);
116 vn89AB = vsubq_f32(vn89AB, vmagic_bias);
117 vnCDEF = vsubq_f32(vnCDEF, vmagic_bias);
118 vnGHIJ = vsubq_f32(vnGHIJ, vmagic_bias);
119
120 float32x4_t vt0123 = vmlaq_f32(vx0123, vn0123, vminus_ln2_hi);
121 float32x4_t vt4567 = vmlaq_f32(vx4567, vn4567, vminus_ln2_hi);
122 float32x4_t vt89AB = vmlaq_f32(vx89AB, vn89AB, vminus_ln2_hi);
123 float32x4_t vtCDEF = vmlaq_f32(vxCDEF, vnCDEF, vminus_ln2_hi);
124 float32x4_t vtGHIJ = vmlaq_f32(vxGHIJ, vnGHIJ, vminus_ln2_hi);
125
126 vt0123 = vmlaq_f32(vt0123, vn0123, vminus_ln2_lo);
127 vt4567 = vmlaq_f32(vt4567, vn4567, vminus_ln2_lo);
128 vt89AB = vmlaq_f32(vt89AB, vn89AB, vminus_ln2_lo);
129 vtCDEF = vmlaq_f32(vtCDEF, vnCDEF, vminus_ln2_lo);
130 vtGHIJ = vmlaq_f32(vtGHIJ, vnGHIJ, vminus_ln2_lo);
131
132 float32x4_t vp0123 = vmulq_f32(vt0123, vc2);
133 float32x4_t vp4567 = vmulq_f32(vt4567, vc2);
134 float32x4_t vp89AB = vmulq_f32(vt89AB, vc2);
135 float32x4_t vpCDEF = vmulq_f32(vtCDEF, vc2);
136 float32x4_t vpGHIJ = vmulq_f32(vtGHIJ, vc2);
137
138 vp0123 = vmlaq_f32(vt0123, vt0123, vp0123);
139 vp4567 = vmlaq_f32(vt4567, vt4567, vp4567);
140 vp89AB = vmlaq_f32(vt89AB, vt89AB, vp89AB);
141 vpCDEF = vmlaq_f32(vtCDEF, vtCDEF, vpCDEF);
142 vpGHIJ = vmlaq_f32(vtGHIJ, vtGHIJ, vpGHIJ);
143
144 float32x4_t vf0123 = vmlaq_f32(vs0123, vs0123, vp0123);
145 float32x4_t vf4567 = vmlaq_f32(vs4567, vs4567, vp4567);
146 float32x4_t vf89AB = vmlaq_f32(vs89AB, vs89AB, vp89AB);
147 float32x4_t vfCDEF = vmlaq_f32(vsCDEF, vsCDEF, vpCDEF);
148 float32x4_t vfGHIJ = vmlaq_f32(vsGHIJ, vsGHIJ, vpGHIJ);
149
150 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
151 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
152 vf89AB = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf89AB), vcltq_f32(vx89AB, vdenorm_cutoff)));
153 vfCDEF = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfCDEF), vcltq_f32(vxCDEF, vdenorm_cutoff)));
154 vfGHIJ = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfGHIJ), vcltq_f32(vxGHIJ, vdenorm_cutoff)));
155
156 vst1q_f32(output, vf0123); output += 4;
157 vst1q_f32(output, vf4567); output += 4;
158 vst1q_f32(output, vf89AB); output += 4;
159 vst1q_f32(output, vfCDEF); output += 4;
160 vst1q_f32(output, vfGHIJ); output += 4;
161
162 vacc0 = vaddq_f32(vacc0, vf0123);
163 vacc0 = vaddq_f32(vacc0, vf4567);
164 vacc0 = vaddq_f32(vacc0, vf89AB);
165 vacc0 = vaddq_f32(vacc0, vfCDEF);
166 vacc0 = vaddq_f32(vacc0, vfGHIJ);
167 }
168
169 float32x4_t vacc = vacc0;
170 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
171 const float32x4_t vi = vld1q_f32(input); input += 4;
172
173 const float32x4_t vx = vsubq_f32(vi, vi_max);
174
175 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
176
177 const int32x4_t ve = vshlq_n_s32(vbicq_s32(vreinterpretq_s32_f32(vn), vmovq_n_s32(INT32_C(0x3F))), 17);
178
179 const uint64x2_t vidx = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask));
180 const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0);
181 const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1);
182 float32x2_t vl_lo = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx_lo]);
183 float32x2_t vl_hi = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx_hi]);
184 vl_lo = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx_lo >> 32)], vl_lo, 1);
185 vl_hi = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx_hi >> 32)], vl_hi, 1);
186 const float32x4_t vl = vcombine_f32(vl_lo, vl_hi);
187 const float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl), ve));
188
189 vn = vsubq_f32(vn, vmagic_bias);
190
191 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
192 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
193
194 float32x4_t vp = vmulq_f32(vt, vc2);
195 vp = vmlaq_f32(vt, vt, vp);
196
197 float32x4_t vf = vmlaq_f32(vs, vs, vp);
198
199 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
200
201 vst1q_f32(output, vf); output += 4;
202
203 vacc = vaddq_f32(vacc, vf);
204 }
205 #if XNN_ARCH_ARM64
206 float vacc_lo = vaddvq_f32(vacc);
207 #else
208 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
209 #endif
210 if (elements != 0) {
211 assert(elements >= 1 * sizeof(float));
212 assert(elements <= 3 * sizeof(float));
213 const float32x4_t vi = vld1q_f32(input); input += 4;
214
215 const float32x4_t vx = vsubq_f32(vi, vi_max);
216
217 float32x4_t vn = vmlaq_f32(vmagic_bias, vx, vlog2e);
218
219 const int32x4_t ve = vshlq_n_s32(vbicq_s32(vreinterpretq_s32_f32(vn), vmovq_n_s32(INT32_C(0x3F))), 17);
220
221 const uint64x2_t vidx = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask));
222 const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0);
223 const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1);
224 float32x2_t vl_lo = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx_lo]);
225 float32x2_t vl_hi = vld1_dup_f32(&xnn_table_exp2_k_over_64[(uint32_t) vidx_hi]);
226 vl_lo = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx_lo >> 32)], vl_lo, 1);
227 vl_hi = vld1_lane_f32(&xnn_table_exp2_k_over_64[(uint32_t) (vidx_hi >> 32)], vl_hi, 1);
228 const float32x4_t vl = vcombine_f32(vl_lo, vl_hi);
229 const float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl), ve));
230
231 vn = vsubq_f32(vn, vmagic_bias);
232
233 float32x4_t vt = vmlaq_f32(vx, vn, vminus_ln2_hi);
234 vt = vmlaq_f32(vt, vn, vminus_ln2_lo);
235
236 float32x4_t vp = vmulq_f32(vt, vc2);
237 vp = vmlaq_f32(vt, vt, vp);
238
239 float32x4_t vf = vmlaq_f32(vs, vs, vp);
240
241 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
242
243 float32x2_t vf_lo = vget_low_f32(vf);
244 if (elements & (2 * sizeof(float))) {
245 vst1_f32(output, vf_lo); output += 2;
246
247 #if XNN_ARCH_ARM64
248 vacc_lo += vaddv_f32(vf_lo);
249 #else
250 vacc_lo = vadd_f32(vacc_lo, vf_lo);
251 #endif
252
253 vf_lo = vget_high_f32(vf);
254 }
255 if (elements & (1 * sizeof(float))) {
256 vst1_lane_f32(output, vf_lo, 0);
257
258 #if XNN_ARCH_ARM64
259 vacc_lo += vget_lane_f32(vf_lo, 0);
260 #else
261 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
262 #endif
263 }
264 }
265 #if XNN_ARCH_ARM64
266 *sum = vacc_lo;
267 #else
268 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
269 #endif
270 }
271