1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/avx2-rr1-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2019 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/raddstoreexpminusmax.h>
15
16
xnn_f32_raddstoreexpminusmax_ukernel__avx2_rr1_p5_x96_acc2(size_t elements,const float * input,const float * max,float * output,float * sum,const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])17 void xnn_f32_raddstoreexpminusmax_ukernel__avx2_rr1_p5_x96_acc2(
18 size_t elements,
19 const float* input,
20 const float* max,
21 float* output,
22 float* sum,
23 const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)])
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const __m256 vi_max = _mm256_broadcast_ss(max);
28 const __m256 vlog2e = _mm256_load_ps(params->avx2_rr1_p5.log2e);
29 const __m256 vmagic_bias = _mm256_load_ps(params->avx2_rr1_p5.magic_bias);
30 const __m256 vminus_ln2 = _mm256_load_ps(params->avx2_rr1_p5.minus_ln2);
31 const __m256 vc5 = _mm256_load_ps(params->avx2_rr1_p5.c5);
32 const __m256 vc4 = _mm256_load_ps(params->avx2_rr1_p5.c4);
33 const __m256 vc3 = _mm256_load_ps(params->avx2_rr1_p5.c3);
34 const __m256 vc2 = _mm256_load_ps(params->avx2_rr1_p5.c2);
35 const __m256 vc1 = _mm256_load_ps(params->avx2_rr1_p5.c1);
36 const __m256 vdenorm_cutoff = _mm256_load_ps(params->avx2_rr1_p5.denorm_cutoff);
37
38 __m256 vacc0 = _mm256_setzero_ps();
39 __m256 vacc1 = _mm256_setzero_ps();
40 for (; elements >= 96 * sizeof(float); elements -= 96 * sizeof(float)) {
41 const __m256 vi0 = _mm256_loadu_ps(input);
42 const __m256 vi1 = _mm256_loadu_ps(input + 8);
43 const __m256 vi2 = _mm256_loadu_ps(input + 16);
44 const __m256 vi3 = _mm256_loadu_ps(input + 24);
45 const __m256 vi4 = _mm256_loadu_ps(input + 32);
46 const __m256 vi5 = _mm256_loadu_ps(input + 40);
47 const __m256 vi6 = _mm256_loadu_ps(input + 48);
48 const __m256 vi7 = _mm256_loadu_ps(input + 56);
49 const __m256 vi8 = _mm256_loadu_ps(input + 64);
50 const __m256 vi9 = _mm256_loadu_ps(input + 72);
51 const __m256 vi10 = _mm256_loadu_ps(input + 80);
52 const __m256 vi11 = _mm256_loadu_ps(input + 88);
53 input += 96;
54
55 const __m256 vx0 = _mm256_sub_ps(vi0, vi_max);
56 const __m256 vx1 = _mm256_sub_ps(vi1, vi_max);
57 const __m256 vx2 = _mm256_sub_ps(vi2, vi_max);
58 const __m256 vx3 = _mm256_sub_ps(vi3, vi_max);
59 const __m256 vx4 = _mm256_sub_ps(vi4, vi_max);
60 const __m256 vx5 = _mm256_sub_ps(vi5, vi_max);
61 const __m256 vx6 = _mm256_sub_ps(vi6, vi_max);
62 const __m256 vx7 = _mm256_sub_ps(vi7, vi_max);
63 const __m256 vx8 = _mm256_sub_ps(vi8, vi_max);
64 const __m256 vx9 = _mm256_sub_ps(vi9, vi_max);
65 const __m256 vx10 = _mm256_sub_ps(vi10, vi_max);
66 const __m256 vx11 = _mm256_sub_ps(vi11, vi_max);
67
68 __m256 vn0 = _mm256_fmadd_ps(vx0, vlog2e, vmagic_bias);
69 __m256 vn1 = _mm256_fmadd_ps(vx1, vlog2e, vmagic_bias);
70 __m256 vn2 = _mm256_fmadd_ps(vx2, vlog2e, vmagic_bias);
71 __m256 vn3 = _mm256_fmadd_ps(vx3, vlog2e, vmagic_bias);
72 __m256 vn4 = _mm256_fmadd_ps(vx4, vlog2e, vmagic_bias);
73 __m256 vn5 = _mm256_fmadd_ps(vx5, vlog2e, vmagic_bias);
74 __m256 vn6 = _mm256_fmadd_ps(vx6, vlog2e, vmagic_bias);
75 __m256 vn7 = _mm256_fmadd_ps(vx7, vlog2e, vmagic_bias);
76 __m256 vn8 = _mm256_fmadd_ps(vx8, vlog2e, vmagic_bias);
77 __m256 vn9 = _mm256_fmadd_ps(vx9, vlog2e, vmagic_bias);
78 __m256 vn10 = _mm256_fmadd_ps(vx10, vlog2e, vmagic_bias);
79 __m256 vn11 = _mm256_fmadd_ps(vx11, vlog2e, vmagic_bias);
80
81 const __m256 vs0 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn0), 23));
82 const __m256 vs1 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn1), 23));
83 const __m256 vs2 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn2), 23));
84 const __m256 vs3 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn3), 23));
85 const __m256 vs4 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn4), 23));
86 const __m256 vs5 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn5), 23));
87 const __m256 vs6 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn6), 23));
88 const __m256 vs7 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn7), 23));
89 const __m256 vs8 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn8), 23));
90 const __m256 vs9 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn9), 23));
91 const __m256 vs10 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn10), 23));
92 const __m256 vs11 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn11), 23));
93
94 vn0 = _mm256_sub_ps(vn0, vmagic_bias);
95 vn1 = _mm256_sub_ps(vn1, vmagic_bias);
96 vn2 = _mm256_sub_ps(vn2, vmagic_bias);
97 vn3 = _mm256_sub_ps(vn3, vmagic_bias);
98 vn4 = _mm256_sub_ps(vn4, vmagic_bias);
99 vn5 = _mm256_sub_ps(vn5, vmagic_bias);
100 vn6 = _mm256_sub_ps(vn6, vmagic_bias);
101 vn7 = _mm256_sub_ps(vn7, vmagic_bias);
102 vn8 = _mm256_sub_ps(vn8, vmagic_bias);
103 vn9 = _mm256_sub_ps(vn9, vmagic_bias);
104 vn10 = _mm256_sub_ps(vn10, vmagic_bias);
105 vn11 = _mm256_sub_ps(vn11, vmagic_bias);
106
107 __m256 vt0 = _mm256_fmadd_ps(vn0, vminus_ln2, vx0);
108 __m256 vt1 = _mm256_fmadd_ps(vn1, vminus_ln2, vx1);
109 __m256 vt2 = _mm256_fmadd_ps(vn2, vminus_ln2, vx2);
110 __m256 vt3 = _mm256_fmadd_ps(vn3, vminus_ln2, vx3);
111 __m256 vt4 = _mm256_fmadd_ps(vn4, vminus_ln2, vx4);
112 __m256 vt5 = _mm256_fmadd_ps(vn5, vminus_ln2, vx5);
113 __m256 vt6 = _mm256_fmadd_ps(vn6, vminus_ln2, vx6);
114 __m256 vt7 = _mm256_fmadd_ps(vn7, vminus_ln2, vx7);
115 __m256 vt8 = _mm256_fmadd_ps(vn8, vminus_ln2, vx8);
116 __m256 vt9 = _mm256_fmadd_ps(vn9, vminus_ln2, vx9);
117 __m256 vt10 = _mm256_fmadd_ps(vn10, vminus_ln2, vx10);
118 __m256 vt11 = _mm256_fmadd_ps(vn11, vminus_ln2, vx11);
119
120 __m256 vp0 = _mm256_fmadd_ps(vc5, vt0, vc4);
121 __m256 vp1 = _mm256_fmadd_ps(vc5, vt1, vc4);
122 __m256 vp2 = _mm256_fmadd_ps(vc5, vt2, vc4);
123 __m256 vp3 = _mm256_fmadd_ps(vc5, vt3, vc4);
124 __m256 vp4 = _mm256_fmadd_ps(vc5, vt4, vc4);
125 __m256 vp5 = _mm256_fmadd_ps(vc5, vt5, vc4);
126 __m256 vp6 = _mm256_fmadd_ps(vc5, vt6, vc4);
127 __m256 vp7 = _mm256_fmadd_ps(vc5, vt7, vc4);
128 __m256 vp8 = _mm256_fmadd_ps(vc5, vt8, vc4);
129 __m256 vp9 = _mm256_fmadd_ps(vc5, vt9, vc4);
130 __m256 vp10 = _mm256_fmadd_ps(vc5, vt10, vc4);
131 __m256 vp11 = _mm256_fmadd_ps(vc5, vt11, vc4);
132
133 vp0 = _mm256_fmadd_ps(vp0, vt0, vc3);
134 vp1 = _mm256_fmadd_ps(vp1, vt1, vc3);
135 vp2 = _mm256_fmadd_ps(vp2, vt2, vc3);
136 vp3 = _mm256_fmadd_ps(vp3, vt3, vc3);
137 vp4 = _mm256_fmadd_ps(vp4, vt4, vc3);
138 vp5 = _mm256_fmadd_ps(vp5, vt5, vc3);
139 vp6 = _mm256_fmadd_ps(vp6, vt6, vc3);
140 vp7 = _mm256_fmadd_ps(vp7, vt7, vc3);
141 vp8 = _mm256_fmadd_ps(vp8, vt8, vc3);
142 vp9 = _mm256_fmadd_ps(vp9, vt9, vc3);
143 vp10 = _mm256_fmadd_ps(vp10, vt10, vc3);
144 vp11 = _mm256_fmadd_ps(vp11, vt11, vc3);
145
146 vp0 = _mm256_fmadd_ps(vp0, vt0, vc2);
147 vp1 = _mm256_fmadd_ps(vp1, vt1, vc2);
148 vp2 = _mm256_fmadd_ps(vp2, vt2, vc2);
149 vp3 = _mm256_fmadd_ps(vp3, vt3, vc2);
150 vp4 = _mm256_fmadd_ps(vp4, vt4, vc2);
151 vp5 = _mm256_fmadd_ps(vp5, vt5, vc2);
152 vp6 = _mm256_fmadd_ps(vp6, vt6, vc2);
153 vp7 = _mm256_fmadd_ps(vp7, vt7, vc2);
154 vp8 = _mm256_fmadd_ps(vp8, vt8, vc2);
155 vp9 = _mm256_fmadd_ps(vp9, vt9, vc2);
156 vp10 = _mm256_fmadd_ps(vp10, vt10, vc2);
157 vp11 = _mm256_fmadd_ps(vp11, vt11, vc2);
158
159 vp0 = _mm256_fmadd_ps(vp0, vt0, vc1);
160 vp1 = _mm256_fmadd_ps(vp1, vt1, vc1);
161 vp2 = _mm256_fmadd_ps(vp2, vt2, vc1);
162 vp3 = _mm256_fmadd_ps(vp3, vt3, vc1);
163 vp4 = _mm256_fmadd_ps(vp4, vt4, vc1);
164 vp5 = _mm256_fmadd_ps(vp5, vt5, vc1);
165 vp6 = _mm256_fmadd_ps(vp6, vt6, vc1);
166 vp7 = _mm256_fmadd_ps(vp7, vt7, vc1);
167 vp8 = _mm256_fmadd_ps(vp8, vt8, vc1);
168 vp9 = _mm256_fmadd_ps(vp9, vt9, vc1);
169 vp10 = _mm256_fmadd_ps(vp10, vt10, vc1);
170 vp11 = _mm256_fmadd_ps(vp11, vt11, vc1);
171
172 vt0 = _mm256_mul_ps(vt0, vs0);
173 vt1 = _mm256_mul_ps(vt1, vs1);
174 vt2 = _mm256_mul_ps(vt2, vs2);
175 vt3 = _mm256_mul_ps(vt3, vs3);
176 vt4 = _mm256_mul_ps(vt4, vs4);
177 vt5 = _mm256_mul_ps(vt5, vs5);
178 vt6 = _mm256_mul_ps(vt6, vs6);
179 vt7 = _mm256_mul_ps(vt7, vs7);
180 vt8 = _mm256_mul_ps(vt8, vs8);
181 vt9 = _mm256_mul_ps(vt9, vs9);
182 vt10 = _mm256_mul_ps(vt10, vs10);
183 vt11 = _mm256_mul_ps(vt11, vs11);
184
185 __m256 vf0 = _mm256_fmadd_ps(vt0, vp0, vs0);
186 __m256 vf1 = _mm256_fmadd_ps(vt1, vp1, vs1);
187 __m256 vf2 = _mm256_fmadd_ps(vt2, vp2, vs2);
188 __m256 vf3 = _mm256_fmadd_ps(vt3, vp3, vs3);
189 __m256 vf4 = _mm256_fmadd_ps(vt4, vp4, vs4);
190 __m256 vf5 = _mm256_fmadd_ps(vt5, vp5, vs5);
191 __m256 vf6 = _mm256_fmadd_ps(vt6, vp6, vs6);
192 __m256 vf7 = _mm256_fmadd_ps(vt7, vp7, vs7);
193 __m256 vf8 = _mm256_fmadd_ps(vt8, vp8, vs8);
194 __m256 vf9 = _mm256_fmadd_ps(vt9, vp9, vs9);
195 __m256 vf10 = _mm256_fmadd_ps(vt10, vp10, vs10);
196 __m256 vf11 = _mm256_fmadd_ps(vt11, vp11, vs11);
197
198 vf0 = _mm256_andnot_ps(_mm256_cmp_ps(vx0, vdenorm_cutoff, _CMP_LT_OS), vf0);
199 vf1 = _mm256_andnot_ps(_mm256_cmp_ps(vx1, vdenorm_cutoff, _CMP_LT_OS), vf1);
200 vf2 = _mm256_andnot_ps(_mm256_cmp_ps(vx2, vdenorm_cutoff, _CMP_LT_OS), vf2);
201 vf3 = _mm256_andnot_ps(_mm256_cmp_ps(vx3, vdenorm_cutoff, _CMP_LT_OS), vf3);
202 vf4 = _mm256_andnot_ps(_mm256_cmp_ps(vx4, vdenorm_cutoff, _CMP_LT_OS), vf4);
203 vf5 = _mm256_andnot_ps(_mm256_cmp_ps(vx5, vdenorm_cutoff, _CMP_LT_OS), vf5);
204 vf6 = _mm256_andnot_ps(_mm256_cmp_ps(vx6, vdenorm_cutoff, _CMP_LT_OS), vf6);
205 vf7 = _mm256_andnot_ps(_mm256_cmp_ps(vx7, vdenorm_cutoff, _CMP_LT_OS), vf7);
206 vf8 = _mm256_andnot_ps(_mm256_cmp_ps(vx8, vdenorm_cutoff, _CMP_LT_OS), vf8);
207 vf9 = _mm256_andnot_ps(_mm256_cmp_ps(vx9, vdenorm_cutoff, _CMP_LT_OS), vf9);
208 vf10 = _mm256_andnot_ps(_mm256_cmp_ps(vx10, vdenorm_cutoff, _CMP_LT_OS), vf10);
209 vf11 = _mm256_andnot_ps(_mm256_cmp_ps(vx11, vdenorm_cutoff, _CMP_LT_OS), vf11);
210
211 _mm256_storeu_ps(output, vf0);
212 _mm256_storeu_ps(output + 8, vf1);
213 _mm256_storeu_ps(output + 16, vf2);
214 _mm256_storeu_ps(output + 24, vf3);
215 _mm256_storeu_ps(output + 32, vf4);
216 _mm256_storeu_ps(output + 40, vf5);
217 _mm256_storeu_ps(output + 48, vf6);
218 _mm256_storeu_ps(output + 56, vf7);
219 _mm256_storeu_ps(output + 64, vf8);
220 _mm256_storeu_ps(output + 72, vf9);
221 _mm256_storeu_ps(output + 80, vf10);
222 _mm256_storeu_ps(output + 88, vf11);
223 output += 96;
224
225 vacc0 = _mm256_add_ps(vacc0, vf0);
226 vacc1 = _mm256_add_ps(vacc1, vf1);
227 vacc0 = _mm256_add_ps(vacc0, vf2);
228 vacc1 = _mm256_add_ps(vacc1, vf3);
229 vacc0 = _mm256_add_ps(vacc0, vf4);
230 vacc1 = _mm256_add_ps(vacc1, vf5);
231 vacc0 = _mm256_add_ps(vacc0, vf6);
232 vacc1 = _mm256_add_ps(vacc1, vf7);
233 vacc0 = _mm256_add_ps(vacc0, vf8);
234 vacc1 = _mm256_add_ps(vacc1, vf9);
235 vacc0 = _mm256_add_ps(vacc0, vf10);
236 vacc1 = _mm256_add_ps(vacc1, vf11);
237 }
238 vacc0 = _mm256_add_ps(vacc0, vacc1);
239
240 __m256 vacc = vacc0;
241 for (; elements >= 8 * sizeof(float); elements -= 8 * sizeof(float)) {
242 const __m256 vi = _mm256_loadu_ps(input);
243 input += 8;
244
245 const __m256 vx = _mm256_sub_ps(vi, vi_max);
246
247 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
248
249 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
250
251 vn = _mm256_sub_ps(vn, vmagic_bias);
252
253 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
254
255 __m256 vp = _mm256_fmadd_ps(vc5, vt, vc4);
256 vp = _mm256_fmadd_ps(vp, vt, vc3);
257 vp = _mm256_fmadd_ps(vp, vt, vc2);
258 vp = _mm256_fmadd_ps(vp, vt, vc1);
259
260 vt = _mm256_mul_ps(vt, vs);
261 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
262
263 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
264
265 _mm256_storeu_ps(output, vf);
266 output += 8;
267
268 vacc = _mm256_add_ps(vacc, vf);
269 }
270 if (elements != 0) {
271 assert(elements >= 1 * sizeof(float));
272 assert(elements <= 7 * sizeof(float));
273 const __m256i vmask = _mm256_loadu_si256((const __m256i*) ((uintptr_t) ¶ms->avx2_rr1_p5.mask_table[7] - elements));
274
275 const __m256 vi = _mm256_maskload_ps(input, vmask);
276
277 const __m256 vx = _mm256_sub_ps(vi, vi_max);
278
279 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
280
281 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
282
283 vn = _mm256_sub_ps(vn, vmagic_bias);
284
285 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
286
287 __m256 vp = _mm256_fmadd_ps(vc5, vt, vc4);
288 vp = _mm256_fmadd_ps(vp, vt, vc3);
289 vp = _mm256_fmadd_ps(vp, vt, vc2);
290 vp = _mm256_fmadd_ps(vp, vt, vc1);
291
292 vt = _mm256_mul_ps(vt, vs);
293 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
294
295 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
296
297 __m128 vf_lo = _mm256_castps256_ps128(vf);
298 if (elements & (4 * sizeof(float))) {
299 _mm_storeu_ps(output, vf_lo);
300 vf_lo = _mm256_extractf128_ps(vf, 1);
301 output += 4;
302 }
303 if (elements & (2 * sizeof(float))) {
304 _mm_storel_pi((__m64*) output, vf_lo);
305 vf_lo = _mm_movehl_ps(vf_lo, vf_lo);
306 output += 2;
307 }
308 if (elements & (1 * sizeof(float))) {
309 _mm_store_ss(output, vf_lo);
310 }
311
312 vacc = _mm256_add_ps(vacc, _mm256_and_ps(vf, _mm256_castsi256_ps(vmask)));
313 }
314 __m128 vacc_lo = _mm_add_ps(_mm256_castps256_ps128(vacc), _mm256_extractf128_ps(vacc, 1));
315 vacc_lo = _mm_add_ps(vacc_lo, _mm_movehl_ps(vacc_lo, vacc_lo));
316 vacc_lo = _mm_add_ss(vacc_lo, _mm_movehdup_ps(vacc_lo));
317 _mm_store_ss(sum, vacc_lo);
318 _mm256_zeroupper();
319 }
320